IDT IDT74LVCH16652 3.3v cmos 16-bit bus transceiver and register with 3-state outputs, 5v tolerant i/o, bus-hold Datasheet

IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS
TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS,
5V TOLERANT I/O, BUS-HOLD
FEATURES:
IDT74LVCH16652
DESCRIPTION:
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
µ W typ. static)
• CMOS power levels (0.4µ
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
This 16-bit transceiver and register is built using advanced dual metal CMOS
technology. This high-speed, low power device is organized as twoindependent
8-bit bus transceivers with 3-state D-type registers. The control circuitry is
organized for multiplexed transmission of data between A bus and B bus either
directly or from the internal storage registers. Each 8-bit transceiver/register
features complementary Output Enable (OEAB and OEBA) inputs to control the
transciever functions and Select lines (SAB and SBA) to select either real-time
data or stored data. Separate clock inputsare provided for A and B port
registers. Data on the A or B data bus, or both,can be stored in the internal
registers by the low-to-high transitions at theappropriate clock pins. Flowthrough organization of signal pins simplifieslayout. All inputs are designed with
hysteresis for improved noise margin.
The LVCH16652A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The LVCH16652A has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1OEBA
56
2OEBA
29
1OEAB
1
2OEAB
28
1CLKBA
55
2CLKBA
30
1SBA
54
2SBA
31
1CLKAB
2
2CLKAB
27
2SAB
26
1SAB
3
B REG
B REG
D
D
C
1A1
5
C
52
A REG
1B1
D
2A1
15
42
A REG
2B1
D
C
C
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-4689/3
IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
°C
–50 to +50
mA
1OEAB
1
56
1OEBA
1CLKAB
2
55
1CLKBA
IOUT
DC Output Current
1SAB
3
54
1SBA
GND
GND
Continuous Clamp Current,
VI < 0 or VO < 0
mA
53
IIK
IOK
–50
4
1A1
5
52
1B1
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
1A2
6
51
1B2
VCC
7
50
VCC
1A3
8
49
1B3
1A4
9
48
1B4
1A5
10
47
1B5
GND
11
46
GND
1A6
12
45
1B6
1A7
13
44
1B7
1A8
14
43
1B8
2A1
15
42
2B1
2A2
16
41
2B2
2A3
17
40
2B3
GND
18
39
GND
2A4
19
38
2B4
2A5
20
37
2B5
2A6
21
36
2B6
VCC
22
35
VCC
2A7
23
34
2B7
2A8
24
33
2B8
GND
25
32
GND
2SAB
26
31
2SBA
2CLKAB
27
30
2CLKBA
2OEAB
28
29
2OEBA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Symbol
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
NOTE:
1. As applicable to the device type.
PIN DESCRIPTION
Pin Names
xAx
SSOP/ TSSOP
TOP VIEW
Description
Data Register A Inputs(1)
Data Register B Outputs
xBx
Data Register B Inputs(1)
Data Register A Outputs
xCLKAB, xCLKBA
xSAB, xSBA
xOEAB, xOEBA
Clock Pulse Inputs
Output Data Source Select Inputs
Output Enable Inputs
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
FUNCTION TABLE(1)
Data I/O(2)
Inputs
xOEAB
xOEBA
xCLKAB
xCLKBA
xSAB
xSBA
xAx
xBx
L
H
H or L
H or L
X
X
Input
Input
Isolation
Operation or Function
L
H
↑
↑
X
X
Input
Input
Store A and B Data
X
H
↑
H or L
X
X
Input
Unspecified(3)
H
H
↑
↑
X(3)
X
Input
Output
Store A in both registers
L
X
H or L
↑
X
X
Unspecified(3)
Input
Hold A, store B
L
L
↑
↑
X
X(3)
Output
Input
Store B in both registers
L
L
X
X
X
L
Output
Input
Real time B data to A bus
Stored B data to A bus
Store A, hold B
L
L
X
H or L
X
H
Output
Input
H
H
X
X
L
X
Input
Output
Real time A data to B bus
H
H
H or L
X
H
X
Input
Output
Stored A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B Bus and
Stored B data to A bus
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
↑ = LOW-to-HIGH Transition
2. The data output functions may be enabled or disabled by various signals at the xOEAB or xOEBA inputs. Data input functions are always enabled, i.e. data at the bus pins will
be stored on every LOW-to-HIGH transition on the clock inputs.
3. Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
VIH
VIL
Min.
Typ.(1)
Max.
Unit
VCC = 2.3V to 2.7V
1.7
—
—
V
VCC = 2.7V to 3.6V
2
—
—
VCC = 2.3V to 2.7V
—
—
0.7
VCC = 2.7V to 3.6V
—
—
0.8
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Test Conditions
V
Input Leakage Current
VCC = 3.6V
VI = 0 to 5.5V
—
—
±5
µA
IOZH
High Impedance Output Current
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
µA
IOZL
(3-State Output pins)
IOFF
Input/Output Power Off Leakage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
±50
µA
VIK
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
—
–0.7
–1.2
V
VH
ICCL
ICCH
ICCZ
∆ICC
Input Hysteresis
Quiescent Power Supply Current
VCC = 3.3V
VCC = 3.6V
VIN = GND or VCC
—
—
100
—
—
10
mV
µA
3.6 ≤ VIN ≤ 5.5V(2)
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
—
—
10
500
µA
IIH
IIL
Quiescent Power Supply Current
Variation
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
3
IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
BUS MANAGEMENT FUNCTIONS
BUS
A
BUS
A
BUS
B
xOEAB xOEBA xCLKAB
L
L
X
xCLKBA
X
xSAB
X
xSBA
L
xOEAB
H
xOEBA
H
Real-Time Transfer Bus B to Bus A
BUS
A
xCLKAB
X
xCLKBA
X
xSAB
L
xSBA
X
Real-Time Transfer Bus A to Bus B
BUS
A
BUS
B
xOEAB xOEBA xCLKAB xCLKBA xSAB
X
X
X
H
↑
X
L
X
↑
X
X
L
H
↑
↑
BUS
B
xSBA
X
X
X
BUS
B
xOEAB xOEBA
L
H
Storage from A and/or B
xCLKAB
H or L
xCLKBA
H or L
xSAB
H
Transfer Stored Data to A and/or B
4
xSBA
X
IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Bus-Hold Input Sustain Current
VCC = 3V
Bus-Hold Input Sustain Current
VCC = 2.3V
IBHL
IBHHO
Typ.(2)
Max.
Unit
– 75
—
—
µA
VI = 0.8V
75
—
—
VI = 1.7V
—
—
—
VI = 0.7V
—
—
—
VI = 0 to 3.6V
—
—
±500
VI = 2V
IBHL
IBHH
Min.
Test Conditions
Bus-Hold Input Overdrive Current
VCC = 3.6V
µA
µA
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol
VOH
VOL
Test Conditions(1)
Parameter
Output HIGH Voltage
Output LOW Voltage
Min.
Max.
Unit
V
VCC = 2.3V to 3.6V
IOH = – 0.1mA
VCC – 0.2
—
VCC = 2.3V
IOH = – 6mA
2
—
VCC = 2.3V
IOH = – 12mA
1.7
—
VCC = 2.7V
2.2
—
VCC = 3V
2.4
—
VCC = 3V
IOH = – 24mA
2
—
VCC = 2.3V to 3.6V
IOL = 0.1mA
—
0.2
VCC = 2.3V
IOL = 6mA
—
0.4
IOL = 12mA
—
0.7
VCC = 2.7V
IOL = 12mA
—
0.4
VCC = 3V
IOL = 24mA
—
0.55
V
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
CPD
Power Dissipation Capacitance per Transceiver Outputs enabled
CPD
Power Dissipation Capacitance per Transceiver Outputs disabled
Test Conditions
Typical
Unit
CL = 0pF, f = 10Mhz
55
pF
12
5
IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V
Symbol
Parameter
VCC = 3.3V ± 0.3V
Min.
Max.
Min.
Max.
Unit
150
—
150
—
MHz
—
6.4
1.4
6.3
ns
—
7.3
2.4
6.4
ns
—
8.8
1.9
7.4
ns
—
6.6
1.6
6.3
ns
—
6.6
1.2
6.2
ns
3.4
—
3
—
ns
0
—
0.2
—
ns
Pulse Duration, CLKAB or CLKBA HIGH or LOW
3.3
—
3.3
—
ns
Output Skew(2)
—
—
—
500
ps
fMAX
tPLH
Propagation Delay
tPHL
xAx to xBx or xBx to xAx
tPLH
Propagation Delay
tPHL
xCLKAB or xCLKBA to xAx or xBx
tPLH
Propagation Delay
tPHL
xSBA or xSAB to xAx or xBx
tPZH
Output Enable Time
tPZL
xOEBA or xOEAB to xAx or xBx
tPHZ
Output Disable Time
tPLZ
xOEBA or xOEAB to xAx or xBx
tSU
Set-up Time, xAx or xBx
before xCLKAB↑ or xCLKBA↑
tH
Hold Time, xAx or xBx
after xCLKAB↑ or xCLKBA↑
tW
tSK(o)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2 Skew between any two outputs of the same package and switching in the same direction.
6
IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
VCC(1)= 3.3V±0.3V VCC(1)= 2.7V
VCC(2)= 2.5V±0.2V
Unit
VLOAD
6
6
2 x Vcc
V
VIH
2.7
2.7
Vcc
V
VT
1.5
1.5
Vcc / 2
V
VLZ
300
300
150
mV
VHZ
300
300
150
mV
CL
50
50
30
pF
500Ω
Pulse (1, 2)
Generator
tPZL
GND
OUTPUT
SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY
OPEN
HIGH
tPHZ
VOH
VHZ
0V
VT
0V
Enable and Disable Times
DATA
INPUT
VLOAD
ASYNCHRONOUS
CONTROL
Disable High
Enable High
GND
SYNCHRONOUS
CONTROL
All Other Tests
Open
tSK (x)
tSU
tH
LOW-HIGH-LOW
PULSE
VOH
VT
VOL
VT
tW
HIGH-LOW-HIGH
PULSE
VT
LVC Link
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
tREM
Set-up, Hold, and Release Times
VOH
VT
VOL
OUTPUT 2
tH
LVC Link
VIH
VT
0V
tPHL1
tSU
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
Switch
tPLH2
VLOAD/2
VLZ
VOL
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
SWITCH POSITION
tSK (x)
tPLZ
VLOAD/2
VT
LVC Link
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
OUTPUT 1
VIH
VT
0V
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
tPLH1
DISABLE
CONTROL
INPUT
CL
Test Circuit for All Outputs
INPUT
VIH
VT
0V
ENABLE
500Ω
Open Drain
Disable Low
Enable Low
tPHL
Propagation Delay
VOUT
Test
tPLH
LVC Link
D.U.T.
RT
tPHL
OPPOSITE PHASE
INPUT TRANSITION
Open
VIN
tPLH
OUTPUT
VLOAD
VCC
VIH
VT
0V
VOH
VT
VOL
SAME PHASE
INPUT TRANSITION
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
7
IDT74LVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT
LVC
X
XX
Bus-Hold
Temp. Range
XXX
Family
XX
XXX
Device Type Package
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Thin Shrink Small Outline Package
652
16-Bit Bus Transceiver and Register with 3-State Outputs
16
Double-Density with Resistors, ±24mA
H
Bus-Hold
74
-40°C to +85°C
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8
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