ATMEL M44C090 Low-current microcontroller for wireless communication Datasheet

M44C090
M44C890
Table of Contents
1
2
3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.4
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.7
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Master Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Power-on Reset and Brown-out Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2
Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3
External Clock Supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
Voltage Monitor Control / Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Oscillator Circuits and External Clock Input Stage . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 1 Fully Integrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 2 with External Trimming Resistor . . . . . . . . . . . . . . . . . . . . . . . . .
4-MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Management Register (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Configuration Register (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6
Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1
Bidirectional Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Data Register (P2DAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 Control Register (P2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2
Bidirectional Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3
Bidirectional Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Universal Timer/Counter / Communication Module (UTCM) . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1
Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 1 Control Register 1 (T1C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 1 Control Register 2 (T1C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev.A4, 14-Dec-01
5
5
5
6
6
6
7
9
9
9
9
11
11
11
12
13
13
13
14
15
15
16
16
16
16
16
17
17
17
18
18
19
19
20
21
21
21
22
24
25
26
27
27
3 (63)
M44C090
M44C890
Table of Contents (continued)
4
5
6
7
4 (63)
Watchdog Control Register (WDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Output Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Control Register (T2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Mode Register 1 (T2M1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Mode Register 2 (T2M2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Compare and Compare Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Compare Mode Register (T2CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 COmpare Register 1 (T2CO1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 COmpare Register 2 (T2CO2) Byte Write . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3
Synchronous Serial Interface (SSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSI Peripheral Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9-bit Shift Mode (I2C compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit Pseudo I2C Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal 2-Wire Multi-Chip Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Control Register 1 (SIC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Control Register 2 (SIC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Status and Control Register (SISC) . . . . . . . . . . . . . . . . . . . . . . .
Serial Transmit Buffer (STB) – Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Receive Buffer (SRB) – Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4
Combination Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Combination Mode Timer 2 and SSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M44C890 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
U505M EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.2
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EEPROM – Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization after a Reset Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2
DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
28
29
30
31
34
34
35
36
37
37
37
37
38
38
38
39
41
42
42
43
43
44
45
45
45
46
46
47
47
47
50
50
51
51
52
52
52
53
53
54
54
54
56
61
62
Rev.A4, 14-Dec-01
M44C090
M44C890
1
Introduction
The M44C090 / M44C890 are members of Atmels family
of 4-bit single-chip microcontrollers. They contain ROM,
RAM, parallel I/O ports, one 8-bit programmable multi-
function timer/counter, voltage supervisor, interval timer
with watchdog function and a sophisticated on-chip clock
generation with integrated RC-, 32-kHz crystal- and
4-MHz crystal-oscillators.
Table 2 provides an overview of the available variants.
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
2 MARC4 Architecture
Table 2 Available variants of M4xCx9x
Version
Flash device
Production
Production
2.1
Type
T48C893
M44C090
M44C890
ROM
4 Kbyte EEPROM
2 Kbyte mask ROM
2 Kbyte mask ROM
General Description
The MARC4 microcontroller consists of an advanced
stack-based, 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with
physically separate program memory (ROM) and data
memory (RAM). Three independent buses, the
instruction bus, the memory bus and the I/O bus, are used
for parallel communication between ROM, RAM and
E2PROM peripheral
Packages
64 byte
SSO20
–––
SSO20
64 byte
SSO20
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes both, an expression and a
return stack. This architecture enables high-level
language programming without any loss of efficiency or
code density.
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
MARC4 CORE
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
X
Reset ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Program
Y
RAM
PC
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
SP
memory
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
RP
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
Instruction
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏ
bus
Memory bus
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
Instruction
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
TOS
decoder
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
SystemÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
CCR
ALU
clock
Interrupt
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
controller
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
I/O bus
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
256 x 4-bit
Reset
Clock
Sleep
On–chip peripheral modules
94 8973
Figure 3. MARC4 core
Rev.A4, 14-Dec-01
5 (63)
M44C090
M44C890
2.2
Components of MARC4 Core
1F8 h
1F0h
1 E8h
1 E0h
7FFFh
SCALL addresses
ROM
(2 K x 8 bit)
Z ero
p age
0 20 h
01 8 h
01 0 h
00 8h
0 00 h
1FFh
Zero page
000h
1 E0 h
INT7
1 C0 h
INT6
18 0h
INT5
14 0h
INT4
1 00 h
INT3
0 C0 h
INT2
0 80 h
INT1
04 0h
INT0
00 8h
0 00 h
$RESET
$AUTOSLEEP
13391
Figure 4. ROM map of M44C090
The core contains ROM, RAM, ALU, program counter,
RAM address registers, instruction decoder and interrupt
controller. The following sections describe each
functional block in more detail:
expression stack, the return stack and data memory for
variables and arrays. The RAM is addressed by any of the
four 8-bit wide RAM address registers SP, RP, X and Y.
2.2.1
The 4-bit wide expression stack is addressed with the
expression stack pointer (SP). All arithmetic, I/O and
memory reference operations take their operands from,
and return their results to the expression stack. The
MARC4 performs the operations with the top of stack
items (TOS and TOS–1). The TOS register contains the
top element of the expression stack and works in the same
way as an accumulator. This stack is also used for passing
parameters between subroutines and as a scratch pad area
for temporary storage of data.
ROM
The program memory (ROM) is mask programmed with
the customer application program during the fabrication
of the microcontroller. The ROM is addressed by a 12–bit
wide program counter, thus predefining a maximum
program bank size of 2 Kbytes. An additional 1 Kbyte of
ROM exists which is reserved for quality control self–test
software The lowest user ROM address segment is taken
up by a 512 byte zero page which contains predefined
start addresses for interrupt service routines and special
subroutines accessible with single byte instructions
(SCALL).
The corresponding memory map is shown in figure 4.
Look-up tables of constants can also be held in ROM and
are accessed via the MARC4’s built-in TABLE
instruction.
2.2.2
RAM
The M44C090 / M44C890 contains 256 x 4-bit wide static
random access memory (RAM). It is used for the
6 (63)
Expression Stack
Return Stack
The 12-bit wide return stack is addressed by the return
stack pointer (RP). It is used for storing return addresses
of subroutines, interrupt routines and for keeping loop
index counts. The return stack can also be used as a
temporary storage area.
The MARC4 instruction set supports the exchange of data
between the top elements of the expression stack and the
return stack. The two stacks within the RAM have a user
definable location and maximum depth.
Rev.A4, 14-Dec-01
M44C090
M44C890
RAM
ÏÏÏÏÏ
ÏÏÏÏÏ
(192 x 4-bit)
Autosleep
3
RAM address register:
Global
variables
X
ÏÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
ÏÏÏÏÏ
SP
TOS–1
RP
SP
4-bit
Expression
stack
ÏÏÏÏÏ
ÏÏÏÏÏ
Return stack
11
Return
stack
Global
vvariables
07h
03h
04h
00h
2.2.3
0
TOS
TOS–1
TOS–2
FFh
FCh
Y
ÏÏÏ
ÏÏÏ
Expression stack
0
RP
12-bit
13392
Figure 5. RAM map
from the ROM. Instructions currently being executed are
decoded in the instruction decoder to determine the
internal micro-operations. For linear code (no calls or
branches) the program counter is incremented with every
instruction cycle. If a branch-, call-, return-instruction or
an interrupt is executed, the program counter is loaded
with a new address. The program counter is also used with
the TABLE instruction to fetch 8-bit wide ROM
constants.
Registers
The MARC4 controller has seven programmable
registers and one condition code register. They are shown
in the following programming model.
Program Counter (PC)
The program counter (PC) is a 12-bit register which
contains the address of the next instruction to be fetched
11
0
PC
Program counter
0
0
7
0
RP
0
Return stack pointer
0
7
SP
Expression stack pointer
0
7
X
RAM address register (X)
7
0
Y
RAM address register (Y)
3
0
3
0
Top of stack register
TOS
CCR
C
–– B
I
Condition code register
Interrupt enable
Branch
Reserved
Carry / borrow
Figure 6. Programming model
Rev.A4, 14-Dec-01
7 (63)
M44C090
M44C890
RAM Address Registers
Top Of Stack (TOS)
The RAM is addressed with the four 8-bit wide RAM
address registers: SP, RP, X and Y. These registers allow
access to any of the 256 RAM nibbles.
The top of stack register is the accumulator of the
MARC4. All arithmetic/logic, memory reference and I/O
operations use this register. The TOS register receives
data from the ALU, ROM, RAM or I/O bus.
Expression Stack Pointer (SP)
The stack pointer (SP) contains the address of the next-totop 4-bit item (TOS–1) of the expression stack. The
pointer is automatically pre-incremented if a nibble is
moved onto the stack or post-decremented if a nibble is
removed from the stack. Every post-decrement operation
moves the item (TOS–1) to the TOS register before the SP
is decremented. After a reset the stack pointer has to be
initialized with ” >SP S0 ” to allocate the start address of
the expression stack area.
Return Stack Pointer (RP)
The return stack pointer points to the top element of the
12-bit wide return stack. The pointer automatically preincrements if an element is moved onto the stack, or it
post-decrements if an element is removed from the stack.
The return stack pointer increments and decrements in
steps of 4. This means that every time a 12-bit element
is stacked, a 4-bit RAM location is left unwritten. This
location is used by the qFORTH compiler to allocate 4-bit
variables. After a reset the return stack pointer has to be
initialized via ”>RP FCh ”.
RAM Address Registers (X and Y)
The X and Y registers are used to address any 4-bit item
in the RAM. A fetch operation moves the addressed
nibble onto the TOS. A store operation moves the TOS to
the addressed RAM location. By using either the
pre–increment or post–decrement addressing mode
arrays in the RAM can be compared, filled or moved.
8 (63)
Condition Code Register (CCR)
The 4-bit wide condition code register contains the
branch, the carry and the interrupt enable flag. These bits
indicate the current state of the CPU. The CCR flags are
set or reset by ALU operations. The instructions
SET_BCF, TOG_BF, CCR! and DI allow direct
manipulation of the condition code register.
Carry/Borrow (C)
The carry/borrow flag indicates that the borrowing or
carrying out of arithmetic logic unit (ALU) occurred
during the last arithmetic operation. During shift and
rotate operations, this bit is used as a fifth bit. Boolean
operations have no affect on the C-flag.
Branch (B)
The branch flag controls the conditional program
branching. Should the branch flag have been set by a
previous instruction a conditional branch will cause a
jump. This flag is affected by arithmetic, logic, shift, and
rotate operations.
Interrupt Enable (I)
The interrupt enable flag globally enables or disables the
triggering of all interrupt routines with the exception of
the non-maskable reset. After a reset or on executing the
DI instruction, the interrupt enable flag is reset thus
disabling all interrupts. The core will not accept any
further interrupt requests until the interrupt enable flag
has been set again by either executing an EI, RTI or
SLEEP instruction.
Rev.A4, 14-Dec-01
M44C090
M44C890
2.2.4
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ALU
RAM
SP
TOS–1
TOS–2
TOS–3
TOS–4
TOS
ALU
CCR
94 8977
Figure 7. ALU zero-address operations
The 4-bit ALU performs all the arithmetic, logical, shift
and rotate operations with the top two elements of the
expression stack (TOS and TOS–1) and returns the result
to the TOS. The ALU operations affect the carry/borrow
and branch flag in the condition code register (CCR).
2.2.5
I/O Bus
The I/O ports and the registers of the peripheral modules
are I/O mapped. All communication between the core and
the on-chip peripherals takes place via the I/O bus and the
associated I/O control. With the MARC4 IN and OUT
instructions the I/O bus allows a direct read or write
access to one of the 16 primary I/O addresses. More about
the I/O access to the on-chip peripherals is described in
the section ”Peripheral Modules”. The I/O bus is internal
and is not accessible by the customer on the final microcontroller device, but it is used as the interface for the
MARC4 emulation (see also the section ”Emulation”).
2.2.6
Instruction Set
The MARC4 instruction set is optimized for the high level
programming language qFORTH. Many MARC4
instructions are qFORTH words. This enables the
compiler to generate a fast and compact program code.
The CPU has an instruction pipeline allowing the
controller to prefetch an instruction from ROM at the
same time as the present instruction is being executed.
Rev.A4, 14-Dec-01
The MARC4 is a zero address machine, the instructions
containing only the operation to be performed and no
source or destination address fields. The operations are
implicitly performed on the data placed on the stack.
There are one and two byte instructions which are
executed within 1 to 4 machine cycles. A MARC4
machine cycle is made up of two system clock
cycles (SYSCL). Most of the instructions are only one
byte long and are executed in a single machine cycle. For
more information refer to the ”MARC4 Programmer’s
Guide”.
2.2.7
Interrupt Structure
The MARC4 can handle interrupts with eight different
priority levels. They can be generated from the internal
and external interrupt sources or by a software interrupt
from the CPU itself. Each interrupt level has a hard-wired
priority and an associated vector for the service routine in
the ROM (see table 2). The programmer can postpone the
processing of interrupts by resetting the interrupt enable
flag (I) in the CCR. An interrupt occurrence will still be
registered, but the interrupt routine only started after the
I flag is set. All interrupts can be masked, and the priority
individually software configured by programming the
appropriate control register of the interrupting module.
(see section ”Peripheral Modules”).
9 (63)
M44C090
M44C890
INT7
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7
INT7 active
6
Priority level
RTI
INT5
5
INT5 active
RTI
INT3
4
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3
INT3 active
2
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INT2
RTI
INT2 pending
1
INT2 active
RTI
SWI0
0
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INT0 pending
INT0 active
RTI
Main /
Autosleep
Main /
Autosleep
Time
94 8978
Figure 8. Interrupt handling
Interrupt Processing
For processing the eight interrupt levels, the MARC4
includes an interrupt controller with two 8-bit wide
”interrupt pending” and ”interrupt active” registers. The
interrupt controller samples all interrupt requests during
every non-I/O instruction cycle and latches these in the
interrupt pending register. If no higher priority interrupt
is present in the interrupt active register, it signals the
CPU to interrupt the current program execution. If the
interrupt enable bit is set, the processor enters an interrupt
acknowledge cycle. During this cycle a short call
(SCALL) instruction to the service routine is executed
and the current PC is saved on the return stack. An
interrupt service routine is completed with the RTI
instruction. This instruction sets the interrupt enable flag,
resets the corresponding bits in the interrupt
pending/active register and fetches the return address
from the return stack to the program counter. When the
interrupt enable flag is reset (triggering of interrupt
routines are disabled), the execution of new interrupt
10 (63)
service routines is inhibited but not the logging of the
interrupt requests in the interrupt pending register. The
execution of the interrupt is delayed until the interrupt
enable flag is set again. Note that interrupts are only lost
if an interrupt request occurs while the corresponding bit
in the pending register is still set (i.e., the interrupt service
routine is not yet finished).
It should also be noted that automatic stacking of the RBR
is not carried out by the hardware and so if ROM banking
is used, the RBR must be stacked on the expression stack
by the application program and restored before the RTI.
After a master reset (power-on, brown-out or watchdog
reset), the interrupt enable flag and the interrupt pending
and interrupt active register are all reset.
Interrupt Latency
The interrupt latency is the time from the occurrence of
the interrupt to the interrupt service routine being
activated. In MARC4 this is extremely short (taking
between 3 to 5 machine cycles depending on the state of
the core).
Rev.A4, 14-Dec-01
M44C090
M44C890
Table 3 Interrupt priority table
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Interrupt
INT0
INT1
Priority
lowest
|
ROM Address
Interrupt Opcode
040h
C8h (SCALL 040h)
080h
D0h (SCALL 080h)
INT2
INT3
|
|
0C0h
100h
D8h (SCALL 0C0h)
E8h (SCALL 100h)
INT4
INT5
INT6
|
|
↓
140h
180h
1C0h
E8h (SCALL 140h)
F0h (SCALL 180h)
F8h (SCALL 1C0h)
INT7
highest
1E0h
FCh (SCALL 1E0h)
Function
Software interrupt (SWI0)
External hardware interrupt, any edge at BP52
or BP53
Timer 1 interrupt
SSI interrupt or external hardware interrupt at
BP40 or BP43
Timer 2 interrupt
Software interrupt (SW15)
External hardware interrupt, at any edge at
BP50 or BP51
Voltage monitor (VM) interrupt
Table 4 Hardware interrupts
Interrupt
Interrupt Mask
Register
Bit
P5CR
P52M1, P52M2
P53M1, P53M2
T1M
T1IM
SISC
SIM
T2CM
T2IM
P5CR
P50M1, P50M2
P51M1, P51M2
VCM
VIM
Interrupt Source
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INT1
INT2
INT3
INT4
INT6
INT7
Software Interrupts
The programmer can generate interrupts by using the
software interrupt instruction (SWI) which is supported
in qFORTH by predefined macros named SWI0...SWI7.
The software triggered interrupt operates exactly like any
hardware triggered interrupt. The SWI instruction takes
the top two elements from the expression stack and writes
the corresponding bits via the I/O bus to the interrupt
pending register. Therefore, by using the SWI instruction,
interrupts can be re-prioritized or lower priority processes
scheduled for later execution.
Hardware Interrupts
In the M44C090, there are eleven hardware interrupt
sources with seven different levels. Each source can be
masked individually by mask bits in the corresponding
control registers. An overview of the possible hardware
configurations is shown in table 4.
Rev.A4, 14-Dec-01
Any edge at BP52
any edge at BP53
Timer 1
SSI buffer full / empty or BP40/BP43 interrupt
Timer 2 compare match / overflow
Any edge at BP50,
any edge at BP51
External / internal voltage monitoring
2.3
Master Reset
The master reset forces the CPU into a well-defined
condition. It is unmaskable and is activated independent
of the current program state. It can be triggered by either
initial supply power-up, a short collapse of the power supply, brown-out detection circuitry, watchdog time-out, or
an external input clock supervisor stage (see figure 9). A
master reset activation will reset the interrupt enable flag,
the interrupt pending register and the interrupt active
register. During the power-on reset phase the I/O bus control signals are set to ’reset mode’ thereby initializing all
on-chip peripherals. All bidirectional ports are set to input
mode. Attention: During any reset phase, the BP20/NTE
input is driven towards VDD by a strong pull-up transistor.
Releasing the reset results in a short call instruction
(opcode C1h) to the ROM address 008h. This activates
the initialization routine $RESET which in turn has to
initialize all necessary RAM variables, stack pointers and
peripheral configuration registers (see table 7).
11 (63)
M44C090
M44C890
V DD
Pull-up
CL
NRST
res
Reset
timer
Internal
reset
CL=SYSCL/4
Power–on
reset
Brown–out
detection
VDD
VSS
VDD
VSS
Watch–
dog res
CWD
Ext. clock
supervisor
ExIn
13752
Figure 9. Reset configuration
The M44C090 / M44C890 has a fully integrated power-on reset and brown-out detection circuitry. For reset
generation no external components are needed .
reached. A reset condition will also be generated should
the supply voltage drop momentarily below the minimum
operating level except when a power down mode is
activated (the core is in SLEEP mode and the peripheral
clock is stopped). In this power-down mode the brownout detection is disabled.
These circuits ensure that the core is held in the reset state
until the minimum operating supply voltage has been
Two values for the brown-out voltage threshold are
programmable via the BOT-bit in the SC-register.
2.3.1
Power-on Reset and Brown-out
Detection
V
DD
2.0 V
1.7 V
t
d
CPU
Reset
BOT = ’1’
td
CPU
Reset
t
td
BOT = ’0’
td = 1.5 ms (typically)
13753
BOT = 1, low brown-out voltage threshold. (1.7 V) is reset value.
BOT = 0, high brown-out voltage threshold (1.9 V).
Figure 10. Brown-out detection
12 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
A power-on reset pulse is generated by a VDD rise across
the default BOT voltage level (1.7 V). A brown-out reset
pulse is generated when VDD falls below the brown-out
voltage threshold. Two values for the brown-out voltage
threshold are programmable via the BOT-bit in the
SC-register. When the controller runs in the upper supply
voltage range with a high system clock frequency, the
high threshold must be used. When it runs with a lower
system clock frequency, the low threshold and a wider
supply voltage range may be chosen. For further details,
see the electrical specification and the SC-register
description for BOT programming.
2.3.2
Watchdog Reset
The watchdog’s function can be enabled at the WDC-register and triggers a reset with every watchdog counter
overflow. To supress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog
register address (CWD).
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
2.3.3
2.4
Voltage Monitor
The voltage monitor consists of a comparator with
internal voltage reference. It is used to supervise the
supply voltage or an external voltage at the VMI-pin. The
comparator for the supply voltage has three internal
programmable thresholds one lower threshold (2.2 V),
one middle threshold (2.6 V). and one higher threshold
(3.0 V). For external voltages at the VMI-pin, the
comparator threshold is set to VBG = 1.3 V. The VMS-bit
indicates if the supervised voltage is below (VMS = 0) or
above (VMS = 1) this threshold. An interrupt can be
generated when the VMS-bit is set or reset to detect a
rising or falling slope. A voltage monitor interrupt (INT7)
is enabled when the interrupt mask bit (VIM) is reset in
the VMC-register.
V
DD
Voltage monitor
BP41/
VMI
OUT
IN
INT7
External Clock Supervisor
The external input clock supervisor function can be
enabled if the external input clock is selected within the
CM- and SC-registers of the clock module.
VMC :
VM2 VM1 VM0 VIM
VMST :
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
Rev.A4, 14-Dec-01
–
–
res VMS
13754
Figure 11. Voltage monitor
13 (63)
M44C090
M44C890
2.4.1
Voltage Monitor Control / Status Register
Primary register address: ’F’hex
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Á
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Á
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Á
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VMC: Write
Bit 3
VM2
Bit 2
VM1
Bit 1
VM0
Bit 0
VIM
Reset value: 1111b
VMST: Read
–––
–––
reserved
VMS
Reset value: xx11b
VM2: Voltage monitor Mode bit 2
VM1: Voltage monitor Mode bit 1
VM0: Voltage monitor Mode bit 0
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VM2
1
1
1
1
0
0
0
0
VM1
1
1
0
0
1
1
0
0
VM0
1
0
1
0
1
0
1
0
Function
Disable voltage monitor
External (VIM-input), internal reference threshold (1.3 V), interrupt with negative slope
Not allowed
External (VMI-input), internal reference threshold (1.3 V), interrupt with positive slope
Internal (supply voltage), high threshold (3.0 V), interrupt with negative slope
Internal (supply voltage), middle threshold (2.6 V), interrupt with negative slope
Internal (supply voltage), low threshold (2.2 V), interrupt with negative slope
Not allowed
VIM Voltage Interrupt Mask bit
VIM = 0, voltage monitor interrupt is enabled
VIM = 1, voltage monitor interrupt is disabled
VMS Voltage Monitor Status bit
VMS = 0, the voltage at the comparator input is below Vref
VMS = 1, the voltage at the comparator input is above Vref
VMS = 1
V
DD
Low threshold
Middle threshold
High threshold
3.0 V
2.6 V
2.2 V
Low threshold
Middle threshold
High threshold
VMS = 0
13755
Figure 12. Internal supply voltage supervisor
Internal reference level
VMI
Negative slope
Interrupt positive slope
VMS = 1
VMS = 1
VMS = 0
VMS = 0
1.3 V
Positive slope
Interrupt negative slope
t
13756
Figure 13. External input voltage supervisor
14 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
2.5
maintained stable to within a tolerance of ± 15% over the
full operating temperature and voltage range.
Clock Generation
2.5.1
Clock Module
The M44C090 / M44C890 contains a clock module with
4 different internal oscillator types: two RC-oscillators,
one 4-MHz crystal oscillator and one 32-kHz crystal
oscillator. The pins OSC1 and OSC2 are the interface to
connect a crystal either to the 4-MHz, or to the 32-kHz
crystal oscillator. OSC1 can be used as input for external
clocks or to connect an external trimming resistor for the
RC-oscillator 2. All necessary circuitry except the crystal
and the trimming resistor is integrated on-chip. One of
these oscillator types or an external input clock can be
selected to generate the system clock (SYSCL).
In applications that do not require exact timing, it is
possible to use the fully integrated RC-oscillator 1
without any external components. The RC-oscillator 1
center frequency tolerance is better than ± 50%. The
RC-oscillator 2 is a trimmable oscillator whereby the
oscillator frequency can be trimmed with an external
resistor attached between OSC1 and VDD. In this
configuration, the RC-oscillator 2 frequency can be
RC
oscillator 1
Ext. clock
OSC1
Oscin
The clock module is programmable via software with the
clock management register (CM) and the system
configuration register (SC). The required oscillator
configuration can be selected with the OS1-bit and the
OS0-bit in the SC-register. A programmable 4-bit divider
stage allows the adjustment of the system clock speed. A
special feature of the clock management is that an
external oscillator may be used and switched on and off
via a port pin for the power-down mode. Before the
external clock is switched off, the internal RC-oscillator
1 must be selected with the CCS-bit and then the SLEEP
mode may be activated. In this state an interrupt can wake
up the controller with the RC-oscillator, and the external
oscillator can be activated and selected by software. A
synchronization stage avoids too short clock periods if the
clock source or the clock speed is changed. If an external
input clock is selected, a supervisor circuit monitors the
external input and generates a hardware reset if the
external clock source fails or drops below 500 kHz for
more than 1 msec.
SYSCL
ExOut
Stop
ExIn
RCOut1
Stop Control
RC oscillator2
RCOut2
Stop
RTrim
IN1
Cin
/2
/2
4–MHz oscillator
Oscin
Oscout
/2
/2
IN2
Divider
4Out
Stop
32–kHz oscillator
OSC2
Oscout
Oscin
Oscout
32Out
Osc–Stop
Sleep
WDL
CM: NSTOP
Cin/16
CCS
CSS1
SUBCL
CSS0
32 kHz
SC:
BOT
–––
OS1
OS0
Figure 14. Clock module
Table 5 Clock modes
Mode
Clock Source for SYSCL
OS0
CCS = 1
CCS = 0
1
RC-oscillator 1 (intern)
External input clock
1
RC-oscillator 1 (intern)
RC-oscillator 2 with
external trimming resistor
0
RC-oscillator 1 (intern)
4-MHz oscillator
0
RC-oscillator 1 (intern)
32-kHz oscillator
Clock Source for SUBCL
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1
2
OS1
1
0
3
4
1
0
Rev.A4, 14-Dec-01
Cin / 16
Cin / 16
Cin / 16
32 kHz
15 (63)
M44C090
M44C890
The clock module generates two output clocks. One is the
system clock (SYSCL) and the other the periphery
(SUBCL). The SYSCL can supply the core and the
peripherals and the SUBCL can supply only the
peripherals with clocks. The modes for clock sources are
programmable with the OS1-bit and OS0-bit in the SCregister and the CCS-bit in the CM-register.
Ext. input clock
ExIn
Osc–Stop
Stop
CCS
Clock monitor
OSC2
2.5.2
RcOut1
ExOut
Ext. OSC1
Clock
Res
Oscillator Circuits and External
Clock Input Stage
The M44C090 / M44C890 series consists of four different
internal oscillators: two RC-oscillators, one 4-MHz crystal oscillator, one 32-kHz crystal oscillator and one
external clock input stage.
RC-Oscillator 1 Fully Integrated
For timing insensitive applications, it is possible to use
the fully integrated RC oscillator 1. It operates without
any external components and saves additional costs. The
RC–oscillator 1 center frequency tolerance is better than
±50% over the full temperature and voltage range. The
basic center frequency of the RC-oscillator 1 is
fO [3.8 MHz The RC oscillator 1 is selected by default
after power–on reset.
RC
oscillator 1
RcOut1
RcOut1
Stop
13759
Figure 16. External input clock
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OS1 OS0 CCS
1
1
x
1
1
0
0
1
x
Supervisor Reset Output
(Res)
enable
disable
disable
RC-Oscillator 2 with External Trimming
Resistor
The RC-oscillator 2 is a high resolution trimmable
oscillator whereby the oscillator frequency can be
trimmed with an external resistor between OSC1 and
VDD. In this configuration, the RC-oscillator 2 frequency
can be maintained stable to within a tolerance of ± 10%
over the full operating temperature and, voltage range
from VDD = 2.5 V to 6V.
For example: An output frequency at the RC-oscillator 2
of 2 MHz, can be obtained by connecting a resistor
Rext = 360 kΩ (see figure 17).
Osc–Stop
VDD
Control
13758
Rext
OSC1
Figure 15. RC-oscillator 1
RC
oscillator 2
RcOut2
RcOut2
RTrim
Osc–Stop
Stop
External Input Clock
The OSC1 can be driven by an external clock source
provided it meets the specified duty cycle, rise and fall
times and input levels. Additionally the external clock
stage contains a supervisory circuit for the input clock.
The supervisor function is controlled via the OS1,
OS0-bit in the SC–register and the CCS–bit in the CMregister. If the external input clock fails and CCS = 0 is set
in the CM-register, the supervisory circuit generates a
hardware reset. The input clock has failed if the frequency
is less than 500 kHz for more than 1 ms.
16 (63)
OSC2
13760
Figure 17. RC-oscillator 2
4-MHz Oscillator
The M44C090 / M44C890 4-MHz oscillator options need
a crystal or ceramic resonator connected to the OSC1 and
OSC2 pins to establish oscillation. All the necessary
oscillator circuitry, with the exception of the actual
crystal, resonator, C3 and C4 are integrated on-chip.
Rev.A4, 14-Dec-01
M44C090
M44C890
32-kHz Oscillator
OSC1
Oscin
4Out
4–MHz
oscillator
Stop
Oscout
XTAL
4 MHz
4Out
Osc–Stop
OSC2
Some applications require long-term time keeping or low
resolution timing. In this case, an on–chip, low power
32-kHz crystal oscillator can be used to generate both the
SUBCL and the SYSCL. In this mode, power
consumption is greatly reduced. The 32-kHz crystal
oscillator can not be stopped while the power-down mode
is in operation.
OSC1
Oscin
Figure 18. 4-MHz crystal oscillator
32Out
32–kHz
oscillator
XTAL
32 kHz
32Out
Oscout
C3
OSC2
OSC1
Oscin
4 MHz
C4
4Out
4–MHz
oscillator
Oscout Stop
Cer.
Res
4Out
Figure 20. 32-kHz crystal oscillator
Osc–Stop
OSC2
2.5.3
C2 = C3 = 22 pF
Clock Management
The clock management register controls the system clock
divider and synchronization stage. Writing to this register
triggers the synchronization cycle.
Figure 19. Ceramic resonator
Clock Management Register (CM)
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Auxiliary register address: ’3’hex
Bit 3
NSTOP
CM:
NSTOP
Bit 2
CCS
Bit 1
CSS1
Bit 0
CSS0
Reset value: 1111b
CCS
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the
internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on
the setting of OS0 and OS1 in the system configuration register
CSS1
CSS0
Core Speed Select 1
Core Speed Select 0
CSS1
0
1
1
0
Rev.A4, 14-Dec-01
CSS0
0
1
0
1
Divider
16
8
4
2
Note
Reset value
17 (63)
M44C090
M44C890
System Configuration Register (SC)
Primary register address: ’3’hex
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Bit 3
BOT
SC: write
BOT
Bit 2
–––
Bit 1
OS1
Bit 0
OS0
Reset value: 1x11b
Brown-Out Threshold
BOT = 1, low brown-out voltage threshold (1.7 V)
BOT = 0, high brown-out voltage threshold (2.0 V)
Oscillator Select 1
Oscillator Select 0
OS1
OS0
Mode
1
2
3
4
OS1
1
0
1
0
OS0
1
1
0
0
Input for SUBCL
Cin / 16
Cin / 16
Cin / 16
32 kHz
Selected Oscillators
RC–oscillator 1 and external input clock
RC-oscillator 1 and RC-oscillator 2
RC-oscillator 1 and 4-MHz crystal oscillator
RC-oscillator 1 and 32-kHz crystal oscillator
If the bit CCS = 0 in the CM-register the RC-oscillator 1 always stops.
2.6
instruction cycles (for example NOP NOP NOP) between
the IN or OUT command and the SLEEP command.
Power-down Modes
The sleep mode is a shut-down condition which is used to
reduce the average system power consumption in applications where the µC is not fully utilized. In this mode, the
system clock is stopped. The sleep mode is entered via the
SLEEP instruction. This instruction sets the interrupt enable bit (I) in the condition code register to enable all
interrupts and stops the core. During the sleep mode the
peripheral modules remain active and are able to generate
interrupts. The µC exits the sleep mode by carrying out
any interrupt or a reset.
The sleep mode can only be kept when none of the interrupt pending or active register bits are set. The application
of the $AUTOSLEEP routine ensures the correct function
of the sleep mode. For standard applications use the $AUTOSLEEP routine to enter the power-down mode. Using
the SLEEP instruction instead of the $AUTOSLEEP following an I/O instruction requires to insert 3 non I/O
The total power consumption is directly proportional to
the active time of the µC. For a rough estimation of the
expected average system current consumption, the following formula should be used:
Itotal (VDD,fsyscl) = ISleep + (IDD
tactive / ttotal)
IDD depends on VDD and fsyscl.
The M44C090 / M44C890 has various power-down
modes. During the sleep mode the clock for the MARC4
core is stopped. With the NSTOP-bit in the clock management register (CM) it is programmable if the clock for the
on–chip peripherals is active or stopped during the sleep
mode. If the clock for the core and the peripherals is
stopped the selected oscillator is switched off. An exception is the 32-kHz oscillator, if it is selected it runs
continously independent of the NSTOP-bit. If the oscillator is stopped or the 32 kHz oscillator is selected, power
consumption is extremely low.
Table 6 Power-down modes
Mode
CPU Core
Osc-Stop*
Brown-out
Function
Active
Power-down
SLEEP
RUN
SLEEP
SLEEP
NO
NO
YES
Active
Active
STOP
RC-Oscillator 1
RC-Oscillator 2
4-MHz Oscillator
RUN
RUN
STOP
32-kHz
Oscillator
External Input
Clock
RUN
RUN
RUN
YES
YES
STOP
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* Osc-Stop = SLEEP & NSTOP & WDL
18 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
3
Peripheral Modules
3.1
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O
bus (see figure 21). The IN or OUT instructions allow direct addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted to enable direct addressing of the ”primary register”. To address the
”auxiliary register”, the access must be switched with an
”auxiliary switching module”. Thus a single IN (or OUT)
to the module address will read (or write) into the module
primary register. Accessing the auxiliary register is performed with the same instruction preceded by writing the
module address into the auxiliary switching module. Byte
wide registers are accessed by multiple IN- (or OUT-)
instructions. For more complex peripheral modules, with
a larger number of registers, extended addressing is used.
In this case a bank of up to 16 subport registers are indirectly addressed with the subport address. The first
OUT-instruction writes the subport address to the subaddress register, the second IN- or OUT-instruction reads
data from or writes data to the addressed subport.
Module M1
Module ASW
Module M2
Module M3
(Address Pointer)
Subaddress Reg.
Bank of
Primary Regs.
Aux. Reg.
Subport Fh
Auxiliary Switch
Module
1
5
Subport Eh
Subport 1
Primary Reg.
Primary Reg.
Primary Reg.
Subport 0
2
3
6
4
I/O bus
to other modules
Dual Register
Access
Indirect Subport
Access
(Primary Register Write)
(Subport Register Write)
1
2
Addr.(SPort) Addr.(M1)
SPort_Data Addr.(M1)
Example of
qFORTH
Program
Code
Addr.(SPort) Addr.(M1)
2
Addr.(M 1)
OUT
(Prima ry Register Write)
3
Prim._Data
4
Address(M2) Address(ASW) OUT
5
Aux._Data
OUT
OUT
(Subport Register Read)
1
Single Register
Access
Address(M2) OU T
6
Prim._Data Address(M3) O UT
( Auxiliary Register Write )
(Prima ry Register Read)
6
Address(M3) IN
Address(M2) OUT
IN
(Primary Register Rea d)
(Subport Register Write Byte)
1
Addr.(SPort) Addr.(M1)
OUT
2
SPort_Data(lo) Addr.(M1)
OUT
2
SPort_Data(hi) Addr.(M1) OUT
3
4
2
2
Address(M2) Address(ASW) OUT
Address(M 2) IN
(Auxiliary Register Write Byte)
(Subport Register Rea d Byte)
Addr.(SPort) Addr.(M1)
IN
(Auxiliary Register Rea d)
5
1
Address(M 2)
OUT
4
Addr.(M 1)
IN (hi)
5
Aux._Data(lo) Address(M2) OUT
Addr.(M 1)
IN (lo)
5
Aux._Data(hi) Address(M2) OUT
Address(M2) Address(ASW) OUT
Addr.(ASW) = Auxiliary Switch Module Address
Aux._Data (hi) = da ta to be written into Auxiliar y Register (high nibble)
Addr.(Mx) = Module Mx Addr ess
SPort_Data(lo) = data to be written into SubP ort (low nibble)
Addr.(SPort) = Subport Address
SPort_Data(hi) = da ta to be written into Subport (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
Prim._Data = data to be written into Primar y Register.
Aux._Data = da ta to be written into Auxilia ry Register
Aux. _Data (lo ) = data to be written into Auxiliar y Re gister (low nibble )
13357
Figure 21. Example of I/O addressing
Rev.A4, 14-Dec-01
19 (63)
M44C090
M44C890
Table 7 Peripheral addresses
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Port Address
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Name
––––
P2DAT
Aux.
P2CR
SC
CWD
Aux.
CM
P4DAT
Aux.
P4CR
P5DAT
Aux.
P5CR
––––
T12SUB
Subport address
0 T2C
1 T2M1
2 T2M2
3 T2CM
4 T2CO1
5 T2CO2
6 ––––
7 ––––
8 T1C1
9 T1C2
A WDC
B-F
ASW
STB
SRB
Aux.
SIC1
SISC
Aux.
SIC2
––––
––––
–––
–––
VMC
VMST
3.2
Write
/Read
Reset Value
W/R
W
W
R
W/R
W/R
W
W/R
W
1111b
1111b
1x11b
xxxxb
1111b
1111b
1111 1111b
1111b
1111 1111b
W
––––
W
W
W
W
W
W
––––
––––
W
W
W
0000b
1111b
1111b
0000b
1111b
1111 1111b
––––
––––
1111b
x111b
1111b
W
W
R
W
W/R
W
1111b
xxxx xxxxb
xxxx xxxxb
1111b
1x11b
1111b
––––
––––
––––
––––
1111b
xx11b
––––
W
R
Bidirectional Ports
Register Function
Reserved
Port 2 – data register / pin data
Port 2 – control register
Port 3 – system configuration register
Watchdog reset
Port 3 – clock management register
Port 4 – data register / pin data
Port 4 – control register (byte)
Port 5 – data register / pin data
Port 5 – control register (byte)
Reserved
Data to Timer 1/2 subport
Timer 2 control register
Timer 2 mode register 1
Timer 2 mode register 2
Timer 2 compare mode register
Timer 2 compare register 1
Timer 2 compare register 2 (byte)
Reserved
Reserved
Timer 1 control register 1
Timer 1 control register 2
Watchdog control register
Reserved
Auxiliary / switch register
Serial transmit buffer (byte)
Serial receive buffer (byte)
Serial interface control register 1
Serial interface status / control register
Serial interface control register 2
Reserved
Reserved
Reserved
Reserved
Voltage monitor control register
Voltage monitor status register
Module
Type
See
Page
M2
21
21
18
26
17
24
24
23
23
M3
M3
M2
M2
M2
M1
19
M1
M1
M1
M1
M1
M1
34
35
36
37
37
37
M1
M1
M1
27
27
28
ASW
M2
19
46
47
45
46
45
M2
M3
M3
14
14
There are three different directional ports available:
Port 2 4-bit wide bitwise-programmable I/O port.
All ports (2, 4 and 5) are 4 bits wide. All ports may be used
for data input or output. All ports are equipped with
Schmitt trigger inputs and a variety of mask options for
open drain, open source, full complementary outputs, pull
up and pull down transistors. All Port Data Registers
(PxDAT) are I/O mapped to the primary address register
of the respective port address and the Port Control Register (PxCR), to the corresponding auxiliary register.
20 (63)
Port 5 4-bit wide bitwise-programmable bidirectional
port with optional strong pull-ups and programmable interrupt logic.
Port 4 4-bit wide bitwise-programmable bidirectional
port also provides the I/O interface to Timer 2,
SSI, voltage monitor input and external interrupt
input.
Rev.A4, 14-Dec-01
M44C090
M44C890
3.2.1
Bidirectional Port 2
This, and all other bidirectional ports include a bitwise
programmable Control Register (P2CR), which enables
the individual programming of each port bit as input or
output. It also opens up the possibility of reading the pin
condition when in output mode. This is a useful feature
for self testing and for serial bus applications.
Port 2 however, has an increased drive capability and an
additional low resistance pull-up/-down transistor mask
option.
*
*
(Data out)
D
DD
Static
Pull-up
*
I/O Bus
Q
P2DATy
S
BP2y
V
*
Master reset
I/O Bus
V
Switched
Pull-up
I/O Bus
* Static
*
D S Q
P2CRy
(Direction)
DD
* Mask options
Pull-down
Switched
Pull-down
Figure 22. Bidirectional Port 2
Port 2 Data Register (P2DAT)
ÁÁÁÁÁÁÁ
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Primary register address: ’2’hex
Bit 3 *
P2DAT3
P2DAT
Bit 2
P2DAT2
Bit 1
P2DAT1
Bit 0
P2DAT0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
Port 2 Control Register (P2CR)
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Auxiliary register address: ’2’hex
Bit 3
P2CR3
P2CR
Bit 2
P2CR2
Bit 1
P2CR1
Bit 0
P2CR0
Reset value: 1111b
Value: 1111b means all pins in input mode
Code
3210
xxx1
xxx0
xx1x
xx0x
x1xx
x0xx
1xxx
0xxx
Function
BP20 in input mode
BP20 in output mode
BP21 in input mode
BP21 in output mode
BP22 in input mode
BP22 in output mode
BP23 in input mode
BP23 in output mode
Rev.A4, 14-Dec-01
21 (63)
M44C090
M44C890
3.2.2
Bidirectional Port 5
This, and all other bidirectional ports include a bitwise
programmable Control Register (P5CR), which allows
the individual programming of each port bit as input or
output. It also opens up the possibility of reading the pin
condition when in output mode. This is a useful feature
for self testing and for serial bus applications.
The port pins can also be used as external interrupt inputs
(see figures 24 & 25). The interrupts (INT1 and INT6) can
be masked or independently configured to trigger on ei-
ther edge. The interrupt configuration and port direction
is controlled by the Port 5 Control Register (P5CR). An
additional low resistance pull–up/–down transistor mask
option provides an internal bus pull–up for serial bus applications.
The Port 5 Data Register (P5DAT) is I/O mapped to the
primary address register of address ’5’h and the Port 5
Control Register (P5CR) to the corresponding auxiliary
register. The P5CR is a byte-wide register and is configured by writing first the low nibble then the high nibble
(see section 2.1 ”Addressing peripherals”).
I/O Bus
Switched
Pull-up
V
*
*
DD
Static
Pull-up
VDD
(Data out)
*
I/O Bus
D
Q
P5DATy
BP5y
S
V
*
DD
Master reset
Static
* Pull-down
*
IN enable
Switched
Pull-down
* Mask options
Figure 23. Bidirectional Port 5
INT1
INT6
Data in
Data in
BP52
BP51
Bidir. Port
Bidir. Port
IN_Enable
IN_Enable
I/O–bus
I/O–bus
Data in
Data in
BP53
BP50
Bidir. Port
Bidir. Port
IN_Enable
IN_Enable
Decoder
Decoder
Decoder
Decoder
P5CR: P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
13764
Figure 24. Port 5 external interrupts
22 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Port 5 Data Register (P5DAT)
ÁÁÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
Primary register address: ’5’hex
P5DAT
Bit 3
Bit 2
Bit 1
Bit 0
P5DAT3
P5DAT2
P5DAT1
P5DAT0
Reset value: 1111b
Port 5 Control Register (P5CR) Byte Write
Auxiliary register address: ’5’hex
P5CR
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
Bit 0
P51M2
P51M1
P50M2
P50M1
Bit 7
Bit 6
Bit 5
Bit 4
P53M2
P53M1
P52M2
P52M1
Reset value: 1111b
Reset value: 1111b
P5xM2, P5xM1 – Port 5x Interrupt mode/direction code
Auxiliary Address: ’5’hex
First Write Cycle
Code
Function
3210
x x 1 1 BP50 in input mode – interrupt disabled
x x 0 1 BP50 in input mode – rising edge interrupt
x x 1 0 BP50 in input mode – falling edge interrupt
x x 0 0 BP50 in output mode – interrupt disabled
1 1 x x BP51 in input mode – interrupt disabled
0 1 x x BP51 in input mode – rising edge interrupt
1 0 x x BP51 in input mode – falling edge interrupt
0 0 x x BP51 in output mode – interrupt disabled
Code
3210
xx11
xx01
xx10
xx00
11xx
01xx
10xx
00xx
Second Write Cycle
Function
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
Rev.A4, 14-Dec-01
BP52 in input mode – interrupt disabled
BP52 in input mode – rising edge interrupt
BP52 in input mode – falling edge interrupt
BP52 in output mode – interrupt disabled
BP53 in input mode – interrupt disabled
BP53 in input mode – rising edge interrupt
BP53 in input mode – falling edge interrupt
BP53 in output mode – interrupt disabled
23 (63)
M44C090
M44C890
3.2.3
Bidirectional Port 4
The bidirectional Port 4 is both a bitwise configurable I/O
port and provides the external pins for the Timer 2, SSI
and the voltage monitor input (VMI). As a normal port,
it performs in exactly the same way as bidirectional Port 2
(see figure 26). Two additional multiplexes allow data
and port direction control to be passed over to other internal modules (Timer 2, VM or SSI). The I/O-pins for SC
and SD line have an additional mode to generate an SSI–
interrupt.
All four Port 4 pins can be individually switched by the
P4CR–register . Figure 26 shows the internal interfaces to
bidirectional Port 4.
V
I/O Bus
DD
Intx
PIn
Static
*
PxMRy
* Pull-up
VDD
POut
*
I/O Bus
Switched
Pull-up
Q
D
BPxy
PxDATy
S
VDD
*
Master reset
(Direction)
I/O Bus
D
S
*
Q
Static
* Pull-down
PxCRy
PDir
* Mask options
Switched
Pull-down
Figure 25. Bidirectional Port 4
Port 4 Data Register (P4DAT)
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Primary register address: ’4’hex
P4DAT
Bit 3
Bit 2
Bit 1
Bit 0
P4DAT3
P4DAT2
P4DAT1
P4DAT0
Reset value: 1111b
Port 4 Control Register (P4CR) Byte Write
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Á
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Á
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Á
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Auxiliary register address: ’4’hex
P4CR
First write cycle
Second write cycle
Bit 3
Bit 2
Bit 1
Bit 0
P41M2
P41M1
P40M2
P40M1
Bit 7
Bit 6
Bit 5
Bit 4
P43M2
P43M1
P42M2
P42M1
Reset value: 1111b
Reset value: 1111b
P4xM2, P4xM1 – Port 4x Interrupt mode/direction code
24 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Auxiliary Address: ’4’hex
First Write Cycle
Code
Function
3210
x x 1 1 BP40 in input mode
x x 1 0 BP40 in output mode
x x 0 1 BP40 enable alternate function (SC for SSI)
Code
3210
xx11
xx10
xx0x
Second Write Cycle
Function
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Á
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Á
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Á
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Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ
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Á
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Á
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Á
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Á ÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
x x 0 0 BP40 enable alternate function (falling
edge interrupt input for INT3)
1 1 x x BP41 in intput mode
1 0 x x BP41 in output mode
0 1 x x BP41 enable alternate function (VMI for
voltage monitor input)
0 0 x x BP41 enable alternate function (T2I external clock input for Timer 2)
3.3
11xx
10xx
01xx
00xx
–––
BP42 in input mode
BP42 in output mode
BP42 enable alternate function (T2O for
Timer 2)
BP43 in input mode
BP43 in output mode
BP43 enable alternate function (SD for SSI)
BP43 enable alternate function (falling
edge interrupt input for INT3)
–––
Universal Timer/Counter / Communication Module (UTCM)
The Universal Timer/counter/ Communication Module
(UTCM) consists of Timer 1, Timer 2 and a Synchronous
Serial Interface (SSI).
Timer 1 is an interval timer that can be used to
generate periodical interrupts and as prescaler for
Timer 2, the serial interface and the watchdog function.
Timer 2 is an 8/12-bit timer with an external clock inSYSCL
SUBCL
put (T2I) and an output (T2O).
The SSI operates as two wire serial interface or as shift
register for modulation. The modulator units work
together with the timers and shift the data bits out of
the shift register.
There is a multitude of modes in which the timers and the
serial interface can work together.
from clock module
Timer 1
NRST
INT2
Watchdog
MUX
Interval / Prescaler
Timer 2
T1OUT
4-bit Counter 2/1
MUX
Compare 2/1
Modu–
lator 2
T2O
I/O bus
T2I
Control
POUT
8-bit Counter 2/2
MUX DCG
INT4
Compare 2/2
TOG2
SSI
SCL
Receive–Buffer
MUX
8-bit Shift–Register
SC
SD
Control
Transmit–Buffer
INT3
13393
Figure 26. UTCM block diagram
Rev.A4, 14-Dec-01
25 (63)
M44C090
M44C890
3.3.1
power-on reset ! If the watchdog function is not activated,
the timer can be restarted by writing into the T1C1
register with T1RM=1.
Timer 1
The Timer 1 is an interval timer which can be used to generate periodical interrupts and as prescaler for Timer 2,
Timer 3, the serial interface and the watchdog function.
Timer 1 can also be used as a watchdog timer to prevent
a system from stalling. The watchdog timer is a 3-bit
counter that is supplied by a separate output of Timer 1.
It generates a system reset when the 3-bit counter
overflows. To avoid this, the 3-bit counter must be reset
before it overflows. The application software has to
accomplish this by reading the CWD register.
The Timer 1 consists of a programmable 14-stage divider
that is driven by either SUBCL or SYSCL. The timer output signal can be used as prescaler clock or as SUBCL and
as source for the Timer 1 interrupt. Because of other
system requirements the Timer 1 output T1OUT is
synchronized with SYSCL. Therefore in the power-down
mode SLEEP (CPU core –> sleep and OSC-Stop –> yes)
the output T1OUT is stopped (T1OUT=0). Nevertheless
the Timer 1 can be active in SLEEP and generate Timer 1
interrupts. The interrupt is maskable via the T1IM bit and
the SUBCL can be bypassed via the T1BP bit of the T1C2
register. The time interval for the timer output can be programmed via the Timer 1 control register T1C1.
After power-on reset the watchdog must be activated by
software in the $RESET initialization routine. There are
two watchdog modes, in one mode the watchdog can be
switched on and off by software, in the other mode the
watchdog is active and locked. This mode can only be
stopped by carrying out a system reset.
The watchdog timer operation mode and the time interval
for the watchdog reset can be programmed via the
watchdog control register (WDC).
This timer starts running automatically after any
SYSCL
WDCL
MUX
SUBCL
CL1
Prescaler
14 bit
NRST
Watchdog
4 bit
INT2
T1CS
T1BP
T1IM
T1OUT
T1MUX
13766
Figure 27. Timer 1 module
T1C1 T1RM T1C2 T1C1 T1C0
T1C2
T1BP T1IM
3
Write of the
T1C1 register
Decoder
T1IM=0
T1MUX
MUX for interval timer
INT2
T1IM=1
T1OUT
RES Q1 Q2 Q3 Q4 Q5
CL1
CL
Q6
Q8
Q11
Q14 SUBCL
Q8
Q11
Q14
Watchdog
Divider / 8
Decoder
MUX for watchdog timer
2
WDC WDL WDR WDT1 WDT0
WDCL
Divider
RESET
RESET
(NRST)
RES
Watchdog
mode control
Read of the
CWD register
13767
Figure 28. Timer 1 and watchdog
26 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Timer 1 Control Register 1 (T1C1)
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Address: ’7’hex – Subaddress: ’8’hex
Bit 3 *
T1RM
T1C1
Bit 2
T1C2
Bit 1
T1C1
Bit 0
T1C0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
T1RM
Timer 1 Restart Mode
T1RM = 0, write access without Timer 1 restart
T1RM = 1, write access with Timer 1 restart
Note: if WDL = 0, Timer 1 restart is impossible
Timer 1 Control bit 2
Timer 1 Control bit 1
Timer 1 Control bit 0
T1C2
T1C1
T1C0
The three bits T1C[2:0] select the divider for timer 1. The
resulting time interval depends on this divider and the
timer 1 input clock source. The timer input can be supplied by the system clock, the 32kHz oscillator or via the
T1C2 T1C1 T1C0 Divider
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
clock management. If the clock management generates
the SUBCL, the selected input clock from the RC oscillator, 4MHz oscillator or an external clock is divided by 16.
Time Interval with
SUBCL
Time Interval with
SUBCL = 32 kHz
Time Interval with
SYSCL = 2/1 MHz
SUBCL / 2
SUBCL / 4
SUBCL / 8
SUBCL / 16
SUBCL / 32
SUBCL / 256
SUBCL / 2048
SUBCL / 16384
61 µs
122 µs
244 µs
488 µs
0.977 ms
7.812 ms
62.5 ms
500 ms
1 µs / 2 µs
2 µs / 4 µs
4 µs / 8 µs
8 µs / 16 µs
16 µs / 32 µs
128 µs / 256 µs
1024 µs / 2048 µs
8192 µs / 16384 µs
2
4
8
16
32
256
2048
16384
Timer 1 Control Register 2 (T1C2)
Address: ’7’hex – Subaddress: ’9’hex
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ÁÁÁÁ
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ÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Bit 3 *
–––
T1C2
Bit 2
T1BP
Bit 1
T1CS
Bit 0
T1IM
Reset value: x111b
* Bit 3 –> MSB, Bit 0 –> LSB
T1BP
T1CS
T1IM
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see figure 28)
T1CS = 0, CL1 = SYSCL (see figure 28)
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
Rev.A4, 14-Dec-01
27 (63)
M44C090
M44C890
Watchdog Control Register (WDC)
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ÁÁ
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ÁÁ
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ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Address: ’7’hex – Subaddress: ’A’hex
Bit 3 *
WDL
WDC
Bit 2
WDR
Bit 1
WDT1
Bit 0
WDT0
Reset value: 1111b
* Bit 3 –> MSB, Bit 0 –> LSB
WDL
WDR
WDT1
WDT0
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the
WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs.
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped / disabled
WDR = 0, the watchdog is active / enabled
WatchDog Time 1
WatchDog Time 0
Both these bits control the time interval for the watchdog reset
WDT1 WDT0 Divider
0
0
1
1
3.3.2
0
1
0
1
Delay Time to Reset with
SUBCL = 32 kHz
Delay Time to Reset with
SYSCL = 2 / 1 MHz
15.625 ms
62.5 ms
0.5 s
4s
0.256 ms / 0.512 ms
1.024 ms / 2.048 ms
8.2 ms / 16.4 ms
65.5 ms / 131 ms
512
2048
16384
131072
Timer 2
Features: 8/12 bit timer for
Interrupt, square-wave,
generation
pulse
and
duty-cycle
Baud-rate generation for the internal shift register
Manchester and Biphase modulation together with the
SSI
Carrier frequency generation
together with the SSI
and
modulation
Timer 2 can be used as interval timer for interrupt
generation, as signal generator or as baud-rate generator
and modulator for the serial interface. It consists of a 4-bit
and an 8-bit up counter stage which both have compare
registers. The 4-bit counter stages of Timer 2 are
cascadable as 12-bit timer or as 8-bit timer with 4-bit
prescaler. The timer can also be configured as 8-bit timer
and separate 4-bit prescaler.
The Timer 2 input can be supplied via the system clock,
the external input clock (T2I), the Timer 1 output clock
or the shift clock of the serial interface. The external input
clock T2I is not synchronized with SYSCL. Therefore it
is possible to use Timer 2 with a higher clock speed than
28 (63)
SYSCL. Furthermore with that input clock the Timer 2
operates in the power-down mode SLEEP (CPU core –>
sleep and OSC–Stop –> yes) as well as in the POWERDOWN (CPU core –> sleep and OSC–Stop –> no). All
other clock sources supplied no clock signal in SLEEP.
The 4-bit counter stages of Timer 2 have an additional
clock output (POUT).
Its output has a modulator stage that allows the generation
of pulses as well as the generation and modulation of
carrier frequencies. The Timer 2 output can modulate
with the shift register internal data output to generate
Biphase- or Manchester-code.
If the serial interface is used to modulate a bitstream, the
4-bit stage of Timer 2 has a special task. The shift register
can only handle bitstream lengths divisible by 8. For other
lengths, the 4-bit counter stage can be used to stop the
modulator after the right bitcount is shifted out.
If the timer is used for carrier frequency modulation, the
4-bit stage works together with an additional 2-bit dutycycle generator like a 6-bit prescaler to generate carrier
frequency and duty cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable
count of pulses.
Rev.A4, 14-Dec-01
M44C090
M44C890
I/O–bus
P4CR
T2M1
T2M2
T2I
DCGO
SYSCL
T1OUT
CL2/1
SCL
4–bit Counter 2/1
RES
T2C
T2O
CL2/2
OVF1
DCG
POUT
Compare 2/1
8–bit Counter 2/2
RES
Control
OUTPUT
OVF2
TOG2
M2
Compare 2/2
MOUT
to
Modulator 3
INT4
CM1
T2CO1
T2CM
Biphase–,
Manchester–
modulator
T2CO2
SSI POUT
SO
Timer 2
modulator
output–stage
Control
I/O–bus
SSI
SSI
13394
Figure 29. Timer 2
For 12-bit compare data value: m = x +1 0 ≤ x ≤ 4095
For programming the time interval, the timer has a 4-bit
and an 8-bit compare register. For programming the timer
function, it has four mode and control registers. The
comparator output of stage 2 is controlled by a special
compare mode register (T2CM). This register contains
mask bits for the actions (counter reset, output toggle,
timer interrupt) which can be triggered by a compare
match event or the counter overflow. This architecture enables the timer function for various modes.
For 8-bit compare data value: n = y +1 0 ≤ y ≤ 255
For 4-bit compare data value:
l = z +1 0 ≤ z ≤ 15
Timer 2 Modes
Mode 1: 12-bit compare counter
The 4-bit stage and the 8-bit stage work together as a
12-bit compare counter. A compare match signal of the
4-bit and the 8-bit stage generates the signal for the
counter reset, toggle flip-flop or interrupt. The compare
action is programmable via the compare mode register
(T2CM). The 4-bit counter overflow (OVF1) supplies the
clock output (POUT) with clocks. The duty-cycle
generator (DCG) has to be bypassed in this mode.
Timer 2 compare data values
The Timer 2 has a 4-bit compare register (T2CO1) and an
8-bit compare register (T2CO2). Both these compare
registers are cascadable as a 12-bit compare register, or
8-bit compare register and 4-bit compare register.
POUT (CL2/1 /16)
CL2/1
4-bit counter
DCG
OVF2
8-bit counter
RES
TOG2
RES
INT4
4-bit compare
8-bit compare
CM2
CM1
4-bit register
T2D1, 0
Timer 2
output mode
and T2OTM–bit
8-bit register
T2RM
T2OTM
T2IM
T2CTM
13778
Figure 30. 12-bit compare counter
Rev.A4, 14-Dec-01
29 (63)
M44C090
M44C890
Mode 2: 8-bit compare counter with 4-bit programmable prescaler
DCGO
POUT
CL2/1
4-bit counter
DCG
OVF2
8-bit counter
RES
TOG2
RES
INT4
4-bit compare
CM2
8-bit compare
CM1
4-bit register
T2D1, 0
Timer 2
output mode
and T2OTM–bit
8-bit register
T2RM
T2OTM
T2IM
T2CTM
13778
Figure 31. 8-bit compare counter
The 4-bit stage is used as programmable prescaler for the
8-bit counter stage. In this mode, a duty-cycle stage is also
available. This stage can be used as an additional 2-bit
prescaler or for generating duty cycles of 25%, 33% and
50%. The 4-bit compare output (CM1) supplies the clock
output (POUT) with clocks.
Mode 3/4: 8-bit compare counter and 4-bit programmable prescaler
In these modes the 4-bit and the 8-bit counter stages work
independently as a 4-bit prescaler and an 8-bit timer with
an 2-bit prescaler or as a duty-cycle generator. Only in the
mode 3 and mode 4, can the 8-bit counter be supplied via
the external clock input (T2I) which is selected via the
P4CR register. The 4-bit prescaler is started via activating
of mode 3 and stopped and reset in mode 4. Changing
mode 3 and 4 has no effect for the 8-bit timer stage. The
4-bit stage can be used as prescaler for the SSI or to
generate the stop signal for modulator 2.
DCGO
T2I
CL2/2
DCG
SYSCL
8-bit counter
OVF2
TOG2
RES
INT4
8-bit compare
CM2
Timer 2
output mode
and T2OTM–bit
P4CR P41M2, 1
T2D1, 0
8-bit register
T2RM
T2OTM
T2IM
T2CTM
T1OUT
SYSCL
MUX
SCL
CL2/1
4-bit counter
RES
4-bit compare
T2CS1, 0
CM1
4-bit register
POUT
13779
Figure 32. 4-/8-bit compare counter
30 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Timer 2 Output Modes
The signal at the timer output is generated via
modulator 2. In the toggle mode, the compare match
event toggles the output T2O. For high resolution dutycycle modulation 8 bits or 12 bits can be used to toggle the
output. In the duty-cycle burst modulator modes the DCG
output is connected to T2O and switched on and off either
by the toggle flipflop output or the serial data line of the
SSI. Modulator 2 also has 2 modes to output the content
of the serial interface as Biphase or Manchester code.
The modulator output stage can be configured by the
output control bits in the T2M2 register. The modulator
is started with the start of the shift register (SIR = 0) and
stopped either by carrying out a shift register stop
(SIR = 1) or compare match event of stage 1 (CM1) of
Timer 2. For this task, Timer 2 mode 3 must be used and
the prescaler has to be supplied with the internal shift
clock (SCL).
DCGO
SO
TOG2
T2O
RE
Biphase/
Manchester
modulator
FE
SSI
CONTROL
Toggle
S1
S3
M2
S2
RES/SET
OMSK
M2
T2M2 T2OS2, 1, 0 T2TOP
13395
Figure 33. Timer 2 modulator output stage
Timer 2 Output Signals
Timer 2 output mode 1:
Toggle mode A: a Timer 2 compare match toggles the output flip-flop (M2) –> T2O
Input
Counter 2
T2R
0
0
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
0
1
Counter 2
CMx
INT4
T2O
13781
Figure 34. Interrupt timer / square wave generator – the output toggles with each edge compare match event
Rev.A4, 14-Dec-01
31 (63)
M44C090
M44C890
Timer 2 output mode 1:
Toggle mode B:
a Timer 2 compare match toggles the output flip-flop (M2) –> T2O
Input
Counter 2
T2R
Counter 2
0
0
0
1
2
3
4
5
6
7
4095/
255 0
1
2
3
4
5
6
CMx
INT4
T2O
Toggle
by start
T2O
13782
Figure 35. Pulse generator – the timer output toggles with the timer start if the T2TS-bit is set
Timer 2 output mode 1:
Toggle mode C:
a Timer 2 compare match toggles the output flip-flop (M2) –> T2O
Input
Counter 2
T2R
Counter 2
0
0
0
1
2
3
4
5
6
7
4095/
255 0
1
2
3
4
5
6
CMx
OVF2
INT4
T2O
13783
Figure 36. Pulse generator – the timer toggles with timer overflow and compare match
Timer 2 output mode 2:
Duty-cycle burst generator 1:
the DCG output signal (DCGO) is given to the output, and gated by the output
flip-flop (M2)
DCGO
1 2 0 1 2 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5
Counter 2
TOG2
M2
T2O
Counter = compare register (=2)
13784
Figure 37. Carrier frequency burst modulation with Timer 2 toggle flip-flop output
32 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Timer 2 output mode 3:
Duty-cycle burst generator 2:
the DCG output signal (DCGO) is given to the output, and gated by the SSI internal
data output (SO)
DCGO
1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter 2
Counter = compare register (=2)
TOG2
SO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12 Bit 13
T2O
13785
Figure 38. Carrier frequency burst modulation with the SSI data output
Timer 2 output mode 4:
Biphase modulator:
Timer 2 modulates the SSI internal data output (SO) to Biphase code.
TOG2
SC
8-bit SR-Data
0
0
Bit 7
0
0
SO
T2O
1
1
1
0
1
1
0
1
0
1
0
Bit 0
1
13786
Data: 00110101
Figure 39. Biphase modulation
Timer 2 output mode 5:
Manchester modulator:
Timer 2 modulates the SSI internal data output (SO) to Manchester code
TOG2
SC
8-bit SR-Data
SO
T2O
0
Bit 7
0
0
1
1
0
1
0
1
Bit 0
0
1
1
0
1
0
Bit 7
1
Bit 0
13787
Data: 00110101
Figure 40. Manchester modulation
Rev.A4, 14-Dec-01
33 (63)
M44C090
M44C890
Timer 2 output mode 7: PWM mode: Pulse–width modulation output on Timer 2 output pin (T2O)
In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period
only the first compare match occurence is used to toggle the timer output flip-flop, until the overflow all further
compare match are ignored. This avoids the stuation that changing the compare register causes the occurence of several
compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other
Timer 2 modes are 8-bit.
Input clock
Counter 2/2
T2R
0
0
50
255 0
100
255 0
150 255 0 50
255 0
100
Counter 2/2
CM2
OVF2
load the next
compare value
INT4
T2O
T1
T2CO2=150
load
T2
T3
T
load
T1
T
T
T2
T
T
13788
Figure 41. PWM modulation
Timer 2 Registers
Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function.
All registers are indirectly addressed using extended addressing as described in section ”Addressing peripherals”. The
alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the
Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.
Timer 2 Control Register (T2C)
Address: ’7’hex – Subaddress: ’0’hex
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ÁÁ
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ÁÁ
T2C
Bit 3
T2CS1
Bit 2
T2CS0
Bit 1
T2TS
Bit 0
T2R
Reset value: 0000b
T2CS1
Timer 2 Clock Select bit 1
T2CS1
T2CS0
T2CS0
Timer 2 Clock Select bit 0
0
0
1
1
0
1
0
1
T2TS
Timer 2 Toggle with Start
T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start
T2TS = 1, the output flip-flop of Timer 2 is toggled when the timer is started with T2R
Timer 2 Run
T2R = 0, Timer 2 stop and reset
T2R = 1, Timer 2 run
T2R
34 (63)
Input Clock (CL 2/1) of
Counter Stage 2/1
System clock (SYSCL)
Output signal of Timer 1 (T1OUT)
Internal shift clock of SSI (SCL)
Reserved
Rev.A4, 14-Dec-01
M44C090
M44C890
Timer 2 Mode Register 1 (T2M1)
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Á
Address: ’7’hex – Subaddress: ’1’hex
T2M1
Bit 3
T2D1
T2D1
T2D0
Timer 2 Duty cycle bit 1
Timer 2 Duty cycle bit 0
T2D1
1
1
0
0
T2MS1
T2MS0
T2D0
1
0
1
0
Bit 2
T2D0
Bit 1
T2MS1
Bit 0
T2MS0
Reset value: 1111b
Function of Duty-Cycle Generator (DCG)
Bypassed (DCGO0)
Duty cycle 1/1 (DCGO1)
Duty cycle 1/2 (DCGO2)
Duty cycle 1/3 (DCGO3)
Additional Divider Effect
/1
/2
/3
/4
Timer 2 Mode Select bit 1
Timer 2 Mode Select bit 0
Mode
1
T2MS1
1
T2MS0
Clock Output (POUT)
1
4-bit counter overflow (OVF1)
2
1
0
4-bit compare output (CM1)
3
0
1
4-bit compare output (CM1)
4
0
0
4-bit compare output (CM1)
Timer 2 Modes
12-bit compare counter, the DCG
have to be bypassed in this mode
8-bit compare counter with 4-bit
programmable prescaler and dutycycle generator
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler run, the
counter 2/1 starts after writing
mode 3
8-bit compare counter clocked by
SYSCL or the external clock input
T2I, 4-bit prescaler stop and resets
Duty-Cycle Generator
The duty-cycle generator generates duty cycles from 25%, 33% or 50%. The frequency at the duty-cycle generator
output depends on the duty cycle and the Timer 2 prescaler setting. The DCG-stage can also be used as additional
programmable prescaler for Timer 2.
DCGIN
DCGO0
DCGO1
DCGO2
DCGO3
13807
Figure 42. DCG output signals
Rev.A4, 14-Dec-01
35 (63)
M44C090
M44C890
Timer 2 Mode Register 2 (T2M2)
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Address: ’7’hex – Subaddress: ’2’hex
Bit 3
T2TOP
T2M2
Bit 2
T2OS2
Bit 1
T2OS1
Bit 0
T2OS0
Reset value: 1111b
T2TOP
Timer 2 Toggle Output Preset
This bit allows the programmer to preset the Timer 2 output T2O.
T2TOP = 0, resets the toggle outputs with the write cycle (M2 = 0)
T2TOP = 1, sets toggle outputs with the write cycle (M2 = 1)
Note: If T2R = 1, no output preset is possible
T2OS2
T2OS1
T2OS0
Timer 2 Output Select bit 2
Timer 2 Output Select bit 1
Timer 2 Output Select bit 0
Output
Mode
1
T2OS2
T2OS1
T2OS0
Clock Output (POUT)
1
1
1
2
1
1
0
3
1
0
1
4
1
0
0
5
0
1
1
6
0
1
0
7
8
0
0
0
0
1
0
Toggle mode: a Timer 2 compare match toggles the
output flip-flop (M2) –> T2O
Duty-cycle burst generator 1: the DCG output signal
(DCG0) is given to the output and gated by the output
flip-flop (M2)
Duty-cycle burst generator 2: the DCG output signal
(DCGO) is given to the output and gated by the SSI internal data output (SO)
Biphase modulator: Timer 2 modulates the SSI internal
data output (SO) to Biphase code
Manchester modulator: Timer 2 modulates the SSI internal data output (SO) to Manchester code
SSI output: T2O is used directly as SSI internal data
output (SO)
PWM mode: an 8/12-bit PWM mode
Not allowed
If one of these output modes is used the T2O alternate function of Port 4 must also be activated.
36 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for
the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2.
The timer compares the contents of the compare register
current counter value and if it matches it generates an
output signal. Dependent on the timer mode, this signal
is used to generate a timer interrupt, to toggle the output
flip-flop as SSI clock or as a clock for the next counter
stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and
T2CO2 bits 4 to 11 of the 12-bit compare value. In all
other modes, the two compare registers work
independently as a 4- and 8-bit compare register. When
assigned to the compare register a compare event will be
supressed.
Timer 2 Compare Mode Register (T2CM)
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Address: ’7’hex – Subaddress: ’3’hex
Bit 3
T2OTM
T2CM
T2OTM
T2CTM
T2RM
T2IM
Bit 2
T2CTM
Bit 1
T2RM
Bit 0
T2IM
Reset value: 0000b
Timer 2 Overflow Toggle Mask bit
T2OTM = 0, disable overflow toggle
T2OTM = 1, enable overflow toggle, a counter overflow (OVF2) toggles output flip-flop (TOG2).
If the T2OTM-bit is set, only a counter overflow can generate an interrupt except on
the Timer 2 output mode 7.
Timer 2 Compare Toggle Mask bit
T2CTM = 0, disable compare toggle
T2CTM = 1, enable compare toggle, a match of the counter with the compare register toggles output flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM-bit is set, only
a match of the counter with the compare register can generate an interrupt.
Timer 2 Reset Mask bit
T2RM = 0, disable counter reset
T2RM = 1, enable counter reset, a match of the counter with the compare register resets the
counter
Timer 2 Interrupt Mask bit
T2IM = 0, disable Timer 2 interrupt
T2IM = 1, enable Timer 2 interrupt
Timer 2 Output Mode
1, 2, 3, 4, 5 and 6
1, 2, 3, 4, 5 and 6
7
T2OTM
0
1
x
T2CTM
x
x
1
Timer 2 Interrupt Source
Compare match (CM2)
Overflow (OVF2)
Compare match (CM2)
Timer 2 COmpare Register 1 (T2CO1)
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Address: ’7’hex – Subaddress: ’4’hex
T2CO1
Write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Timer 2 COmpare Register 2 (T2CO2) Byte Write
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Address: ’7’hex – Subaddress: ’5’hex
T2CO2
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: 1111b
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: 1111b
Rev.A4, 14-Dec-01
37 (63)
M44C090
M44C890
3.3.3
Synchronous Serial Interface (SSI)
SSI Features:
(SI), a serial output data terminal (SO) and a shift clock
(SC). The SSI uses BP40 as shift clock (SC), while the
serial data input (SI) is applied to BP43 (configured in
P4CR as input!). Serial output data (SO) in this case is
passed through to BP42 (configured in P4CR to T2O) via
the Timer 2 output stage (T2M2 configured in mode 6).
2 and 3 wire NRZ
2 wire mode (I2C compatible)
(additional internal 2 wire link for multi-chip
packaging solutions)
c)
Timer/SSI combined modes – the SSI used
together with Timer 2 is capable of performing a variety
of data modulation and functions (see Timer Section).
The modulating data is converted by the SSI into a
continuous serial stream of data which is in turn
modulated in one of the timer functional blocks.
With Timer 2:
Biphase modulation
Manchester modulation
pulse-width demodulation
Burst modulation
SSI Peripheral Configuration
The synchronous serial interface (SSI) can be used either
for serial communication with external devices such as
EEPROMs, shift registers, display drivers, other
microcontrollers, or as a means for generating and
capturing on-chip serial streams of data. External data
communication takes place via the Port 4 (BP4)
multi-functional port which can be software configured
by writing the appropriate control word into the P4CR
register. The SSI can be configured in any one of the
following ways:
a)
2-wire external interface for bidirectional data
communication with one data terminal and one shift
clock. The SSI uses the Port BP43 as a bidirectional serial
data line (SD) and BP40 as shift clock line (SC).
b)
3-wire external interface for simultaneous input
and output of serial data, with a serial input data terminal
d)
Multi-chip link (MCL) – the SSI can also be used
as an interchip data interface for use in single package
multi–chip modules or hybrids. For such applications, the
SSI is provided with two dedicated pads (MCL_SD and
MCL_SC) which act as a two-wire chip-to-chip link. The
MCL can be activated by the MCL control bit. Should
these MCL pads be used by the SSI, the standard SD and
SC pins are not required and the corresponding Port 4
ports are available as conventional data ports.
General SSI Operation
The SSI is comprised essentially of an 8-bit shift register
with two associated 8-bit buffers – the receive buffer
(SRB) for capturing the incoming serial data and a transmit buffer (STB) for intermediate storage of data to be
serially output. Both buffers are directly accessable by
software. Transferring the parallel buffer data into and out
of the shift register is controlled automatically by the SSI
control, so that both single byte transfers or continuous bit
streams can be supported.
I/O-bus
Timer 2
SIC1
SIC2
SISC
SO
Control
SC
SI SCI
INT3
SC
SSI-Control
MCL_SC
TOG2
POUT
T1OUT
SYSCL
Output
/2
SO
Shift_CL
MSB
8-bit Shift Register
STB
SI
LSB
MCL_SD
SD
SRB
Transmit
Buffer
Receive
Buffer
I/O–bus
14103
Figure 43. Block diagram of the synchronous serial interface
38 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
The SSI can generate the shift clock (SC) either from one
of several on-chip clock sources or accept an external
clock. The external shift clock is output on, or applied to
the Port BP40. Selection of an external clock source is
performed by the Serial Clock Direction control bit
(SCD). In the combinational modes, the required clock is
selected by the corresponding timer mode.
The SSI can operate in three data transfer modes –
synchronous 8-bit shift mode, I2C compatible 9-bit shift
modes or 8-bit pseudo I2C protocol (without acknowledge-bit).
External SSI clocking is not supported in these modes.
The SSI should thus generate and has full control over the
shift clock so that it can always be regarded as an I2C Bus
Master device.
All directional control of the external data port used by
the SSI is handled automatically and is dependent on the
transmission direction set by the Serial Data Direction
(SDD) control bit. This control bit defines whether the
SSI is currently operating in Transmit (TX) mode or
Receive (RX) mode.
Serial data is organized in 8-bit telegrams which are
shifted with the most significant bit first. In the 9-bit I2C
mode, an additional acknowledge bit is appended to the
end of the telegram for handshaking purposes (see I2C
protocol).
At the beginning of every telegram, the SSI control loads
the transmit buffer into the shift register and proceeds
immediately to shift data serially out. At the same time,
incoming data is shifted into the shift register input. This
incoming data is automatically loaded into the receive
buffer when the complete telegram has been received.
Data can, if required thus be simultaneously received and
transmitted.
Before data can be transferred, the SSI must first be
activated. This is performed by means of the SSI reset
control (SIR) bit. All further operation then depends on
the data directional mode (TX/RX) and the present status
of the SSI buffer registers shown by the Serial Interface
Ready Status Flag (SRDY). This SRDY flag indicates the
(empty/full) status of either the transmit buffer (in TX
mode), or the receive buffer (in RX mode). The control
logic ensures that data shifting is temporarily halted at
any time, if the appropriate receive/transmit buffer is not
ready (SRDY = 0). The SRDY status will then
automatically be set back to ‘1’ and data shifting resumed
as soon as the application software loads the new data into
the transmit register (in TX mode) or frees the shift
register by reading it into the receive buffer (in RX mode).
A further activity status (ACT) bit indicates the present
status of the serial communication. The ACT bit remains
high for the duration of the serial telegram or if I2C stop
or start conditions are currently being generated. Both the
current SRDY and ACT status can be read in the SSI
status register. To deactivate the SSI, the SIR bit must be
set high.
8-bit Synchronous Mode
In the 8-bit synchronous mode, the SSI can operate as
either a 2 or 3 wire interface (see SSI peripheral
configuration). The serial data (SD) is received or
transmitted in NRZ format, synchronised to either the
rising or falling edge of the shift clock (SC). The choice
of clock edge is defined by the Serial Mode Control bits
(SM0,SM1). It should be noted that the transmission edge
refers to the SC clock edge with which the SD changes.
To avoid clock skew problems, the incoming serial input
data is shifted in with the opposite edge.
When used together with one of the timer modulator or
demodulator stages, the SSI must be set in the 8-bit
synchronous mode 1.
In RX mode, as soon as the SSI is activated (SIR= 0), 8
shift clocks are generated and the incoming serial data is
shifted into the shift register. This first telegram is
automatically transferred into the receive buffer and the
SRDY set to 0 indicating that the receive buffer contains
valid data. At the same time an interrupt (if enabled) is
generated.
SC
(rising edge)
SC
(falling edge)
DATA
0
0
1
1
0
1
0
1
Bit 0
0
1
1
0
1
0
1
Bit 0
Bit 7
SD/TO2
0
Bit 7
Data: 00110101
13823
Figure 44. 8-bit synchronous mode
Rev.A4, 14-Dec-01
39 (63)
M44C090
M44C890
The SSI then continues shifting in the following 8-bit
telegram. If, during this time the first telegram has been
read by the controller, the second telegram will also be
transferred in the same way into the receive buffer and the
SSI will continue clocking in the next telegram. Should,
however, the first telegram not have been read
(SRDY=1), then the SSI will stop, temporarily holding
the second telegram in the shift register until a certain
point of time when the controller is able to service the
receive buffer. In this way no data is lost or overwritten.
Deactivating the SSI (SIR=1) in mid–telegram will
immediately stop the shift clock and latch the present
contents of the shift register into the receive buffer. This
can be used for clocking in a data telegram of less than 8
bits in length. Care should be taken to read out the final
complete 8-bit data telegram of a multiple word message
before deactivating the SSI (SIR=1) and terminating the
reception. After termination, the shift register contents
will overwrite the receive buffer.
SC
msb
SD
lsb
7 6 5 4 3 2 1
msb
0
lsb msb
lsb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
tx data 1
tx data 2
0
tx data 3
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Write STB
(tx data 1)
Write STB
(tx data 2)
Write STB
(tx data 3)
13824
Figure 45. Example of 8-bit synchronous transmit operation
SC
lsb
msb
SD
msb
lsb
msb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
rx data 1
lsb
7 6 5 4 3 2 1 0 7 6 5 4
rx data 2
rx data 3
SIR
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
Read SRB
(rx data 1)
Read SRB
(rx data 2)
Read SRB
(rx data 3)
13825
Figure 46. Example of 8-bit synchronous receive operation
40 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
9-bit Shift Mode (I2C compatible)
In the 9-bit shift mode, the SSI is able to handle the I2C
protocol (described below). It always operates as an I2C
master device, i.e., SC is always generated and output by
the SSI. Both the I2C start and stop conditions are automatically generated whenever the SSI is activated or
deactivated by the SIR–bit. In accordance with the I2C
protocol, the output data is always changed in the clock
low phase and shifted in on the high phase.
Before activating the SSI (SIR=0) and commencing an
I2C dialog, the appropriate data direction for the first
word must be set using the SDD control bit. The state of
this bit controls the direction of the data port (BP43 or
MCL_SD). Once started, the 8 data bits are, depending on
the selected direction, either clocked into or out of the
shift register. During the 9th clock period, the port
direction is automatically switched over so that the
corresponding acknowledge bit can be shifted out or read
in. In transmit mode, the acknowledge bit received from
the slave device is captured in the SSI Status Register
(TACK ) where it can be read by the controller. and in
receive mode, the state of the acknowledge bit to be
returned to the slave device is predetermined by the SSI
Status Register (RACK ).
Changing the directional mode (TX/RX) should not be
performed during the transfer of an I2C telegram. One
should wait until the end of the telegram which can be
detected using the SSI interrupt (IFN =1) or by
interrogating the ACT status.
A 9-bit telegram, once started will always run to
completion and will not be prematurely terminated by the
SIR bit. So, if the SIR–bit is set to ‘1’ in mit telegram, the
SSI will complete the current transfer and terminate the
dialog with an I2C stop condition.
Start
Stop
SC
lsb
msb
SD
7 6 5 4 3 2 1 0 A
msb
lsb
7 6 5 4 3 2 1 0 A
tx data 1
tx data 2
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Write STB
(tx data 2)
13826
Figure 47. Example of I2C transmit dialog
Rev.A4, 14-Dec-01
41 (63)
M44C090
M44C890
Start
Stop
SC
msb
SD
lsb
7 6 5 4 3 2 1 0 A
tx data 1
msb
lsb
7 6 5 4 3 2 1 0 A
rx data 2
SRDY
ACT
Interrupt
(IFN = 0)
Interrupt
(IFN = 1)
SIR
SDD
Write STB
(tx data 1)
Read SRB
(rx data 2)
13827
Figure 48. Example of I2C receive dialog
8-bit Pseudo I2C Mode
In this mode, the SSI exhibits all the typical I2C operational features except for the acknowledge-bit which is
never expected or transmitted.
I2C Bus Protocol
The I2C protocol constitutes a simple 2-wire bidirectional
communication highway via which devices can
communicate control and data information. Although the
I2C protocol can support multi-master bus
configurations, the SSI, in I2C mode is intended for use
purely as a master controller on a single master bus
system. So all reference to multiple bus control and bus
contention will be omitted at this point.
All data is packaged into 8-bit telegrams plus a trailing
handshaking or acknowledge-bit. Normally the
42 (63)
communication channel is opened with a so-called start
condition, which initializes all devices connected to the
bus. This is then followed by a data telegram, transmitted
by the master controller device. This telegram usually
contains an 8-bit address code to activate a single slave
device connected onto the I2C bus. Each slave receives
this address and compares it with it’s own unique address.
The addressed slave device, if ready to receive data will
respond by pulling the SD line low during the 9th clock
pulse. This represents a so-called I2C acknowledge. The
controller on detecting this affirmative acknowledge then
opens a connection to the required slave. Data can then be
passed back and forth by the master controller, each 8-bit
telegram being acknowledged by the respective recipient.
The communication is finally closed by the master device
and the slave device put back into standby by applying a
stop condition onto the bus.
Rev.A4, 14-Dec-01
M44C090
M44C890
(1)
(2)
(4)
(4)
(3)
(1)
SC
SD
Start
condition
Data
valid
Data
change
Data
valid
Stop
condition
13832
Figure 49. I2C bus protocol 1
Bus not busy (1)
Data valid (4)
Both data and clock lines remain HIGH.
The state of the data line represents valid data
when, after START condition, the data line is
stable for the duration of the HIGH period of the
clock signal.
Start data transfer (2)
A HIGH to LOW transition of the SD line while
the clock (SC) is HIGH defines a START
condition.
Stop data transfer (3)
A LOW to HIGH transition of the SD line while
the clock (SC) is HIGH defines a STOP condition.
Acknowledge
All address and data words are serially transmitted
to and from device in eight–bit words. The
receiving device returns a zero on the data line
during the ninth clock cycle to acknowledge word
receipt.
SC
1
SD
Start
n
1st Bit
8
9
8th Bit
ACK
Stop
13833
Figure 50. I2C bus protocol 2
SSI Interrupt
The SSI interrupt INT3 can be generated either by an SSI
buffer register status (i.e., transmit buffer empty or
receive buffer full) at the end of SSI data telegram or on
the falling edge of the SC/SD pins on Port 4 (see P4CR).
SSI interrupt selection is performed by the Interrupt
FunctioN control bit (IFN). The SSI interrupt is usually
used to synchronize the software control of the SSI and
inform the controller of the present SSI status. The Port
4 interrupts can be used together with the SSI or, if the SSI
itself is not required, as additional external interrupt
sources. In either case this interrupt is capable of waking
the controller out of sleep mode.
Rev.A4, 14-Dec-01
To enable and select the SSI relevant interrupts use the
SSI interrupt mask (SIM) and the Interrupt Function
(IFN) while the Port 4 interrupts are enabled by setting
appropriate control bits in P4CR register.
Modulation
If the shift register is used together with Timer 2 for
modulation purposes, the 8-bit synchronous mode must
be used. In this case, the unused Port 4 pins can be used
as conventional bidirectional ports.
The modulation stage, if enabled, operates as soon as the
SSI is activated (SIR=0) and ceases when deactivated
(SIR=1).
43 (63)
M44C090
M44C890
Due to the byte-orientated data control, the SSI when
running normally generates serial bit streams which are
submultiples of 8 bits. An SSI output masking (OMSK)
function permits, however, the generation of bit streams
of any length. The OMSK signal is derived indirectly
from the 4-bit prescaler of the Timer 2 and masks out a
programmable number of unrequired trailing data bits
during the shifting out of the final data word in the bit
stream. The number of non-masked data bits is defined by
the value pre-programmed in the prescaler compare
register. To use output masking, the modulator stop mode
bit (MSM) must be set to ’0’ before programming the
final data word into the SSI transmit buffer. This in turn,
enables shift clocks to the prescaler when this final word
is shifted out. On reaching the compare value, the
prescaler triggers the OMSK signal and all following data
bits are blanked.
Internal 2-Wire Multi-Chip Link
Two additional on-chip pads (MCL_SC and MCL_SD)
for the SC and the SD line can be used as chip-to-chip link
for multi-chip applications. These pads can be activated
by setting the MCL-bit in the SISC-register.
U505M
SCL
SDA
Multi chip link
MCL_SC
MCL_SD
V DD
V SS
BP40/SC
BP43/SD
M44C090
13835
Figure 51. Multi-chip link
Timer 2
CL2/1
4-bit counter 2/1
SCL
Compare 2/1
CM1
OMSK
SO
Control
SC
SSI-control
Output
TOG2
POUT
T1OUT
SYSCL
SO
/2
Shift_CL
MSB
8-bit shift register
SI
LSB
13834
Figure 52. SSI output masking function
44 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Serial Interface Registers
Serial Interface Control Register 1 (SIC1)
Auxiliary register address: ’9’hex
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Bit 3
SIR
SIC1
SIR
Bit 2
SCD
Bit 1
SCS1
Bit 0
SCS0
SCD
Serial Interface Reset
SIR = 1, SSI inactive
SIR = 0, SSI active
Serial Clock Direction
SCD = 1, SC line used as output
SCD = 0, SC line used as input
Note: This bit has to be set to ’1’ during the I2C mode
SCS1
SCS0
Serial Clock source Select bit 1
Serial Clock source Select bit 0
Note: with SCD = ’0’ the bits SCS1
and SCS0 are insignificant
SCS1
1
1
0
0
SCS0
1
0
1
0
Reset value: 1111b
Internal Clock for SSI
SYSCL / 2
T1OUT / 2
POUT / 2
TOG2 / 2
•
In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been loaded (SRDY = 1).
•
Setting SIR-bit loads the contents of the shift register into the receive buffer (synchronous 8-bit mode only).
•
In I2C modes, writing a 0 to SIR generates a start condition and writing a 1 generates a stop condition.
Serial Interface Control Register 2 (SIC2)
Auxiliary register address: ’A’hex
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Bit 3
MSM
SIC2
Bit 2
SM1
Bit 1
SM0
Bit 0
SDD
Reset value: 1111b
MSM
Modular Stop Mode
MSM = 1, modulator stop mode disabled (output masking off)
MSM = 0, modulator stop mode enabled (output masking on) – used in modulation modes for
generating bit streams which are not sub-multiples of 8 bit.
SM1
SM0
Serial Mode control bit 1 Mode SM1 SM0
SSI Mode
Serial Mode control bit 0
1
1
1
8-bit NRZ-Data changes with the rising edge of SC
2
1
0
8-bit NRZ-Data changes with the falling edge of SC
3
0
1
9-bit two-wire I2C compatible
4
0
0
8-bit two-wire pseudo I2C compatible (no
acknowledge)
SDD
Serial Data Direction
SDD = 1, transmit mode – SD line used as output (transmit data). SRDY is set by a transmit buffer
write access.
SDD = 0, receive mode – SD line used as input (receive data). SRDY is set by a receive buffer
read access
Note: SDD controls port directional control and defines the reset function for the SRDY–flag
Rev.A4, 14-Dec-01
45 (63)
M44C090
M44C890
Serial Interface Status and Control Register (SISC)
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Primary register address: ’A’hex
SISC
write
Bit 3
MCL
SISC
read
–––
MCL
RACK
TACK
SIM
IFN
SRDY
ACT
Bit 2
RACK
Bit 1
SIM
Bit 0
IFN
Reset value: 1111b
TACK
ACT
SRDY
Reset value: xxxxb
Multi-Chip Link activation
MCL = 1,
multi-chip link disabled. This bit has to be set to ’0’ during transactions to/from
EEPROM of the M44C890
MCL = 0,
connnects SC and SD additional to the internal multi-chip link pads
Receive ACKnowledge status/control bit for I2C mode
RACK = 0, transmit acknowledge in next receive telegram
RACK = 1, transmit no acknowledge in last receive telegram
Transmit ACKnowledge status/control bit for I2C mode
TACK = 0, acknowledge received in last transmit telegram
TACK = 1, no acknowledge received in last transmit telegram
Serial Interrupt Mask
SIM = 1,
disable interrupts
SIM = 0,
enable serial interrupt. An interrupt is generated.
Interrupt FuNction
IFN = 1,
the serial interrupt is generated at the end of telegram
IFN = 0,
the serial interrupt is generated when the SRDY goes low (i.e., buffer becomes
empty/full in transmit/receive mode)
Serial interface buffer ReaDY status flag
SRDY = 1, in receive mode:
receive buffer empty
in transmit mode: transmit buffer full
SRDY = 0, in receive mode:
receive buffer full
in transmit mode: transmit buffer empty
Transmission ACTive status flag
ACT = 1,
transmission is active, i.e., serial data transfer. Stop or start conditions are currently in
progress.
ACT = 0,
transmission is inactive
Serial Transmit Buffer (STB) – Byte Write
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Primary register address: ’9’hex
STB
First write cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
The STB is the transmit buffer of the SSI. The SSI transfers the transmit buffer into the shift register and starts shifting
with the most significant bit.
46 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Serial Receive Buffer (SRB) – Byte Read
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Primary register address: ’9’hex
SRB
First read cycle
Bit 7
Bit 6
Bit 5
Bit 4
Reset value: xxxxb
Second read cycle
Bit 3
Bit 2
Bit 1
Bit 0
Reset value: xxxxb
The SRB is the receive buffer of the SSI. The shift register clocks serial data in (most significant bit first) and loads
content into the receive buffer when complete telegram has been received.
3.3.4
Combination Modes
The UTCM consists of one timer (Timer 2) and a serial interface. There is a multitude of modes in which the timers
and serial interface can work together.
The 8-bit wide serial interface operates as shift register for modulation. The modulator units work together with the
timer and shift the data bits into or out of the shift register.
Combination Mode Timer 2 and SSI
I/O–bus
P4CR
T2M1
T2M2
T2I
DCGO
SYSCL
T1OUT
reserved
SCL
CL2/1
4-bit Counter 2/1
RES
T2C
CL2/2
OVF1
T2O
DCG
POUT
Compare 2/1
8-bit Counter 2/2
RES
Timer 2 – control
OUTPUT
OVF2
TOG2
Compare 2/2
MOUT
INT4
POUT
T2CO1
CM1
T2CM
Biphase–,
Manchester–
modulator
T2CO2
TOG2
SO
Timer 2
modulator
output–stage
Control
I/O–bus
SIC1
SIC2
SISC
Control
TOG2
POUT
T1OUT
SYSCL
INT3
SCLI
SO
SC
SSI–control
MCL_SC
SCL
Output
SO
Shift_CL
MSB
8-bit shift register
STB
SI
MCL_SD
SD
LSB
SRB
Transmit
buffer
Receive
buffer
I/O–bus
13397
Figure 53. Combination Timer 2 and SSI
Rev.A4, 14-Dec-01
47 (63)
M44C090
M44C890
Combination mode 1: Burst modulation
SSI mode 1:
8-bit NRZ and internal data SO output to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler and DCG
Timer 2 output mode 3:
Duty-cycle burst generator
DCGO
1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1 2 0 1
Counter 2
Counter = compare register (=2)
TOG2
SO
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 Bit 11 Bit 12 Bit 13
T2O
13785
Figure 54. Carrier frequency burst modulation with the SSI internal data output
Combination mode 2: Biphase modulation 1
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 4:
The modulator 2 of Timer 2 modulates the SSI internal data output to Biphase code
TOG2
SC
8-bit SR-data
SO
T2O
0
0
Bit 7
0
1
0
1
1
0
1
1
0
1
0
1
0
Bit 0
1
13786
Data: 00110101
Figure 55. Biphase modulation 1
Combination mode 3: Manchester modulation 1
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 1, 2, 3 or 4: 8-bit compare counter with 4-bit programmable prescaler
Timer 2 output mode 5:
The modulator 2 of Timer 2 modulates the SSI internal data output to Manchester code
TOG2
SC
8-bit SR-data
SO
T2O
0
Bit 7
0
0
1
1
0
1
0
1
Bit 0
0
1
1
0
1
0
Bit 7
1
Bit 0
13787
Data: 00110101
Figure 56. Manchester modulation 1
48 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Combination mode 4: Manchester modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 3:
Timer 2 output mode 5:
8-bit compare counter and 4-bit prescaler
The modulator 2 of Timer 2 modulates the SSI data output to Manchester code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special
mode to supply the prescaler with the shift-clock. The control output signal (OMSK) of the SSI is used as stop signal
for the modulator. This is an example for a 12-bit Manchester telegram:
SCLI
Buffer full
SIR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
SC
MSM
Timer 2
Mode 3
SCL
Counter 2/1
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 4)
0
0
0
0
1
2
3
4
0
1
2
3
OMSK
T2O
13837
Figure 57. Manchester modulation 2
Combination mode 5: Biphase modulation 2
SSI mode 1:
8-bit shift register internal data output (SO) to the Timer 2 modulator stage
Timer 2 mode 3:
Timer 2 output mode 4:
8-bit compare counter and 4-bit prescaler
The modulator 2 of Timer 2 modulates the SSI data output to Biphase code
The 4-bit stage can be used as prescaler for the SSI to generate the stop signal for modulator 2. The SSI has a special
mode to supply the prescaler via the shift-clock. The control output signal (OMSK) of the SSI is used as stop signal
for the modulator. This is an example for a 13-bit Biphase telegram:
SCLI
Buffer full
SIR
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
SC
MSM
Timer 2
Mode 3
SCL
Counter 2/1
0
0
0
0
0
Counter 2/1 = Compare Register 2/1 (= 5)
0
0
0
0
1
2
3
4
5
0
1
2
OMSK
T2O
13838
Figure 58. Biphase modulation
Rev.A4, 14-Dec-01
49 (63)
M44C090
M44C890
4
M44C890
U505M
SCL
The M44C890 is a multi-chip product which offers a
combination of a MARC4-based microcontroller and a
serial EEPROM data memory in a single package. As
microcontroller the M44C090 is used and as serial
EEPROM the U505M. Two internal lines can be used as
chip-to-chip link in a single package. The maximum
internal data communication frequency between the
M44C090 and the U505M over the chip link (MCL_SC
and MCL_SD) is fSC_MCL = 500 kHZ.
The microcontroller and the EEPROM portions of this
multi-chip device are equivalent to their respective
individual component chips, except for the electrical
specification.
Internal 2-wire multi-chip link
Two additional on-chip pads (MCL_SC and MCL_SD)
for the SC and the SD line can be used as chip-to-chip link
for multi-chip applications. These pads can be activated
by setting the MCL-bit in the SISC-register.
VDD
VSS
SCL
SDA
Multi chip link
MCL_SC
V SS
BP40/SC
BP43/SD
M44C090
13835
Figure 59. Link between M44C090 and U505M
4.1
U505M EEPROM
The U505M is a 512-bit EEPROM internally organized
32 x 16 bit. The programming voltage as well as the writecycle timing is generated on-chip. The U505M features
a serial interface allowing operation on a simple two-wire
bus with an I2C-compatible protocol. Its low power consumption makes it well suited for battery applications.
HV–generator
Address
control
EEPROM
32 x 16
I/O
control
MCL_SD
V DD
Timing control
Mode
control
SDA
16–bit read/write buffer
8–bit data register
13883
Figure 60. Block diagram EEPROM
50 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
4.1.1
Serial Interface
The U505M has an I2C-like two-wire serial interface to
the microcontroller for read and write accesses to the
EEPROM. The U505M is considered to be a slave in all
these applications. That means, the controller has to be
the master that initiates the data transfer and provides the
clock for transmit and receive operations.
The serial interface is controlled by the M44C890
microcontroller which generates the serial clock and
controls the access via the SCL-line and SDA-line. SCL
is used to clock the data into and out of the device. SDA
is a bidirectional line that is used to transfer data into and
out of the device. The following protocol is used for the
data transfers.
Serial Protocol
Data states on the SDA-line changing only while SCL
is low.
Changes on the SDA-line while SCL is high are
interpreted as START or STOP condition.
A START condition is defined as high to low transition on the SDA-line while the SCL-line is high.
A STOP condition is defined as low to high transition
on the SDA-line while the SCL-line is high.
Each data transfer must be initialized with a START
condition and terminated with a STOP condition. The
START condition wakes the device from standby
mode and the STOP condition returns the device to
standby mode.
A receiving device generates an acknowledge (A)
after the reception of each byte. This requires an
additional clock pulse, generated by the master. If the
reception was successful the receiving master or slave
device pulls down the SDA-line during that clock
cycle. If an acknowledge is not detected (N) by the
interface in transmit mode, it will terminate further
data transmissions and go into receive mode. A master
device must finish its read operation by a non-acknowledge and then send a stop condition to bring the
device into a known state.
SCL
SDA
Stand Start
by condition
Data
valid
Data
Data/
change acknowledge
valid
Stop Stand–
condition by
13884
Figure 61. I2C protocol
Before the START condition and after the STOP
condition the device is in stand-by mode and the SDA
line is switched as input with pull-up resistor.
termines the following operation. It consists of the
5-bit row address, 2 mode control bits and the READ
/ NWRITE bit that is used to control the direction of
the following transfer. A ”0” defines a write access
and a ”1” a read access.
The control byte that follows the START condition de-
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Control byte format:
Mode control
bits
EEPROM address
Start
A4
A3
A2
A1
A0
C1
C0
Read/
NWrite
R/NW
Ackn
Control byte format:
Start
Rev.A4, 14-Dec-01
Control byte
Ackn
Data byte
Ackn
Data byte
Ackn
Stop
51 (63)
M44C090
M44C890
4.1.2
Two special control bytes enable the complete
initialization of EEPROM with ”0” or with ”1.
EEPROM
The EEPROM has a size of 512 bits and is organized as
32 x 16-bit matrix. To read and write data to and from the
EEPROM the serial interface must be used. The interface
supports one and two byte write accesses and one to
n-byte read accesses to the EEPROM.
EEPROM – Operating Modes
The operating modes of the EEPROM are defined via the
control byte. The control byte contains the row address,
the mode control bits and the read/not-write bit that is
used to control the direction of the following transfer. A
”0” defines a write access and a ”1” a read access. The
five address bits select one of the 32 rows of the EEPROM
memory to be accessed. For all accesses the complete
16-bit word of the selected row is loaded into a buffer. The
buffer must be read or overwritten via the serial interface.
The two mode control bits C1 and C2 define in which order the accesses to the buffer are performed: High byte –
low byte or low byte – high byte. The EEPROM also supports autoincrement and autodecrement read operations.
After sending the start address with the corresponding
mode, consecutive memory cells can be read row by row
without transmission of the row addresses.
Write Operations
The EEPROM permits 8-bit and 16-bit write operations.
A write access starts with the START condition followed
by a write control byte and one or two data bytes from the
master. It is completed via the STOP condition from the
master after the acknowledge cycle.
The programming cycle consists of an erase cycle (write
”zeros”) and the write cycle (write ”ones”). Both cycles
together take about 10 ms.
Acknowledge Polling
If the EEPROM is busy with an internal write cycle, all
inputs are disabled and the EEPROM will not
acknowledge until the write cycle is finished. This can be
used to detect the end of the write cycle. The master must
perform acknowledge polling by sending a start condition
followed by the control byte. If the device is still busy
with the write cycle, it will not return an acknowledge and
the master has to generate a stop condition or perform further acknowledge polling sequences. If the cycle is
complete, it returns an acknowledge and the master can
proceed with the next read or write cycle.
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Write One Data Byte
Start
Control byte
A
Data byte 1
A
Stop
A
Data byte 1
A
Data byte 2
Write Two Data Bytes
Start
Control byte
A
Stop
Write Control Byte Only
Start
Control byte
A
Stop
Write Control Bytes
MSB
Write low byte first
A4
LSB
A3
A2
A1
A0
Row address
Byte order
LB(R)
C1
C0
R/NW
0
1
0
HB(R)
MSB
Write high byte first
A4
LSB
A3
A2
A1
Row address
Byte order
HB(R)
A0
C1
C0
R/NW
1
0
0
LB(R)
A –> acknowledge; HB: high byte; LB: low byte; R: row address
52 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
Read Operations
The EEPROM allows byte-, word- and current address
read operations. The read operations are initiated in the
same way as write operations. Every read access is initiated by sending the START condition followed by the
control byte which contains the address and the read
mode. After the device receives a read command it returns an acknowledge, loads the addressed word into the
read\write buffer and sends the selected data byte to the
master. The master has to acknowledge the received byte
if it wants to proceed the read operation. If two bytes are
read out from the buffer the device increments respectively decrements the word address automatically and
loads the buffer with the next word. The read mode bits
determines if the low or high byte is read first from the
buffer and if the word address is incremented or decremented for the next read access. If the memory address
limit is reached, the data word address will ”roll over” and
the sequential read will continue. The master can terminate the read operation after every byte by not responding
with an acknowledge (N) and by issuing a stop condition.
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Á
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Á
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Á
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Á
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Á
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Á
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Á
Á
Read One Data Byte
Start
Control byte
A
Data byte 1
N
Stop
A
Data byte 1
A
Data byte 2
N
Stop
A
Data byte 1
A
Data byte 2
A
––––
Read Two Data Bytes
Start
Control byte
Read n Data Bytes
Start
Control byte
Data byte n
N
Stop
Read Control Bytes
MSB
Read low byte first, address increment
Byte order
LB(R)
A4
LSB
A3
HB(R)
A2
A1
A0
C1
C0
R/NW
Row address
0
1
1
LB(R+1)
–––
HB(R+1)
LB(R+n)
MSB
Read high byte first, addr. decrement
A4
LSB
A3
A2
A1
A0
Row address
Byte order
HB(R)
LB(R)
HB(R+n)
HB(R–1)
LB(R–1)
C1
C0
R/NW
1
0
1
–––
HB(R–n)
LB(R–n)
A –> acknowledge, N –> no acknowledge; HB: high byte; LB: low byte, R: row address
Initialization after a Reset Condition
The EEPROM with the serial interface has its own reset circuitry. In systems with microcontrollers that have their own
reset circuitry for power on reset, watchdog reset or brown-out reset, it may be necessary to bring the U505M into a
known state independent of its internal reset. This is performed by writing:
ÁÁ
ÁÁÁ
ÁÁ
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ÁÁ
ÁÁ
ÁÁÁ
ÁÁ
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ÁÁ
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ÁÁ
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ÁÁ
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Á
ÁÁ
Á
ÁÁÁ
ÁÁ
ÁÁ
ÁÁÁ
ÁÁÁÁ
Start
Control byte
A
Data byte 1
N
Stop
to the serial interface. If the U505M acknowledges this sequence it is in a defined state. Maybe it is necessary to perform
this sequence twice.
Rev.A4, 14-Dec-01
53 (63)
M44C090
M44C890
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
Voltages are given relative to VSS
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Parameters
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to + 6.5
V
Input voltage (on any pin)
VIN
VSS –0.3 VIN VDD +0.3
V
Output short circuit duration
tshort
indefinite
s
Operating temperature range
Tamb
–40 to +85
°C
Storage temperature range
Tstg
–40 to +130
°C
RthJA
140
K/W
Tsld
260
°C
Thermal resistance (SSO20)
Soldering temperature (t ≤ 10 s)
Stresses greater than those listed under absolute
maximum ratings may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at any condition above those
indicated in the operational section of this specification
is not implied. Exposure to absolute maximum rating
condition for an extended period may affect device
5.2
reliability. All inputs and outputs are protected against
high electrostatic voltages or electric fields. However,
precautions to minimize the build-up of electrostatic
charges during handling are recommended. Reliability of
operation is enhanced if unused inputs are connected to
an appropriate logic voltage level (e.g. VDD).
DC Operating Characteristics
VSS = 0 V, Tamb = –40 to 85°C unless otherwise specified.
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Parameters
Test Conditions / Pins
Symbol
Min.
VDD
VPOR
Typ.
Max.
Unit
6.5
V
150
220
600
350
µA
µA
µA
30
50
150
100
µA
µA
µA
Power supply
Operating voltage at VDD
Active current
CPU active
fSYSCL = 1 MHz
VDD = 1.8 V
VDD = 3.0 V
VDD = 6.5 V
IDD
Power down current
(CPU sleep,
RC oscillator active,
4-MHz quartz-osc. active)
fSYSCL = 1 MHz
VDD = 1.8 V
VDD = 3.0 V
VDD = 6.5 V
Sleep current
(CPU sleep,
VDD = 1.8 V
VDD = 3.0 V
VDD = 6.5 V
ISleep
ISleep
32-kHz quartz-osc. inactive
4-MHz quartz-osc. inactive)
VDD = 1.8 V for M44C090
VDD = 3.0 V for M44C090
VDD = 6.5 V for M44C090
VDD = 6.5 V for M44C890
Pin capacitance
Any pin to VSS
32-kHz quartz-osc. active
4-MHz quartz-osc. inactive)
Sleep current
(CPU sleep,
54 (63)
IPD
CL
0.4
0.6
0.8
1.3
1.8
µA
µA
µA
0.1
0.3
0.5
0.6
0.5
0.8
1.0
µA
µA
µA
µA
7
10
pF
Rev.A4, 14-Dec-01
M44C090
M44C890
VSS = 0 V, Tamb = –40 to +85°C unless otherwise specified.
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Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Power-on reset threshold voltage
POR threshold voltage
BOT = 1
VPOR
1.6
1.7
1.8
V
POR threshold voltage
BOT = 0
VPOR
1.75
1.9
2.05
V
POR hysteresis
VPOR
50
VMThh
3.0
mV
Voltage monitor threshold voltage
VM high threshold voltage
VDD > VM, VMS = 1
VM high threshold voltage
VDD < VM, VMS = 0
VMThh
VM middle thresh. voltage
VDD > VM, VMS = 1
VMThm
VM middle thresh. voltage
VDD < VM, VMS = 0
VMThm
VM low threshold voltage
VDD > VM, VMS = 1
VMThl
VM low threshold voltage
VDD < VM, VMS = 0
VMThl
VMI
VMI > VBG, VMS = 1
VVMI
VMI
VMI < VBG, VMS = 0
VVMI
2.8
3.0
2.6
2.4
V
V
2.8
2.6
2.2
2.0
3.25
V
V
2.4
2.2
V
V
External input voltage
1.3
1.2
1.4
1.3
V
V
All Bidirectional Ports
VSS = 0 V, Tamb = –40 to 85°C unless otherwise specified.
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Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
Input voltage LOW
VDD = 1.8 to 6.5 V
VIL
VSS
0.2*VDD
V
Input voltage HIGH
VDD = 1.8 to 6.5 V
VIH
0.8* VDD
VDD
V
Input LOW current
(switched pull-up)
VDD = 2.0 V,
VDD = 3.0 V, VIL= VSS
VDD = 6.5 V
IIL
–2
–10
–50
–4
–20
–100
–12
–40
–200
µA
µA
µA
Input HIGH current
(switched pull-down)
VDD = 2.0 V,
VDD = 3.0 V, VIH = VDD
VDD = 6.5 V
IIH
2
10
50
4
20
100
12
40
200
µA
µA
µA
Input LOW current
(static pull-up)
VDD = 2.0 V,
VDD = 3.0 V, VIL= VSS
VDD = 6.5 V
IIL
–20
–80
–300
–50
–160
–600
–100
–320
–1200
µA
µA
µA
Input LOW current
(static pull-down)
VDD = 2.0 V,
VDD = 3.0 V, VIH= VDD
VDD = 6.5 V
IIH
20
80
300
50
160
600
100
320
1200
µA
µA
µA
Input leakage current
VIL= VSS
IIL
100
nA
Input leakage current
VIH= VDD
IIH
100
nA
Output LOW current
VOL = 0.2 VDD
VDD = 2.0 V
VDD = 3.0 V,
VDD = 6.5 V
Output HIGH current
VOH = 0.8 VDD
VDD = 2.0 V
VDD = 3.0 V,
VDD = 6.5 V
IOL
0.6
3
8
1.2
5.0
15
2.5
8
22
mA
mA
mA
IOH
–0.6
–3
–8
–1.2
–5
–16
–2.5
–8
–24
mA
mA
mA
Note: The Pin BP20/NTE has a static pull-up resistor during the reset-phase of the microcontroller
Rev.A4, 14-Dec-01
55 (63)
M44C090
M44C890
5.3
AC Characteristics
Operation Cycle Time
VSS = 0 V
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Parameters
System clock cycle
Test Conditions / Pins
Symbol
Min.
VDD = 1.8 to 6.5 V
Tamb = –40 to 85°C
tSYSCL
VDD = 2.4 to 6.5 V
Tamb = –40 to 85°C
tSYSCL
Typ.
Max.
Unit
500
2000
ns
250
2000
ns
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = 25°C unless otherwise specified.
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ÁÁÁÁ
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Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
5
MHz
Timer 2 input timing Pin T2I
Timer 2 input clock
fT2I
Timer 2 input LOW time
Rise / fall time < 10 ns
tT2IL
100
ns
Timer 2 input HIGH time
Rise / fall time < 10 ns
tT2IH
100
ns
Interrupt request input timing
Int. request LOW time
Rise / fall time < 10 ns
tIRL
100
ns
Int. request HIGH time
Rise / fall time < 10 ns
tIRH
100
ns
EXSCL at OSC1 input
EMC = EN
Rise / fall time < 10 ns
fEXSCL
0.5
4
MHz
EXSCL at OSC1 input
EMC = DI
Rise / fall time < 10 ns
fEXSCL
0.02
4
MHz
Input HIGH time
Rise / fall time < 10 ns
tIH
0.1
External system clock
µs
Reset timing
Power-on reset time
VDD u VPOR
tPOR
1.5
fRcOut1
3.8
5
ms
RC oscillator 1
Frequency
Stability
VDD = 2.0 to 6.5 V
Tamb = –40 to 85°C
∆f/f
MHz
"50
%
RC oscillator 2 – external resistor
Frequency
Rext = 170 kΩ
Stability
VDD = 2.0 to 6.5 V
Tamb = –40 to 85°C
Stabilization time
fRcOut2
4
MHz
∆f/f
"15
%
tS
10
µs
4-MHz crystal oscillator (operating range 2.2 V to 6.5 V)
Frequency
fX
Start-up time
tSQ
Stability
∆f/f
56 (63)
4
MHz
5
–10
ms
10
ppm
Rev.A4, 14-Dec-01
M44C090
M44C890
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
32-kHz crystal oscillator (operating range 2.0 V to 6.5 V)
Frequency
fX
32.768
kHz
Start-up time
tSQ
0.5
s
Stability
∆f/f
–10
10
ppm
External 32-kHz crystal parameters
Crystal frequency
fX
32.768
kHz
Serial resistance
RS
30
Static capacitance
C0
1.5
pF
Dynamic capacitance
C1
3
fF
Crystal frequency
fX
4.0
MHz
Serial resistance
RS
40
150
Ω
Static capacitance
C0
1.4
3
pF
Dynamic capacitance
C1
3
fF
Frequency
fX
4.0
MHz
Serial resistance
RS
8
20
Ω
Static capacitance
C0
36
45
pF
Dynamic capacitance
C1
4.4
50
kΩ
External 4-MHz crystal parameters
External 4-MHz ceramic resonator parameters
fF
Crystal Characteristics
L
Equivalent
circuit
OSCIN
SCLIN
OSCOUT
SCLOUT
C1
RS
C0
96 11553
Figure 62. Crystal equivalent circuit
Supply voltage VDD = 1.8 to 6.5 V, VSS = 0 V, Tamb = 25°C unless otherwise specified.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
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ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
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ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
Parameters
Test Conditions / Pins
Symbol
Min.
Typ.
Max.
Unit
600
1300
µA
EEPROM
Operating current during
erase/write cycle
Endurance
IWR
Erase- / write-cycles
Data erase/write cycle time for 16-bit access
ED
500,000
tDEW
1,000,000
9
Cycles
12
10
ms
Data retension time
tDR
years
Power-up to read operation
tPUR
0.2
ms
Power-up to write operation
tPUW
0.2
ms
500
kHz
Serial interface
SCL clock frequency
Rev.A4, 14-Dec-01
fSC_MCL
100
57 (63)
M44C090
M44C890
1100
1000
Tamb = 25C
400
fSYSCLK = 500 kHz
VDD = 6.5 V
350
900
700
600
4V
500
3V
400
2V
300
Tamb = 25C
300
5V
IDDact ( mA )
IDDact ( µA )
800
250
200
150
100
200
50
100
0
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
fSYSCLK ( MHz )
VDD ( V )
Figure 63. Active supply current vs. frequency
1100
1000
900
Figure 66. Active supply current vs. VDD
90
Tamb = 25C
Tamb = 25C
80
VDD = 6.5 V
70
5V
800
60
4V
600
500
3V
400
IPD ( µA )
IPD ( µA )
700
2V
300
50
40
30
20
200
10
100
0
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
fSYSCLK ( MHz )
VDD ( V )
Figure 67. Power-down supply current vs. VDD
1.0
1.0
0.9
0.9
0.8
0.8
0.7
0.7
0.6
0.5
0.4
VDD = 6.5 V
0.3
IDDsleep ( µA )
IDDsleep ( µA )
Figure 64. Power-down supply current vs. frequency
0.6
VDD = 6.5 V
0.5
0.4
5V
0.3
5V
0.2
0.1
3V
0.2
3V
0.1
0.0
–40–30–20–10 0 10 20 30 40 50 60 70 80 90
0.0
–40–30–20–10 0 10 20 30 40 50 60 70 80 90
Tamb ( C )
Tamb ( C )
Figure 65. Sleep current vs. Tamb
M44C090
Figure 68. Sleep current vs. Tamb
M44C890
58 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
6.0
6.0
5.5
Tamb = –40C
5.0
fRC_INT ( MHz )
fRC_INT ( MHz )
5.5
4.5
25C
4.0
3.5
85C
3.0
5.0
4.5
4.0
VDD = 6.5 V
3.5
3.0
2V
2.5
2.5
2.0
–40
2.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
–20
Figure 69. Internal RC frequency vs. VDD
M44C090
20
40
60
80
Figure 72. Internal RC frequency vs. Tamb
M44C090
4.6
4.6
Rext = 170 kOhm
Rext = 170 kOhm
4.4
Tamb = –40C
4.2
25C
4.0
85C
3.8
fRC_EXT ( MHz )
4.4
fRC_EXT ( MHz )
0
Tamb ( C )
VDD ( V )
3.6
4.2
VDD = 6.5 V
3V
4.0
2V
3.8
3.6
3.4
3.4
–40–30–20–10 0 10 20 30 40 50 60 70 80 90
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD ( V )
Tamb ( C )
Figure 70. External RC frequency vs. VDD
Figure 73. External RC frequency vs. Tamb
10.00
7.5
SYSCLKmax
Tamb = 25C,
VDD = 3 V
SYSCLKmin
0.10
fRC_EXT ( MHz )
fSYSCLK ( MHz )
6.5
1.00
5.5
4.5
3.5
max.
typ.
2.5
min.
0.01
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
1.5
100
150
200
250
300
350
400
VDD ( V )
Rext ( kOhm )
Figure 71. System clock vs. VDD
Figure 74. External RC frequency vs. Rext
Rev.A4, 14-Dec-01
59 (63)
M44C090
M44C890
1000.00
1000.00
VIH = VDD
VIL = VSS
Tamb = 85C
25C
100.00
–40C
RPD ( kΩ )
RPU ( kΩ )
Tamb = 85C
10.00
25C
100.00
–40C
10.00
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD ( V )
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD ( V )
Figure 75. Pull-up resistor vs. VDD
Figure 78. Pull-down resistor vs. VDD
100.00
100.00
VIH = VDD
RSPD ( kΩ )
RSPU ( kΩ )
VIL = VSS
Tamb = 85C
Tamb = 85C
25C
25C
–40C
–40C
10.00
10.00
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD ( V )
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD ( V )
Figure 76. Strong pull-up resistor vs. VDD
Figure 79. Strong pull-down resistor vs. VDD
30
0
VDD = 2.0 V
Tamb = 25C
–5
3.0 V
20
–15
4.0 V
–20
5.0 V
–25
IOL ( mA )
IOH ( mA )
–10
Tamb = 25C
6.5 V
–40
5.0 V
15
10
–30
–35
VDD = 6.5 V
25
4.0 V
3.0 V
5
2.0 V
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VDD – VOH ( V )
VOL ( V )
Figure 77. Output high current vs. VDD – output high voltage
Figure 80. Output low current vs. output low voltage
60 (63)
Rev.A4, 14-Dec-01
M44C090
M44C890
0
25
–5
20
max.
–10
IOL ( mA )
IOH ( mA )
min.
typ.
–15
max.
15
typ.
10
min.
–20
5
–25
–40–30–20–10 0 10 20 30 40 50 60 70 80 90
0
–40–30–20–10 0 10 20 30 40 50 60 70 80 90
Tamb ( C )
Tamb ( C )
Figure 81. Output high current vs. Tamb = 25C
VDD = 6.5 V, VOH = 0.8 VDD
6
Figure 82. Output low current vs. Tamb
VDD = 6.5 V, VOL = 0.2 VDD
Package Information
Package SSO20
5.7
5.3
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
6.6
6.3
0.65
5.85
20
11
technical drawings
according to DIN
specifications
13007
1
Rev.A4, 14-Dec-01
10
61 (63)
M44C090
M44C890
7
Ordering Information
Please select the option setting from the list below and insert ROM CRC.
Port 2
Port52
BP20 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
BP21 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP22 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP23 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP40 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP41 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
ECM(External clock monitor)
BP42 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP43 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
Port 4
62 (63)
CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP51 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP52 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
BP53 CMOS
Open drain [N] Open drain [P] Switched pull-up
Switched pull-down
Static pull-up
Static pull-down
Clock used
File:____________. HEX
Approval
BP50 Date: ____–____–____
Watchdog
External resistor
External clock
32-kHz crystal
4-MHz crystal
Enable
Disable
Softlock
Hardlock
CRC: _____________ HEX
Signature: _______________
Rev.A4, 14-Dec-01
M44C090
M44C890
Ozone Depleting Substances Policy Statement
It is the policy of Atmel Germany GmbH to
1. Meet all present and future national and international statutory requirements.
2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems
with respect to their impact on the health and safety of our employees and the public, as well as their impact on
the environment.
It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as
ozone depleting substances (ODSs).
The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid
their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these
substances.
Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed
in the following documents.
1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively
2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental
Protection Agency (EPA) in the USA
3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.
Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances
and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice.
Parameters can vary in different applications. All operating parameters must be validated for each customer
application by the customer. Should the buyer use Atmel products for any unintended or unauthorized application,
the buyer shall indemnify Atmel against all claims, costs, damages, and expenses, arising out of, directly or
indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use.
Data sheets can also be retrieved from the Internet:
http://www.atmel–wm.com
1.
Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany
Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423
Rev.A4, 14-Dec-01
63 (63)