CXP88340/88348 CMOS 8-bit Single Chip Microcomputer Description The CXP88340/88348 is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, high precision timing pattern generation circuit, PWM output, VISS/VASS circuit, 32kHz timer/counter, remote control receiving circuit, VSYNC separator and the measurement circuit which measure signals of capstan FG and drum FG/PG and other servo systems, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip. Also, the CXP88340/88348 provides sleep/stop functions which enable to lower power consumption. 100 pin QFP (Plastic) Structure Silicon gate CMOS IC Features • A wide instruction set (213 instructions) which covers various types of data — 16-bit arithmetic/multiplication and division/boolean bit operation instructions • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation • Incorporated ROM capacity 40K bytes (CXP88340) 48K bytes (CXP88348) • Incorporated RAM capacity 1376 bytes • Peripheral functions — A/D converter 8 bits, 12 channels, successive approximation system (Conversion time of 20µs/16MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channnel Incorporated two-wire 8-bit and 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel — Timer 8-bit timer/counter, 2 channels 19-bit time-base timer 32kHz timer/counter — High precision timing pattern generation PPG: Maximum of 19 pins 32 stages programmable circuit RTG: 5 pins, 1 channel 7-bit, 10-satge FIFO (RECCTL control/ATC control), 1 channel — PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency 62.5kHz at 16MHz) DA gate pulse output: 13 bits, 2 channels — Analog signal input circuit PBCTL amplifier circuit Reel FG comparator — CTL write/rewrite circuit Recording current control circuit — Servo input control Capstan FG, Drum FG/PG, CTL, Reel FG input — VSYNC separator — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — VISS/VASS circuit Pulse duty auto detection circuit — Remote control receiving circuit 8-bit pulse measurement counter, 6-stage FIFO — Tri-state output PPG output 2 pins — High speed head switching circuit • Interruption 22 factors, 15 vectors, multi-interruption possible • Standby mode Sleep/stop • Package 100-pin plastic QFP • Piggy/evaluation chip CXP88400 100-pin ceramic PQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98835-PS AVDD SERIAL INTERFACE UNIT (CH0) CS0 SI0 SO0 SCK0 SO1 ADJ CTLHEAD HEADL PWM1 DAA1 DAA0 PWM0 PWM RMC EXI0 EXI1 CFG DFG DPG CTLFAMPI RFG0 RFG1 SYNC TO/DDO EC SCK1 FIFO RAM FIFO CTL R/W CONTROL 12-BIT PWM GENERATOR CH1 12-BIT PWM GENERATOR CH0 14-BIT PWM GENERATOR VISS/VASS FIFO SERVO INPUT CONTROL REMOCON INPUT PBCTL AMP REEL COMPARATOR DRUM CAPSTAIN V SYNC SEPARATOR 8-BIT TIMER1 8-BIT TIMER/COUNTER 0 SERIAL INTERFACE UNIT (CH1) SERIAL INTERFACE UNIT (CH2) SI1 AVss A/D CONVERTER AVREF SCL0 SCL1 SDA0 SDA1 12 5 4 2 5 2 2 2 2 INT0 NMI INT2 INT1/NMI 2 VDD Vss XTAL TEX TX RST MP CH0 FIFO CH1 REALTIME PULSE GENERATOR 32kHz TIMER/COUNTER PRESCALER/ TIME-BASE TIMER RAM 1376 BYTES CLOCK GENERATOR/ SYSTEM CONTROL 5 FIFO ROM 40K/48K BYTES SPC700 CPU CORE AA 19 RAM FRC CAPTURE UNIT PROGRAMABLE PATTERN GENERATOR INTERRUPT CONTROLLER PPO0 to PPO18 AN0 to AN11 EXTAL RTO3 to RTO7 PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H –2– PORT I Block Diagram PH4 to PH7 4 PI0 to PI7 PH0 to PH3 4 8 PG0 to PG3 4 PF4 to PF7 PF0 to PF3 4 4 PE0, 1, 6, 7 PD0 to PD7 8 PE2 to PE5 PC0 to PC7 8 6 PB0 to PB7 8 2 PA0 to PA7 8 CXP88340/88348 CXP88340/88348 PE4/EXI0 PE3/SYNC PE2/SI1 PE1/SO1 PE0/SCK1 TEX TX VSS VDD NC PA7/PPO7 PA6/PPO6 PA5/PPO5 PA4/PPO4 PA3/PPO3 PA2/PPO2 PA1/PPO1 PA0/PPO0 PB7/PPO15 PB6/PPO14 Pin Assignment (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 1 80 PE5/EXI1 PB4/PPO12 2 79 PE6/PWM0/DAA0 PB3/PPO11 3 78 PE7/PWM1/DAA1 PB2/PPO10 4 77 RFG0 PB1/PPO9 5 76 RFG1 PB0/PPO8 6 75 ANOUT PC7/RTO7 7 74 AMPVDD PC6/RTO6 8 73 CTLFAMPO PC5/RTO5 9 72 CTLSAMPI PC4/RTO4 10 71 CTLAGND PC3/RTO3 11 70 CTLFAMPI (–) PC2/PPO18 12 69 CTLFAMPI (+) PC1/PPO17 13 68 HEADL (–) PC0/PPO16 14 67 HEADL (+) PI7 15 66 CTLHEAD (+) PI6 16 65 CTLHEAD (–) PI5 17 64 AMPVSS PI4 18 63 VDD PI3 19 62 AN0 PI2 20 61 AN1 AN2 PI1 21 60 PI0/INT0 22 59 AN3 PD7/SI0 23 58 PF0/AN4 PF1/AN5 PD6/SO0 24 57 PD5/SCK0 25 56 PF2/AN6 PD4/CS0 26 55 PF3/AN7 PD3/SRVO/TO/DDO/ADJ 27 54 AVDD PD2/PWM 28 53 AVREF PD1/RMC 29 52 AVSS PD0/INT1/NMI 30 51 PF4/AN8 Note) 1. NC (Pin 90) is always connected to VDD. 2. VDD (Pins 63 and 89) are both connected to VDD 3. Vss (Pins 41 and 88) are both connected to GND. 4. MP (Pin 39) is always connected to GND. –3– PF5/AN9 PF6/AN10 PF7/AN11 PG0/CFG PG1/DFG PG2/DPG PG3/EC/INT2 EXTAL VSS XTAL RST MP PH0/SCL0 PH1/SCL1 PH3/SDA1 PH2/SDA0 PH4 PH5 PH6 PH7 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CXP88340/88348 Pin Description Symbol PA0/PPO0 to PA7/PPO7 I/O Output/ Real-time output PB0/PPO8 to PB7/PPO15 Output/ Real-time output PC0/PPO16 to PC2/PPO18 I/O/ Real-time output Description (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) Head switching output. Programmable pattern generator (PPG) output. Functions as high precision realtime pulse output port. (19 pins) PB0 and PB2 can be tri-state controlled with PPG. Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. PC3 can be tri-state controlled with RTG. (5 pins) PC3/RTO3 to PC7/RTO7 I/O/ Real-time output PD0/INT1/ NMI I/O/Input/Input Input pin to request external interruption and non-maskable interruption. PD1/RMC I/O/Input Remote control receiving circuit input pin. PD2/PWM I/O/Output 14-bit PWM output pin. PD3/TO DDO/ADJ SRVO Timer/counter, CTL duty detector, 32kHz oscillation adjustment and servo amplifier output pin. PD4/CS0 I/O/Output/Output/ (Port D) Output/Output 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) I/O/Input PD5/SCK0 I/O/I/O Serial clock (CH0) I/O pin. PD6/SO0 I/O/Output Serial data (CH0) output pin. PD7/SI0 I/O/Input Serial data (CH0) input pin. PE0/SCK1 Output/I/O Serial clock (CH1) I/O pin. PE1/SO1 Output/Output Serial data (CH1) output pin. PE2/SI1 Input/Input PE3/SYNC Input/Input PE4/EXI0 Input/Input PE5/EXI1 Input/Input PE6/PWM0/ DAA0 Output/Output PE7/PWM1/ DAA1 Output/Output Serial chip select (CH0) input pin. Serial data (CH1) input pin. (Port E) 8-bit port. Bits 2, 3, 4 and 5 Composite sync signal input pin. are for inputs; bits 0, 1, 6 and 7 are for outputs. External input pin for FRC capture unit. (8 pins) (2 pins) PWM output pin. (2 pins) –4– DA gate pulse output pin. (2 pins) CXP88340/88348 Description Description I/O AN0 to AN3 Input PF0/AN4 to PF3/AN7 Input/Input PF4/AN8 to PF7/AN11 Output/Input (Port F) Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits also serve as standby release input pins. (8 pins) Capstan FG input pin. PG0/CFG PG1/DFG Input/Input Input/Input/Input PH0/SCL0 PH1/SCL1 PH2/SDA0 PH3/SDA1 Drum FG input pin. (Port G) 4-bit input port. (4 pins) PG2/DPG PG3/EC/ INT2 Analog input pin to A/D converter. (12 pins) I/O/I/O Drum PG input pin. Input pin to request External event input external interruption. pin for Active when falling timer/counter. edge. (Port H) Serial clock (CH2) I/O pin. 8-bit I/O port. Upper four bits are for outputs. I/O can be set in a unit of Serial data (CH2) I/O pin. single bits for lower four bits. Lower four bits are N-ch open drain outputs and which can drive 12mA sink current. Upper four bits are for outputs; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) PH4 to PH7 Output PI0/INT0 I/O/Input PI1 to PI7 I/O RFG0, RFG1 Input Input ports. (2 pins) Reel FG input pin. ANOUT Output Output port. (1 pin) Internal waveform output pin of analog circuit. CTLFAMPO Output Output port. (1 pin) PBCTL signal 1st amplifier output pin. CTLSAMPI Input Input port. (1 pin) PBCTL signal 2nd amplifier input pin. CTLAGND Output Output port. (1 pin) Smoothing capacitor connecting pin. CTLFAMPI (–) CTLFAMPI (+) Input Input ports. (2 pins) Input PBCTL signal with capacitor coupled. HEADL (–) HEADL (+) Output Output ports. (2 pins) During playback, connect to CTLHEAD (–) and CTLHEAD (+) with internal switch. CTLHEAD (–) CTLHEAD (+) I/O I/O ports. (2 pins) During playback, input pin of PBCTL signal; during recording, output pin of PBCTL signal. Input pin to request external interruption. (Port I) Active when falling edge. 8-bit I/O port. I/O can be set in a unit of single bits. Function as standby release input can be set in a unit of single bits. (8 pins) AMPVSS Analog signal input circuit GND pin. AMPVDD Analog signal input circuit power supply pin. –5– CXP88340/88348 Symbol I/O Description EXTAL Input XTAL Output TEX Input TX Output Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (In this time, feedback resistor is not removed.) RST Input System reset pin; active at low level. NC pin. Connect this pin to VDD for normal operation. NC MP Input Test mode input pin. Always connect to GND. Positive power supply pin of A/D converter. AVDD AVREF Connecting pin of crystal oscillator for system clock. When supplying the external clock, input it to EXTAL pin and input the opposite phase clock to XTAL pin. Input Reference voltage input pin of A/D converter. AVSS GND pin of A/D converter. VDD Positive power supply pin. VSS GND pin. Connect both Vss pins to GND. –6– CXP88340/88348 Input/Output Circuit Formats for Pins Pin Circuit format Port A PA0/PPO0 to PA7/PPO7 AAAAA AAAAA PPO data Port B Ports A and B data PB4/PPO12 to PB7/PPO15 AA AA After a reset Hi-Z Internal data bus RD (Port A or Port B) Output becomes active from high impedance by data writing to port data register. 12 pins Port B PB0/PPO8 PB2/PPO10 AA AA AAAA AAAA PPO8, PPO10 data PB0, PB2 data Hi-Z Internal data bus RD (Port B) 2 pins AAAA AAAA AAAA AAAA AAAA PPO9, PPO11 data Output becomes active from high impedance by data writing to port data register. PPG control/status register bit 0 Tri-state control selection AA AA "0" after a reset PB1/PPO9 PB3/PPO11 PPO9, PPO11 data PB1, PB3 data Internal data bus RD (Port B) 2 pins –7– Output becomes active from high impedance by data writing to port data register. Hi-Z CXP88340/88348 Circuit format Pin A A Port C AAAA AAAA AAAA PPO, RTO data PC0/PPO16 to PC2/PPO18 PC5/RTO5 to PC7/RTO7 A A Port C data After a reset Input protection circuit Port C direction Hi-Z IP "0" after a reset Internal data bus RD (Port C) Internal data bus 6 pins RD (Port C direction) Port C AAAA AAAA AAAA RTO3 data PC3 data PC3 direction "0" after a reset PC3/RTO3 Internal data bus RD (Port C) AA AA A A IP Hi-Z Internal data bus AAAA AAAA AAAA AAAA AAAA AAAA RD (Port C direction) RTO4 data 1 pin RTG interruption control register bit 7 Tri-state control selection "0" after a reset RTO4 data PC4 data PC4/RTO4 PC4 direction "0" after a reset Internal data bus RD (Port C) Internal data bus 1 pin RD (Port C direction) –8– AA AA A IP Hi-Z CXP88340/88348 AAAA AAAA AAAA AAAA Pin After a reset Circuit format Port D AA AA A A Port D data PD0/INT1/NMI PD1/RMC PD4/CS0 PD7/SI0 Port D direction "0" after a reset IP Internal data bus RD (Port D) Hi-Z Schmitt input Internal data bus RD (Port D direction) 4 pins PD1: Remote control circuit PD0: Interruption circuit PD4, PD7: Serial CH0 Port D AAA AAA AAA AAA AAAA AAA AAAAAAA Port D function select "0" after a reset PD2: PD3: PD2/PWM PD3/SRVO/ TO/DDO/ ADJ 14-bit PWM Timer/counter, CTL duty detection circuit, 32kHz timer, amplifier circuit MPX Port D data Port D direction "0" after a reset Internal data bus RD (Port D) AA AA AA AA Hi-Z IP Internal data bus 2 pins RD (Port D direction) AAAA AAAAAA AA AAAA AA AAA AAAA AA AAA AAAA AAA AAA Port D Port D function select "0" after a reset SIO CH0 MPX PD5/SCK0 PD6/SO0 Port D data Port D direction MPX Note) PD5 is schmitt input PD6 is inverter input "0" after a reset Internal data bus RD (Port D) 2 pins A A AA AA SIO CH0 –9– IP Hi-Z CXP88340/88348 Pin AAAA AAAA AAAA AAAA After a reset Circuit format Port E Port/SCK output select "1" after a reset SIO CH1 PE0/SCK1 Port E data Internal data bus AA AA AA AA MPX Hi-Z control SIO CH1 1 pin RD (Port E) Port E AAAA AAAA AAAA AAAA Port E function select "1" after a reset SIO CH1 PE1/SO1 Port E data Internal data bus AA AA AA AA AA AA A A IP AA AA MPX Hi-Z Hi-Z Hi-Z control RD (Port E) 1 pin Port E AAAA Schmitt input PE2/SI1 PE3/SYNC PE4/EXI0 PE5/EXI1 PE2: SIO CH1 PE3 PE4 : Servo input PE5 IP Hi-Z Internal data bus RD (Port E) 4 pins Note) For PE3/SYNC, CMOS schmitt input or TTL schmitt input can be selected with the mask option. Port E AAAA AAAA AAAA AAAA Port/DA/PWM select PE6/PWM0/ DAA0 PE7/PWM1/ DAA1 "1" after a reset DA gate output or PWM output Port E data Internal data bus 2 pins AA AA AA AA MPX Hi-Z control RD (Port E) – 10 – AA AA High level CXP88340/88348 Pin AN0 to AN3 4 pins After a reset Circuit format AA AA AAAA AA AA AAAA Input multiplexer Hi-Z A/D converter IP Port F PF0/AN4 to PF3/AN7 Input multiplexer A/D converter IP 4 pins Hi-Z Internal data bus RD (Port F) Port F PF4/AN8 to PF7/AN11 AAAA AA AA AAAA AA AA AAAA Port F data Internal data bus Hi-Z IP RD (Port F) Port/AD select 4 pins Input multiplexer "1" after a reset A/D converter Port G PG0/CFG PG1/DFG PG2/DPG Power ON/OFF control AAAA Schmitt input Servo input IP Hi-Z Internal data bus RD (Port G) Schmitt width selection 3 pins Port G AAAA Schmitt input PG3/EC/INT2 IP Hi-Z Internal data bus RD (Port G) 1 pin – 11 – CXP88340/88348 Pin Circuit format Port H AAAA AAAA AAAA SCL, SDA I2C output enable Port H data PH0/SCL0 PH1/SCL1 PH2/SDA0 PH3/SDA1 Port H direction AA AA A A After a reset IP "0" after a reset Schmitt input Internal data bus Hi-Z RD (Port H) Internal data bus SCL, SDA (Serial interface (CH2) circuit) RD (Port H direction) 4 pins Port H AAAA AAAA ∗ Port H data PH4 to PH7 Other serial interface (CH2) pin AA AA Hi-Z Internal data bus ∗ 12V drive voltage, large current 12mA RD (Port H) 4 pins Port I AAA AAA AAA AAA Pull-up resistor ∗ AA AAAA AA "0" after a reset PI0 data PI0 direction IP "0" after a reset Internal data bus PI0/INT0 RD (Port I) Hi-Z Internal data bus RD (Port I direction) Internal data bus RD (pull-up resistor) Standby release Interruption circuit 1 pin AA AA Edge detection ∗ Pull-up transistors approx. 100kΩ – 12 – CXP88340/88348 Pin After a reset Circuit format Port I AAA AAA AAA AAA Pull-up resistor ∗ AA AA AA AA "0" after a reset Port I data Port I direction IP "0" after a reset Internal data bus PI1 to PI7 RD (Port I) Hi-Z Internal data bus RD (Port I direction) Internal data bus AA AA A RD (pull-up resistor) Standby release ∗ Pull-up transistors approx. 100kΩ 7 pins CTLFAMPI (+) CTLFAMPI (–) CTLFAMPO Edge detection AAAA AA A AAA AAA A AAAAA A AA AAAAA AAAA AAAA AA AA AAAA AA AA CTLAGND CTLFAMPI (+) IP IP 1/2AMPVDD CTLFAMPO CTLFAMPI (–) 3 pins Input pin charge control Input pin charge control CTLSAMPI IP LPF circuit CTLAGND 1 pin – 13 – 1/2AMPVDD CXP88340/88348 Pin After a reset Circuit format AA AA AA AA AMPVDD CTLAGND 1/2AMPVDD IP 1 pin CTL AMP AMPVSS AMPVDD AA AAAA AA AA AA Write current select Recording current control circuit RTO6 CTLHEAD (+) IP RTO7 Hi-Z HEADL (+) pin RTO3 AMPVSS 1 pin RTG control permission AMPVDD AA AAAA AA AA AA Write current select Recording current control circuit RTO7 CTLHEAD (–) IP RTO6 Hi-Z HEADL (–) pin RTO3 AMPVSS 1 pin HEADL (+) RTG control permission CTLHEAD (+) pin RTO3 AAA IP Hi-Z RTG control permission 1 pin HEADL (–) AMPVSS CTLHEAD (–) pin RTO3 AAA IP RTG control permission 1 pin AMPVSS – 14 – Hi-Z CXP88340/88348 Pin RFG0 RFG1 After a reset Circuit format A AA AA AA AA AA AA AA AA AA AA AA AA AA AA Comparator Servo output IP 2 pins EXTAL XTAL EXTAL 2 pins XTAL TEX TX 2 pins RST 1 pin TEX • Shows the circuit composition during oscillation. IP • Feedback resistor is removed and XTAL outputs High level during stop. 32kHz timer/counter IP AA AA Pull-up resistor AA Schmitt input OP IP – 15 – Oscillation • Shows the circuit composition during oscillation. • Feedback resistor is removed during 32kHz oscillation circuit stop by software. At that time, TEX outputs Low level and TX outputs High level. TX Mask option Hi-Z Oscillation Low level (during a reset) CXP88340/88348 Absolute Maximum Ratings Item (Vss = 0V reference) Symbol Rating Unit V AVDD –0.3 to +7.0 AVss to +7.0∗1 AVSS –0.3 to +0.3 V VDD Supply voltage AMPVDD AMPVSS to +7.0∗2 Remarks V V V Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗3 Output voltage VOUT –0.3 to +7.0∗3 V Medium drive output voltage VOUTP –0.3 to +15.0 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total of output pins IOL 15 mA Other than large current output ports (value per pin) IOLC 20 mA Large current output port∗4 (value per pin) Low level total output current ∑IOL 130 mA Total of output pins Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 600 mW AMPVSS V Low level output current ∗1 ∗2 ∗3 ∗4 Port H (PH7 to PH4) pin QFP package type AVDD should not exceed VDD + 0.3V. AMPVDD should not exceed VDD + 0.3V. VIN and VOUT should not exceed VDD + 0.3V. The large current output port is port H (PH7 to PH4). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. – 16 – CXP88340/88348 Recommended Operating Conditions Item Supply voltage Analog supply voltage High level input voltage Symbol Min. Max. 4.5 5.5 Guaranteed operation range for 1/2 and 1/4 frequency dividing clock 3.5 5.5 Guaranteed operation range for 1/16 frequency dividing clock or during sleep mode 2.7 5.5 2.5 5.5 AVDD 4.5 5.5 V Guaranteed data hold operation range during stop ∗1 AMPVDD 4.5 5.5 V ∗2 VIH 0.7VDD VDD V ∗3 VIHS 0.8VDD VDD V VIHTS 2.2 VDD V CMOS schmitt input∗4 TTL schmitt input∗5 V EXTAL pin∗6 TEX pin∗7 ∗3 VDD VIHEX Low level input voltage Operating temperature (Vss = 0V reference) VDD – 0.4 VDD + 0.3 Unit V Remarks Guaranteed operation range by TEX clock VIL 0 0.3VDD V VILS 0 0.2VDD V VILTS 0 0.8 V CMOS schmitt input∗4 TTL schmitt input∗5 VILEX –0.3 0.4 V EXTAL pin∗6 TEX pin∗7 Topr –20 +75 °C ∗1 ∗2 ∗3 ∗4 AVDD and VDD should be set to the same voltage. AMPVDD and VDD should be set to the same voltage. Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PI1 to PI7 and PH0 to PH3), MP pin Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE0/SCK1, PE2/SI1, PE3/SYNC, PE4/EXI0, PE5/EXI1, PI0/INT0, PG3/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is selected with mask option.) ∗5 PE3/SYNC (when TTL schmitt input is selected with mask option.) ∗6 Specifies only during external clock input. ∗7 Specifies only during external event input. – 17 – CXP88340/88348 Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Low level output voltage Symbol VOH VOL IIHE Pins IIHT Conditions 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V 0.4 V VDD = 4.5V, IOL = 3.6mA 0.6 V PH VDD = 4.5V, IOL = 12.0mA 1.5 V EXTAL TEX VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA VDD = 5.5V, VIH = 5.5V 0.1 10 µA VDD = 5.5V, VIL = 0.4V –0.1 –10 µA –1.5 –400 µA ±10 µA RST∗1 I/O leakage current IIZ PA to PF, PG3, PI, MP, VDD = 5.5V, AN0 to AN3, VI = 0, 5.5V RST∗1 Open drain output leakage current (N-CH Tr off state) ILOH PH4 to PH7 VDD = 5.5V, VOH = 12V 50 µA PH0 to PH3 VDD = 5.5V, VOH = 5.5V 10 µA 37 50 mA 2.1 8 mA 58 100 µA 9 35 µA 10 µA 16MHz crystal oscillation (C1 = C2 = 15pF) IDD1 VDD = 5.5V∗3 Sleep mode IDDS1 VDD = 5.5V IDDS2 32kHz crystal oscillation (C1 = C2 = 47pF) VDD, VSS VDD = 3.3V Sleep mode VDD = 3V ± 0.3V IDDS3 Max. Unit VDD = 4.5V, IOH = –0.5mA IILR IDD2 Typ. VDD = 4.5V, IOL = 1.8mA IILT Supply current∗2 Min. PA to PD, PE0 to PE1, PE6 to PE7, PF4 to PF7, PH (VOL only) PI IILE Input current (Ta = –20 to +75°C, Vss = 0V reference) Stop mode (EXTAL and TEX pins oscillation stop) VDD = 5V ± 0.5V – 18 – CXP88340/88348 Item Input capacity Symbol CIN Pins Conditions PC, PD, PE0, PE2 to PE5, PF, PG, PI, CTLHEAD (+), CTLHEAD (–), Clock 1MHz CTLFAMPI (+), 0V other than the measured pins CTLFAMPI (–), CTLSAMPI, RFG, XTAL, TEX Min. Typ. 10 Max. Unit 20 pF ∗1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when no resistor is selected. ∗2 When entire output pins are left open. ∗3 When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEh) to "00" and operating in high speed mode (1/2 frequency dividing clock). – 19 – CXP88340/88348 AC Characteristics (1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Min. Conditions System clock frequency fC XTAL EXTAL Fig. 1, Fig. 2 1 System clock input pulse width tXL, tXH XTAL EXTAL Fig. 1, Fig. 2 External clock drive 28 XTAL EXTAL Fig. 1, Fig. 2 External clock drive EC Fig. 3 Event count clock input rise and fall times tCR, tCF tEH, tEL tER, tEF EC Fig. 3 System clock frequency fC TEX TX VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Event count clock input pulse width tTL, tTH tTR, tTF TEX Fig. 3 TEX Fig. 3 System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times ∗1 Typ. Max. Unit 16 MHz ns 200 tsys + 200∗1 ns ns 20 ms kHz 32.768 µs 10 20 ms tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") 1/fc VDD – 0.4V EXTAL XTAL 0.4V tCF tXH tXL tCR Fig. 1. Clock timing AAAA AAAA AAAA AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL C1 XTAL External clock EXTAL C2 32kHz clock applied condition Crystal oscillation TEX XTAL 74HC04 TX C1 C2 Fig. 2. Clock applied condition 0.8VDD TEX EC 0.2VDD tEH tEF tEL tER tTH tTF tTL tTR Fig. 3. Event count clock timing – 20 – CXP88340/88348 (2) Serial transfer (CH0) Item (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Symbol Pins Conditions Min. Max. Unit CS0 ↓ → SCK0 delay time tDCSK SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↑ → SCK0 floating delay time tDCSKF SCK0 Chip select transfer mode (SCK0 = output mode) tsys + 200 ns CS0 ↓ → SO0 delay time tDCSO SO0 Chip select transfer mode tsys + 200 ns CS0 ↑ → SO0 floating delay time tDCSOF SO0 Chip select transfer mode tsys + 200 ns CS0 high level width tWHCS CS0 Chip select transfer mode tsys + 200 ns SCK0 cycle time tKCY Input mode 2tsys + 200 ns SCK0 16000/fc ns SCK0 high and low level widths tKH tKL Input mode tsys + 100 ns SCK0 Output mode 8000/fc – 100 ns SI0 input set-up time (against SCK0 ↑) tSIK SCK0 input mode –tsys + 100 ns SI0 200 ns SI0 input hold time (against SCK0 ↑) tKSI 2tsys + 100 ns SI0 100 ns SCK0 ↓ → SO0 delay time tKSO SO0 Output mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode 2tsys + 100 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. – 21 – CXP88340/88348 tWHCS 0.8VDD CS0 0.2VDD tKCY tDCSK tKL tDCSKF tKH 0.8VDD 0.8VDD SCK0 0.2VDD tSIK tKSI 0.8VDD SI0 Input data 0.2VDD tDCSO tKSO tDCSOF 0.8VDD SO0 Output data 0.2VDD Fig. 4. Serial transfer timing (CH0) – 22 – CXP88340/88348 Serial transfer (CH1) (SIO mode) Item Symbol (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Pins Conditions Min. tKCY SCK1 SCK1 high and low level widths tKH tKL SCK1 SI1 input setup time (for SCK1 ↑) tSIK SI1 SI1 input hold time (for SCK1 ↑) tKSI SI1 SCK1 ↓ → SO1 delay time tKSO SO1 Unit 2tsys + 200 ns Output mode 16000/fc ns Input mode tsys +100 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns tsys + 200 ns 100 ns Input mode SCK1 cycle time Max. Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode tsys + 200 ns 100 ns Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”) Note 2) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. tKCY tKL tKH SCK1 0.8VDD 0.2VDD tSIK tKSI 0.8VDD SI1 Input data 0.2VDD tKSO 0.8VDD Output data SO1 0.2VDD Fig. 5. Serial transfer CH1 timing (SIO mode) – 23 – CXP88340/88348 Serial transfer (CH1) (Special mode) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. ∗1 Typ. Max. Unit SO1 cycle time tLCY SO1 SI1 SI1 data setup time tLSU tLHD SI1 2 µs SI1 2 µs SI1 data hold time ∗1 104 µs tLCY is specified only when serial mode register (CH1) (SIOM1: 05F2h) lower 2 bits (SO1 clock selection) are set at 104µs. Note) The load of SO1 pin is 50pF + 1TTL. tLCY SO1 tLCY Start bit 0.5VDD Output data bit tLCY/2 tLSU tLHD Input data bit SI1 0.8VDD 0.2VDD Fig. 6. Serial transfer CH1 timing (Special mode) – 24 – CXP88340/88348 Serial transfer (CH2) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions Min. Max. Unit 400 kHz SCL clock frequency fSLC SCL Bus-free time before starting transfer tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SDA, SCL 2.6 µs SDA, SCL 1.0 µs SCL 1.0 µs SCL 1.0 µs SDA, SCL µs SDA, SCL 1.0 0∗1 SDA, SCL 100 ns Hold time for starting transfer Clock low level width Clock high level width Setup time for repeated transfers Data hold time Data set-up time SDA, SCL rise time SDA, SCL fall time Setup time for transfer completion µs SDA, SCL 300 ns SDA, SCL 300 ns SDA, SCL 1.6 µs ∗1 The SCL fall time (300ns Max.) is not included in the data hold time. SDA tBUF tR tF tHD; STA SCL tHD; STA tSU; STA P S tLOW tHD; DAT tHIGH tSU; DAT St tSU; STO P Fig. 7. Serial transfer timing (CH2) Device RS Device RS RS R S RP RP SDA0 (or SDA1) SCL0 (or SCL1) Fig. 8. Device recommended circuit • A pull-up resistor (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1). • The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance (Rs = 300Ω or less) can be used to reduce the spike noise caused by CRT flashover. – 25 – CXP88340/88348 (4) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V reference) Item Symbol Pins Conditions Min. Typ. Max. Unit 8 Bits ±1 LSB ±2 LSB Resolution Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Linearity error Absolute error 160/fADC∗1 12/fADC∗1 tCONV tSAMP Conversion time Sampling time Reference input voltage VREF Analog input voltage VIAN AVREF AN0 to AN7 IREF AVREF FFh FEh µs AVDD – 0.5 AVDD V 0 AVREF V 1.0 mA 10 µA 0.6 Operating mode AVREF current µs Sleep mode Stop mode 32kHz operating mode Digital conversion value ∗1 fADC indicates the below values due to the peripheral clock control register (PCC: 05F8h) bit 3 and clock control register (CLC: 00FEh) upper 2 bits. ADCCK 0 (φ/2 selection) 1 (φ selection) PCK1, PCK0 Linearity error 01h 00 (φ = fEX/2) fADC = fc/2 fADC = fc 01 (φ = fEX/4) fADC = fc/4 fADC = fc/2 11 (φ = fEX/16) fADC = fc/16 fADC = fc/8 00h VZT VFT Analog input Fig. 9. Definitions of A/D converter terms – 26 – CXP88340/88348 (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol Pins Conditions External interruption high and low level widths tIH tIL INT0 INT1 INT2 NMI PI0 to PI7 Reset input low level width tRSL RST Min. Unit 1 µs 32/fc µs tIH INT0 INT1 INT2 NMI PI0 to PI7 (During standby release input) (Falling edge) Max. tIL 0.8VDD 0.2VDD Fig. 10. Interruption input timing tRSL RST 0.2VDD Fig. 11. Reset input timing (5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item Symbol tCFH tCFL DFG input tDFH high and low level widths tDFL DPG minimum pulse width tDPW CFG input high and low level widths Pins Conditions Min. Max. Unit CFG 24tFRC + 200 ns DFG 16tFRC + 200 ns DPG 8tFRC + 200 ns 16tFRC + 200 ns 8tFRC + 200 + tsys ns DPG minimum removal time trem DPG EXI input high and low level widths tEIH tEIL EXI0 EXI1 tsys = 2000/fc Note 1) tFRC = 1000/fc [ns] Note 2) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") – 27 – CXP88340/88348 tCFH tCFL 0.8VDD CFG 0.2VDD tDFH tDFL 0.8VDD DFG 0.2VDD tDPW trem trem 0.8VDD DPG tEIH EXI0 EXI1 tEIL 0.8VDD 0.2VDD Fig. 12. Other timings – 28 – CXP88340/88348 Analog Circuit Characteristics (1) Amplifier circuit reference voltage characteristics (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –20 to +75°C) Item Symbol Reference level VOR output voltage Pins CTLAGND (2) CTL 1st amplifier characteristics Item Voltage gain∗1 Output offset voltage Symbol AVCTL1 VOSCTL1 Conditions Pins CTLFAMPI (–) CTLFAMPI (+) CTLFAMPI (–) CTLFAMPI (+) Min. Typ. Max. Unit 2.20 2.45 2.75 V (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –20 to +75°C) Min. Typ. Max. CTLFAMPI (–) = 0V, Gain = 16dB 13.5 15.5 17.5 CTLFAMPI (–) = 0V, Gain = 34dB 31.8 33.8 35.8 CTLFAMPI (–) = 0V, Gain = 49dB 46.5 48.5 50.5 CTLFAMPI (–) = 0V, Gain = 55dB 52.5 54.5 56.5 CTLFAMPI (–), CTLFAMPI (+) = open, Gain = 16dB –25 0 +25 Conditions Unit dB mV ∗1 The result after monitoring CTLFAMPO pin when the electrolytic capacitor (10µF) is connected to CTLFAMP (–) and CTLFAMP (+). (3) CTL 2nd amplifier characteristics Item Voltage gain∗1 Symbol AVCTL2 Pins CTLSAMPI Output offset voltage VOSCTL2 CTLSAMPI LPF cut-off frequency FCCTL CTLSAMPI (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –20 to +75°C) Conditions Min. Typ. Max. Gain = 5dB 3.5 5.5 7.5 Gain = 8dB 6.2 8.2 10.2 Gain = 11dB 9.0 11.0 13.0 Gain = 14dB 12.0 14.0 16.0 Gain = 17dB 15.0 17.0 19.0 Gain = 20dB 18.0 20.0 22.0 CTLSAMPI = open, Gain = 5dB –30 0 +30 12kHz, fDC – 3dB 8 12 24 20kHz, fDC – 3dB 12 20 42 – 29 – Unit dB mV kHz CXP88340/88348 Item Comparator level∗2 Symbol VCCTL Pins CTLSAMPI Conditions Min. Typ. Max. Comparator level = +100mV0-p 80 110 140 Comparator level = +150mV0-p 110 150 190 Comparator level = +200mV0-p 160 200 240 Comparator level = +250mV0-p 210 250 290 Comparator level = +300mV0-p 250 290 330 Comparator level = +400mV0-p 340 380 420 Comparator level = +500mV0-p 420 470 520 Comparator level = +600mV0-p 530 570 610 Comparator level = +1000mV0-p 850 920 990 Comparator level = –100mV0-p –90 –120 –150 Comparator level = –150mV0-p –110 –130 –190 Comparator level = –200mV0-p –150 –190 –230 Comparator level = –250mV0-p –200 –240 –280 Comparator level = –300mV0-p –240 –280 –320 Comparator level = –400mV0-p –340 –380 –420 Comparator level = –500mV0-p –430 –480 –530 Comparator level = –600mV0-p –540 –580 –620 Comparator level = –1000mV0-p –870 –970 –1070 Unit mV ∗1 The result after monitoring ANOUT pin when the electrolytic capacitor (10µF) is connected to CTLSAMPI. ∗2 The reference value of the comparator level is CTLAGND. (4) CTL amplifier characteristics (CTL1stAMP + CTL2ndAMP) (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –20 to +75°C) Item Voltage gain∗3 Input sensitivity Symbol AVCTL VSCTL Pins CTLHEAD (–) CTLHEAD (+) CTLHEAD (–) CTLHEAD (+) Conditions Min. Typ. Max. CTLHEAD (–) = 0V, Gain = (16dB + 5dB) 17.0 20.5 23.5 CTLHEAD (–) = 0V, Gain = (55dB + 20dB) 70.5 74.5 77.0 60 70 140 CTLHEAD (–) = 0V, Gain = (55dB + 20dB) Comparator = ±150mV0-p Unit dB µVp-p ∗3 The result when waveform is input from CTLHEAD (+) pin and ANOUT pin is monitored after performing coupling electrolytic capacitor (10µF) of CTLHEAD (–) and CTLHEAD (+), and coupling electrolytic capacitor (10µF) of HEADL (–) and HEADL (+), CTLFAMPI (–) and CTLFAMPI (+) , and CTLFAMPO and CTLSAMPI. Gain is maximum –1.5dB lowered when waveform is input from CTLHEAD (+) pin. – 30 – CXP88340/88348 (5) RECCTL write circuit characteristics Item Symbol Write current∗1 Pins Conditions CTLHEAD (–) CTLHEAD (+) IOREC (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –20 to +75°C) Min. Typ. Max. Write current 2.0mAp-p 0.8 1.8 3.6 Write current 3.0mAp-p 1.4 2.8 5.0 Write current 4.0mAp-p 2.0 3.8 7.0 Write current 5.0mAp-p 2.4 4.8 8.5 Write current 6.0mAp-p 3.0 6.0 10.0 Write current 7.0mAp-p 3.5 6.8 11.5 Write current 8.0mAp-p 4.5 7.8 13.0 Write current 9.0mAp-p 5.0 8.8 15.0 Write current 10.0mAp-p 5.5 7.7 17.0 Unit mA ∗1 The current which flows when CTLHEAD (–) and CTLHEAD (+) shorts. (6) Auto threshold control circuit (ATC) characteristics (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –20 to +75°C) Item Symbol ATC peak hold circuit initialize voltage value∗2 VATCINIT ATC comparator level offset voltage∗3 Pins VATCOFF Conditions Min. Typ. Max. Voltage = –150mV0-P –110 –150 –190 Voltage = –400mV0-P –350 –400 –450 Gain = 1/6 (16.7%) –70 –160 Gain = 1/5 (20%) –90 –210 Gain = 1/4 (25%) –90 –210 Gain = 1/3 (33.3%) –70 –160 Gain = 2/5 (40%) –90 –210 Gain = 1/2 (50%) –70 –160 Gain = 3/5 (60%) –90 –210 Unit mV mV ∗2 Reference is CTLAGND. ∗3 Reference is CTLAGND. When comparator level is generated using ATC, actual comparator level is as follows by the offset voltage inside of ATC. Vin × gain + |offset voltage| Example: Gain = 1/2 Vin × 1/2 + 160 (AMPVDD = VDD = 5.0V, AMPVSS = Vss = 0V, Ta = –20 to +75°C) (7) Schmitt characteristics Item Symbol Pins RTG schmitt width SRFG RFG0, RFG1 CFG/DFG/DPG SCFG SDFG SDPG CFG, DFG, DPG Conditions Min. Typ. Max. Unit Schmitt width 1Vp-p 820 920 1020 mV Schmitt width 410mVp-p 180 300 420 Schmitt width 1Vp-p 700 900 1100 – 31 – mV CXP88340/88348 Appendix (i) AAAA AAAA AAAA EXTAL AAAA AAAA AAAA (ii) TEX XTAL Rd Rd C1 TX C2 C2 C1 Fig. 13. Recommended oscillation circuit Manufacturer RIVER ELETEC CO., LTD. Model HC-49/U03 Rd (Ω) Circuit example 0 (i) fc (MHz) C1 (pF) C2 (pF) 8.00 10 10 5 5 8.00 16 (12) 16 (12) 10.00 16 (12) 16 (12) 12.00 12 12 0 16.00 12 12 0 32.768kHz 30 18 470k 10.00 12.00 16.00 KINSEKI LTD. HC-49/U (-S) P3 Mask option table Item Reset pin pull-up resistor Input circuit format∗1 Content Non-existent Existent CMOS schmitt TTL schmitt ∗1 The input circuit format can be selected for PE3/SYNC pin. – 32 – 0 (i) (ii) CXP88340/88348 Characteristics Curve IDD vs. VDD IDD vs. fc (fc = 16MHz, Ta = 25°) (VDD = 5.0V, Ta = 25°) 100 40 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode Sleep mode 1 32kHz mode (instruction) 0.1 (100µA) IDD – Supply current [mA] IDD – Supply current [mA] 10 1/2 dividing mode 30 20 1/4 dividing mode 10 32kHz Sleep mode 1/16 dividing mode 0.01 (10µA) Sleep mode 0 0 2 3 4 5 6 VDD – Supply voltage [V] 0 5 10 15 fc – System clock [MHz] – 33 – CXP88340/88348 Package Outline Unit: mm 100PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.4 20.0 – 0.1 + 0.1 0.15 – 0.05 80 51 + 0.4 14.0 – 0.1 17.9 ± 0.4 15.8 ± 0.4 50 81 A 31 100 1 0.65 30 + 0.15 0.3 – 0.1 0.13 + 0.2 0.1 – 0.05 + 0.35 2.75 – 0.15 M 0° to 10° DETAIL A 0.8 ± 0.2 (16.3) 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-100P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE QFP100-P-1420 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 1.7g JEDEC CODE – 34 –