LSI LS7366R 32-bit quadrature counter with serial interface Datasheet

UL
LSI/CSI
®
LS7366R
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747
(631) 271-0400 FAX (631) 271-0405
A3800
32-BIT QUADRATURE COUNTER WITH SERIAL INTERFACE
GENERAL DESCRIPTION:
LS7366R is a 32-bit CMOS counter, with direct interface for quadrature clocks from incremental encoders. It also interfaces with the
index signals from incremental encoders to perform variety of
marker functions.
For communications with microprocessors or microcontrollers, it
provides a 4-wire SPI/MICROWIRE bus.The four standard bus I/Os
are SS/, SCK, MISO and MOSI. The data transfer between a microcontroller and a slave LS7366R is synchronous. The synchronization is done by the SCK clocks supplied by the microcontroller. Each
transmission is organized in blocks of 1 to 5 bytes of data. A transmission cycle is intitiated by a high to low transition of the SS/ input.
The first byte received in a transmission cycle is always an instruction byte, whereas the second through the fifth bytes are always
interpreted as data bytes. A transmission cycle is terminated with
the low to high transition of the SS/ input. Received bytes are shifted
in at the MOSI input, MSB first, with the leading edges (high transition) of the SCK clocks. Output data are shifted out on the MISO
output, MSB first, with the trailing edges (low transition) of the SCK
clocks.
7366R-050106-1
PIN ASSIGNMENT
TOP VIEW
14 V DD
f CKO
1
f CKi
2
13 CNT_EN
Vss
3
12 A
SS/
4
SCK
5
MISO
6
9 DFLAG/
MOSI
7
8 LFLAG/
LS7366R
SPI/MICROWIRE (Serial Peripheral Interface):
• Standard 4-wire connection: MOSI, MISO, SS/ and SCK.
• Slave mode only.
May 2006
LSI
GENERAL FEATURES:
• Operating voltage: 3V to 5.5V (VDD - VSS)
• 5V count frequency: 40MHz
• 3V count frequency: 20MHz
• 32-bit counter (CNTR).
• 32-bit data register (DTR) and comparator.
• 32-bit output register (OTR).
• Two 8-bit mode registers (MDR0, MDR1)
for programmable functional modes.
• 8-bit instruction register (IR).
• 8-bit status register (STR).
• Latched Interrupt output on Carry or Borrow or Compare or Index.
• Index driven counter load, output register load or counter reset.
• Internal quadrature clock decoder and filter.
• x1, x2 or x4 mode of quadrature counting.
• Non-quadrature up/down counting.
• Modulo-N, Non-recycle, Range-limit or
Free-running modes of counting
• 8-bit, 16-bit, 24-bit and 32-bit programmable configuration
synchronous (SPI) serial interface
• LS7366R (DIP), LS7366R-S (SOIC), LS7366R-TS (TSSOP)
- See Figure 1 -
11 B
10 INDEX/
FIGURE 1
Read and write commands cannot be combined.
For example, when the device is shifting out read
data on MISO output, it ignores the MOSI input,
even though the SS/ input is active. SS/ must be
terminated and reasserted before the device will
accept a new command.
The counter can be configured to operate as 1, 2, 3
or 4-byte counter. When configured as an n-byte
counter, the CNTR, DTR and OTR are all configured as n-byte registers, where n = 1, 2, 3 or 4.
The content of the instruction/data identity is
automatically adjusted to match the n-byte configuration. For example, if the counter is configured as a
2-byte counter, the instruction “write to DTR”
expects 2 data bytes following the instruction byte.
If the counter is configured as a 3-byte counter, the
same instruction will expect 3 bytes of data following the instruction byte.
Following the transfer of the appropriate number of
bytes any further attempt of data transfer is ignored
until a new instruction cycle is started by switching
the SS/ input to high and then low.
The counter can be programmed to operate in a
number of different modes, with the operating
characteristics being written into the two mode
registers MDR0 and MDR1. Hardware I/Os are
provided for event driven operations, such as
processor interrupt and index related functions.
I/O Pins:
Following is a description of all the input/output pins.
A (Pin 12) B (Pin 11)
Inputs. A and B quadrature clock outputs from incremental
encoders are directly applied to the A and B inputs of the
LS7366R. These clocks are ideally 90 degrees out-of-phase
signals. A and B inputs are validated by on-chip digital filters
and then decoded for up/down direction and count clocks.
In non-quadrature mode, A serves as the count input and B
serves as the direction input (B = high enables up count,
B = low enables down count). In non-quadrature mode,
the A and B inputs are not filtered internally, and are instantaneous in nature.
INDEX/ (Pin 10)
Input. The INDEX/ is a programmable input that can be
driven directly by the Index output of an incremental encoder. It can be programmed via the MDR0 to function as one
of the following:
LCNTR (load CNTR with data from DTR), RCNTR (reset
CNTR), or LOTR (load OTR with data from CNTR).
Alternatively, the INDEX input can be masked out for "no
functionality".
In quadrature mode, the INDEX/ input can be configured to
operate in either synchronous or asynchronous mode. In the
synchronous mode the INDEX/ input is sampled with the
same filter clock used for sampling the A and the B inputs
and must satisfy the phase relationship in which the INDEX/
is in the active level of Logic 0 during a minimum of a
quarter cycle of both A and B High or both A and B Low. In
non-quadrature mode, the INDEX/ input is unconditionally
set to the asynchronous mode. In the asynchronous mode,
the INDEX/ input is not sampled and can be applied in any
phase relationship with respect to A and B.
fCKi (Pin 2), fCK0 (Pin 1)
Input, Output. A crystal connected between these 2 pins
generates the basic clock for filtering the A, B and INDEX/
inputs in the quadrature count mode. Instead of a crystal the
fCKi input may also be driven by an external clock.
The frequency at the fCKi input is either divided by 2
(if MDR0 <B7> = 1) or divided by 1 (if MDR0 <B7> = 0) for
the filter circuit. For proper filtering of the A, B and the Index/
inputs the following condition must be satisfied:
ff ≥ 4fQA
Where ff is the internal filter clock frequency derived from the
fCKi in accordance with the status of MDR0 <B7> and fQA is
the maximum frequency of Clock A in quadrature mode. In
non-quadrature count mode, fCKi is not used and should be
tied off to any stable logic state.
SS/ (Pin 4)
A high to low transition at the SS/ (Slave Select) input
selects the LS7366R for serial bi-directional data transfer; a
low to high transition disables serial data transfer and brings
the MISO output to high impedance state. This allows for the
accommodation of multiple slave units on the serial I/O.
7366R-050106-2
CNT_EN (Pin 13)
Input. Counting is enabled when CNT_EN input is high; counting
is disabled when this input is low. There is an internal pull-up
resistor on this input.
LFLAG/ (Pin 8), DFLAG/ (Pin 9)
Outputs. LFLAG/ and DFLAG/ are programmable outputs to flag
the occurences of Carry (counter overflow), Borrow (counter
underflow), Compare (CNTR = DTR) and INDEX. The LFLAG/ is
an open drain latched output. In contrast, the DFLAG/ is a pushpull instantaneous output. The LFLAG/ can be wired in multislave configuration, forming a single processor interrupt line.
When active LFLAG/ switches to logic 0 and can be restored to
the high impedence state only by clearing the status register,
STR. In contrast, the DFLAG/ dynamically switches low with
occurences of Carry, Barrow, Compare and INDEX conditions.
The configuration of LFLAG/ and DFLAG/ are made through the
control register MDR1.
MOSI (RXD) (Pin 7)
Input. Serial output data from the host processor is shifted into
the LS7366R at this input.
MISO (TXD) (Pin 6)
Output. Serial output data from the LS7366R is shifted out on
the MISO (Master In Slave Out) pin. The MISO output goes into
high impedance state when SS/ input is at logic high, providing
multiple slave-unit serial outputs to be wire-ORed.
SCK (Pin 5)
Input. The SCK input serves as the shift clock input for transmitting data in and out of LS7366R on the MOSI and the MISO
pins, respectively. Since the LS7366R can operate only in the
slave mode, the SCK signal is provided by the host processor
as a means for synchronizing the serial transmission between
itself and the slave LS7366R.
REGISTERS:
The following is a list of LS7366 internal registers:
Upon power-up the registers DTR, CNTR, STR, MDR0 and
MDR1 are reset to zero.
DTR. The DTR is a software configurable 8, 16, 24 or 32-bit
input data register which can be written into directly from MOSI,
the serial input. The DTR data can be transferred into the 32-bit
counter (CNTR) under program control or by hardware index
signal. The DTR can be cleared to zero by software control. In
certain count modes, such as modulo-n and range-limit, DTR
holds the data for "n" and the count range, respectively. In
compare operations, whereby compare flag is set, the DTR is
compared with the CNTR.
CNTR. The CNTR is a software configurable 8, 16, 24 or 32-bit up/down counter which counts the up/down pulses resulting from
the quadrature clocks applied at the A and B inputs, or alternatively, in non-quadrature mode, pulses applied at the A input.
By means of IR intructions the CNTR can be cleared, loaded from the DTR or in turn, can be transferred into the OTR.
OTR. The OTR is a software configuration 8, 16, 24 or 32-bit register which can be read back on the MISO output.
Since instantaneous CNTR value is often needed to be read while the CNTR continues to count, the OTR serves as a
convenient dump site for instantaneous CNTR data which can then be read without interfering with the counting process.
CY: Carry (CNTR overflow) latch
BW: Borrow (CNTR underflow) latch
CMP: Compare (CNTR = DTR) latch
IDX: Index latch
CEN: Count enable status: 0: counting disabled,
1: counting enabled
STR. The STR is an 8-bit status register which stores
count related status information.
CY
7
BW
6
CMP
5
IDX
4
CEN
3
PLS
2
U/D
1
S
0
PLS: Power loss indicator latch; set upon power up
U/D: Count direction indicator: 0: count down, 1: count up
S: Sign bit. 1: negative, 0: positive
IR. The IR is an 8-bit register that fetches instruction bytes from
the received data stream and executes them to perform such
functions as setting up the operating mode for the chip (load the
MDR) and data transfer among the various registers.
B7
B6
B5
B4
B3
B2
B1
B0
B2 B1 B0 = XXX (Don’t care)
B5 B4 B3 = 000: Select none
= 001: Select MDR0
= 010: Select MDR1
= 011: Select DTR
= 100: Select CNTR
= 101: Select OTR
= 110: Select STR
= 111: Select none
B7 B6 = 00: CLR register
= 01: RD register
= 10: WR register
= 11: LOAD register
The actions of the four functions, CLR, RD, WR and LOAD are elaborated in Table 1.
Number of Bytes OP Code
1
CLR
2 to 5
RD
2 to 5
1
7366R-122205-3
WR
LOAD
TABLE 1
Register
MDR0
MRD1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
STR
MDR0
MDR1
DTR
CNTR
OTR
Operation
Clear MDR0 to zero
Clear MDR1 to zero
None
Clear CNTR to zero
None
Clear STR to zero
Output MDR0 serially on TXD (MISO)
Output MDR1 serially on TXD (MISO)
None
Transfer CNTR to OTR, then output OTR serially
on TXD (MISO)
Output OTR serially on TXD (MISO)
Output STR serially on TXD (MISO)
Write serial data at RXD (MOSI) into MDR0
Write serial data at RXD (MOSI) into MDR1
Write serial data at RXD (MOSI) into DTR
None
None
None
None
None
None
Transfer DTR to CNTR in “parallel”
Transfer CNTR to OTR in “parallel”
MDR0. The MDR0 (Mode Register 0) is an 8-bit read/write register that sets up the operating mode for the LS7366R. The MDR0 is
written into by executing the "write-to-MDR0" instruction via the instruction register. Upon power up MDR0 is cleared to zero. The
following is a breakdown of the MDR bits:
B7
B6
B5
B4
B3
B2
B1
B0
B1 B0 = 00: non-quadrature count mode. (A = clock, B = direction).
= 01: x1 quadrature count mode (one count per quadrature cycle).
= 10: x2 quadrature count mode (two counts per quadrature cycle).
= 11: x4 quadrature count mode (four counts per quadrature cycle).
B3 B2 = 00: free-running count mode.
= 01: single-cycle count mode (counter disabled with carry or borrow, re-enabled with reset or load).
= 10: range-limit count mode (up and down count-ranges are limited between DTR and zero,
respectively; counting freezes at these limits but resumes when direction reverses).
= 11: modulo-n count mode (input count clock frequency is divided by a factor of (n+1),
where n = DTR, in both up and down directions).
B5 B4 = 00: disable index.
= 01: configure index as the "load CNTR" input (transfers DTR to CNTR).
= 10: configure index as the "reset CNTR" input (clears CNTR to 0).
= 11: configure index as the "load OTR" input (transfers CNTR to OTR).
B6 = 0:
= 1:
B7 = 0:
= 1:
Asynchronous Index
Synchronous Index (overridden in non-quadrature mode)
Filter clock division factor = 1
Filter clock division factor = 2
MDR1. The MDR1 (Mode Register 1) is an 8-bit read/write register which is appended to MDR0 for additional modes.
Upon power-up MDR1 is cleared to zero.
B7
B1 B0 = 00:
= 01:
= 10:
= 11:
B2 = 0:
= 1:
B3 = :
B4 = 0:
= 1:
B5 = 0:
= 1:
B6 = 0:
= 1:
B7 = 0:
= 1:
B6
B5
B4
B3
B2
B1
B0
4-byte counter mode
3-byte counter mode
2-byte counter mode.
1-byte counter mode
Enable counting
Disable counting
not used
NOP
FLAG on IDX (B4 of STR)
NOP
FLAG on CMP (B5 of STR)
NOP
FLAG on BW (B6 of STR)
NOP
FLAG on CY (B7 of STR)
NOTE: Applicable to both
LFLAG/ and DFLAG/
ABSOLUTE MAXIMUM RATINGS:
(All voltages referenced to Vss)
Parameter
DC Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
7366R-041906-4
Symbol
VDD
VIN
TA
TSTG
Values
+7.0
Vss - 0.3 to VDD + 0.3
-25 to +80
65 to +150
Unit
V
V
oC
oC
DC Electrical Characteristics. (TA = -25˚C to +85°C)
Parameter
Symbol
Min.
Supply Voltage
VDD
3.0
Supply Current
IDD
300
IDD
700
Input Voltages
fCKi, Logic high
VCH
2.3
VCH
3.7
fCKi, Logic Low
VCL
VCL
All other inputs, Logic High
VAH
2.1
VAH
3.5
All other inputs, Logic Low
Input Currents:
CNT_EN Low
CNT_EN High
All other inputs, High or Low
Output Currents:
LFLAG, DFLAG Sink
LFLAG Source
DFLAG Source
fCKO Sink
fCKO Source
TXD/MISO:
Sink
Source
TYP
400
800
Max.
5.5
450
950
Unit
V
µA
µA
Remarks
VDD = 3.0V
VDD = 5.0V
-
0.7
1.3
V
V
V
V
V
V
VDD = 3.0V
VDD = 5.0V
VDD = 3.0V
VDD = 5.0
VDD = 3.0V
VDD = 5.0V
0.5
1.0
V
V
VDD = 3.0V
VDD = 5.0V
VAL
VAL
-
-
IIEL
IIEL
-
3.0
10.0
5.0
15.0
µA
µA
VAL = 0.7V, VDD = 3.0V
VAL = 1.2V, VDD = 5.0V
IIEH
IIEH
-
-
1.0
4.0
0
3.0
6.0
0
µA
µA
µA
VAH = 1.9V, VDD = 3.0V
VAH = 3.2V, VDD = 5.0V
-
IOFL
IOFL
IOFH
IOFH
-1.3
-3.2
0
1.0
2.8
-2.0
-4.0
0
1.8
3.6
-
mA
mA
mA
mA
mA
VOUT = 0.5V, VDD = 3.0V
VOUT = 0.5V, VDD = 5.0V
Open Drain Output
VOUT = 2.5V, VDD = 3.0V
VOUT = 4.5V, VDD = 5.0V
IOCL
IOCL
IOCH
IOCH
-1.3
-3.2
1.3
3.2
-2.0
-4.0
2.0
4.0
-
mA
mA
mA
mA
VOUT = 0.5V, VDD = 3.0V
VOUT = 0.5V, VDD = 5.0V
VOUT = 2.5V, VDD = 3.0V
VOUT = 4.5V, VDD = 5.0V
IOML
IOML
-1.5
-3.8
-2.4
-4.8
-
mA
mA
VOUT = 0.5V, VDD = 3.0V
VOUT = 0.5V, VDD = 5.0V
IOMH
IOMH
1.5
3.8
2.4
4.8
-
mA
mA
VOUT = 2.5V, VDD = 3.0V
VOUT = 4.5V, VDD = 5.0V
Transient Characteristics. (TA = -25˚C to +85˚C, VDD = 5V ± 10%)
Parameter
(See Fig. 2)
SCK High Pulse Width
SCK Low Pulse Width
SS/ Set Up Time
SS/ Hold Time
Quadrature Mode
(See Fig. 5, 7 & 8 )
fCKI High Pulse Width
fCKI Pulse Width
fCKI Frequency
Effective Filter Clock fF Period
Effective Filter Clock fF frequency
Quadrature Separation
Quadrature Clock Pulse Width
Quadrature Clock frequency
Quadrature Clock to Count Delay
x1 / x2 / x4 Count Clock Pulse Width
Index Input Pulse Width
Index Set Up Time
Index Hold Time
Quadrature clock to
DFLAG/ or LFLAG/ delay
DFLAG/ output width
7366R-041906-5
Symbol
Min. Value
Max.Value
Unit
Remarks
tCH
tCL
tCSL
tCSH
100
100
100
100
-
ns
ns
ns
ns
-
t1
t2
fFCK
t3
t3
fF
t4
t5
fQA, fQB
tQ1
tQ2
tid
tis
tih
tfl
12
12
25
50
26
52
4t3
12
32
4.5t3
40
40
9.6
5t3
5
5
5.5t3
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
t3 = t1+t2, MDR0 <7> = 0
t3 = 2(t1+t2), MDR0 <7> = 1
fF = 1/ t3
t4 > t3
t5 ≥ 2t3
fQA = fQB < 1/4t3
tQ2 = (t3)/2
tid > t4
-
tfw
26
-
ns
tfw = t4
Parameter
Non-Quadrature Mode
(See Fig. 6 & 9)
Clock A - High Pulse Width
Clock A - Low Pulse Width
Direction Input B Set-up Time
Direction Input B Hold Time
Clock Frequency (non-Mod-N)
Clock to DFLAG/ or
LFLAG/ delay
DFLAG/ output width
Symbol
Min. Value
Max.Value
Unit
Remarks
t6
t7
t8S
t8H
fA
t9
12
12
12
10
20
40
-
ns
ns
ns
ns
MHz
ns
fA = (1/(t6 + t7))
-
t10
12
-
ns
t10 = t7
Transient Characteristics. (TA = -25˚C to +85˚C, VDD = 3.3V ± 10%)
Parameter
(See Fig. 2)
SCK High Pulse Width
SCK Low Pulse Width
SS/ Set Up Time
SS/ Hold Time
Quadrature Mode
(See Fig. 5, 7 & 8)
fCKI High Pulse Width
fCKI Pulse Width
fCKI Frequency
Effective Filter Clock fF Period
Effective Filter Clock fF frequency
Quadrature Separation
Quadrature Clock Pulse Width
Quadrature Clock frequency
Quadrature Clock to Count Delay
x1/x2/x4 Count Clock Pulse Width
Index Input Pulse Width
Index Set Up Time
Index Hold Time
Quadrature clock to
DFLAG/ or LFLAG/ delay
DFLAG/ output width
Non-Quadrature Mode
(See Fig. 6 & 9)
Clock A - High Pulse Width
Clock A - Low Pulse Width
Direction Input B Set-up Time
Direction Input B Hold Time
Clock Frequency (non-Mod-N)
Clock to DFLAG/or
LFLAG/ delay
DFLAG/ output width
7366R-041906-6
Symbol
Min. Value
Max.Value
Unit
Remarks
tCH
tCL
tCSL
tCSH
120
120
120
120
-
ns
ns
ns
ns
-
t1
t2
fFCK
t3
t3
fF
t4
t5
fQA, fQB
tQ1
tQ2
tid
tis
tih
tfl
24
24
50
100
52
105
4t3
25
60
4.5t3
20
20
4.5
5t3
10
10
5.5t3
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
ns
ns
ns
t3 = t1+t2, MDR0 <7> = 0
t3 = 2(t1+t2), MDR0 <7> = 1
fF = 1/ t3
t4 > t3
t5 ≥ 2t3
fQA = fQB < 1/4t3
tQ2 = (t3)/2
tid > t4
-
tfw
52
-
ns
tfw = t4
t6
t7
t8S
t8H
fA
t9
24
24
24
24
40
40
-
ns
ns
ns
ns
MHz
ns
fA = (1/(t6 + t7))
-
t10
24
-
ns
t10 = t7
tCSL
tCSH
SS/
((
))
t CL
tCH
SCK
((
))
((
))
MOSI
MSB
((
))
HIGH IMPEDANCE
MISO
LSB
Note 1. The SPI port of the host MCU must be set up as follows:
1.
2.
3.
4.
SPI master mode.
SCK idle state = low
Clock edge for MOSI data shift = high to low
Clock edge for input data (MISO) sample by the Processor = low to high (or bit middle)
Note 2. To conform with the multibyte transmission protocol of LS7366R, the SS/ output port
of the MCU may require direct manipulation by the application program.
FIGURE 2. SPI TIMINGS
7366R-041906-7
START OF NEW COMMAND
tCSL
SS/
tCL
tCH
SCK
WR
MDR1
MOSI
BIT #
7
6
5
4
RD
DATA
3
X
X
X
2
1
0
MDR1
D7 D6 D5 D4 D3 D2 D1 D0 X
7
6
5 4
3
2
1
0
7
6
5 4
3
X
X
X RANDOM DATA
2
1
0
D7 D6 D5 D4 D3 D2 D1 D0
MISO
BIT #
7
6
5
4
3
2
1
X
X
X
2
1
0
TRI-STATE
NOTE: Write to MDR1 followed by Read from MDR1 operation
FIGURE 3. WR MDR1 - RD MDR1
tC S I
SS/
SCK
RD
CLR
CNTR
MOSI
BIT #
7
6
5
4
3
X
X
X
2
1
0
STR
RANDOM DATA
7
BYTE 1
6
5
4
3
BYTE 0
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MISO
BIT #
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
TRI-STATE
NOTE: Read CNTR (in 2-byte configuration) followed by CLR STR operation.
FIGURE 4. RD CNTR - CLR STR
t1
f CKi
t2
t3
f f (Note 4)
t3
(MDR0 <7> = 0)
f f (Note 4)
t5
(MDR0 <7> = 1)
A
B
INDEX/
t4
t5
t4
t4
tih
tis
Note 1
tid
Note 1. Synchronous index coincident with both A and B high.
Note 2. Synchronous index coincident with both A and B low..
Note 3. fF is the internal effective filter clock.
FIGURE 5. fCKI, A, B and INDEX
7366R-041906-8
t4
tis
tih
Note 2
0
DOWN
t6
UP
DOWN
t 8s
t7
t 8H
FIGURE 6. COUNT (A) AND DIRECTION (B) INPUTS IN NON-QUADRATURE MODE
UP
DOWN
t Q1
A
B
X4_CLK
(see note)
X2_CLK
(see note)
t Q2
X1_CLK
(see note)
Note: x1, x2, and x4 CLKs are internal up/down clocks derived from filtered and decoded quadrature clocks.
FIGURE 7. A/B QUADRATURE CLOCKS vs INTERNAL COUNT CLOCKS
DOWN
UP
A
B
X4_CLK
CNTR
FFFFFC
FFFFFD
FFFFFE
000000
FFFFFF
t fl
DFLG/
CY
000001
000002
000001 000000 FFFFFF
(SHOWN WITH DTR = 000OO1)
CMP
tfl
LFLG/
Note: CNTR values are indicated in 3-byte mode
FIGURE 8. QUADRATURE CLOCKS vs FLAG OUTPUTS
7366-050106-9
BW
t fw
FFFFFE
FFFFFD
UP
DOWN
B
A
(Shown with DTR = 2)
CNTR
FFFFFFC FFFFFFD FFFFFFE FFFFFFF
0
2
1
0
t9
DFLG/
CY
FFFFFFF
t 10
CNTR DISABLED
CNTR DISABLED
t11
INDX/
(LOAD CNTR)
CNTR ENABLED
NOTE: CNTR values are indicated in 2-byte mode
FIGURE 9. SINGLE-CYCLE, NON-QUADRATURE
B
DOWN
UP
A
(Shown with DTR = 3)
CNTR
000000 000001 000002 000003 000000 000001 000002
DFLAG/
000001 000000 000003 000002 000001
BW
CMP
NOTE: CNTR values are indicated in 1-byte mode
FIGURE 10. MODULO-N, NON-QUADRATURE
B
DOWN
UP
A
(Shown with DTR = 3)
CNTR
DFLAG/
000000
000001 000002
000003
CMP
CMP
000002 000001
CMP
CMP
NOTE: CNTR values are indicated in 1-byte mode
FIGURE 11. RANGE-LIMIT, NON-QUADRATURE
7366R-050106-10
000000
BW
BW
BW
(8)
SCK
5
CLOCK
CONTROL
V+
IO SHIFT
REG
IO DATA
CONTROL
6
BUFFER
(8)
TXD/MIS0
(8)
RXD/MOSI
EN_DTR
7
SPI_XMIT/
DTR
POR
(32)
SS/
4
A 12
B
FILTER
11
(32)
÷2
LOAD
EN_MDR0
MDR0
FLAGS
(8)
MDR0<7>
CNT_EN 13
EN_MDR1
WR
MDR1
(8)
POR
POR
V DD 14
(V+)
3
(V-)
V SS
FLAG
MASK
EN_STR
STR
RD
POR GEN
(8)
CLR
EN_DTR
FLAGS
EN_CNTR
EN_OTR
IR
(5)
EN_MDR0
LOAD CLR RD WR
EN_MDR1
EN_STR
FIGURE 12. LS7366R BLOCK DIAGRAM
7366R-041906-11
9 DFLAG/
8 LFLAG/
FLAG
LOGIC
MUX
V+
1
BUFFER
EN_OTR
OTR
fCK i 2
CMPR
LOAD
MODE
CONTROL
INDEX/ 10
fCKO
EN_CNTR
CNTR
(32)
+V
+V
+V
VDD
VDD
LS7366R
MCU
15pF
1
40MHz
LFLAG/
f CKI
1MΩ
2
MISO
C
f KO
MOSI
15pF
10
ENCODER
12
11
INDEX/
SCK
A
SS/
B
8
INT/
6
RXD
7
TXD
5
SCK
4
SS/
Vss
GND
3
FIGURE 13. GENERAL I/O CONNECTIONS
PIC18CXXX
RA5
RC3/SCK
RC4/SDI
RC5/SDO
LS7366R
4
5
SCK
6
7
FIGURE 14. PIC18C TO LS7366R
7366R-042106-12
SS/
MISO
MOSI
;Sample routines for PIC18CXXX interface
/***********************************************************************************************************************/
;Initialize PIC18Cxxx portc in LS7366 compatible SPI
;Setup: master mode, SCK idle low, SDI/SDO datashift on high to low transition of SCK
;SS/ assertion/deassertion made with direct manipulation of RA5
;Initialize portc
CLRF
CLRF
MOVLW
MOVWF
BCF
BSF
CLRF
BSF
MOVLW
MOVWF
PORTC
LATC
0x10
TRISC
TRISA, 5
PORTA, 5
SSPSTAT
SSPSTAT, CKE
0x21
SSPCON
;Clear portc
;Clear data latches
;RC4 is input, RC3 & RC5 are outputs
;RC3=CLK, RC4=SDI, RC5=SDO
;RA5=output
;RA5=SS/=high
;SMP=0 => SDI data sampled at mid-data
;CKE=1 => data shifts on active to idle SCK transitions
;SPI mode initialization data
;Master mode, CLK/16, CKP=0 => CLK idles low
;data shifted on active to idle CLK edge
/***********************************************************************************************************************/
; WR_MDR0
BSF
BCF
MOVLW
MOVWF
LOOP1 BTFSS
BRA
MOVF
MOVLW
MOVWF
LOOP2 BTFSS
BRA
BSF
PORTA, 5
PORTA, 5
0x88
SSPBUF
SSPSTAT, BF
LOOP1
SSPBUF, W
0xA3
SSPBUF
SSPSTAT, BF
LOOP2
PORTA, 5
;SS/=high
;SS/=low
;LS7366 WR_MDR0 command
;Transmit command byte
;Transmission complete with BF flag set?
;No, check again
;Dummy read to clear BF flag.
;MDR0 data:fck/2, synchronous index. index=rcntr, x4
;Transmit data
;BF set?
;No, check again
;SS/=high
/***********************************************************************************************************************/
;RD_MDR0
BSF
BCF
MOVLW
MOVWF
LOOP1 BTFSS
BRA
MOVWF
LOOP2 BTFSS
BRA
MOVF
MOVWF
BSF
7366R-041906-13
PORTA, 5
PORTA, 5
0x48
SSPBUF
SSPSTAT, BF
LOOP1
SSPBUF
SSPSTAT, BF
LOOP2
SSPBUF, W
RXDATA
PORTA, 5
;SS/=high
;SS/=low
;LS7366 RD_MDR0 command
;Transmit command byte
;BF flag set?
;No, check again
;Send dummy byte to generate clock & receive data
;BF flag set?
;No, check again
;Recieved data in WREG.
;Save received data in RAM
;SS/=high