LINER LTC3718 Low input voltage dc/dc controller for ddr/qdr memory termination Datasheet

LTC3718
Low Input Voltage
DC/DC Controller for
DDR/QDR Memory Termination
DESCRIPTIO
U
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
The LTC®3718 is a high current, high efficiency synchronous switching regulator controller for DDR and QDRTM
memory termination. It operates from an input as low as
1.5V and provides a regulated output voltage equal to
(0.5)VIN. The controller uses a valley current control
architecture to enable high frequency operation with very
low on-times without requiring a sense resistor. Operating
frequency is selected by an external resistor and is compensated for variations in VIN and VOUT. The LTC3718 uses
a pair of standard 5V logic level N-channel external
MOSFETs, eliminating the need for expensive P-channel
or low threshold devices.
Very Low VIN(MIN): 1.5V
Ultrafast Transient Response
True Current Mode Control
5V Drive for N-Channel MOSFETs Eliminates
Auxillary 5V Supply
No Sense Resistor Required
Uses Standard 5V Logic-Level N-Channel MOSFETs
VOUT(MIN): 0.4V
VOUT Tracks 1/2 VIN or External VREF
Symmetrical Source and Sink Output Current Limit
Adjustable Switching Frequency
tON(MIN) <100ns
Power Good Output Voltage Monitor
Programmable Soft-Start
Output Overvoltage Protection
Optional Short-Circuit Shutdown Timer
Small 24-Lead SSOP Package
Forced continuous operation reduces noise and RF interference. Fault protection is provided by internal foldback
current limiting, an output overvoltage comparator and an
optional short-circuit timer. Soft-start capability for supply sequencing can be accomplished using an external
timing capacitor. OPTI-LOOP® compensation allows the
transient response to be optimized over a wide range of
loads and output capacitors.
U
APPLICATIO S
■
■
■
Bus Termination: DDR/QDR Memory, SSTL, HSTL, ...
Servers, RAID Systems
Distributed Power Systems
Synchronous Buck with General Purpose Boost
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation. No RSENSE is a
trademark of Linear Technology Corporation. QDR RAMs and Quad Data Rate RAMs comprise a
new family of products developed by Cypress Semiconductor, IDT and Micron Technology, Inc.
U
■
TYPICAL APPLICATIO
SHDN
TG
VREF
CSS
0.1µF
VFB1
Efficiency vs Load Current
D1
B340A
100
PGOOD
SW1
90
SENSE +
80
L1 0.8µH
PGND1
SENSE
+
–
M2
Si7440DP
BG
RUN/SS
C1 820pF X7R
M1
Si7440DP
LTC3718
ION
VOUT
CB
0.33µF
D2
B340A
COUT
470µF
×2
VOUT
1.25V
±10A
INTVCC
RC 4.75k
ITH
VIN1
SGND1
VIN2
SGND2
VFB2
RF1 12.1k
60
50
40
30
CIN2
4.7µF
PGND2
VIN
L2
4.7µH
CVCC1
10µF
20
10
0
0.01
SW2
RF2 37.4k
VIN = 2.5V
VOUT = 1.25V
70
EFFICIENCY (%)
RON
237k
BOOST
VIN
2.5V
CIN1
22µF
×2
DB
CMDSH-3
D3
MBR0520
FIGURE 1 CIRCUIT
0.1
1
10
LOAD CURRENT (A)
100
3718 G05/TA01a
COUT: SANYO POSCAP 4TPB470M
L1: SUMIDA CEP125-0R8MC
L2: PANASONIC ELJPC4R7MF
3718 TA01
Figure 1. High Efficiency Bus Termination Supply without Auxiliary 5V Supply
3718fa
1
LTC3718
W W
W
AXI U
U
ABSOLUTE
RATI GS
U
U
W
PACKAGE/ORDER I FOR ATIO
(Note 1)
Input Supply Voltage (VIN2) .......................10V to – 0.3V
Boosted Topside Driver Supply Voltage
(BOOST) ............................................... 42V to – 0.3V
VIN1, ION, SW1 Voltage ............................. 36V to – 0.3V
RUN/SS, PGOOD Voltages ......................... 7V to – 0.3V
VON, VREF, VRNG Voltages .......(INTVCC + 0.3V) to – 0.3V
ITH, VFB1 Voltages .................................... 2.7V to – 0.3V
SW2 Voltage ............................................. 36V to – 0.4V
VFB2 Voltage ................................................. VIN2 + 0.3V
SHDN Voltage ......................................................... 10V
TG, BG, INTVCC Peak Currents .................................. 2A
TG, BG, INTVCC RMS Currents ............................ 50mA
Operating Ambient Temperature
Range (Note 4) ................................... – 40°C to 85°C
Junction Temperature (Note 2) ............................ 125°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
RUN/SS
1
24 BOOST
VON
2
23 TG
PGOOD
3
22 SW1
VRNG
4
21 SENSE +
ITH
5
20 SENSE –
SGND1
6
19 PGND1
ION
7
18 BG
VFB1
8
17 INTVCC
VREF
9
16 VIN1
SHDN 10
15 VIN2
SGND2 11
VFB2 12
LTC3718EG
14 PGND2
13 SW2
G PACKAGE
24-LEAD PLASTIC SSOP
TJMAX = 125°C, θJA = 130°C/ W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN1 = 15V, VIN2 = 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
Input DC Supply Current (VIN1)
Normal
Shutdown Supply Current
VRUN/SS = 0V
VFB1
Feedback Voltage Accuracy
ITH = 1.2V (Note 3)
∆VFB1(LINE)
Feedback Voltage Line Regulation
VIN1 = 4V to 36V, ITH = 1.2V (Note 3)
∆VFB1(LOAD)
Feedback Voltage Load Regulation
ITH = 0.5V to 1.9V (Note 3)
gm(EA)
Error Amplifier Transconductance
ITH = 1.2V (Note 3)
tON
On-Time
ION = 60µA, VON = 1.5V
ION = 30µA, VON = 1.5V
tON(MIN)
Minimum On-Time
ION = 180µA
tOFF(MIN)
Minimum Off-Time
VSENSE(MAX)
Maximum Current Sense Threshold
VPGND – VSW1 (Source)
VRNG = 1V, VFB1 = VREF/2 – 50mV
VRNG = 0V, VFB1 = VREF/2 – 50mV
VRNG = INTVCC, VFB1 = VREF/2 – 50mV
VSENSE(MIN)
Minimum Current Sense Threshold
VPGND – VSW1 (Sink)
VRNG = 1V, VFB1 = VREF/2 + 50mV
VRNG = 0V, VFB1 = VREF/2 + 50mV
VRNG = INTVCC, VFB1 = VREF/2 + 50mV
∆VFB1(OV)
Output Overvoltage Fault Threshold
∆VFB1(UV)
Output Undervoltage Fault Threshold
VRUN/SS(ON)
RUN Pin Start Threshold
VRUN/SS(LE)
RUN Pin Latchoff Enable
MIN
TYP
MAX
UNITS
1000
15
2000
30
µA
µA
0.1
0.65
Buck Regulator
IQ(VIN1)
●
– 0.65
0.002
– 0.05
– 0.3
%
0.93
1.13
1.33
mS
200
400
250
500
300
600
ns
ns
●
●
●
●
50
100
ns
300
400
ns
108
76
148
135
95
185
162
114
222
mV
mV
mV
–140
–97
– 200
–165
–115
– 235
–190
–133
– 270
mV
mV
mV
8
10
12
%
– 25
●
RUN/SS Pin Rising
%
%/V
0.8
%
1.5
2
V
4
4.5
V
3718fa
2
LTC3718
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VIN1 = 15V, VIN2 = 1.5V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VRUN/SS(LT)
RUN Pin Latchoff Threshold
RUN/SS Pin Falling
IRUN/SS(C)
Soft-Start Charge Current
VRUN/SS = 0V
IRUN/SS(D)
Soft-Start Discharge Current
VRUN/SS = 4.5V, VFB = 0V
VIN(UVLO)
VIN1 Undervoltage Lockout
VIN Falling
VIN Rising
TG RUP
TG Driver Pull-Up On Resistance
TG High
TG RDOWN
TG Driver Pull-Down On Resistance
TG Low
BG RUP
BG Driver Pull-Up On Resistance
BG High
BG RDOWN
BG Driver Pull-Down On Resistance
TG tr
TG Rise Time
TG tf
MIN
TYP
MAX
UNITS
3.5
4.2
V
–1.2
–3
µA
1.8
3
µA
3.4
3.5
3.9
4.0
V
V
2
3
Ω
2
3
Ω
3
4
Ω
BG Low
1
2
CLOAD = 3300pF
20
ns
TG Fall Time
CLOAD = 3300pF
20
ns
BG tr
BG Rise Time
CLOAD = 3300pF
20
ns
BG tf
BG Fall Time
CLOAD = 3300pF
20
ns
– 0.5
0.8
●
●
Ω
Internal VCC Regulator
VINTVCC
Internal VCC Voltage
6V < VIN1 <30V
∆VLDO(LOAD)
Internal VCC Load Regulation
ICC = 0mA to 20mA
●
4.7
5
5.3
V
– 0.1
±2
%
PGOOD Output
∆VFB1H
PGOOD Upper Threshold
VFB1 = Rising
8
10
12
%
∆VFB1L
PGOOD Lower Threshold
VFB1 = Falling
–8
–10
–12
%
∆VFB1(HYS)
PGOOD Hysterisis
VFB1 = Returning
1
2
%
VPGL
PGOOD Low Voltage
IPGOOD = 5mA
0.15
0.4
V
0.9
1.5
V
10
V
3
0.01
4.5
1
mA
µA
1.23
1.23
1.255
1.26
V
V
27
80
nA
Boost Regulator
VIN2(MIN)
Minimum Operating Voltage
VIN2(MAX)
Maximum Operating Voltage
IQ(VIN2)
Input DC Supply Current (VIN2)
Normal
Shutdown Supply Current
VSHDN=0V
VFB2 Feedback Voltage
0°C < T < 70°C
VFB2
●
IVFB2
VFB2 Pin Bias Current
∆VFB2(LINE)
Boost Reference Line Regulation
1.5V < VIN2 < 10V
fBOOST
BOOST Switching Frequency
0°C < T < 70°C
1.205
1.20
●
●
DCBOOST(MAX)
BOOST Maximum Duty Cycle
ILIM(BOOST)
BOOST Switch Current Limit
(Note 5)
VCESAT(BOOST)
BOOST Switch VCESAT
ISW = 300mA
ISWLKG(BOOST)
BOOST Switch Leakage Current
VSW = 5V
VSHDN(HIGH)
SHDN Input Voltage High
VSHDN(LOW)
SHDN Input Voltage Low
ISHDN
SHDN Pin Bias Current
1.0
0.9
0.02
0.2
%/V
1.4
1.4
1.8
1.9
MHz
MHz
82
86
%
500
800
mA
300
350
mV
0.01
1
µA
1
VSHDN = 3V
VSHDN = 0V
V
25
0.01
0.3
V
50
0.1
µA
µA
3718fa
3
LTC3718
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: TJ is calculated from the ambient temperature TA and power
dissipation PD as follows:
LTC3718EG: TJ = TA + (PD • 130°C/W)
Note 3: The LTC3718 is tested in a feedback loop that adjusts VFB1 to
achieve a specified error amplifier output voltage (ITH).
Note 4: The LTC3718 is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 5: Current limit guaranteed by design and/or correlation to static test.
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Boost Converter Oscillator
Frequency vs Temperature
2.00
1000
50
TA = 25°C
1.50
VIN = 1.5V
1.25
1.00
0.75
0.50
900
40
CURRENT LIMIT (mA)
SHDN PIN BIAS CURRENT (µA)
VIN = 5V
1.75
SWITCHING FREQUENCY (MHz)
Boost Converter Current Limit
vs Duty Cycle
SHDN Pin Current vs VSHDN
30
20
10
0.25
0
–25
0
25
50
TEMPERATURE (°C)
75
0
100
1
2
3
4
SHDN PIN VOLTAGE (V)
600
25°C
500
–40°C
400
200
5
10
20
30
40
50
60
DUTY CYCLE (%)
70
3718 G02
3718 G01
VFB2, Feedback Pin Voltage
VOUT/VIN Tracking Ratio vs Input
Voltage
100
90
80
3718 G03
Efficiency vs Load Current
1.25
50.00
VIN = 2.5V
VOUT = 1.25V
49.95
LOAD = 0A
80
1.24
49.90
1.23
1.22
VOUT/VIN (%)
70
EFFICIENCY (%)
FEEDBACK PIN VOLTAGE (V)
70°C
700
300
0
–50
60
50
40
30
LOAD = 1A
49.85
LOAD = 10A
49.80
49.75
20
1.21
–25
0
25
50
TEMPERATURE (°C)
49.70
10
FIGURE 1 CIRCUIT
1.20
–50
800
75
100
3718 G04
0
0.01
FIGURE 1 CIRCUIT
0.1
1
10
LOAD CURRENT (A)
FIGURE 1 CIRCUIT
100
3718 G05/TA01a
49.65
1.5
1.7
1.9 2.1 2.3 2.5
INPUT VOLTAGE (V)
2.7
2.9
3718 G06
3718fa
4
LTC3718
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Frequency vs Input Voltage
Load Regulation
450
0
400
LOAD = 10A
VIN = 2.5V
VOUT = 1.25V
–0.1
300
250
∆VOUT/VOUT (%)
FREQUENCY (kHz)
350
LOAD = 0A
200
150
–0.2
–0.3
–0.4
100
–0.5
VOUT = 1.25V
FIGURE 1 CIRCUIT
50
FIGURE 1 CIRCUIT
–0.6
0
1.5
1.7
1.9 2.1 2.3 2.5
INPUT VOLTAGE (V)
2.7
2.9
1
0
2
3 4 5 6 7
LOAD CURRENT (A)
3718 G07
VOUT
1V/DIV
IL
5A/DIV
IL
2A/DIV
VIN = 2.5V
20µs/DIV
VOUT = 1.25V
LOAD = 500mA TO 10A STEP
FIGURE 1 CIRCUIT
VIN = 2.5V
4ms/DIV
VOUT = 1.25V
LOAD = 0.2Ω
FIGURE 1 CIRCUIT
3718 G10.eps
On-Time vs VON Voltage
On-Time vs Temperature
300
IION = 30µA
3718 G09.eps
On-Time vs ION Current
10k
VVON = 0V
IION = 30µA
250
600
400
200
ON-TIME (ns)
ON-TIME (ns)
800
ON-TIME (ns)
10
Start-Up Response
VOUT
200mV/DIV
150
100
200
0
9
3718 G08
Load-Step Transient
1000
8
1k
100
50
0
2
1
VON VOLTAGE (V)
3
3718 G11
0
–50 –25
10
50
25
75
0
TEMPERATURE (°C)
100
125
3718 G12
1
10
ION CURRENT (µA)
100
3718 G13
3718fa
5
LTC3718
U W
TYPICAL PERFOR A CE CHARACTERISTICS
–0.1
2
–0.2
–0.3
5.0
RUN/SS THRESHOLD (V)
3
FCB PIN CURRENT (µA)
∆INTVCC (%)
0
PULL-DOWN CURRENT
1
0
PULL-UP CURRENT
LATCHOFF ENABLE
4.0
3.5
0
10
30
40
20
INTVCC LOAD CURRENT (mA)
LATCHOFF THRESHOLD
–2
–50 –25
50
50
25
0
75
TEMPERATURE (°C)
100
Undervoltage Lockout Threshold
vs Temperature
3.0
2.5
75
0
25
50
TEMPERATURE (C)
100
125
300
250
200
150
100
50
0
0.50
0.75
1.00
1.25 1.50
VRNG (V)
1.75
3718 G17
2.00
100
125
160
140
120
100
80
60
40
20
0
2.0
2.2
2.4
2.6 2.8 3.0
RUN/SS (V)
3.2
3.4 3.6
2718 G19
3718 G18
Error Amplifier gm
vs Temperature
Maximum Current Sense Threshold
vs Temperature, VRNG = 1V
180
1.50
160
1.40
140
1.30
120
1.20
gm (ms)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
75
0
25
50
TEMPERATURE (°C)
Maximum Current Sense Threshold
vs RUN/SS Voltage, VRNG = 1V
MAXIMUM CURRENT SENSE THRESHOLD (mV)
MAXIMUM CURRENT SENSE THRESHOLD (mV)
3.5
–25
3718 G16
Maximum Current Sense Threshold
vs VRNG Voltage
4.0
2.0
–50 –25
3.0
–50
125
3718 G15
3718 G14
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
4.5
–1
–0.4
–0.5
RUN/SS Latchoff Thresholds
vs Temperature
RUN/SS Latchoff Thresholds
vs Temperature
INTVCC Load Regulation
100
80
1.10
1.00
60
0.90
40
0.80
20
0
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
0.70
–50 –30 –10 10 30 50 70 90 110 130
TEMPERATURE (°C)
3718 G20
3718 G21
3718fa
6
LTC3718
U
U
U
PI FU CTIO S
RUN/SS (Pin 1): Run Control and Soft-Start Input. A
capacitor to ground at this pin sets the ramp time to full
output current (approximately 3s/µF) and the time delay
for overcurrent latchoff (see Applications Information).
Forcing this pin below 0.8V shuts down the device.
VON (Pin 2): On-Time Voltage Input. Voltage trip point for
the on-time comparator. Tying this pin to the output
voltage makes the on-time proportional to VOUT. The
comparator input defaults to 0.7V when the pin is grounded,
2.4V when the pin is tied to INTVCC.
PGOOD (Pin 3): Power Good Output. Open-drain logic
output that is pulled to ground when the output voltage of
the buck section is not within ±10% of the regulation point.
VFB2 (Pin 12): Boost Converter Feedback. The VFB2 pin is
connected to INTVCC through a resistor divider to set the
voltage on INTVCC. Set INTVCC voltage according to:
VINTVCC = 1.23V(1 + RF2/RF1)
SW2 (Pin 13): Boost Converter Switch Pin. Connect
inductor/diode for boost converter portion here. Minimize
trace area at this pin to keep EMI down.
PGND (Pins 14, 19): Power Ground. Connect these pins
closely to the source of the bottom N-channel MOSFET,
the (–) terminal of CVCC and the (–) terminal of CIN.
VIN2 (Pin 15): Input Supply Pin for Boost Converter
Portion of LTC3718. Must be locally bypassed.
VRNG (Pin 4): Sense Voltage Range Input. The voltage at
this pin is ten times the nominal sense voltage at maximum output current and can be set from 0.5V to 2V by a
resistive divider from INTVCC. The nominal sense voltage
defaults to 70mV when this pin is tied to ground, 140mV
when tied to INTVCC.
VIN1 (Pin 16): Main Input Supply. Decouple this pin to
PGND with at least a 1µF ceramic capacitor.
ITH (Pin 5): Current Control Threshold and Error Amplifier
Compensation Point. The current comparator threshold
increases with this control voltage. The voltage ranges
from 0V to 2.4V with 1.2V corresponding to zero sense
voltage (zero current).
BG (Pin 18): Bottom Gate Drive. Drives the gate of the
bottom N-channel MOSFET between ground and INTVCC.
SGND (Pins 6, 11): Signal Ground. All small-signal components and compensation components should connect to
this ground, which in turn connects to PGND at one point.
ION (Pin 7): On-Time Current Input. Tie a resistor from VIN
to this pin to set the one-shot timer current and thereby set
the switching frequency.
INTVCC (Pin 17): Internal Regulator Output. The driver and
control circuits are powered from this voltage when VIN is
greater than 5V. Decouple this pin to power ground with a
minimum of 4.7µF low ESR tantalum or ceramic capacitor.
SENSE – (Pin 20): Negative Current Sense Comparator
Input. The (–) input to the current comparator is normally
connected to power ground unless using a resistive divider from INTVCC (see Applications Information).
SENSE + (Pin 21): Positive Current Sense Comparator
Input. The (+) input to the current comparator is normally
connected to the SW node unless using a sense resistor
(see Applications Information).
VFB1 (Pin 8): Error Amplifier Feedback Input. This pin
connects the negative error amplifier input to VOUT.
SW1 (Pin 22): Switch Node. The (–) terminal of the
bootstrap capacitor CB connects here. This pin swings
from a diode voltage drop below ground up to VIN.
VREF (Pin 9): Positive Input of Internal Error Amplifier.
Reference voltage for output voltage, power good threshold, and short-circuit shutdown threshold. The output
voltage is set to VREF/2.
TG (Pin 23): Top Gate Drive. Drives the top N-channel
MOSFET with a voltage swing equal to INTVCC superimposed on the switch node voltage SW.
SHDN (Pin 10): Shutdown, Active Low. Tie to 1V or more
to enable boost converter portion of the LTC3718. Ground
to shut down.
BOOST (Pin 24): Boosted Floating Driver Supply. The (+)
terminal of the bootstrap capacitor CB connects here. This
pin swings from a diode voltage drop below INTVCC up to
VIN + INTVCC.
3718fa
7
LTC3718
W
FU CTIO AL DIAGRA S
U
U
RON
VIN
VON
2
16 VIN1
7 ION
+
CIN
0.7V
2.4V
0.8V
REF
5V
REG
BOOST
tON =
24
VVON
(10pF)
IION
R
S
Q
SW1
22
+
ICMP
SENSE+
SWITCH
LOGIC
IREV
L1
21
–
–
M1
23
ON
20k
+
CB
TG
VOUT
DB
INTVCC
17
SHDN
1.4V
+
OV
COUT
CVCC
BG
M2
18
VRNG
PGND1
4
×
19
SENSE –
20
0.7V
PGOOD
3
5.7µA
1
240k
+
Q2
3/10VREF
UV
–
ITHB
R3
20k
VFB1
8
Q1
R4
40k
+
Q5
SGND1
OV
6
–
–
SS
RUN
SHDN
+
1.2µA
EA
+
–
–
+
VREF 9
11/30VREF
6V
0.6V
R2
80k
5 ITH
R1
40k
RC
CC1
0.6V
1 RUN/SS CSS
3718 FD01
VIN2 15
R5
40k
R6
40k
VOUT2
13 SW2
+
A1
gm
R7
(EXTERNAL)
VFB2
FB2 12
–
–
Q1
R8
(EXTERNAL)
Q2
x10
RC2
RAMP
GENERATOR
Σ
+
COMPARATOR
A2
R
FF
S
DRIVER
Q3
Q
+
CC2
R9
30k
R10
140k
0.15Ω
–
1.4MHz
OSCILLATOR
SHDN
11 SGND2
10
SHUTDOWN
14 PGND2
3718 FD02
3718fa
8
LTC3718
U
OPERATIO
Main Control Loop
INTVCC Power
The LTC3718 is a current mode controller for DC/DC
step-down converters designed to operate from low input
voltages. It incorporates a boost converter with a buck
regulator.
Power for the top and bottom MOSFET drivers and most
of the internal controller circuitry is derived from the
INTVCC pin. The top MOSFET driver is powered from a
floating bootstrap capacitor CB. This capacitor is recharged from INTVCC through an external Schottky diode
DB when the top MOSFET is turned off.
Buck Regulator Operation
In normal operation, the top MOSFET is turned on for a
fixed interval determined by a one-shot timer OST. When
the top MOSFET is turned off, the bottom MOSFET is
turned on until the current comparator ICMP trips, restarting the one-shot timer and initiating the next cycle. Inductor current is determined by sensing the voltage between
the SENSE+ and SENSE– pins using the bottom MOSFET
on-resistance . The voltage on the ITH pin sets the comparator threshold corresponding to inductor valley current. The error amplifier EA adjusts this voltage by comparing the feedback signal VFB1 from the output voltage
with an internal reference generated from one half of the
voltage on VREF. If the load current increases, it causes a
drop in the feedback voltage relative to the reference. The
ITH voltage then rises until the average inductor current
again matches the load current.
The operating frequency is determined implicitly by the
top MOSFET on-time and the duty cycle required to
maintain regulation. The one-shot timer generates an ontime that is proportional to the ideal duty cycle, thus
holding frequency approximately constant with changes
in VIN. The nominal frequency can be adjusted with an
external resistor RON.
Overvoltage and undervoltage comparators OV and UV
pull the PGOOD output low if the output feedback voltage
exits a ±10% window around the regulation point.
Furthermore, in an overvoltage condition, M1 is turned off
and M2 is turned on and held on until the overvoltage
condition clears.
Pulling the RUN/SS pin low forces the controller into its
shutdown state, turning off both M1 and M2. Releasing the
pin allows an internal 1.2µA current source to charge up an
external soft-start capacitor CSS. When this voltage reaches
1.5V, the controller turns on and begins switching, but
with the ITH voltage clamped at approximately 0.6V below
the RUN/SS voltage. As CSS continues to charge, the softstart current limit is removed.
Boost Regulator Operation
The 5V power source for INTVCC can be provided by a
current mode, internally compensated fixed frequency
step-up switching regulator that has been incorporated
into the LTC3718.
Operation can be best understood by referring to the
Functional Diagrams. Q1 and Q2 form a bandgap reference core whose loop is closed around the output of the
regulator. The voltage drop across R5 and R6 is low
enough such that Q1 and Q2 do not saturate, even when
VIN2 is 1V. When there is no load, VFB2 rises slightly above
1.23V, causing VC (the error amplifier’s output) to decrease. Comparator A2’s output stays high, keeping switch
Q3 in the off state. As increased output loading causes the
VFB2 voltage to decrease, A1’s output increases. Switch
current is regulated directly on a cycle-by-cycle basis by
the VC node. The flip-flop is set at the beginning of each
switch cycle, turning on the switch. When the summation
of a signal representing switch current and a ramp generator (introduced to avoid subharmonic oscillations at
duty factors greater than 50%) exceeds the VC signal,
comparator A2 changes state, resetting the flip-flop and
turning off the switch. More power is delivered to the
output as switch current is increased. The output voltage,
attenuated by external resistor divider R7 and R8, appears
at the VFB2 pin, closing the overall loop. Frequency compensation is provided internally by RC and CC. Transient
response can be optimized by the addition of a phase lead
capacitor CPL in parallel with R7 in applications where
large value or low ESR output capacitors are used.
As the load current is decreased, the switch turns on for
a shorter period each cycle. If the load current is further
decreased, the boost converter will skip cycles to maintain output voltage regulation. If the VFB2 pin voltage is
increased significantly above 1.23V, the boost converter
will enter a low power state.
3718fa
9
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
A typical LTC3718 application circuit is shown in
Figure 1. External component selection is primarily determined by the maximum load current and begins with
the selection of the sense resistance and power MOSFET
switches. The LTC3718 uses the on-resistance of the
synchronous power MOSFET for determining the inductor current. The desired amount of ripple current and
operating frequency largely determines the inductor value.
Finally, CIN is selected for its ability to handle the large
RMS current into the converter and COUT is chosen with
low enough ESR to meet the output voltage ripple and
transient specification.
the SENSE + and SENSE – pins as a Kelvin connection to the
sense resistor with SENSE + at the source of the bottom
MOSFET and the SENSE – pin to PGND1. Using a sense
resistor provides a well defined current limit, but adds cost
and reduces efficiency. Alternatively, one can eliminate the
sense resistor and use the bottom MOSFET as the current
sense element by simply connecting the SENSE + pin to the
drain and the SENSE – pin to the source of the bottom
MOSFET. This improves efficiency, but one must carefully
choose the MOSFET on-resistance as discussed in a later
section.
Maximum Sense Voltage and VRNG Pin
The LTC3718 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V(BR)DSS,
threshold voltage V(GS)TH, on-resistance RDS(ON), reverse
transfer capacitance CRSS and maximum current IDS(MAX).
Inductor current is determined by measuring the voltage
across a sense resistance that appears between the
SENSE + and SENSE – pins. The maximum sense voltage
is set by the voltage applied to the VRNG pin and is equal
to approximately (0.13)VRNG for sourcing current and
(0.17)VRNG for sinking current. The current mode control
loop will not allow the inductor current valleys to exceed
(0.13)VRNG/RSENSE for sourcing current and (0.17)VRNG
for sinking current. In practice, one should allow some
margin for variations in the LTC3718 and external component values and a good guide for selecting the sense
resistance is:
RSENSE =
VRNG
10 • IOUT (MAX)
when VRNG = 0.5 – 2V.
An external resistive divider from INTVCC can be used to
set the voltage of the VRNG pin between 0.5V and 2V
resulting in nominal sense voltages of 50mV to 200mV.
Additionally, the VRNG pin can be tied to SGND or INTVCC
in which case the nominal sense voltage defaults to 70mV
or 140mV, respectively. The maximum allowed sense
voltage is about 1.3 times this nominal value for positive
output current and 1.7 times the nominal value for negative output current.
Connecting the SENSE + and SENSE – Pins
The LTC3718 can be used with or without a sense resistor.
When using a sense resistor, it is placed between the
source of the bottom MOSFET M2 and ground. Connect
Power MOSFET Selection
The gate drive voltage is set by the 5V INTVCC supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3718 applications.
When the bottom MOSFET is used as the current sense
element, particular attention must be paid to its
on-resistance. MOSFET on-resistance is typically specified with a maximum value RDS(ON)(MAX) at 25°C. In this
case, additional margin is required to accommodate the
rise in MOSFET on-resistance with temperature:
RDS(ON)(MAX) =
RSENSE
ρT
The ρT term is a normalization factor (unity at 25°C)
accounting for the significant variation in on-resistance
with temperature, typically about 0.4%/°C as shown in
Figure 2. For a maximum junction temperature of 100°C,
using a value ρT = 1.3 is reasonable.
The power dissipated by the top and bottom MOSFETs
strongly depends upon their respective duty cycles and
the load current. During normal operation, the duty cycles
for the MOSFETs are:
3718fa
10
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
ρT NORMALIZED ON-RESISTANCE
2.0
tON =
1.5
Tying a resistor RON from VIN to the ION pin yields an ontime inversely proportional to VIN. For a step-down
converter, this results in approximately constant frequency operation as the input supply varies:
1.0
0.5
f=
0
– 50
50
100
0
JUNCTION TEMPERATURE (°C)
150
3718 F02
Figure 2. RDS(ON) vs Temperature
VOUT
VIN
V –V
= IN OUT
VIN
D TOP =
DBOT
VVON
(10pF )
IION
The resulting power dissipation in the MOSFETs at maximum output current are:
PTOP = DTOP IOUT(MAX)2 ρT(TOP) RDS(ON)(MAX)
+ k VIN2 IOUT(MAX) CRSS f
PBOT = DBOT IOUT(MAX)2 ρT(BOT) RDS(ON)(MAX)
I2R
Both MOSFETs have
losses and the top MOSFET
includes an additional term for transition losses, which are
largest at high input voltages. The constant k = 1.7A–1 can
be used to estimate the amount of transition loss. The
bottom MOSFET losses are greatest when the bottom duty
cycle is near 100%, during a short-circuit or at high input
voltage.
Operating Frequency
The choice of operating frequency is a tradeoff between
efficiency and component size. Low frequency operation
improves efficiency by reducing MOSFET switching losses
but requires larger inductance and/or capacitance in order
to maintain low output ripple voltage.
The operating frequency of LTC3718 applications is determined implicitly by the one-shot timer that controls the
on-time tON of the top MOSFET switch. The on-time is set
by the current into the ION pin and the voltage at the VON
pin according to:
VOUT
[Hz]
VVONRON (10pF )
To hold frequency constant during output voltage changes,
tie the VON pin to VOUT. The VON pin has internal clamps
that limit its input to the one-shot timer. If the pin is tied
below 0.7V, the input to the one-shot is clamped at 0.7V.
Similarly, if the pin is tied above 2.4V, the input is clamped
at 2.4V.
Because the voltage at the ION pin is about 0.7V, the
current into this pin is not exactly inversely proportional to
VIN, especially in applications with lower input voltages.
To account for the 0.7V drop on the ION pin, the following
equation can be used to calculate frequency:
f=
(VIN − 0.7V) • VOUT
VVON • VIN • RON (10pF )
To correct for this error, an additional resistor RON2
connected from the ION pin to the 5V INTVCC supply will
further stabilize the frequency.
RON2 =
5V
RON
0.7V
Changes in the load current magnitude will also cause
frequency shift. Parasitic resistance in the MOSFET
switches and inductor reduce the effective voltage across
the inductance, resulting in increased duty cycle as the
load current increases. By lengthening the on-time slightly
as current increases, constant frequency operation can be
maintained. This is accomplished with a resistive divider
from the ITH pin to the VON pin and VOUT. The values
required will depend on the parasitic resistances in the
specific application. A good starting point is to feed about
25% of the voltage change at the ITH pin to the VON pin as
shown in Figure 3a. Place capacitance on the VON pin to
3718fa
11
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
RVON1
30k
RVON1
3k
VON
VOUT
CVON
0.01µF
RVON2
100k
LTC3718
RC
ITH
VOUT
10k
CVON
0.01µF
RVON2
10k
INTVCC
VON
LTC3718
RC
Q1
2N5087
ITH
CC
CC
(3a)
3718 F03
(3b)
Figure 3. Adjusting Frequency Shift with Load Current Changes
filter out the ITH variations at the switching frequency. The
resistor load on ITH reduces the DC gain of the error amp
and degrades load regulation, which can be avoided by
using the PNP emitter follower of Figure 3b.
Inductor L1 Selection
Given the desired input and output voltages, the inductor
value and operating frequency determine the ripple
current:
 V  V 
∆IL =  OUT   1 − OUT 
VIN 
 fL  
Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). The largest ripple current
occurs at the highest VIN. To guarantee that ripple current
does not exceed a specified maximum, the inductance
should be chosen according to:
 VOUT  
VOUT 
L=
  1−

 f ∆IL(MAX)   VIN(MAX) 
Once the value for L is known, the type of inductor must
be selected. High efficiency converters generally cannot
afford the core loss found in low cost powdered iron
cores, forcing the use of more expensive ferrite,
molypermalloy or Kool Mµ® cores. A variety of inductors
designed for high current, low voltage applications are
Kool Mµ is a registered trademark of Magnetics, Inc.
available from manufacturers such as Sumida, Panasonic, Coiltronics, Coilcraft and Toko.
Schottky Diode D1, D2 Selection
The Schottky diodes, D1 and D2, shown in Figure 1
conduct during the dead time between the conduction of
the power MOSFET switches. It is intended to prevent the
body diodes of the top and bottom MOSFETs from turning
on and storing charge during the dead time, which can
cause a modest (about 1%) efficiency loss. The diodes can
be rated for about one half to one fifth of the full load current
since they are on for only a fraction of the duty cycle. In
order for the diode to be effective, the inductance between
it and the bottom MOSFET must be as small as possible,
mandating that these components be placed adjacently.
The diodes can be omitted if the efficiency loss is tolerable.
CIN and COUT Selection
The input capacitance CIN is required to filter the square
wave current at the drain of the top MOSFET. Use a low
ESR capacitor sized to handle the maximum RMS current.
IRMS ≅ IOUT (MAX)
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT(MAX) / 2. This simple worst-case condition is
commonly used for design because even significant
deviations do not offer much relief. Note that ripple
current ratings from capacitor manufacturers are often
based on only 2000 hours of life which makes it advisable
to derate the capacitor.
The selection of COUT is primarily determined by the ESR
required to minimize voltage ripple and load step
3718fa
12
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
transients. The output ripple ∆VOUT is approximately
bounded by:

1 
∆VOUT ≤ ∆IL  ESR +

8fC OUT 

Since ∆IL increases with input voltage, the output ripple is
highest at maximum input voltage. Typically, once the ESR
requirement is satisfied, the capacitance is adequate for
filtering and has the necessary RMS current rating.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount
packages. Special polymer capacitors offer very low ESR
but have lower capacitance density than other types.
Tantalum capacitors have the highest capacitance density
but it is important to only use types that have been surge
tested for use in switching power supplies. Aluminum
electrolytic capacitors have significantly higher ESR, but
can be used in cost-sensitive applications providing that
consideration is given to ripple current ratings and long
term reliability. Ceramic capacitors have excellent low
ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of
ceramic capacitors with trace inductance can also lead to
significant ringing. When used as input capacitors, care
must be taken to ensure that ringing from inrush currents
and switching does not pose an overvoltage hazard to the
power switches and controller. To dampen input voltage
transients, add a small 5µF to 50µF aluminum electrolytic
capacitor with an ESR in the range of 0.5Ω to 2Ω. High
performance through-hole capacitors may also be used,
but an additional ceramic capacitor in parallel is recommended to reduce the effect of their lead inductance.
Top MOSFET Driver Supply (CB, DB)
An external bootstrap capacitor CB connected to the BOOST
pin supplies the gate drive voltage for the topside MOSFET.
This capacitor is charged through diode DB from INTVCC
when the switch node is low. When the top MOSFET turns
on, the switch node rises to VIN and the BOOST pin rises
to approximately VIN + INTVCC. The boost capacitor needs
to store about 100 times the gate charge required by the
top MOSFET. In most applications a 0.1µF to 0.47µF X5R
or X7R dielectric capacitor is adequate.
Fault Condition: Current Limit
The maximum inductor current is inherently limited in a
current mode controller by the maximum sense voltage. In
the LTC3718, the maximum sense voltage is controlled by
the voltage on the VRNG pin. With valley current control,
the maximum sense voltage and the sense resistance
determine the maximum allowed inductor valley current.
The corresponding output current limit is:
ILIMITPOSITIVE =
VSNS(MAX) 1
+ ∆IL
RDS(ON)ρT 2
ILIMITNEGATIVE =
VSNS(MIN) 1
− ∆IL
RDS(ON)ρT 2
The current limit value should be checked to ensure that
ILIMIT(MIN) > IOUT(MAX). The minimum value of current limit
generally occurs with the largest VIN at the highest ambient temperature, conditions that cause the largest power
loss in the converter. Note that it is important to check for
self-consistency between the assumed MOSFET junction
temperature and the resulting value of ILIMIT which heats
the MOSFET switches.
Caution should be used when setting the current limit
based upon the RDS(ON) of the MOSFETs. The maximum
current limit is determined by the minimum MOSFET onresistance. Data sheets typically specify nominal and
maximum values for RDS(ON), but not a minimum. A
reasonable assumption is that the minimum RDS(ON) lies
the same amount below the typical value as the maximum
lies above it. Consult the MOSFET manufacturer for further
guidelines.
Minimum Off-time and Dropout Operation
The minimum off-time tOFF(MIN) is the smallest amount of
time that the LTC3718 is capable of turning on the bottom
MOSFET, tripping the current comparator and turning the
MOSFET back off. This time is generally about 250ns. The
minimum off-time limit imposes a maximum duty cycle of
tON/(tON + tOFF(MIN)). If the maximum duty cycle is reached,
3718fa
13
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
due to a dropping input voltage for example, then the
output will drop out of regulation. The minimum input
voltage to avoid dropout is:
VIN(MIN) = VOUT
tON + tOFF(MIN)
tON
Soft-Start and Latchoff with the RUN/SS Pin
Output Voltage Programming
When VFB is connected to VOUT, the output voltage is
regulated to one half of the voltage at the VREF pin. A
resistor connected between VFB and VOUT can be used to
further adjust the output voltage according to the following equation:
 60k + RFB 
VOUT = VREF 

 120k 
RFB
249k
VFB1
LTC3718
RFB
499k
VREF
The RUN/SS pin provides a means to shut down the
LTC3718 as well as a timer for soft-start and overcurrent
latchoff. Pulling the RUN/SS pin below 0.8V puts the
LTC3718 into a low quiescent current shutdown
(IQ < 30µA). Releasing the pin allows an internal 1.2µA
current source to charge up the external timing capacitor
CSS. If RUN/SS has been pulled all the way to ground,
there is a delay before starting of about:
tDELAY =
If VREF exceeds 3V, resistors should be placed in series
with the VREF pin and the VFB pin to avoid exceeding the
input common mode range of the internal error amplifier.
To maintain the VOUT = VREF/2 relationship, the resistor in
series with the VREF pin should be made twice as large as
the resistor in series with the VFB pin.
VOUT
Alternately, the external buffer circuit shown in Figure 5
can be used. Note that the bipolar devices reduce the
signal swing at the MOSFET gate.
VREF
3718 F04
(
)
1.5V
C SS = 1.3s/µF C SS
1.2µA
When the voltage on RUN/SS reaches 1.5V, the LTC3718
begins operating with a clamp on ITH of approximately
0.9V. As the RUN/SS voltage rises to 3V, the clamp on ITH
is raised until its full 2.4V range is available. This takes an
additional 1.3s/µF, during which the load current is folded
back. During start-up, the maximum load current is reduced until either the RUN/SS pin rises to 3V or the output
reaches 75% of its final value. The pin can be driven from
logic as shown in Figure 6. Diode D1 reduces the start
delay while allowing CSS to charge up slowly for the softstart function.
INTVCC
Figure 4
External Gate Drive Buffers
3.3V OR 5V
The LTC3718 drivers are adequate for driving up to about
30nC into MOSFET switches with RMS currents of 50mA.
Applications with larger MOSFET switches or operating at
frequencies requiring greater RMS currents will benefit
from using external gate drive buffers such as the LTC1693.
10Ω
GATE
OF M1
Q2
FMMT720
SW
10Ω
GATE
OF M2
BG
Q4
FMMT720
PGND
Figure 5. Optional External Gate Driver
RUN/SS
RSS*
D2*
RUN/SS
CSS
CSS
3718 F06
*OPTIONAL TO OVERRIDE
OVERCURRENT LATCHOFF
(6b)
Figure 6. RUN/SS Pin Interfacing with Latchoff Defeated
Q3
FMMT619
Q1
FMMT619
D1
(6a)
INTVCC
BOOST
TG
RSS*
VIN
3718 F05
After the controller has been started and given adequate
time to charge up the output capacitor, CSS is used as a
short-circuit timer. After the RUN/SS pin charges above
4V, if the output voltage falls below 75% of its regulated
value, then a short-circuit fault is assumed. A 1.8µA current then begins discharging CSS. If the fault condition
3718fa
14
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
persists until the RUN/SS pin drops to 3.5V, then the controller turns off both power MOSFETs, shutting down the
converter permanently. The RUN/SS pin must be actively
pulled down to ground in order to restart operation.
The overcurrent protection timer requires that the softstart timing capacitor CSS be made large enough to guarantee that the output is in regulation by the time CSS has
reached the 4V threshold. In general, this will depend upon
the size of the output capacitance, output voltage and load
current characteristic. A minimum soft-start capacitor can
be estimated from:
CSS > COUT VOUT RSENSE (10 – 4 [F/V s])
Generally 0.1µF is more than sufficient.
Overcurrent latchoff operation is not always needed or
desired. The feature can be overridden by adding a pullup current greater than 5µA to the RUN/SS pin. The
additional current prevents the discharge of C SS during a
fault and also shortens the soft-start period. Using a
resistor to VIN as shown in Figure 6a is simple, but slightly
increases shutdown current. Connecting a resistor to
INTVCC as shown in Figure 6b eliminates the additional
shutdown current, but requires a diode to isolate CSS. Any
pull-up network must be able to pull RUN/SS above the
4.2V maximum threshold of the latchoff circuit and overcome the 4µA maximum discharge current.
INTVCC Supply
The 5V supply that powers the drivers and internal circuitry within the LTC3718 can be supplied by either an
internal P-channel low dropout regulator if VIN is greater
than 5V or the internal boost regulator if VIN is less than 5V.
The INTVCC pin can supply up to 50mA RMS and must be
bypassed to ground with a minimum of 4.7µF tantalum or
other low ESR capacitor. Good bypassing is necessary to
supply the high transient currents required by the MOSFET
gate drivers. Applications using large MOSFETs with a
high input voltage and high frequency of operation may
cause the LTC3718 to exceed its maximum junction temperature rating or RMS current rating. In continuous mode
operation, this current is IGATECHG = f(Qg(TOP) + Qg(BOT)).
The junction temperature can be estimated from the
equations given in Note 2 of the Electrical Characteristics.
Inductor Selection for Boost Converter
For the boost converter, the inductance should be 4.7µH
for input voltages less then 3.3V and 10µH for inputs
above 3.3V. The inductor should have a saturation current
rating of approximately 0.5A or greater. A guide for selecting an inductor for the boost converter is to choose a ripple
current that is 40% of the current supplied by the boost
converter. To ensure that the ripple current doesn’t exceed
a specified amount, the inductance can be chosen according to the following equation:

VIN2(MAX) 
VIN2(MIN)  1 –

 VOUT (BOOST) 
L=
∆I • f
Diode D3 Selection
A Schottky diode is recommended for use in the boost
converter section. The Motorola MBR0520 is a very good
choice.
Boost Converter Output Capacitor
Because the LTC3718’s boost converter is internally compensated, loop stability must be carefully considered when
choosing its output capacitor. Small, low cost tantalum
capacitors have some ESR, which aids stability. However,
ceramic capacitors are becoming more popular, having
attractive characteristics such as near-zero ESR, small size
and reasonable cost. Simply replacing a tantalum output
capacitor with a ceramic unit will decrease the phase margin,
in some cases to unacceptable levels. With the addition of
a phase-lead capacitor and isolating resistor, the boost
converter portion of the LTC3718 can be used successfully with ceramic output capacitors.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Although all dissipative
elements in the circuit produce losses, four main sources
account for most of the losses in LTC3718 circuits:
3718fa
15
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
1. DC I2R losses. These arise from the resistances of the
MOSFETs, inductor and PC board traces and cause the
efficiency to drop at high output currents. In continuous
mode the average output current flows through L, but is
chopped between the top and bottom MOSFETs. If the two
MOSFETs have approximately the same RDS(ON), then the
resistance of one MOSFET can simply be summed with the
resistances of L and the board traces to obtain the DC I2R
loss. For example, if RDS(ON) = 0.01Ω and RL = 0.005Ω, the
loss will range from 1% up to 10% as the output current
varies from 1A to 10A for a 1.5V output.
2. Transition loss. This loss arises from the brief amount
of time the top MOSFET spends in the saturated region
during switch node transitions. It depends upon the input
voltage, load current, driver strength and MOSFET capacitance, among other factors. The loss is significant at input
voltages above 20V and can be estimated from:
Transition Loss ≅ (1.7A–1) VIN2 IOUT CRSS f
3. INTVCC current. This is the sum of the MOSFET driver
and control currents.
4. CIN loss. The input capacitor has the difficult job of
filtering the large RMS input current to the regulator. It
must have a very low ESR to minimize the AC I2R loss and
sufficient capacitance to prevent the RMS current from
causing additional upstream losses in fuses or batteries.
Other losses, including COUT ESR loss, Schottky diode D1
conduction loss during dead time and inductor core loss
generally account for less than 2% additional loss.
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased. If there is no change in input
current, then there is no change in efficiency.
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, VOUT immediately shifts by an amount
equal to ∆ILOAD (ESR), where ESR is the effective series
resistance of COUT. ∆ILOAD also begins to charge or
discharge COUT generating a feedback error signal used
by the regulator to return VOUT to its steady-state value.
During this recovery time, VOUT can be monitored for
overshoot or ringing that would indicate a stability
problem. The ITH pin external components shown in
Figure 1 will provide adequate compensation for most
applications. For a detailed explanation of switching
control loop theory see Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: VIN = 2.5V, VOUT = 1.25V ±100mV,
IOUT(MAX) = ±6A, f = 300kHz. First, calculate the timing
resistor with VON = VOUT:
RON =
2.5V − 0.7V
= 240k
(2.5V)(300kHz)(10pF )
Next, use a standard value of 237k and choose the inductor
for about 40% ripple current at the maximum VIN:
L=
 1.25V 
1.25V
1–
 = 0.87µH
(300kHz)(0.4)(6A) 
2.5V 
Selecting a standard value of 1µH results in a maximum
ripple current of:
∆IL =
 1.25V 
1.25V
1–
 = 2.1A
(300kHz)(1µH) 
2.5V 
Next, choose the synchronous MOSFET switch. Choosing
an IRF7811A (RDS(ON) = 0.013Ω, CRSS = 60pF, θJA =
50°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (6A)(1.3)(0.013Ω) = 101.4mV
Tying VRNG to 1V will set the current sense voltage range
for a nominal value of 100mV with current limit occurring
at 133mV. To check if the current limit is acceptable,
assume a junction temperature of about 10°C above a
50°C ambient with ρ60°C = 1.15:
ILIMIT ≥
133mV
1
+ (2.1A) = 9.9A
(1.15)(0.013Ω) 2
3718fa
16
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
ESR of 0.005Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
and double check the assumed TJ in the MOSFET:
2
PBOT
2.5V – 1.25V  9.9A 
=

 (1.15)(0.013Ω)
2.5V
 2 
∆VOUT(RIPPLE) = ∆IL(MAX) (ESR)
= (2.6A) (0.005Ω) = 13mV
= 0.18W
However, a 0A to 6A load step will cause an output change
of up to:
TJ = 50°C + (0.18W)(50°C/W) = 59°C
Now check the power dissipation of the top MOSFET at
current limit with ρ90°C = 1.35:
∆VOUT(STEP) = ∆ILOAD (ESR) = (6A) (0.005Ω) = 30mV
The inductor for the boost converter is selected by first
choosing an allowable ripple current. The boost converter
will be operating in discontinous mode. If we select a ripple
current of 170mA for the boost converter, then:
( ) (1.35)(0.013Ω)
2
+ (1.7)(2.5V )(9.9A ) (60pF )(300kHz )
PTOP =
1.25V
9.9A
2.5V
2
 3.3V 
3.3V 1 −

5V 

= 0.87 W
L=
TJ = 50°C + (0.87W)(50°C/W) = 93.5°C
CIN is chosen for an RMS current rating of about 6A at
temperature. The output capacitors are chosen for a low
1
2
PGOOD
3
RR1
10k
4
RC
4.75k
5
C2
100pF
C1 820pF
RON
237k
6
7
8
9
10
11
12
RF1
12.1k
RF3
10k
RUN/SS
BOOST
VON
TG
PGOOD
SW1
24
23
SENSE +
21
ITH
SENSE –
20
PGND1
LTC3718
ION
BG
VFB1
INTVCC
VREF
VIN1
SHDN
VIN2
SGND2
PGND2
VFB2
SW2
RF2
37.4k
CIN1
22µF
×2
DB
CMDSH-3
CB
0.33µF
M1
IRF7811A
CIN2
330µF
VIN
2.5V
D1
B340A
22
VRNG
SGND1
= 4.7µH
The complete circuit is shown in Figure 7.
CSS
0.1µF
RR2
39.2k
RPG
100k
(170mA)(1.4MHz)
L1
1µH
COUT
270µF
×2
19
18
M2
IRF7811A
D2
B340A
VOUT
1.25V
± 6A
17
16
15
CIN2
4.7µF
14
L2
4.7µH
13
D3
MBR0520
CVCC1
10µF
CF4
1000pF
3718 F07
Figure 7. Design Example: 1.25V/±6A at 300kHz from 2.5V
3718fa
17
LTC3718
U
W
U U
APPLICATIO S I FOR ATIO
PC Board Layout Checklist
• Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power component. You can connect the copper
areas to any DC net (VIN, VOUT, GND or to any other DC
rail in your system).
When laying out a PC board follow one of the two
suggested approaches. The simple PC board layout
requires a dedicated ground plane layer. Also, for higher
currents, it is recommended to use a multilayer board to
help with heat sinking power components.
When laying out a printed circuit board, without a ground
plane, use the following checklist to ensure proper operation of the controller. These items are also illustrated in
Figure 8.
• The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
• Place CIN, COUT, MOSFETs, D1 and inductor all in one
compact area. It may help to have some components
on the bottom side of the board.
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to
the source of M2.
• Place LTC3718 chip with Pins 13 to 24 facing the
power components. Keep the components connected
to Pins 1 to 12 close to LTC3718 (noise sensitive
components).
• Place M2 as close to the controller as possible, keeping the PGND, BG and SW traces short.
• Connect the input capacitor(s) CIN close to the power
MOSFETs. This capacitor carries the MOSFET AC
current.
• Use an immediate via to connect the components to
ground plane including SGND and PGND of LTC3718.
Use several bigger vias for power components.
• Keep the high dV/dt SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Use compact plane for switch node (SW) to improve
cooling of the MOSFETs and to keep EMI down.
• Connect the INTVCC decoupling capacitor CVCC closely
to the INTVCC and PGND pins.
• Use planes for VIN and VOUT to maintain good voltage
filtering and to keep power losses low.
• Connect the top driver boost capacitor CB closely to
the BOOST and SW pins.
CSS
1
2
3
4
C1
RC
5
6
RON
C2
7
8
9
10
11
12
RF3
RF5
RUN/SS
BOOST
VON
TG
SW1
PGOOD
VRNG
ITH
22
21
SENSE –
20
INTVCC
VFB1
VREF
VIN1
SHDN
VIN2
SGND2
PGND2
VFB2
SW2
VIN
CB
23
SENSE +
SGND1
PGND1
LTC3718
ION
BG
+
24
M1
CIN
DB
L1
VOUT
COUT
19
M2
D2
18
17
CVCC
–
16
15
3718 F08
14
13
CIN2
L2
BOLD LINES INDICATE HIGH CURRENT PATHS
D3
RF4
Figure 8. LTC3718 Layout Diagram
3718fa
18
LTC3718
U
TYPICAL APPLICATIO
One Half VIN, ±10A Bus Terminator
CSS
0.1µF X7R
RPG
100k
1
2
3
PGOOD
C1
820pF
X7R
4
RC 4.75k
5
C2
100pF
6
RON
237k
7
8
9
10
11
12
RUN/SS
VON
TG
PGOOD
SW1
21
ITH
SENSE –
20
PGND1
LTC3718
ION
BG
VFB1
INTVCC
VREF
VIN1
SHDN
VIN2
PGND2
SGND2
SW2
VFB2
M1
Si7440DP
CIN2****
330µF
D1
B340A
22
SENSE +
SGND1
CB 0.33µF
X7R
23
VRNG
RF3
10k
RF1
12.1k
BOOST
DB
CMDSH-3
24
VIN
2.5V
CIN1
22µF X5R
×2
L1**
0.8µH
+
19
18
M2
Si7440DP
D2
B340A
COUT*
470µF
×2
VOUT
1.25V
±10A
22µF
X5R
17
16
15
4.7µF
6.3V X7R
14
L2***
4.7µH
13
CVCC1
10µF 6.3V
X5R
RF2
37.4k
D3
MBR0520
3718 TA02
CF4
1000pF X7R
*SANYO POSCAP 4TPB470M
**SUMIDA CEP125-0R8MC
***PANASONIC ELJPC4R7MF
****SANYO POSCAP 6TPB330M
U
PACKAGE DESCRIPTIO
G Package
24-Lead Plastic SSOP (5.3mm)
(Reference LTC DWG # 05-08-1640)
7.90 – 8.50*
(.311 – .335)
24 23 22 21 20 19 18 17 16 15 14 13
1.25 ±0.12
7.8 – 8.2
5.3 – 5.7
7.40 – 8.20
(.291 – .323)
0.42 ±0.03
RECOMMENDED SOLDER PAD LAYOUT
0.65
BSC
1 2 3 4 5 6 7 8 9 10 11 12
2.0
(.079)
5.00 – 5.60**
(.197 – .221)
0° – 8°
0.09 – 0.25
(.0035 – .010)
0.55 – 0.95
(.022 – .037)
0.65
(.0256)
BSC
0.22 – 0.38
0.05
(.009 – .015)
(.002)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED .152mm (.006") PER SIDE
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
3. DRAWING NOT TO SCALE
G24 SSOP 0802
3718fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC3718
U
TYPICAL APPLICATIO
Dual Output 2.5V, ±10A Buck Converter and 5V to 12V/130mA Boost Converter
CSS
0.1µF X7R
RPG
100k
1
2
3
PGOOD
C1
3300pF
X7R
4
RC 10k
5
C2
100pF
RON
237k
6
7
RFB
249k
8
RREF
499k
9
10
11
12
RF3
10k
RF1
12.3k
RUN/SS
BOOST
VON
TG
SW1
PGOOD
SENSE +
VRNG
ITH
SENSE
SGND1
–
PGND1
LTC3718
ION
BG
VFB1
INTVCC
VREF
VIN1
SHDN
VIN2
SGND2
PGND2
VFB2
SW2
VIN
6V TO 24V
CIN1****
33µF
×2
25V
DB
CMDSH-3
24
CB 0.33µF
X7R
23
D1
B340A
M1
Si7440DP
22
21
L1**
1.8µH
20
19
RF
1Ω
18
M2
Si7440DP
+
D2
B340A
COUT*
470µF
×2
VOUT1
2.5V
±10A
17
CF
0.1µF
16
15
CVCC2
4.7µF
VIN2
5V
CIN2
22µF X5R
14
L2***
10µH
13
RF2
107k
CVCC1
4.7µF
X5R
CF4
200pF X7R
D3
MBR0520
*SANYO POSCAP 4TPB470M
**TOKO D104C
***PANASONIC ELJPC4R7MF
****KEMET T495X336K025AS
VOUT2
12V
130mA
3718 TA03
RELATED PARTS
PART NUMBER
®
DESCRIPTION
COMMENTS
TM
LT 1613
ThinSOT Step-Up DC/DC Converter
1.4MHz, 1.1V < VIN < 10V
LTC1735
High Efficiency Synchronous Switching Regulator
4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 6V, SSOP-16
LTC1772
ThinSOT Current Mode Step-Down Controller
Small Solution, 2.5V ≤ VIN ≤ 9.8V, 0.8V ≤ VOUT ≤ VIN
LTC1773
Synchronous Current Mode Step-Down Controller
2.65V ≤ VIN ≤ 8.5V, 0.8V ≤ VOUT ≤ VIN,
550kHz Operation, > 90% Efficiency
LTC1778
No RSENSETM Synchronous Step-Down Controller
No Sense Resistor Required, 4V ≤ VIN ≤ 36V,
0.8V ≤ VOUT ≤ VIN
LTC1876
2-Phase, Dual Synchronous Step-Down Controller with Step-Up Regulator
2.6V ≤ VIN ≤ 36V, Dual Output: 0.8V ≤ VOUT ≤ (0.9)VIN
LTC3413
3A Monolithic DDR Memory Termination Regulator
±3A Output Current, 2.25V ≤ VIN ≤ 5.5V
LTC3711
5-Bit, Adjustable, No RSENSE Synchronous Step-Down Controller
0.925V ≤ VOUT ≤ 2V, 4V ≤ VIN ≤ 36V
LTC3713
Low Input Voltage, High Power, No RSENSE Synchronous Controller
No Sense Resistor Required, VIN(MIN) = 1.5V
LTC3717
High Power DDR Memory Termination Regulator
4V ≤ VIN ≤ 36V, VOUT Tracks VIN or VREF,
IOUT from 1A to 20A
LTC3778
No RSENSE Synchronous Step-Down Controller
Optional Sense Resistor, 4V ≤ VIN ≤ 36V,
0.6V ≤ VOUT ≤ VIN
LTC3831
High Power DDR Memory Termination Regulator
VOUT Tracks 1/2 VIN or VREF, 3V ≤ VIN ≤ 8V,
IOUT from 1A to 20A
No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
3718fa
20 Linear Technology Corporation
LT/TP 1103 1K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2002