Ordering number : EN5775A Monolithic Linear IC LA7477W For Digital Video Camera Audio Signal I/O Interface IC Overview The LA7477W is a digital video camera audio signal I/O interface IC that integrates on a single chip a block previous implemented with discrete components. The LA7477W integrates the volume control circuit used for both headphones and speakers, and thus supports the implementation of circuit structures ideal for digital video cameras that include an LCD panel. Features • Three-wire serial bus control • Headphone and speaker volume controls (Support for both serial and parallel operation) • Supports bilingual audio • Supports record, playback, and overdubbing • Low-power mode Functions • Three inputs (microphone, line 1, line 2) • ALC (That can be turned on or off) • Fader circuit • Low-pass filter (used for both record and playback) • Electronic volume control circuit • Deemphasis circuit • Left + right channel mixer • Power muting function Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 61108 MS PC/N1506 MS PC B8-3058 No.5775-1/12 LA7477W Specifications Maximum Ratings at Ta = 25°C Parameter Maximum supply voltage Allowable power dissipation Symbol Conditions Ratings Unit VCC Pd max 7 Ta ≤ 75°C V 200 mV Operating temperature Topr -10 to +75 °C Storage temperature Tstg -55 to +150 °C Operating Conditions at Ta = 25°C Parameter Symbol Conditions Ratings Unit Recommended supply voltage VCC1 Operating supply voltage range VCC1 opg VCC2 opg 4.5 to 5.5 V VCC2 3.15 V 4.75 V 3.0 to 3.6 V Electrical Characteristics at Ta = 25°C, VCC1 = 3.15V, VCC2 = 4.75V, f = 1kHz, Lch, Rch, EVR ; CENTER Parameter Symbol Ratings Conditions min typ Unit max Record current 1 ICC3R1 VCC (L) = 3.15V, REC 13.3 17.8 22.3 mA Record current 2 ICC5R2 VCC (H) = 4.75V, REC 4.1 5.5 6.9 mA Playback current 1 ICC3P1 VCC (L) = 3.15V, PB 6.9 9.3 11.7 mA Playback current 2 ICC5P2 Line output reference level Line output left/right level VCC (H) = 4.75V, PB 4.1 5.5 6.9 mA VOL VIN (MIC) = -40dBV, VIN (LINE1, 2) = -30dBV -11 -10 -9 dBV VOLD VIN (MIC) = -40dBV, VIN (LINE1, 2) = -30dBV 0 ±1 dB VOLTHD VIN (MIC) = -40dBV, VIN (LINE1, 2) = -30dBV 0.1 0.3 % MIC IN MODE, ALC-ON, Rg = 1k, -73 -70 dBV -79 -76 dBV -83 -80 dBV -87 -84 dBV -3.0 -1.5 dBV 0.2 0.5 % difference (THD) Line output total harmonic distortion Line output noise voltage 1 VNOL1 JIS-A FILTER Line output noise voltage 2 VNOL2 MIC IN MODE, ALC-OFF, Rg = 1k, JIS-A FILTER Line output noise voltage 3 VNOL3 LINE1, 2 IN MODE, ALC-ON, Rg = 1k, JIS-A FILTER Line output noise voltage 4 VNOL4 LINE1, 2 IN MODE, ALC-OFF, Rg = 1k, JIS-A FILTER Line output ALC level Line output ALC (20dB boost) VOLa VOLaT VIN (MIC) = -30dBV, VIN (LINE1, 2) = -20dBV -4.5 VIN (MIC) = -20dBV harmonic distortion (THD) Record output reference level Record output left/right level VOR VIN (MIC) = -40dBV, VIN (LINE1, 2) = -30dBV -17 -16 dBV VORD1 VIN (MIC) = -40dBV, VIN (LINE1, 2) = -30dBV -18 0 ±1 dB VORTHD VIN (MIC) = -40dBV, VIN (LINE1, 2) = -30dBV 0.1 0.3 % MIC IN MODE, ALC-ON, Rg = 1k, -81 -78 dBV -86 -83 dBV -91 -88 dBV -96 -93 dBV -10.0 -8.5 dBV difference Record output total harmonic distortion (THD) Record output noise voltage 1 VNOR1 JIS-A FILTER Record output noise voltage 2 VNOR2 MIC IN MODE, ALC-OFF, Rg = 1k, JIS-A FILTER Record output noise voltage 3 VNOR3 LINE1, 2 IN MODE, ALC-ON, Rg = 1k, JIS-A FILTER Record output noise voltage 4 VNOR4 LINE1, 2 IN MODE, ALC-OFF, Rg = 1k, JIS-A FILTER Record output ALC level Record output maximum output VORa VORMAX level Record forward/reverse output VIN (MIC) = -30dBV, VIN (LINE1, 2) = -20dBV ALC-OFF, VIN (MIC, LINE1, 2) -11.5 -4 dBV at REC OUT THD = 1% VORD2 VIN (MIC) = -40dBV, VIN (LINE1, 2) = -30dB 0 ±0.2 dB No signal 0 ±7 mV level difference Record forward/reverse output VOROFF DC offset Continued on next page. No.5775-2/12 LA7477W Continued from preceding page. Parameter Symbol Ratings Conditions min Maximum input level VIN max ALC-ON, VIN (MIC, LINE1, 2) at LINE OUT THD = 1% Line maximum output level VOL max ALC OFF at LINE OUT THD = 1% Line muting attenuated output VOMUTE VIN (MIC) = -25dBV, JIS-A FILTER Fader output at maximum VOFADE VIN (MIC) = -40dBV, JIS-A FILTER VRLPF1 VIN (MIC) = -40dBV, the 20kHz/1kHz ratio VRLPF2 VIN (MIC) = -40dBV, the 200kHz/1kHz ratio typ Unit max -5 2.5 dBV 3.5 -75 dBV -73 dBV -71 dBV -1.0 dB attenuation Record first-order low-pass filter -0.5 frequency characteristics 1 Record first-order low-pass filter -3.5 -5.0 dB frequency characteristics 2 Inter-input crosstalk INCR VIN (LINE1, 2) = -30dBV, MIC IN MODE, Rg = 1k, JIS-A FILTER -75 -71 dBV VIN (MIC) = -40dBV, VIN (LINE1) = -30dBV, LINE2 IN MODE, Rg = 1k, JIS-A FILTER -85 -81 dBV VIN (MIC) = -40dBV, VIN (LINE2) = -30dBV, LINE1 IN MODE, Rg = 1k, JIS-A FILTER -85 -81 dBV -35 -32 dBV Headphone output level VOHP VIN (MIC) = -40dBV, EVR CENTER, 8Ω termination for a 47+8Ω load. Headphone output left/right level VHPD VIN (MIC) = -40dBV, EVR CENTER, 8Ω termination for a 47+8Ω load. 0 ±2 dB VOHPD VIN (MIC) = -40dBV, EVR CENTER, 8Ω termination for a 47+8Ω load. 0.2 0.5 % -70 -60 dB -18 -15 dBV 0.1 0.3 % -10.0 -9.5 dBV 0 -1 difference Headphone output harmonic distortion (THD) EVR maximum fluctuation EVR max VIN (MIC) = -40dBV, EVR CENTER→MAX EVR minimum fluctuation EVR min VIN (MIC) = -40dBV, EVR CENTER→MIN Speaker output reference level Speaker output harmonic VOSP VIN (MIC) = -40dBV, EVR CENTER VOSPD VIN (MIC) = -40dBV, EVR CENTER -38 10 -21 12 dB distortion (THD) Playback line output level Playback third-order low-pass VOPB PBIN = -21dBV VPLPF1 PBIN = -21dBV, the 20kHz/1kHz ratio VPLPF2 PBIN = -21dBV, the 50kHz/1kHz ratio CHCR1 VIN (MIC) = -40dBV, (Rch/Lch) Rg = 1k (Lch/Rch), ALC-ON, LINE OUT, -10.5 dB filter frequency characteristics 1 Playback third-order low-pass -5 -9 dB filter frequency characteristics 2 Inter-channel crosstalk -70 -68 dBV -76 -74 dBV -80 -78 dBV -86 -84 dBV JIS-A FILTER CHCR2 VIN (MIC) = -40dBV, (Rch/Lch) Rg = 1k (Lch/Rch), ALC-OFF, LINE OUT, JIS-A FILTER CHCR3 VIN (LINE1, 2) = -30dBV, (Rch/Lch) Rg = 1k (Lch/Rch), ALC-ON, LINE OUT, CHCR4 VIN (LINE1, 2) = -30dBV, (Rch/Lch) Rg = 1k (Lch/Rch), ALC-OFF, LINE OUT, JIS-A FILTER JIS-A FILTER No.5775-3/12 LA7477W Package Dimensions unit : mm (typ) 3163B 36 0.5 9.0 7.0 25 24 48 13 7.0 9.0 37 1 12 0.5 0.18 0.15 (1.5) 0.1 1.7max (0.75) SANYO : SQFP48(7X7) No.5775-4/12 MUTE 1kΩ 42 41 40 47μF 45 44 43 47μF 1kΩ EVR 2 5.6kΩ 47kΩ 56kΩ 0.22μF 48 47 46 3 + POWER MUTE 0.22μF 35 34 1 5.6kΩ FADE 36 33μF 39 VREF 5.6kΩ 0.22μF 47kΩ 47μF + SP 47Ω 4.7μF + + SPEAKER DRIVER HEAD PHONE 47Ω 37 33μF 38 + + + VCC(L) 3.15V Rch LINE IN2 Lch LINE IN2 + 4.7μF Rch LINE IN1/OUT 47kΩ 0.22μF 47kΩ 5.6kΩ Lch LINE IN1/OUT Lch MIC AMP Rch INT MIC VCC EXT MIC VCC(H) 4.75V EVR 4 32 ALC 6 31 0.22μF 5 DET EVR 33 0.22μF - 29 EVR 7 LPF + 33kΩ 9 11 DBEMPH 26 10μF 10 + INTERFACE SERIAL DATA + 4.7μF 33μF 8 28 27 10μF + D.C MUTE FADE LPF 30 Rch + + EVR 12 - + 25 13 14 15 16 17 18 19 20 21 22 23 24 CS SYSTEM CONTROL 1000pF CLK DATA CONT4 CONT3 CONT2 CONT1 1000pF DA AD LA7477W Block Diagram No.5775-5/12 LA7477W Serial Communications Serial data Parameter Initial values Bit 1 EVR CTL 1 L : 0, H : 1 0 Bit 2 EVR CTL 2 L : 0, H : 1 0 Bit 3 EVR CTL 3 L : 0, H : 1 0 Bit 4 EVR CTL 4 L : 0, H : 1 0 Bit 5 EVR CTL 5 L : 0, H : 1 0 Bit 6 Headphone and speaker ON : 0, OFF : 1 1 Bit 7 EVR SERIAL ON : 0, OFF : 1 1 Bit 8 12dB amplifier through state OFF : 0, ON : 1 1 Bit 9 REC EVR SW OFF : 0, ON : 1 0 Bit 10 DE-EMPH OFF : 0, ON : 1 0 Bit 11 CONT1 OUT L : 0, H : 1 1 Bit 12 CONT2 OUT L : 0, H : 1 1 Bit 13 CONT3 OUT L : 0, H : 1 1 Bit 14 CONT4 OUT L : 0, H : 1 1 Bit 15 RFU SW OFF : 0, ON : 1 0 Bit 16 STEREO/MAIN/SUB STEREO : 0, MAIN : 0, SUB : 1 0 Bit 17 STEREO : 0, MAIN : 1, SUB : 0 0 Bit 18 ALC SW ON : 0, OFF : 1 0 Bit 19 LINE OUT ON : 0, OFF : 1 0 Bit 20 MIC/LINE1/LINE2/SPEAKER OFF Bit 21 MIC : 0, LINE1 : 0, LINE2 : 1, SPEAKER OFF : 1 0 MIC : 0, LINE1 : 1, LINE2 : 0, SPEAKER OFF : 1 0 Bit 22 MUTE SW OFF : 0, ON : 1 1 Bit 23 REC/PB/EE/POWER SAVE REC : 0, PB : 0, EE : 1, POWER SAVE : 1 0 REC : 0, PB : 1, EE : 0, POWER SAVE : 1 0 Bit 24 Serial Transfer Timing tWC CS tCS tWH tWL fMAX tCH CLOCK tDS tDH DATA LSB MSB Maximum clock frequency fMAX 800kHz Clock pulse width (low) tWL 625ns minimum Clock pulse width (high) tWH 625ns minimum Chip enable setup time tCS 625ns minimum Chip enable hold time tCH 625ns minimum Data setup tim tDS 625ns minimum Data hold time tDH 625ns minimum Chip enable pulse width tWC 625ns minimum No.5775-6/12 LA7477W Power on state (serial communication) H Power supply L H A width of a few hundred ns Power on pulse (IC internal signal) (1) (2) L H Chip select (3) L The first data communication operation A delay of a few hundred ns H Power-on reset (IC internal signal) (4) L Power-on reset state Serial communication state The data of the first transmission is latched. The power-on reset state lasts from the rise of the power on pulse (1) created internally in the IC at power on to the second chip select signal rising edge (3) that is input after (2). However, since there is actually a delay of a few hundred ns internally in the IC the first data state starts at (4) and the IC enters the normal serial communication state after (4). No.5775-7/12 LA7477W Headphone, Speaker, and Line Out Output States Serial data MODE Output Bit 6 Bit 23 Bit 24 Headphone Speaker Line out REC 0 0 0 ON ON *2 PB 0 0 1 ON ON *2 EE 0 1 0 ON ON *2 POWER SAVE *1 1 1 OFF OFF OFF Headphone and speaker switches 1 *1 *1 OFF OFF *2 Notes. *1 : These are don't care states. *2 : In states other than power saving mode, this state does not depend on bits 6, 23, and 24 in the data, but rather is controlled by bit 19 in the data. Furthermore, the speaker output can be controlled by bits 20 and 21 in the serial data, and has the logic shown below in each mode. However, note that the input selector goes to microphone mode if bits 20 and 21 are (1, 1). The table below lists the speaker output control logic in each mode. Serial data REC PB EE POWER SAVE 0 ON ON ON OFF 1 ON ON ON OFF Bit 20 Bit 21 0 0 1 0 ON ON ON OFF 1 1 OFF OFF OFF OFF Note than in record mode, if bits 20 and 21 are (0, 0), care is require when using this IC, since the speakers will be turned on at the same time as the system switches to microphone mode. Output Signal Table Serial data Bit 15 Bit 16 Output Bit 17 Line Left channel Headphone Left Speaker Headphone Right Line Right channel 0 0 0 L L L+R R R 1 0 0 L+R L L+R R R 0 0 1 L L L L L 1 0 1 L+R L L L L 0 1 0 R R R R R 1 1 0 L+R R R R R No.5775-8/12 LA7477W Pin Functions Pin No. 1 Pin Name EVR CTL IN DC voltage AC voltage 1.575V Description Equivalent circuit Controls the EVR. This pin can be used for external control by applying a voltage through 1.575V 1 an external resistor. This IC can also be controlled from serial data by connecting this pin to pin 2 through an external resistor. 2 EVR CTL Control output when EVR is SERIAL OUT controlled by serial data 2 3 LINE IN2 R -30dBV Right channel line 2 input 5 MIC IN R -40dBV Right channel microphone input 32 MIC IN L -40dBV Left channel microphone input 34 LINE IN2 L -30dBV Left channel line 2 input 36 LINE IN1 L -30dBV Left channel line 1 input 48 LINE IN1 R -30dBV Right channel line 1 input 1.80V 3 34 5 36 32 48 (Reference inputs) 50kΩ VREF 4 FADE IN Controls the fade characteristics 70kΩ 4 50kΩ 6 GND R Right channel ground 33 GND L Left channel ground 44 GND LINE Line input ground 8 EXT EVR OUT R Connect to the right channel external EVR output. 30 EXT EVR OUT L Connect to the left channel external EVR output. 8 30 50kΩ VREF 7 EXT EVR IN R 1.80V -40dBV (Microphone Connect to the right channel external EVR input. mode) 31 EXT EVR IN L -30dBV (Line mode) Connect to the left channel external EVR input. 7 31 Continued on next page. No.5775-9/12 LA7477W Continued from preceding page. Pin No. 9 Pin Name DC voltage AC voltage ALC DET Description Equivalent circuit ALC detection IR (MIC) ≈ 1.8μA IR (LINE) ≈ 0.5μA 30kΩ 9 IR 10 DC DET R 28 DC DET L 1.80V Detects the DC level and cancels the offset. 15kΩ 10kΩ 10kΩ 10 28 11 REC OUT + R -17dBV Right channel record output + phase 12 REC OUT - R 1.80V (Reference Right channel record output - phase 26 REC OUT - L inputs) 27 REC OUT + L Left channel record output - phase Left channel record output + phase 11 27 12 26 13 DE-EMPHASIS R 25 DE-EMPHASIS L 1.80V Deemphasis control 13 25 15kΩ 35kΩ 1.80V Right channel playback + phase input 14 AMP + IN R 15 AMP - IN R Right channel playback - phase input 23 AMP - IN L Left channel playback - phase input 24 AMP + IN L Left channel playback + phase input VREF 12kΩ 14 24 12kΩ 15kΩ 15kΩ 15 23 16 CHIP SELECT IN Chip select input 17 CLOCK IN Clock input 18 DATA IN Data input 50kΩ 3pF 50kΩ 16 17 18 Continued on next page. No.5775-10/12 LA7477W Continued from preceding page. Pin No. Pin Name 19 CONT4 20 CONT3 21 CONT2 22 CONT1 29 MUTE CTL DC voltage AC voltage Description Equivalent circuit CONT outputs 50kΩ 19 21 20 22 Muting control 2.3V or higher: Muting on 108kΩ 20kΩ 0.7V or lower: Muting off 29 50kΩ 35 VCCH 37 POWER MUTE 4.75V Used to temporarily set the IC to the VCCH muted state when power is applied or removed. 10kΩ 30kΩ 1kΩ 1kΩ 37 200Ω 38 39 VREF VREF OUT 1.80V Ripple rejection filter connection 1.80V VREF output 40.2kΩ 38 39 53kΩ 40 VCCL 3.15V 41 LINE OUT L 2.375V 47 LINE OUT R -10dBV (Reference Left channel line output VCCH Right channel line output inputs) 10.2kΩ 41 47 2kΩ 2kΩ 8.2kΩ 42 HEADPHONE L 45 SPEAKER OUT 46 HEADPHONE R 2.375V -35dBV Left channel headphone output -18dBV Speaker output -35dBV Right channel headphone output VCCH (Reference 42 45 46 inputs) 43 POWER MUTE Muting control output used when OUT power is applied or removed. VCCH 10kΩ 200Ω 43 No.5775-11/12 LA7477W SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of June, 2008. Specifications and information herein are subject to change without notice. PS No.5775-12/12