Micrel MIC4223 Dual 4a, 4.5v to 18v, 15ns switch time, low-side mosfet drivers with enable Datasheet

MIC4223/MIC4224/MIC4225
Dual 4A, 4.5V to 18V, 15ns Switch Time,
Low-Side MOSFET Drivers with Enable
General Description
Features
The MIC4223/MIC4224/MIC4225 are a family of a dual 4A,
High-Speed, Low-side MOSFET drivers with logic-level
driver enables. The devices are fabricated on Micrel’s
Bipolar/CMOS/DMOS (BCD) process and operate from a
4.5V to 18V supply voltage. The devices parallel Bipolar
and CMOS output stage architecture provides high-current
throughout the MOSFETs Miller Region allowing the driver
to sink and source 4A of peak current from a 12V supply
and quickly charge and discharge a 2000pF load
capacitance in under 15ns, while allowing the outputs to
swing within 0.3V of VDD and 0.16V of ground.
The MIC4223/MIC4224/MIC4225 driver and enable inputs
feature TTL and CMOS logic-level thresholds which are
independent of supply voltage. Each driver features a
dedicated active-high enable input which is internally
pulled high to VDD through 100kΩ, allowing the pins to be
left unconnected if it is not required to disable the driver
outputs. The driver inputs have been designed to protect
against ground bounce and are protected to withstand -5V
of voltage swing at -40mA. Driver outputs are also
protected to withstand 500mA of reverse current.
The MIC4223/MIC4224/MIC4225 are available in three
configurations using industry standard pin out; dual
inverting (MIC4223), dual non-inverting (MIC4224) and
complimentary (MIC4225). They are available in 8-pin
SOIC and thermally enhanced e-PAD 8-pin MSOP and
support operating junction temperatures from -40°C to
+125°C.
• 4.5V to 18V supply voltage operating range
• High peak source/sink current
– ±3A at VDD = 8V
– ±4A at VDD = 12V
• 15ns/15ns Rise and Fall times with 2000pF load
• 25ns/35ns (Rising/Falling) input propagation delay
• 20ns/45ns (Rising/Falling) enable propagation delay
• Active-high driver enable inputs with 100kΩ pull-ups
• CMOS and TTL logic input and enable thresholds
independent of supply voltage
• Driver input protection to -5V at -40mA
• Output Latch-up protection to >500mA reverse current
• Industry standard pin out with two package options
– ePAD MSOP-8 (θJA = 60°C/W)
– 8-pin SOIC (θJA = 120°C/W)
• Available in dual-inverting (MIC4223), dual noninverting (MIC4224) and complementary (MIC4225)
• Dual output drive by paralleling channels
• -40°C to +125°C operating junction temperature range
Block Diagram
Applications
•
•
•
•
•
•
•
•
High-Efficiency MOSFET switching
Switch mode power supplies
DC-to-DC converters
Motor and solenoid drivers
Clock and line drivers
Synchronous rectifiers
Pulse transformer drive
Class D switching amplifiers
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 2009
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Ordering Information
Part Number
Configuration
Junction Temp. Range
MIC4223YM
Dual Inverting
–40° to +125°C
8-pin SOIC
Pb-Free
MIC4223YMME
Package
Lead Finish
Dual Inverting
–40° to +125°C
8-pin EPAD-MSOP
Pb-Free
MIC4224YM
Dual Non-inverting
–40° to +125°C
8-pin SOIC
Pb-Free
MIC4224YMME
Dual Non-inverting
–40° to +125°C
8-pin EPAD-MSOP
Pb-Free
MIC4225YM
Inverting + Non-inverting
–40° to +125°C
8-pin SOIC
Pb-Free
MIC4225YMME
Inverting + Non-inverting
–40° to +125°C
8-pin EPAD-MSOP
Pb-Free
Pin Configuration
8-Pin SOIC (YM)
8-Pin ePAD MSOP (YMME)
8-Pin SOIC (YM)
8-Pin ePAD MSOP (YMME)
8-Pin SOIC (YM)
8-Pin ePAD-MSOP (YMME)
Pin Description
Pin Number
Pin Name
1
ENA
Enable pin for output A. TTL/CMOS-compatible logic input. A logic-level high enables the
device. An internal pull-up enables the part if pin is open. A logic-level low disables the device
and the output will be low regardless of the input state.
2
INA
Control Input A: TTL/CMOS-compatible logic input. Connect to VDD or ground if not used and
connect ENA to ground to disable driver A.
3
GND
Ground
4
INB
Control Input B: TTL/CMOS compatible logic input. Connect to VDD or ground if not used and
connect ENB to ground to disable driver B.
5
OUTB
6
VDD
7
OUTA
8
ENB
Enable pin for output B. TTL/CMOS-compatible logic input. A logic-level high enables the
device. An internal pull-up enables the part if pin is open. A logic-level low disables the device
and the output will be low regardless of the input state.
EP
GND
Exposed thermal pad for ePad MSOP package only (Not available on SOIC-8L package).
Connect to ground. Must make a full connection to the ground plane to maximize thermal
performance of the package.
June 2009
Pin Function
Output B: Parallel Bipolar/CMOS output.
Voltage Supply Input: +4.5V to +18V
Output A: Parallel Bipolar/CMOS output.
2
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD)....................................................+20V
Input Voltage (VINA, VINB) ................ VDD + 0.3V to GND - 5V
Enable Voltage (VENA, VENB)…..…….... ...0.3V to VDD + 0.3V
Junction Temperature (TJ) .........................-55°C to +150°C
Storage Temperature ................................–65°C to +150°C
Lead Temperature (10 sec.)....................................... 300°C
ESD Rating................................. HBM = 2kV, MM = 200V(3)
Supply Voltage (VDD)..................................... +4.5V to +18V
Junction Temperature (TJ) ........................ –40°C to +125°C
Package Thermal Resistance
EPAD MSOP (θJA) .............................................60°C/W
SOIC (θJA) ........................................................120°C/W
Electrical Characteristics
4.5V ≤ VDD ≤ 18V; CL = 2000pF. TA = 25°C, bold values indicate full operating junction temperature range, unless noted.
Symbol
Parameter
Condition
Min
Typ
2.4
2.2
Max
Units
Input
VIH
Logic 1 Input Voltage
VIL
Logic 0 Input Voltage
1.95
Hysteresis
IIN
V
0.8
0.25
Input Current
0 ≤ VIN ≤ VDD
–1
–10
VIN = -5V
V
V
1
10
-40
µA
µA
mA
Output
VDD - 0.45
VOH
High Output Voltage
IOUT = -10mA, VDD = 18V
VOL
Low Output Voltage
IOUT = 10mA, VDD = 18V
RO
Output Resistance – Source
Output Resistance – Sink
IOUT = -10mA, VDD = 18V
IOUT = 10mA, VDD = 18V
30
16
IPK
Peak Output Current
VDD = 8V
±3
I
Latch-Up Protection
Withstand reverse current
VDD = 12V
V
0.30
V
45
30
Ω
A
±4
>500
mA
Switching Time
tR
Rise Time
Test Figure 1; CL = 2000pF
15
40
ns
tF
Fall Time
Test Figure 1; CL = 2000pF
15
40
ns
tD1
Delay Time
Test Figure 1; CL = 2000pF
25
45
ns
tD2
Delay Time
Test Figure 1; CL = 2000pF
35
50
ns
Enable (ENA, ENB)
VEN_H
High Level Enable Voltage
LO to HI transition
VEN_L
Low Level Enable Voltage
HI to LO transition
2.4
1.9
1.55
Hysteresis
V
0.8
0.35
V
V
REN
Enable Impedance
VDD = 18V, VENA = VENB = GND
100
tD3
Propagation Delay Time
CL = 2000pF
20
60
kΩ
ns
tD4
Propagation Delay Time
CL = 2000pF
45
150
ns
Power Supply
ISH
Power Supply Current
VINA = VINB = 3.0V, VENA = VENB = open
1.7
2.5
mA
ISL
Power Supply Current
VINA = VINB = 0.0V, VENA = VENB = open
0.7
1.5
mA
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
June 2009
3
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Test Circuit
Figure 1. Test Circuit
Timing Diagram
Inverting Driver
Non-Inverting Driver
Enable to Output Timing Diagram
June 2009
4
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Typical Characteristics
Conditions: TA =25ºC.
VINA, B Threshold vs.
Temperature
VINA, B Threshold vs. VDD
2.0
VDD =12V
2.15
2.2
Threshold (V)
VIH
2.1
2.05
2
1.95
VIL
1.8
1.6
2.0
1.85
1.8
VIL
1.2
1.7
6
8
10
12
14
16
1.0
-40
18
-20
0
Enable Threshold vs.
Temperature
40
60
80
100 120 140
4
VEN_H
IDD (mA)
IDD (mA)
VEN_L
0.4
0.2
0.0
1.3
-40
-20
0
20
40
60
80
0.0
100 120 140
4
6
8
10
Temperature (°C)
12
14
16
18
IDD vs. Temperature
(Disabled)
0.0
1.5
1.0
0.2
-20
0
20
40
60
80
100 120 140
VDD = 4.5V; VIN = 500kHz
0.5
VDD = 4.5V; VIN = 0
0.0
0.0
-40
-40
Temperature (°C)
-20
0
20
40
60
80
-40
100 120 140
-20
0
20
40
60
80
100 120 140
Temperature (°C)
Temperature (°C)
IDD vs. Frequency (VDD = 5V)
IDD vs. Frequency (VDD = 5V)
Both Drivers Switching
Both Drivers Switching
50
18
VDD = 12V; VIN = 500kHz
2.0
VDD = 12; VIN = 0
0.6
0.4
VDD = 4.5V; VIN = 0
16
2.5
0.8
VDD = 12V; VIN = 0
0.2
14
3.0
VDD = 4.5; VIN = VDD
IDD (mA)
IDD (mA)
0.6
12
3.5
1.2
VDD = 4.5V; VIN = VDD
10
4.0
VDD = 12; VIN = VDD
1.0
0.4
8
IDD vs. Temperature
(Switching)
1.4
0.8
6
VDD (V)
IDD vs. Temperature
(Enabled)
VDD = 12; VIN = VDD
1.0
4
VDD (V)
1.2
18
VINA = VINB = 0
0.6
VINA = VINB = 0
0.2
1.4
16
0.8
0.4
1.5
14
1.0
0.6
1.6
12
VINA = VINB = VDD
1.2
0.8
1.7
10
1.4
VINA = VINB = VDD
1.0
1.8
8
IDD vs. VDD (Enabled)
1.2
VDD =12V
1.9
6
VDD (V)
IDD vs. VDD (Disabled)
2.1
Threshold (V)
20
Temperature (°C)
VDD (V)
2.0
VEN_L
1.4
1.9
1.8
4
VEN_H
VIH
2.1
1.9
IDD (mA)
VENA, B Threshold vs. VDD
2.3
2.2
IDD vs. Frequency (VDD = 12V)
Both Drivers Switching
120
180
160
40
100
140
30
1nF
20
10nF
120
IDD (mA)
IDD (mA)
IDD (mA)
2.2nF
100
80
4.7nF
40
0
470pF
0
0
500
1000
1500
Frequency (kHz)
June 2009
2000
1nF
20
20
470pF
60
40
60
10
2.2nF
80
0
0
500
1000
1500
Frequency (kHz)
5
2000
0
500
1000
1500
2000
Frequency (kHz)
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Conditions: TA = 25ºC.
IDD vs. Frequency (VDD = 12V)
IDD vs. VDD (CL = 2.2nF)
Both Drivers Switching
Both Drivers Switching
IDD vs. VDD (CL = 2.2nF)
Both Drivers Switching
120
20
140
18
120
12
4.7nF
80
IDD (mA)
10nF
IDD (mA)
100kHz
10
60
8
60
40
6
4
20
500kHz
50kHz
20
2
0
0
0
0
200
400
600
800
1000
4
6
8
10
12
14
16
IDD vs. VDD (CL = 4.7nF)
Both Drivers Switching
Both Drivers Switching
40
160
35
140
200kHz
IDD (mA)
IDD (mA)
100kHz
15
10
2MHz
1MHz
80
500kHz
60
40
50kHz
6
8
10
12
14
16
4
6
8
10
VDD (V)
8
Output Rise Time vs. VDD
4
12
14
16
4
18
20
4.7nF
10
14
10
8
4
0
0
14
16
1nF
6
2
12
2.2nF
12
5
10
Output Fall Time (ns)
45
Output Fall Time (ns)
50
16
8
470pF
12
14
16
35
10nF
30
25
20
4.7nF
15
10
0
6
8
10
12
14
16
18
4
20
6
8
10
12
14
16
VDD (V)
VDD (V)
VDD (V)
Propagation Delay (tD1)
vs. VDD
Propagation Delay (tD1)
vs. VDD
Propagation Delay (tD2)
vs. VDD
2.2nF
20
1nF
15
10
5
470pF
30
10nF
25
20
4.7nF
15
10
5
0
0
6
8
10
12
VDD (V)
14
16
18
18
30
Propagation Delay (ns)
Propagation Delay (ns)
25
18
40
35
June 2009
10
5
4
18
30
4
8
Output Fall Time vs. VDD
18
6
6
VDD (V)
35
4
470pF
2
40
15
1nF
Output Fall Time vs. VDD
25
18
6
VDD (V)
10nF
16
0
18
30
14
2.2nF
0
4
12
10
20
0
10
Output Rise Time vs. VDD
100
5
8
12
120
25
20
6
VDD (V)
IDD vs. VDD (CL = 4.7nF)
30
4
18
VDD (V)
Frequency (kHz)
Propagation Delay (ns)
1MHz
80
Output Rise Time (ns)
IDD (mA)
2MHz
14
40
Output Rise Time (ns)
100
200kHz
16
100
2.2nF
25
1nF
20
15
10
470pF
5
0
4
6
8
10
12
VDD (V)
6
14
16
18
4
6
8
10
12
14
16
18
VDD (V)
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Conditions: TA = 25ºC.
60
Resistance (Ω)
40
10nF
30
25
20
4.7nF
15
10
IDD = 10mA
VDD = 4.5V
50
VDD = 12V
40
30
VDD = 18V
VDD = 12V
30
VDD = 4.5V
20
20
VDD = 18V
5
0
10
10
4
6
8
10
12
14
16
18
-40
-20
0
VDD (V)
60
80
-40
100 120 140
12
VDD = 12V
10
CL = 2nF
VDD = 4.5V
18
14
12
0
20
40
60
80
100 120 140
Prop. Delay (Non-Inverting)
vs. Temperature
0
20
40
60
80
100 120 140
20
10
VDD = 12V; tD2
VDD = 12V; tD1
0
20
40
60
80
100 120 140
Temperature (°C)
June 2009
0
VDD = 4.5V
30
25
VDD = 12V
20
40
60
100 120 140
CL = 2nF
VDD = 4.5V
70
60
VDD = 18V
50
VDD = 12V
40
15
80
Enable to Output Delay
(tD4) vs. Temperature
80
35
20
Temperature (°C)
CL = 2nF
10
-20
-20
VDD = 18V
0
-40
-40
Prop. Delay (ns)
30
VDD = 12V; tD2
VDD = 12V; tD1
10
40
VDD = 4.5V; tD2
VDD = 4.5V; tD2
20
Enable to Output Delay
(tD3) vs. Temperature
Prop. Delay (ns)
40
100 120 140
VDD = 4.5V; tD1
Temperature (°C)
VDD = 4.5V; tD1
80
0
-40 -20
Temperature (°C)
CL = 2nF
60
30
VDD = 12V
VDD = 18V
10
8
-40 -20
40
40
16
8
20
Prop. Delay (Inverting)
vs. Temperature
Delay (ns)
14
VDD = 18V
0
50
CL = 2nF
VDD = 4.5V
16
-20
Temperature (°C)
20
CL = 2nF
Output Fall Time (ns)
Output Rise Time (ns)
40
Output Fall Time
vs. Temperature
18
50
20
Temperature (°C)
Output Rise Time
vs. Temperature
Delay (ns)
40
IDD = 10mA
45
Resistance (Ω)
Propagation Delay (ns)
50
35
Output Sink Resistance
vs. Temperature
Output Source Resistance
vs. Temperature
Propagation Delay (tD2)
vs. VDD
30
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
7
-40
-20
0
20
40
60
80
100 120 140
Temperature (°C)
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Functional Diagram
Logic Table
Enables
Inputs
MIC4223
MIC4224
MIC4225
ENA
ENB
INA
INB
OUTA
OUTB
OUTA
OUTB
OUTA
OUTB
H
H
L
L
H
H
L
L
H
L
H
H
L
H
H
L
L
H
H
H
H
H
H
L
L
H
H
L
L
L
H
H
H
H
L
L
H
H
L
H
L
L
X
X
L
L
L
L
L
L
Block Diagram
June 2009
8
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Functional Description
The MIC4223, MIC4224 and MIC4225 are a family of dual
high speed, high current drivers. The drivers come in both
inverting and non-inverting versions. Each driver has an
enable pin that turns the output off (low) regardless of the
input.
The MIC4223 is a dual inverting driver. The MIC4224 is a
dual non-inverting driver and the MIC4225 contains an
inverting and non-inverting driver.
Enable
Each output has an independent enable pin that forces the
output low when the enable pin is driven low. Each enable
pin is internally pulled-up to VDD. The outputs are enabled
by default if the enable pin is left open. Pulling the enable
pin low, below its threshold voltage, forces the output low.
A fast propagation delay between the enable and output
pins quickly disables the output, which is a requirement
during a system fault condition.
Input Stage
The driver input stage is high impedance, TTL-compatible
input stage. The driver’s input threshold voltage makes it
compatible with TTL and CMOS devices that are powered
from supply voltages between 3V and VDD. Hysteresis on
the input pin improves noise immunity and prevents input
signals with slow rise times from falsely triggering the
output. The VDD pin current is slightly higher when the
input voltage is above the high level threshold. See the
Typical Characteristic graphs for additional information.
The input voltage signal may go up to -5V below ground
without damage to the driver or cause a latch up condition.
Negative input voltages that are 0.7V below ground or
greater will increase propagation delay.
Figure 2. Output Driver
The slew rate of the output is non-adjustable and depends
only on the VDD voltage and how much capacitance is
present at the OUTA, B pin. Changing the slew rate at the
driver’s input pin will not affect the output rise or fall times.
The slew rate at the MOSFET gate can be adjusted by
adding a resistor between the MOSFET gate and the
driver output.
Output Driver Section
A functional diagram of the driver output is shown in Figure
2. The output drive is a parallel combination of MOSFET
and Bipolar transistor. For a given silicon area, a bipolar
device has a lower on-resistance than an equivalent MOS
device. It sources and sinks current more consistently as
the voltage across it changes. The low drive impedance of
the bipolar allows fast turn-on and turn-off of the external
MOSFET. The driver’s internal MOSFET gives the output
near rail-to-rail drive capability. This ensures a low RDSON
for the external MOSFET as well as noise immunity from
dv/dt induced glitching.
June 2009
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M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Application Information
Power Dissipation Considerations
Power dissipation in the driver can be separated into two
areas:
Output driver stage dissipation
Quiescent current dissipation used to supply the
internal logic and control functions.
Output Driver Stage Power Dissipation
Power dissipation in the driver’s output stage is mainly
caused by charging and discharging the gate to source
and gate to drain capacitance of the external MOSFET.
Figure 3 shows a simplified circuit of the MIC4223 driving
an external MOSFET.
Figure 4. MOSFET Gate Charge vs. VGS
The energy dissipated during turn-on is calculated as:
E = 12 × Ciss × VGS
2
where C iss is the MOSFET' s total gate capacitance
but :
Q = C× V
so
E = 1/2 × Q G × VGS
Figure 3. Functional MOSFET/Driver Diagram
An equivalent amount of energy is dissipated in the
driver’s sink circuit when the MOSFET turns off. The total
energy and power dissipated by the drive components is:
EDRIVER = QG × VGS
and
PDRIVER =QG ×VGS × fS
Dissipation Caused by Switching the External
MOSFET
Energy from capacitor CVDD is used to charge up the input
capacitance of the MOSFET (CGD and CGS). The energy
delivered to the MOSFET is dissipated in the upper driver
MOSFET and Bipolar impedances. The effective
capacitance of CGD and CGS is difficult to calculate since
they vary non-linearly with ID, VGS, and VDS. Fortunately,
most power MOSFET specifications include a typical
graph of total gate charge vs. VGS. Figure 4 shows a
typical MOSFET gate charge curve. The graph illustrates
that for a gate voltage of 10V, the MOSFET requires about
23.5nC of charge.
June 2009
Where:
EDRIVER is the energy dissipated per switching cycle
PDRIVER is the power dissipated by switching the
MOSFET on and off
QG is the total Gate charge at VGS
VGS is the MOSFETs Gate to Source voltage
fS is the switching frequency of the Gate drive
circuit
10
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Quiescent Current Power Dissipation
Quiescent current powers the internal logic, level shifting
circuitry and bias for the output drivers. This current is
proportional to operating frequency and VDD voltage. The
typical characteristic graphs show how supply current
varies with switching frequency and supply voltage.
The power dissipated by the driver’s quiescent current is:
PDISS: GATE Charge
vs. Frequency
1.4
VDD=5V
50nC
1.2
PDISS (W)
1.0
Pdiss quiescent = V DD × I DD
40nC
0.8
30nC
0.6
20nC
0.4
Total Power Dissipation and Thermal Considerations
Total package power dissipation equals the power
dissipation of each driver caused by driving the external
MOSFETs plus the supply current.
10nC
0.2
0
100k
1M
FREQUENCY (Hz)
PdissTOTAL = Pdissquiescent + PdriverA + PdriverB
10M
Figure 5a. PDISS vs. QG and fS for VDD = 5V
The die temperature may be calculated once the total
power dissipation is known.
TJ = T A + PdissTOTAL × θ JA
PDISS: GATE Charge
vs. Frequency
Where:
TA is the Maximum ambient temperature
TJ is the junction temperature (°C)
PdissTOTAL is the power dissipation of the Driver
2.0
V =12V
1.8 DD
50nC
40nC
30nC
PDISS (W)
1.6
θJA is the thermal resistance from junction-toambient air (°C/W)
The following graphs help determine the maximum gate
charge that can be driven with respect to switching
frequency, supply voltage and ambient temperature.
Figure 5a shows the power dissipation in the driver for
different values of gate charge with VDD = 5V. Figure 5b
shows the power dissipation at VDD = 12V. Figure 5c show
the maximum power dissipation for a given ambient
temperature for the SOIC and ePAD MSOP packages.
The maximum operating frequency of the driver may be
limited by the maximum power dissipation of the driver
package.
1.4
1.2
1.0
20nC
0.8
0.6
10nC
0.4
0.2
0
100k
1M
FREQUENCY (Hz)
10M
Figure 5b. PDISS vs. QG and fS for VDD = 12V
Maximum Power
Dissipation
Power Dissipation (W)
2.0
1.5
1.0
0.5
0.0
20
40
60
80
100
120
140
Ambient Temperature (°C)
Figure 5c. Maximum PDISS vs. Ambient Temperature
June 2009
11
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Micrel, Inc.
Bypass Capacitor Selection
Bypass capacitors are required for proper operation by
supplying the charge necessary to drive the external
MOSFETs as well as minimize the voltage ripple on the
supply pins.
Ceramic capacitors are recommended because of their
low impedance and small size. Z5U type ceramic capacitor
dielectrics are not recommended due to the large change
in capacitance over temperature and voltage.
Manufacturer specifications should be checked to insure
voltage and temperature do not reduce the capacitance
below the value needed. A minimum value of 1µF is
required regardless of the MOSFETs being driven. Larger
MOSFETs, with their higher input capacitance may require
larger decoupling capacitance values for proper operation.
The voltage rating of the capacitors depends on the supply
voltage, ambient temperature and the voltage derating
used for reliability.
Placement of the decoupling capacitors is critical. The
bypass capacitor for VDD should be placed as close as
possible between the VDD and GND pins. The etch
connections must be short, wide and direct. The use of a
ground plane to minimize connection impedance is
recommended. Multiple vias insure a low inductance path
and help with power dissipation. Refer to the section on
layout and component placement for more information.
Grounding, Component Placement and Circuit Layout
Nanosecond switching speeds and ampere peak currents
in and around the MOSFET driver necessitate proper
placement and trace routing of all components. Improper
placement may cause degraded noise immunity, false
switching and excessive ringing.
Figure 6 shows the critical current paths when the driver
outputs go high and turn on the external MOSFETs. It also
helps demonstrate the need for a low impedance ground
plane. Charge needed to turn-on the MOSFET gates
comes from the decoupling capacitors CVDD. Current in the
gate driver flows from CVDD through the internal driver, into
the MOSFET gate and out the Source. The return
connection back to the decoupling capacitor is made
through the ground plane. Any inductance or resistance in
the ground return path causes a voltage spike or ringing to
appear on the source of the MOSFET. This voltage works
against the gate drive voltage and can either slow down or
turn off the MOSFET during the period where it should be
turned on.
June 2009
MIC4223/MIC4224/MIC4225
Figure 6. Driver Turn-On Current Path
Figure 7 shows the critical current paths when the driver
outputs go low and turn off the external MOSFETs. Short,
low impedance connections are important during turn-off
for the same reasons given in the turn-on explanation.
Current from the VDD supply replenishes charge in the
decoupling capacitor, CVDD.
Figure 7. Driver Turn-Off Current Path
The following circuit guidelines should be adhered to for
optimum circuit performance:
The VDD bypass capacitor must be placed close to the
VDD and ground pins. It is critical that the etch length
between the decoupling capacitor and the VDD and GND
pins be minimized to reduce pin inductance. Multiple vias
in parallel help minimize inductance in the ground and VDD
paths.
A ground plane is recommended to minimize parasitic
inductance and impedance of the return paths. The
MIC4223 family of drivers is capable of high peak currents
and very fast transition times. Any impedance between
the driver, the decoupling capacitors and the external
MOSFET will degrade the performance of the circuit.
Trace out the high di/dt and dv/dt paths, as shown in
Figures 6 and 7 and minimize etch length and loop area
for these connections. Minimizing these parameters
decreases the parasitic inductance and the radiated EMI
generated by fast rise and fall times.
12
M9999-061109-A
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Micrel, Inc.
MIC4223/MIC4224/MIC4225
Evaluation Board Schematic (SOIC)
SOIC Package
June 2009
13
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Bill of Materials (SOIC)
Item
C1
Part Number
VJ0603Y104KXXAT
Manufacturer
(1)
Vishay
0.1µF/25V, X7R Ceramic Capacitor, Size 0603
1
1µF/25V, X5R, Ceramic Capacitor, Size 0603
2
1µF/25V, X5R, Ceramic Capacitor, Size 0603
2
MuRata
1µF/25V, X5R, Ceramic Capacitor, Size 0603
2
(2)
1µF/25V, X7R, Ceramic Capacitor, Size 1206
2
(3)
1µF/25V, X7R, Ceramic Capacitor, Size 1206
2
1µF/25V, X7R, Ceramic Capacitor, Size 1206
2
30V N-Channel MOSFET
2
Open location – Size 0603
0
1kΩ Resistor, Size 1206
2
C1608X5R1E105M
TDK
or
06033D105MAT
AVX(3)
C4, C5
GRM188R61E105KA93
C3216X7R1E105K
or
12063D105MAT
or
GRM31MR71H105KA01
Q1, Q2
Si4174DY
(4)
TDK
AVX
MuRata(4)
(1)
Vishay
C3,
R4,
C6,
R9,
R1,
R2,
R6, R8
R5, R7
CRCW12061001FRT1
Qty.
(2)
C2, C7
or
Description
Vishay(1)
(5)
U1
MIC4223YM
Micrel, Inc.
Dual Inverting 4A MOSFET Driver with SOIC Package
1
or
MIC4224YM
Micrel, Inc.(5)
Dual Non-Inverting 4A MOSFET Driver with SOIC Package
1
MIC4225YM
(5)
Dual Inverting/Non-Inverting 4A MOSFET Driver with SOIC
Package
1
or
Micrel, Inc.
Notes:
1. Vishay: www.vishay.com
2. TDK: www.tdk.com
3. AVX: www.avx.com
4. MuRata: www.murata.com
5. Micrel, Inc: www.micrel.com
June 2009
14
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
PCB Layout (SOIC)
June 2009
15
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Evaluation Board Schematic (e-PAD MSOP)
ePAD MSOP
June 2009
16
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
PCB Layout (ePAD MSOP)
June 2009
17
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Bill of Materials (ePAD MSOP)
Item
C1
Part Number
VJ0603Y104KXXAT
Manufacturer
(1)
Vishay
(2)
Description
Qty.
0.1µF/25V, X7R Ceramic Capacitor, Size 0603
1
C2, C7
C1608X5R1E105M
TDK
1µF/25V, X5R, Ceramic Capacitor, Size 0603
2
or
06033D105MAT
AVX(3)
1µF/25V, X5R, Ceramic Capacitor, Size 0603
2
or
GRM188R61E105KA93
MuRata(4)
1µF/25V, X5R, Ceramic Capacitor, Size 0603
2
1µF/25V, X7R, Ceramic Capacitor, Size 1206
2
C4, C5
C3216X7R1E105K
or
12063D105MAT
or
GRM31MR71H105KA01
TDK
(2)
(3)
AVX
MuRata(4)
C3,
R4,
C6,
R9,
R1,
R2,
R6, R8
Q1, Q2
R5, R7
Si4174DY
CRCW12061001FRT1
Vishay(1)
(1)
Vishay
(5)
(5)
1µF/25V, X7R, Ceramic Capacitor, Size
2
1µF/25V, X7R, Ceramic Capacitor, Size
2
Open location – Size 0603
0
30V N-Channel MOSFET
2
1kΩ Resistor, Size 1206
2
U1
MIC4223YMME
Micrel, Inc.
Dual Inverting 4A MOSFET Driver with ePAD MSOP Package
1
or
MIC4224YMME
Micrel, Inc.
Dual Non-Inverting 4A MOSFET Driver with ePAD MSOP
Package
1
MIC4225YM
Micrel, Inc.(5)
Dual Inverting/Non-Inverting 4A MOSFET Driver with ePAD
MSOP Package
1
or
Notes:
1. Vishay: www.vishay.com
2. TDK: www.tdk.com
3. AVX: www.avx.com
4. MuRata: www.murata.com
5. Micrel, Inc: www.micrel.com
June 2009
18
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
Package Information
8-Pin SOIC (M)
June 2009
19
M9999-061109-A
(408) 944-0800
Micrel, Inc.
MIC4223/MIC4224/MIC4225
8-Pin ePAD MSOP (MME)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2009 Micrel, Incorporated.
June 2009
20
M9999-061109-A
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