MOTOROLA MC12179 500 - 2800 mhz single channel frequency synthesizer Datasheet

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500 – 2800 MHz
SINGLE CHANNEL
FREQUENCY SYNTHESIZER
SEMICONDUCTOR
TECHNICAL DATA
2.8 GHz Maximum Operating Frequency
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The MC12179 is a monolithic Bipolar synthesizer integrating the high
frequency prescaler, phase/frequency detector, charge pump, and reference
oscillator/buffer functions. When combined with an external loop filter and
VCO, the MC12179 serves as a complete PLL subsystem. Motorola’s
advanced MOSAIC V technology is utilized for low power operation at a
5.0 V supply voltage. The device is designed for operation up to 2.8 GHz for
high frequency applications such as CATV down converters and satellite
receiver tuners.
Low Power Supply Current of 3.5 mA Typical, Including ICC
and IP Currents
Supply Voltage of 5.0 V Typical
Integrated Divide by 256 Prescaler
On–Chip Reference Oscillator/Buffer
– 2.0 to 11 MHz Operation When Driven From Reference Source
– 5.0 to 11 MHz Operation When Used With a Crystal
Digital Phase/Frequency Detector with Linear Transfer Function
8
1
Balanced Charge Pump Output
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
Space Efficient 8–Lead SOIC
Operating Temperature Range of –40 to 85°C
For additional information on calculating the loop filter components, an
InterActiveApNote document containing software (based on a Microsoft
Excel spreadsheet) and an Application Note is available. Please order
DK306/D from the Motorola Literature Distribution Center.
PIN CONNECTIONS
MOSAIC V, Mfax and InterActiveApNote are trademarks of Motorola, Inc.
MAXIMUM RATINGS (Note 1)
Parameter
Symbol
Value
Unit
Power Supply Voltage, Pin 2
VCC
–0.5 to 6.0
Vdc
Power Supply Voltage, Pin 7
VP
VCC to 6.0
Vdc
Storage Temperature Range
Tstg
–65 to 150
°C
NOTES: 1. Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation should be restricted to the Recommended
Operating Conditions as identified in the Electrical Characteristics table.
2. ESD data available upon request.
OSCin
1
8
OSCout
VCC
2
7
VP
Gnd
3
6
PDout
Fin
4
5
GndP
Block Diagram
OSCin
Crystal
Oscillator
OSCout
Fin
fr
Phase/Frequency
Detector
Prescaler
÷256
(Top View)
Charge
Pump
PDout
ORDERING INFORMATION
fv
Device
Operating
Temperature Range
Package
MC12179D
TA = –40° to +85°C
SO–8
 Motorola, Inc. 1997
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ELECTRICAL CHARACTERISTICS (VCC = 4.5 to 5.5 V; VP = VCC to 5.5 V; TA = –40 to 85°C, unless otherwise noted.)
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Supply Current for VP
Operating Frequency
fINmax
fINmin
Operating Frequency
Crystal Mode
External Oscillator OSCin
Input Sensitivity
Fin
Input Sensitivity
External Oscillator OSCin
Symbol
Min
Typ
Max
Unit
ICC
–
3.1
5.6
mA
Note 1
Condition
IP
–
0.4
1.3
mA
Note 1
FIN
2800
–
–
–
–
500
MHz
Note 2
FOSC
5
2
–
–
11
11
MHz
Note 3
Note 4
VIN
200
–
1000
mVP–P
Note 2
Note 4
VOSC
500
–
2200
mVP–P
Output Source Current5
(PDout)
IOH
–2.8
–2.2
–1.6
mA
VP = 4.5 V, VPDout
= VP/2
Output Sink Current5
(PDout)
IOL
1.6
2.2
2.8
mA
VP = 4.5 V, VPDout
= VP/2
Output Leakage Current
(PDout)
IOZ
–
0.5
15
nA
VP = 5.0 V, VPDout
= VP/2
NOTES: 1. VCC and VP = 5.5 V; FIN = 2.56 GHz; FOSC = 10 MHz crystal; PDout open.
2. AC coupling, FIN measured with a 1000 pF capacitor.
3. Assumes C1 and C2 (Figure 1) limited to ≤30 pF each including stray and parasitic capacitances.
4. AC coupling to OSCin.
5. Refer to Figure 15 and Figure 16 for typical performance curves over temperature and power supply voltage.
PIN FUNCTION DESCRIPTION
2
Pin
Symbol
I/O
Function
1
OSCin
I
Oscillator Input — An external parallel–resonant, fundamental crystal is connected between OSCin
and OSCout to form an internal reference oscillator (crystal mode). External capacitors C1 and C2, as
shown in Figure 1, are required to set the proper crystal load capacitance and oscillator frequency.
For an external reference oscillator, an external signal is AC–coupled to the OSCin pin with a
1000 pF coupling capacitor, with no connection to OSCout. In either mode, a resistor with a nominal
value of 50 kΩ MUST be placed across the OSCin and OSCout pins for proper operation.
2
VCC
—
Positive Power Supply. Bypass capacitors should be placed as close as possible to the pin and be
connected directly to the ground plane.
3
Gnd
—
Ground.
4
Fin
I
5
GndP
—
Ground — For charge pump circuitry.
6
PDout
O
Single ended phase/frequency detector output (charge pump output). Three–state current
sink/source output for use as a loop error signal when combined with an external low pass filter. The
phase/frequency detector is characterized by a linear transfer function.
7
VP
—
Positive power supply for charge pump. VP MUST be equal or greater than VCC. Bypass capacitors
should be placed as close as possible to the pin and be connected directly to the ground plane.
8
OSCout
O
Oscillator output, for use with an external crystal as shown in Figure 1.
Prescaler Input — The VCO signal is AC coupled into the Fin pin.
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Characteristic
Supply Current for VCC
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MC12179
Figure 1. MC12179 Expanded Block Diagram
+5.0 V
VCC
1
OSCin
8
OSCout
C2
NOTE: External 50 kΩ resistor
across Pins 1 and 8 is necessary in
either crystal or driven mode.
4
VCO
1000 pF
VP
Crystal
Oscillator
fr
Phase/Frequency
Detector
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To Loop Filter
PDout
Prescaler
÷256
GND
3
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6
Charge
Pump
fv
Fin
7
GNDP
5
PHASE CHARACTERISTICS
The phase comparator in the MC12179 is a high speed
digital phase/frequency detector circuit. The circuit
determines the “lead” or “lag” phase relationship and time
difference between the leading edges of the VCO (fv) signal
and the reference (fr) input. The detector can cover a range of
±2π radian of fv/fr phase difference. The operation of the
charge pump output is shown in Figure 2.
fr lags fv in phase OR fv>fr in frequency
When the phase of fr lags that of fv or the frequency of fv is
greater than fr, the Do output will sink current. The pulse
width will be determined by the time difference between the
two rising edges.
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C1
+5.0 V
2
fr leads fv in phase OR fv<fr in frequency
When the phase of fr leads that of fv or the frequency of fv
is less than fr, the Do output will source current. The pulse
width will be determined by the time difference between the
two rising edges.
fr = fv in phase and frequency
When the phase and frequency of fr and fv are equal, the
charge pump will be in a quiet state, except for current spikes
when signals are in phase. This situation indicates that the
loop is in lock and the phase comparator will maintain the
loop in its locked state.
Figure 2. Phase/Frequency Detector and Charge Pump Waveforms
H
fr
(OSCin)
L
H
fv
(Fin ÷256)
L
Sourcing Current Pulse
Z
Sinking Current Pulse
PDout
H = High voltage level; L = Low voltage level; Z = High impedance
NOTES: Phase difference detection range: ∼ –2π to 2π
Kp–Charge Pump Gain
mA
[ |Isource4| p) |Isink| + |2.2| )4p|–2.2| + p1.1radian
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Figure 3. Typical Block Diagram of Complete PLL
MC12179 PLL
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External Ref
10.0 MHz
VCO
φ/Freq
Det
Charge
Pump
Loop
Filter
2560.00 MHz
Since the MC12179 is realized with an all–bipolar ECL
style design, the internal oscillator circuitry is different from
more traditional CMOS oscillator designs which realize the
crystal oscillator with a modified inverter topology. These
CMOS designs typically excite the crystal with a rail–to–rail
signal which may overdrive the crystal resulting in damage or
unstable operation. The MC12179 design does not exhibit
these phenomena because the swing out of the OSCout pin is
less than 600mV. This has the added advantage of
minimizing EMI and switching noise which can be generated
by rail–to–rail CMOS outputs. The OSCout output should not
be used to drive other circuitry.
The oscillator buffer in the MC12179 is a single stage, high
speed, differential input/output amplifier; it may be
considered to be a form of the Pierce oscillator. A simplified
circuit diagram is seen in Figure 4.
Figure 4. Simplified Crystal Oscillator/Buffer Circuit
VCC
÷P
256
As can be seen from the block diagram, with the addition
of a VCO, a loop filter, and either an external oscillator or
crystal, a complete PLL sub–system can be realized. Since
most of the PLL function is integrated into the MC12179, the
user’s primary focus is on the loop filter design and the
crystal reference circuit. Figure 13 and Figure 14 illustrate
typical VCO spectrum and phase noise characteristics.
Figure 17 and Figure 18 illustrate the typical input impedance
versus frequency for the prescaler input.
Crystal Oscillator Design
The MC12179 is used as a multiply–by–256 PLL circuit
which transfers the high stability characteristic of a low
frequency reference source to the high frequency VCO in the
PLL loop. To facilitate this, the device contains an input circuit
which can be configured as a crystal oscillator or a buffer for
accepting an external signal source.
In the external reference mode, the reference source is
AC–coupled into the OSCin input pin. The input level signal
should be between 500–2200 mVpp. When configured with
an external reference, the device can operate with input
frequencies down to 2MHz, thus allowing the circuit to control
the VCO down to 512 MHz. To optimize the phase noise of
the PLL when used in this mode, the input signal amplitude
should be closer to the upper specification limit. This
maximizes the slew rate of the input signal as it switches
against the internal voltage reference.
In the crystal mode, an external parallel–resonant
fundamental mode crystal is connected between the OSCin
and OSCout pins. This crystal must be between 5.0 MHz and
11 MHz. External capacitors, C1 and C2 as shown in
Figure 1, are required to set the proper crystal load
capacitance and oscillator frequency. The values of the
capacitors are dependent on the crystal chosen and the input
capacitance of the device and any stray board capacitance.
In either mode, a 50kΩ resistor must be connected
between the OSCin and the OSCout pins for proper device
operation. The value of this resistor is not critical so a 47kΩ or
51kΩ ±10% resistor is acceptable.
4
OSCout
OSCin
To Phase/
Frequency
Detector
Bias
Source
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The MC12179 is intended for applications where a fixed
local oscillator is required to be synthesized. The prescaler
on the MC12179 operates up to 2.8GHz which makes the
part ideal for many satellite receiver applications as well as
applications in the 2nd ISM (Industrial, Scientific, and
Medical) band which covers the frequency range of
2400MHz to 2483MHz. The part is also intended for MMDS
(Multi–channel Multi–point Distribution System) block
downconverter applications. Below is a typical block diagram
of the complete PLL.
OSCin drives the base of one input of an NPN transistor
differential pair. The non–inverting input of the differential pair
is internally biased. OSCout is the inverted input signal and is
buffered by an emitter follower with a 70 µA pull–down
current and has a voltage swing of about 600 mVpp. Open
loop output impedance is about 425Ω. The opposite side of
the differential amplifier output is used internally to drive
another buffer stage which drives the phase/frequency
detector. With the 50 kΩ feedback resistor in place, OSCin
and OSCout are biased to approximately 1.1V below VCC.
The amplifier has a voltage gain of about 15 dB and a
bandwidth in excess of 150 MHz. Adherence to good RF
design and layout techniques, including power supply pin
decoupling, is strongly recommended.
A typical crystal oscillator application is shown in Figure 1.
The crystal and the feedback resistor are connected directly
between OSCin and OSCout, while the loading capacitors, C1
and C2, are connected between OSCin and ground, and
OSCout and ground respectively. It is important to understand
that as far as the crystal is concerned, the two loading
capacitors are in series (albeit through ground). So when the
crystal specification defines a specific loading capacitance,
this refers to the total external (to the crystal) capacitance
seen across its two pins.
This capacitance consists of the capacitance contributed
by the amplifier (IC and packaging), layout capacitance, and
the series combination of the two loading capacitors. This is
illustrated in the equation below:
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C2
+ CAMP ) CSTRAY ) C1
C1 ) C2
Provided the crystal and associated components are
located immediately next to the IC, thus minimizing the stray
capacitance, the combined value of CAMP and CSTRAY is
approximately 5pF. Note that the location of the OSCin and
OSCout pins at the end of the package, facilitates placing the
crystal, resistor and the C1 and C2 capacitors very close to
the device. Usually, one of the capacitors is in parallel with an
adjustable capacitor used to trim the frequency of oscillation.
It is important that the total external (to the IC) capacitance
seen by either OSCin or OSCout, be no greater than 30pF.
In operation, the crystal oscillator will start up with the
application of power. If the crystal is in a can that is not
grounded it is often possible to monitor the frequency of
oscillation by connecting an oscilloscope probe to the can;
this technique minimizes any disturbance to the circuit. If a
malfunction is indicated, a high impedance, low capacitance,
FET probe may be connected to either OSCin or OSCout.
Signals typically seen at those points will be very nearly
sinusoidal with amplitudes of roughly 300 to 600 mVpp.
Some distortion is inevitable and has little bearing on the
accuracy of the signal going to the phase detector.
Loop Filter Design
Because the device is designed for a non–frequency agile
synthesizer (i.e., how fast it tunes is not critical) the loop filter
design is very straight forward. The current output of the
charge pump allows the loop filter to be realized without the
need of any active components. The preferred topology for
the filter is illustrated below in Figure 5.
Figure 5. Loop Filter
Xtl
Osc
Ph/Frq
Det
Chrg
Pump
Kp
÷256
N
VCO
Ro
Co
Rx
Kv
Ca
Cx
MC12179
The Ro/Co components realize the primary loop filter. Ca is
added to the loop filter to provide for reference sideband
suppression. If additional suppression is needed, the Rx/Cx
realizes an additional filter. In most applications, this will not
be necessary. If all components are used, this results in a 4th
order PLL, which makes analysis difficult. To simplify this, the
loop design will be treated as a 2nd order loop (Ro/Co) and
additional guidelines are provided to minimize the influence
of the other components. If more rigorous analysis is needed,
mathematical/system simulation tools can be used.
Component
Guideline
Ca
<0.1 × Co
Rx
>10 × Ro
Cx
<0.1 × Co
The focus of the design effort is to determine what the
loop’s natural frequency, ωo, should be. This is determined by
Ro, Co, Kp, Kv, and N. Because Kp, Kv, and N are given, it is
only necessary to calculate values for Ro and Co. There are
3 considerations in selecting the loop bandwidth:
1) Maximum loop bandwidth for minimum tuning speed
2) Optimum loop bandwidth for best phase noise
performance
3) Minimum loop bandwidth for greatest reference
sideband suppression
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Usually a compromise is struck between these 3 cases,
however, for the fixed frequency application, minimizing the
tuning speed is not a critical parameter.
To specify the loop bandwidth for optimal phase noise
performance, an understanding of the sources of phase
noise in the system and the effect of the loop filter on them is
required. There are 3 major sources of phase noise in the
phase–locked loop – the crystal reference, the VCO, and the
loop contribution. The loop filter acts as a low–pass filter to
the crystal reference and the loop contribution equal to the
total divide–by–N ratio. This is mathematically described in
Figure 10. The loop filter acts as a high–pass filter to the VCO
with an in–band gain equal to unity. This is described in
Figure 11. The loop contribution includes the PLL IC, as well
as noise in the system; supply noise, switching noise, etc.
For this example, a loop contribution of 15 dB has been
selected, which corresponds to data in Figure 14.
The crystal reference and the VCO are characterized as
high–order 1/f noise sources. Graphical analysis is used to
determine the optimum loop bandwidth. It is necessary to
have noise plots from the manufacturer. This method
provides a straightforward approximation suitable for quickly
estimating the optimal bandwidth. The loop contribution is
characterized as white–noise or low–order 1/f noise given in
the form of a noise factor which combines all the noise effects
into a single value. The phase noise of the Crystal Reference
is increased by the noise factor of the PLL IC and related
circuitry. It is further increased by the total divide–by–N ratio
of the loop. This is illustrated in Figure 6.
The point at which the VCO phase noise crosses the
amplified phase noise of the Crystal Reference is the point of
the optimum loop bandwidth. In the example of Figure 6, the
optimum bandwidth is approximately 15 KHz.
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Figure 6. Graphical Analysis of Optimum Bandwidth
–60
15kHz/2.5 or 6kHz (37.7krads) with a damping coefficient,
ζ ≈ 1. T(s) is the transfer function of the loop filter.
Optimum Bandwidth
–70
Figure 8. Design Equations for the 2nd Order System
–80
VCO
T(s)
–100
20*log(256)
–110
–120
–130
Crystal Reference
–150
100
1k
10k
100k
1M
Hz
Figure 7. Closed Loop Frequency Response for ζ = 1
Natural Frequency
10
3dB Bandwidth
0
–10
–20
dB
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10
–30
–40
–50
–60
0.1
1
10
Hz
100
ǒ Ǔ
NCo
K pK v
1k
To simplify analysis further a damping factor of 1 will be
selected. The normalized closed loop response is illustrated
in Figure 7 where the loop bandwidth is 2.5 times the loop
natural frequency (the loop natural frequency is the
frequency at which the loop would oscillate if it were
unstable). Therefore the optimum loop bandwidth is
s2
)1
) RoCos ) 1
ǒǓ)
+ǒ Ǔ
)ǒ Ǔ )
2z
wo s
1
2
wo2 s
1
2z
wo s
1
ǒ Ǔ+ǒ Ǔ³ +Ǹ ³ [ǒ Ǔ
Ǔ³ +ǒ Ǔ
+ǒ Ǔ³ +ǒ
NCo
KpKv
15dB NF of the Noise
Contribution from Loop
–140
+
RoCos
RoCo
1
wo2
2z
wo
wo
z
Kp Kv
NCo
woRoCo
2
Co
Ro
KpKv
Nwo2
2z
woCo
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dB
–90
In summary, follow the steps given below:
Step 1: Plot the phase noise of crystal reference and the
VCO on the same graph.
Step 2: Increase the phase noise of the crystal reference by
the noise contribution of the loop.
Step 3: Convert the divide–by–N to dB (20log 256 – 48 dB)
and increase the phase noise of the crystal
reference by that amount.
Step 4: The point at which the VCO phase noise crosses the
amplified phase noise of the Crystal Reference is the
point of the optimum loop bandwidth. This is
approximately 15 kHz in Figure 6.
Step 5: Correlate this loop bandwidth to the loop natural
frequency and select components per Figure 8. In
this case the 3.0 dB bandwidth for a damping
coefficient of 1 is 2.5 times the loop’s natural
frequency. The relationship between the 3.0 dB loop
bandwidth and the loop’s “natural” frequency will
vary for different values of ζ. Making use of the
equations defined above in a math tool or spread
sheet is useful. To aid in the use of such a tool the
equations are summarized in Figures 9 through 11.
Figure 9. Loop Parameter Relations
Let:
NCo
KpKv
Let: Ca
+ w1 2
o
+ aCo ,
, RoCo
Cx
+ w2zo
+ bCo , A + 1 ) a ,
and B
+1)a)b
+ w13 , RxCx + w14 , Ro(Ca ) Cx) + w15
K3w3 + wo , K4w4 + wo , K5w5 + wo
Let: RoCo
Let:
6
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Figure 10. Transfer Function for the Crystal Noise in the Frequency Plane
T(jw)
+N@
ǒ
1
)
) j ǒ 2z ww Ǔ
* B ww Ǔ ) j ǒ 2z ww * (AK4 ) K5) ww
1
4
K3K4 w 4
wo
o
3
2
o
o2
o3
Ǔ
Figure 11. Transfer Function for the VCO Noise in the Frequency Plane
+
ǒ
1
* B ww Ǔ * j ǒ (AK4 ) K5) ww Ǔ
* B ww Ǔ ) j ǒ 2z ww * (AK4 ) K5) ww
4
K3K4 w 4
) K3K4 ww
wo
4
o4
2
3
o2
o3
3
2
o
o2
o3
Ǔ
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T(jw)
ǒ
overall transfer function of the loop filter. To use these
equations in determining the overall transfer function of a PLL
multiply the filter’s impedance by the gain constant of the
phase detector then multiply that by the filter’s transfer
function (which is unity in the 2nd and 3rd order cases
below).
Appendix: Derivation of Loop Filter Transfer Function
The purpose of the loop filter is to convert the current from
the phase detector to a tuning voltage for the VCO. The total
transfer function is derived in two steps. Step 1 is to find the
voltage generated by the impedance of the loop filter. Step 2
is to find the transfer function from the input of the loop filter to
its output. The “voltage” times the “transfer function” is the
Figure 12. Overall Transfer Function of the PLL
For the 2nd Order PLL:
Vp
Vt
Ro
ZLF(s)
Co
TLF(s)
For the 3rd Order PLL:
Vp
Vt
Ro
Ca
Co
ZLF(s)
+ VVpt(s)
+1 ,
(s)
Vp(s)
+ Kp(s)ZLF(s)
+ C R CRso2C)os(C) 1) C )s
o o a
TLF(s)
For the 4th Order PLL:
+ RoCCooss) 1
+ VVpt(s)
+1 ,
(s)
Vp
o
Vp(s)
a
+ Kp(s)ZLF(s)
Vt
Ro
Ca
Rx
Cx
Co
ZLF(s)
+ C R C R C s3 ) [ (C )(RC o)RCosC))1)C(RRxC(Cxs ))1)C ) ] s2 ) (C ) C ) C )s
o o a x x
o
a x x
o o x
a
o
a
x
TLF(s)
+ VVpt(s)
+ (RxCx1s ) 1)
(s)
, Vp(s)
+ Kp(s)ZLF(s)
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Figure 13. VCO Output Spectrum with MC12179, VCC = 5.0 V
(ECLiPTEK 8.9 MHz Crystal and ZCOM 2500 VCO)
NOTE: Spurs can be reduced further by narrowing the loop bandwidth of the PLL loop filter and/or
adding an extra filter (Rx/Cx)
Figure 14. Typical Phase Noise Plot, 2200 MHz VCO
(With the MC12179 in a Closed Loop)
HP 3048A
CARRIER
2200MHz
0
–25
dBc/Hz
–50
–75
–100
–125
–150
–170
1k
10k
100k
1M
10M
40M
L(f) [dBc/Hz] vs f[Hz]
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Figure 15. Typical Charge Pump Current versus Temperature
(VCC = Vpp = 5.0 V)
2.5
2.0
SINK
1.5
–40°C
+25°C
+85°C
0.5
0.0
–0.5
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–1.0
–1.5
SOURCE
–2.0
–2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Voltage at PDout (V)
Figure 16. Typical Charge Pump Current versus Voltage
(T = 25°C)
2.5
2.0
SINK
1.5
4.5V VCC/VPP
5.0V VCC/VPP
5.5V VCC/VPP
1.0
Sink/Source Current (mA)
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Sink/Source Current (mA)
1.0
0.5
0.0
–0.5
–1.0
–1.5
SOURCE
–2.0
–2.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Voltage at PDout (V)
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Freescale Semiconductor,
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MC12179
Figure 17. Typical Real Input Impedance versus Input Frequency
(For the Fin Input)
100
80
R (Ohms)
60
20
0
250
500
750
1000
1250
1500
1750
2000
2250
2500
2750
Frequency (MHz)
Figure 18. Typical Imaginary Input Impedance versus Input Frequency
(For the Fin Input)
50
25
0
–25
jX (Ohms)
–50
–75
–100
–125
–150
–175
–200
–225
–250
250
500
750
1000
1250
1500
1750
2000
2250
2500
2750
Frequency (MHz)
10
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ARCHIVE INFORMATION
Freescale Semiconductor, Inc...
ARCHIVE INFORMATION
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Freescale Semiconductor,
Inc.
MC12179
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC PACKAGE
CASE 751-06
(SO–8)
ISSUE T
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
5
0.25
H
E
M
B
M
1
4
h
Freescale Semiconductor, Inc...
ARCHIVE INFORMATION
B
X 45 _
e
q
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
DIM
A
A1
B
C
D
E
e
H
h
L
q
S
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
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D
A
Mfax is a trademark of Motorola, Inc.
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