[AK1572]
AK1572
Down Converter Mixer with
Fractional-N Frequency Synthesizer and VCO
1.
Overview
AK1572 is the down-converter mixer with fractional-N frequency synthesizer and integrated VCO.
AK1572 is targeted at the application that requires a high linearity performance in frequency
conversion. The mixer block is comprised of the single input and the differential output. Input
frequency range is from 690MHz to 4000MHz and output frequency range is from 20MHz to 500MHz.
The current consumption and the analog performance can be adjusted by a resistance connected to
BIAS pin. The power supply voltage of mixer covers 4.75 to 5.25V.
The local signal output frequency range is from 262.5MHz to 4400MHz generated by internal VCO,
synthesizer and divider. Not only a local signal is supplied to an internal mixer, but also can be taken
to outside. A power supply voltage range of VCO/synthesizer is 2.7V to 3.6V or 4.75V to 5.25V.
The CPU interface is 24bit serial data and its voltage is ranging from 2.7V to 5.25V
2.
Features
General
RF input frequency Range
IF output frequency Range
LO frequency Range
Supply Voltage :
690MHz to 4.0GHz
20MHz to 500MHz
262.5MHz to 4.4GHz
4.75V to 5.25 V (Mixer)
2.7 to 3.6V / 4.75 to 5.25V (Synthesizer /VCO)
150mA typ.
32pin QFN (0.5mm pitch, 5mm 5mm 0.85mm)
-40°C ~ 85°C
Current Consumption:
Package:
Operating Temperature :
Synthesizer/VCO
Normalized Phase Noise
Phase Noise
-218dBc/Hz
-111dBc/Hz @100kHz fo=2.1GHz
Mixer (frf=2GHz)
Conversion Gain
Input 3rd orders intercept point
Noise Figure
-1.5dB typ.
+23dBm typ.
14dB typ.
Application
Microwave Radio Link
Cellular
BTS / Repeater
MS1551-E-00
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2013//8
[AK1572]
3.
Table of Content
1.
Overview____________________________________________________________ 1
2.
Features ____________________________________________________________ 1
3.
Table of Content _____________________________________________________ 2
4.
Block Diagram and Function____________________________________________ 3
5.
Pin function Description and Assignment ________________________________ 4
6.
Absolute Maximum Rating _____________________________________________ 6
7.
Recommended Operating Range ________________________________________ 7
8.
Electrical Characteristics ______________________________________________ 7
9.
Block Functional Descriptions _________________________________________ 11
10.
Loop filter /Charge Pump _____________________________________________ 12
11.
Register Map _______________________________________________________ 13
12.
Lock Detect ________________________________________________________ 22
13.
Frequency Setup ____________________________________________________ 25
14.
Fast Lock mode _____________________________________________________ 26
15.
VCO _______________________________________________________________ 27
16.
Power up Sequence _________________________________________________ 28
17.
Typical Evaluation Board Schematic ____________________________________ 29
18.
Interface Circuit _____________________________________________________ 31
19.
Outer Dimensions ___________________________________________________ 33
20.
Marking ____________________________________________________________ 34
MS1551-E-00
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2013//8
[AK1572]
GND
CPVDD
PDN
CPBIAS
SVDD
Lock
Detect
Dig
LDO
VREF1
CPBUFVDD
Block Diagram and Function
TEST1
TEST2
4.
LD
GND
R Counter
8bit
REFIN
CLK
DATA
LE
Phase
Frequency
Detector
VIREFGEN
VCOVDD
VCNT
VCO
Calibration
Divider
1/N
N=1,2,4,8
GND
VREF2
GND
VCO
ΔΣ
Modulator
MIXBIAS
CP
Fast Counter
Register
24bit
PVDD
Charge
Pump
LOP
LON
MUX
N-Counter
OAVDD
MIXINP
MIXINN
MUX
MIXOUTN
MIXOUTP
LOVDD
MIXVDD
Mixer
Fig. 1
AK1572 Block diagram
Block function description
Block
Function
Mixer
Frequency Mixer which converts RF signal to IF signal
Frequency divider which divides the signal of VCO and pass it to
phase frequency detector
Control the modulus of N divider and realize fractional dividing
Frequency divider which divides the signal of reference clock and
pass it to phase frequency detector
Detect a phase difference between the divided VCO signal and
comparison frequency, and then drive the charge pump
Output the electric charge according to the phase difference
detected by PFD
The voltage controlled oscillator divided into three bands
N divider
ΔΣ Modulator
R counter
PFD (Phase Frequency Detector)
Charge Pump
VCO
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[AK1572]
5.
Pin function Description and Assignment
1. Pin Functions
No
Name
I/O
1
VREF1
AO
2
3
PVDD
GND
P
G
4
MIXBIAS
AI
5
6
7
MIXINN
MIXINP
MIXVDD
AI
AI
P
8
9
10
LOVDD
MIXOUTP
MIXOUTN
P
AO
AO
11
PDN
DI
12
13
14
15
16
17
18
19
20
21
LE
CLK
DATA
LD
SVDD
LOP
LON
OAVDD
GND
VCNT
DI
DI
DI
DO
P
AIO
AIO
P
G
AI
22
VREF2
AO
23
24
GND
VCOVDD
G
P
25
CPBIAS
AI
26
CP
AO
27
28
GND
CPVDD
G
P
29
CPBUFVDD
P
MS1551-E-00
Pin function
Power
Down
Remarks
Connecting a capacitor to the ground
plane
Synthesizer Power Supply
Connecting a resistor to the ground
plane
Mixer Input
Mixer Complementary Input
Mixer Power Supply
Mixer Local Power Supply
Mixer Output
Mixer Complementary Output
Power Control
A logic low on this pin powers down
the device
Load Enable
Serial Clock Input
Serial Data Input
Lock Detect Output
Interface Power Supply
Local complementary Input / Output
Local Input / Output
Local Output Amplifier Power Supply
Open collector
Open collector
Schmidt trigger input
Schmidt trigger input
Schmidt trigger input
Schmidt trigger input
LOW
Control Input to VCO
Connecting a capacitor to the ground
plane
VCO Power Supply
Connecting a resistor to the ground
plane
Charge Pump Output
Tri-St
ate
Charge Pump Power Supply
Charge Pump Pre-Buffer Power
Supply
4
2013//8
[AK1572]
No
Name
I/O
30
TEST1
DI
31
TEST2
DI
32
REFIN
AI
Power
Down
Pin function
Test enable
A logic low on this pin test mode the
device.
Test enable
A logic low on this pin test mode the
device.
Reference Input
Remarks
Pull Down
Schmidt trigger input
Pull Down
Schmidt trigger input
Note 1) The exposed pad at the center of the backside should be connected to ground.
The following table shows the meaning of abbreviations used in the “I/O” column above.
AI:Analog input pin
AO:Analog output pin AIO:Analog I/O pin
DI:Digital input pin
DO:Digital output pin P: Power supply pin
G:Ground pin
2. Pin Assignments
24
23
22
21
20
19
18
17
25
16
26
15
27
14
28
13
33
29
12
30
11
31
10
32
9
1
2
3
4
5
6
7
8
32pin QFN (0.5mm pitch, 5mm x 5mm)
Fig. 2 Package Pin Layout (Top View)
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[AK1572]
6.
Parameter
Supply Voltage
Ground Level
Maximum RF Input Level
Maximum Lo Input Level
Analog Input Voltage
Digital Input Voltage1
Digital Input Voltage 2
Input Current
Storage Temperature
Absolute Maximum Rating
Symbol
VDD1
VDD2
VDD3
VSS
RFPOW
LOPOW
VAIN
VDIN1
VDIN2
IIN
Tstg
Min.
-0.3
-0.3
-0.3
0
VSS-0.3
VSS-0.3
VSS-0.3
-10
-55
Max.
5.5
5.5
5.5
0
12
12
VDD3+0.3
VDD1+0.3
VDD3+0.3
10
125
Unit
V
V
V
V
dBm
dBm
V
V
V
mA
C
Remarks
Note1, Note2
Note 3
Note4
Note5
Note6
Note7
Note1, Note8
Note1, Note9
Note1, Note10
Note1
All voltage reference ground level: 0V
Note2
Applied to the [SVDD] pin
Note3
Applied to the [MIXVDD] and [LOVDD] pins
Note4
Applied to the [CPVDD], [CPBUFVDD], [PVDD], [VCOVDD] and [OAVDD] pins
Note5
Applied to the All [GND] pins
Note6
Applied to the [MIXINP] and [MIXINN] pins
Note7
Applied to the [LOP] and [LON] pins
Note8
Applied to the [VCNT] and [REFIN] pins
Note9
Applied to the [CLK], [DATA], [LE] and [PDN] pins
Note10 Applied to the [TEST1] and [TEST2] pins
Exceeding these maximum ratings may result in damage to the AK1572. Normal operation is not
guaranteed at these extremes.
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[AK1572]
7.
Parameter
Operating
Temperature
Recommended Operating Range
Symbol
Min.
Typ.
Max.
Unit
85
C
Ta
-40
VDD1
VDD2
2.7
4.75
2.7
3.0
5
3
5.25
5.25
3.6
V
V
V
4.75
5
5.25
V
Supply Voltage
VDD3
Remarks
Note1
Applied to the [SVDD] pin
Note2
Applied to the [MIXVDD] and [LOVDD] pins
Note3
Applied to the [CPVDD], [CPBUFVDD], [PVDD], [VCOVDD] and [OAVDD] pins
8.
Electrical Characteristics
1. Digital DC Characteristics
Parameter
High level input
voltage
Low level input
voltage
High level input
current 1
High level input
current 2
Low level input
current
High level output
voltage
Low level output
voltage
Symbol Conditions
Min.
Vih
0.8VDD1
Vil
Iih1
Vih = VDD1=5.25V
-1
Iih2
Vih = VDD2=5.25V
27
Iil
Vil = 0V,
-1
VDD1=5.25V
Voh
Ioh = -500A
Vol
Iol = 500A
53
Max.
Unit
Remarks
V
Note 1)
0.2VDD1
V
Note 1)
1
A
Note 1)
106
A
Note 2)
1
A
Note 1)
V
Note 3)
V
Note 3)
VDD1-0.4
0.4
Note1
Applied to the [CLK], [DATA], [LE], and [PDN] pins
Note2
Applied to the [TEST1] and [TEST2] pins
Note3
Applied to the [LD] pin
MS1551-E-00
Typ.
7
2013//8
[AK1572]
2. Serial Interface Timing
<Write-In Timing>
Tcsu
Tlesu
Tle
LE
(Input)
Tch
Tcl
CLK
(Input)
Tsu
DATA
(Input)
D19
Thd
D18
6
D0
A3
A2
A1
A0
Max.
Unit
Fig.3 Serial Interface Timing
Serial Interface Timing
Parameter
Symbol
Min.
Typ.
Clock L level hold time
Tcl
25
ns
Clock H level hold time
Tch
25
ns
Clock setup time
Tcsu
10
ns
Data setup time
Tsu
10
ns
Data hold time
Thd
10
ns
LE setup time
Tlesu
10
ns
LE pulse width
Tle
25
ns
MS1551-E-00
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Remarks
2013//8
[AK1572]
3. Analog Circuit Characteristics
VDD1=2.7~5.25V, VDD2=4.75～5.25V,VDD3=2.7~3.6V or 4.75~5.25V, -40℃＜Ta＜85℃,
CPBIAS=27kohm, MIXBIAS=33kohm, IF output frequency=200MHz, Internal VCO using
unless otherwise specified.
Item
Min.
Typ.
Max.
Unit
RF Frequency Range
690
4000
MHz
IF Frequency Range
20
500
MHz
262.5
4400
MHz
Internal LO Frequency Range
LO Input Level
-5
LO Input Level 2
0
+5
-5
LO Output Level @1GHz
+1
dBm
Remark
{MODE}=2,differential input
or {MODE}=3
dBm
{MODE}=2, single input
6
dBm
{LOLV}=3
3
dBm
{LOLV}=2
0
dBm
{LOLV}=1
-6
dBm
{LOLV}=0
Mixer
Mixer Input impedance
50
Ω
with matching circuit
Mixer Output impedance
200
Ω
with matching circuit
kΩ
Connect to [MIXBIAS] pin
Current Adjusting resistance
22
33
56
RFIN=2GHz
Conversion Gain
-4.5
Half IF response
-1.5
1.5
dB
-60
dBc
Pin=-5dBm
RF P1dB
7
10
dBm
IIP3
20
23
dBm
guaranteed by design
dB
guaranteed by design
NF
Local Leakage
Local Leakage
14
LO-to-RF
LO-to-IF
17
-60
dBm
Use internal VCO
-55
dBc
Use external Local
-80
dBm
Use internal VCO
-70
dBc
Use external Local
RFIN=1GHz
NF
12
dB
RFIN=4GHz
NF
MS1551-E-00
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9
dB
2013//8
[AK1572]
Item
Min.
Typ.
Max.
Unit
Remark
REFIN characteristics
Input Sensitivity
0.4
2
Vpp
Input Frequency
10
300
MHz
Phase Frequency Detector
PFD frequency
1.2
40
MHz
Charge Pump
CP Maximum current
2400
μA
CP Minimum current
300
μA
1
nA
Icp TRI-STATE leak current
CP Output Range
CP current adjusting
resistance
VDD3
0.5
22
Normalized Phase Noise
Ta=25°C
V
-0.5
27
kΩ
33
-218
Connect to [CPBIAS] pin
dBc/Hz
VCO
Operating Frequency Range
2100
3000
MHz
VCO1
3000
3400
MHz
VCO2
3400
4400
MHz
VCO3
VCO sensitivity
fv×0.02
MHz/V
Phase Noise
10kHz offset
-85
dBc/Hz
@2.1GHz
100kHz offset
-111
dBc/Hz
1MHz offset
-132
dBc/Hz
10MHz offset
-152
dBc/Hz
Item
Min.
Typ.
Max.
fv: Oscillation Frequency
Unit
Remark
[PDN]=”L”
[PDN]=”H”,{MIXEN}=1,
{MODE}=0,{DIV}=0
[PDN]=”H”,{MIXEN}=1,
{MODE}=0,{DIV}≥2
[PDN]=”H”,{MIXEN}=1,
{MODE}=1,{DIV}≥2
Current Consumption
IDD1
1
2
mA
IDD2
140
200
mA
IDD3
150
210
mA
IDD4
190
270
mA
MS1551-E-00
2013//8
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[AK1572]
9.
・
Block Functional Descriptions
Operation Mode
AK1572 operation is controlled as follows by the [PDN] pin and registers.
Function
Pin
Registers
Operating state
[PDN]
{MIXEN}
MODE[1]
MODE[2] Mixer
Synthesizer
VCO
Local Out
StandBy1
”L”
X
X
X
OFF
OFF
OFF
OFF
Prohibited
”H”
0
0
0
OFF
ON
ON
OFF
Func1
”H”
0
0
1
OFF
ON
ON
Output
Func2
”H”
0
1
0
OFF
ON
OFF
Input
StandBy2
”H”
0
1
1
OFF
OFF
OFF
OFF
Func3
”H”
1
0
0
ON
ON
ON
OFF
Func4
”H”
1
0
1
ON
ON
ON
Output
Func5
”H”
1
1
0
ON
ON
OFF
Input
Func6
”H”
1
1
1
ON
OFF
OFF
Input
StandBy1:Stand-by mode. Current consumption is minimized. It is available to write to the registers.
Func1: VCO and Synthesizer are active and Local signal outputs from [LOP] and [LON] pins.
Func2:Only Synthesizer is active. PLL operation is available with the external VCO.
StandBy2: Stand-by mode. Current consumption is minimized. It is available to write to the registers.
Func3: VCO, Synthesizer and Mixer are active.
Func4: VCO, Synthesizer and Mixer are active and Local signal outputs from [LOP] and [LON] pins.
Func5: Synthesizer and Mixer are active. PLL operation is available with the external VCO.
Func6: Only Mixer is active. A local signal needs to be input from [LOP] and [LON] pins.
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2013//8
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[AK1572]
10. Loop filter /Charge Pump
Phase Detector
Loop Filter
up
R3
CP
C1
down
R2
C3
Timer
C2
VCO
Fig.4
MS1551-E-00
2013//8
Loop Filter Schematic
12
[AK1572]
11. Register Map
Name
Data
Address
0
0
0
1
0
0
1
0
Freq3
0
0
1
1
Function
0
1
0
0
Freq1
Freq2
Name
D19 - D0
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10
D7
D6
D5
D4
D3
D2
D1
D0
Address
INT
[9]
INT
[8]
INT
[7]
INT
[6]
INT
[5]
INT
[4]
INT
[3]
INT
[2]
INT
[1]
INT
[0]
0x01
0
0
0
VCO
[1]
VCO
[0]
DIV
[1]
DIV
[0]
0
Freq2
0
CP1
[2]
CP1
[1]
CP1
[0]
0
CP2
[2]
CP2
[1]
CP2
[0]
FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC FRAC
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
FRAC
[0]
0x02
Freq3
R
[7]
R
[6]
R
[5]
R
[4]
R
[3]
R
[2]
R
[1]
R
[0]
MOD
[11]
MOD
[10]
MOD
[9]
MOD
[8]
MOD
[7]
MOD
[6]
MOD
[5]
MOD
[4]
MOD
[3]
MOD
[1]
MOD
[0]
0x03
0
LDCNT
SEL
LD
MTLD
FAST
EN
FAST
[3]
FAST
[2]
FAST
[1]
FAST
[0]
CP
HIZ
DSM
ON
MIX
EN
MODE MODE LOLV
[1]
[0]
[1]
LOLV
[0]
0x04
CALTM CALTM CALTM CALTM
[3]
[2]
[1]
[0]
MS1551-E-00
INT
[10]
D8
Freq1
Function
INT
[11]
D9
13
MOD
[2]
2013/8
[AK1572]
Notes for writing into registers
1) The setting of <Address 0x02> and <Address 0x03> is reflected to each circuit when writing
to <Address 0x01>.
2) <Address 0x04> behavior is reflected by itself.
When AK1572 powers on, the initial registers value is not defined. It is required to write the data
in all addresses in order to commit it.
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[AK1572]
< Address0x01:Freq1 >
D [16:15]
VCO[1:0] : Select VCO
In accordance with the used frequency, select the VCO.
VCO[1:0]
VCO oscillating range
Dec
Frequency
0
2.1GHz~3.0GHz
1
3.0GHz~3.4GHz
2
3.4GHz~.4GHZ
3
prohibited
D [14:13]
DIV[1:0] : LoDivider
In accordance with the used frequency, select the division number.
DIV[1:0]
LoDivider
Dec
Divide Number
0
No divide
1
2 divide
2
4 divide
3
8 divide
D [11:0]
INT[11:0] : NDivider
N divider divided number.
The allowed range is 35 to 4091.
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[AK1572]
< Address0x02:Freq2 >
D [18: 16]
CP1[2:0] ： Set the charge pump current for normal status
D [14:12]
CP2[2:0] ： Set the charge pump current for fast lock
CP1 is the charge pump current setting of the normal mode.
CP2 is the charge pump current setting of the fast lock mode
Charge pump current is determined by the following formula.
Charge pump current [A] = Icp_min [A] × (CP1 or CP2 setting value+1)
Icp_min [A] = 8.1 / R [ohm]
R: the resistance value which is connected to [CPBIAS] pin
Charge pump current (typ) unit : μA
CP1[2:0]
R
CP2[2:0]
33kΩ
27kΩ
22kΩ
0
245
300
368
1
491
600
736
2
736
900
1105
3
982
1200
1473
4
1227
1500
1841
5
1473
1800
2209
6
1718
2100
2577
7
1964
2400
2945
D [11:0]
FRAC[11:0]：Fractional Numerator determination
Set the Numerator of Fractional divider.
The allowed range is from 0 to (MOD[11:0] -1).
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[AK1572]
< Address0x03:Freq3 >
D[19：12]
R [7:0]: 8bit Reference Counter
Maximum PFD frequency is 40MHz
R[13:0]
Divide Ratio
0
Prohibited
1
1
2
2
3
3
4
4
•
•
•
•
•
•
253
253
254
254
255
255
D [11:0]
MOD[11:0]：Fractional Denominator determination
Set the denominator of Fractional divider.
The allowed range is from 2 to 4095.
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[AK1572]
< Address0x04: function >
D[19：16]
CALTM [3:0]: Set the calibration precision of VCO
The register {CALTM [3:0]} determines the calibration precision and time for VCO. When
{CALTM [3:0]} is larger, the calibration precision increases, but the required time becomes
long as trade-off. The value calculated by the following formula is recommended to get
enough calibration precision. However, {CALTM [3:0]} should be set between from 1 to 11.
0 and over 11 is prohibited.
{CALTM[3:0]}≧ log2(FPFD/20000)
FPFD : PFD frequency
The calibration time can be estimated as following calculation;
Calibration time = 1 /FPFD × {(6 + 2^{CALTM[3:0]})×8 + 3}
D [14]
LDCNTSEL: Lock Detect Precision
Set the counter value for digital lock detect.
LDCNTSEL
0
1
Function
15 times Count
unlocked to locked
3 times Count
locked to unlocked
31 times Count
unlocked to locked
7 times Count
locked to unlocked
D [13]
LD: Lock detect function
Set the lock detect function.
0: Digital lock detect
1: Analog lock detect
D [12]
MTLD: Local signal mute
0: Don’t mute local signal in unlock state.
1: Mute local signal in unlock state.
※Please use {MTLD} =0 at the time of {LD}=1.
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[AK1572]
D [11]
FASTEN : Fast Lock mode setting
Enable / disable fast lock mode.
0: Disable fast lock mode
1: Enable fast lock mode
Please refer to "14. Fast lock mode" for details.
D[10:7]
FAST [3:0] : Fast lock timer setting
Set the count number of fast lock timer.
Count Number = 511 + FAST[3:0] × 512
TIMER[3:0]
Count Number
0
511
1
1023
2
1535
3
2047
4
2559
5
3071
6
3583
7
4095
8
4607
9
5119
10
5631
11
6143
12
6655
13
7167
14
7679
15
8191
D [6]
CPHIZ: Charge Pump TRI-STATE
Set the charge pump output in Tri-State.
0: Normal
1: Tri-State
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[AK1572]
D [5]
DSMON: ΔΣ-modulator activation
In Integer-N setting、set the ΔΣ-modulator to active.
0: ΔΣ-modulator inactive
1: ΔΣ-modulator active
D [4]
MIXEN: Mixer Enable
0: Stand-by
1: Enable
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D [3:2]
MODE [1:0]: Local operation mode
Set the operation of Synthesizer, VCO and LOP/LON pins.
MODE[1:0]
0
1
Local Operating MODE
Internal Synthesizer and VCO are active.
Internal Synthesizer and VCO are active and the local signal
outputs from LOP/LON pins.
2
The mode operating external VCO with internal synthesizer.
3
The mode using an external local signal.
D [1:0]
LOLV [1:0]: Local output power
At the state of {MODE [1:0]} =1, set the power of the local signal output from LOP/LON
pins.
MS1551-E-00
LOLV[1:0]
LOP, LON output power [dBm]
0
-6
1
0
2
3
3
6
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12. Lock Detect
Lock detect output can be selected by {LD} in D [13] of <Address0x04>. When {LD} is set to “1”,
the [LD] pin outputs a phase comparison result which is from phase detector directly. (This is called
“analog lock detect”.) When {LD} is set to “0”, the output is the lock detect signal according to the
on-chip logic. (This is called “digital lock detect”.)
The digital lock detect can be done as following:
The [LD] pin is in unlocked state (which outputs “L”) when a frequency setup is made.
In the digital lock detect, the [LD] pin outputs “H” (which means the locked state) when a phase error
smaller than a cycle of [REFIN] clock (T) is detected for N times consecutively. When a phase error
larger than T is detected for N times consecutively while the [LD] pin outputs “H”, then the [LD] pin
outputs “L” (which means the unlocked state). The counter value N can be set by {LDCNTSEL} in D
[14] of <Address0x04>. The N is different between “unlocked to locked” and “locked to unlocked”.
{LDCNTSEL}
unlocked to locked
locked to unlocked
0
N=15
N=3
1
N=31
N=7
The lock detect signal is shown below
Reference clock
Phase Comparison signal
T/2
Divided VCO signal
Phase detector output signal
This is ignored because it
cannot be sampled.
Valid
ignore
LD output
ignore
d
Valid
ignore
The [LD] pin outputs HIGH when a
phase error which is smaller than T/2
is detected for N times consecutively.
Case of “R = 1”
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Reference clock
Phase Comparison signal
T
Divided signal of RF signal
PFD output signal
This is ignored because it
cannot be sampled.
Valid
This is ignored
because it cannot
be sampled.
Valid
ignore
The [LD] pin outputs will be HIGH
when a phase error which is smaller
than T is detected for N times
consecutively.
LD output
Case of “R > 1”
Fig6. .Digital Lock Detect Operations
Unlock⇒Lock
Unlock(LD=LOW)
Flag=0
No
Phase Error < T
Yes
Flag=Flag+1
No
Flag>N
Yes
Lock(LD=HIGH)
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Lock⇒unlock
Lock(LD=HIGH)
Flag=0
No
Phase Error > T
Yes
Flag=Flag+1
No
Flag>N
Yes
Unlock(LD=LOW)
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13. Frequency Setup
The following formula is used to calculate the frequency setting for the AK1572.
Frequency setting ＝Ref Frequency × (INT+FRAC/MOD)
Ref Frequency
：PFD fequency
INT
：Integer divide Number (Refer to <Address 0x01>：INT[11:0])
FRAC
：Numenator setting number (Refer to <Address 0x02>：FRAC[11:0])
MOD
：Denominator setting number (Refer to <Address 0x03>：MOD[11:0])
Set in the range of 35 to 4091 for INT[11:0].
Set in the range of 0 to (MOD-1) for FRAC[11:0]
Set in the range of 2 to 4095 for MOD[11:0]
○ Example
To complete Ref Frequency=19.2MHz, Frequency setting=2460.1MHz, set as follows
INT
=
128
FRAC
=
25
MOD
=
192
Frequency setting = 19.2MHz × (128 + (25 / 192)) = 2460.1MHz
By writing <Address 0x01, 0x02, 0x03>, frequency is set. When <Address 0x01> is written, the
setting of <Address 0x03> and <Addresses 0x02> is reflected in the internal circuit. At the time of the
writing of <Address 0x01>, it is necessary for a synthesizer block to be powered on. The writing of
<Address 0x01> as a trigger, frequency setting and VCO calibration are carried out, and fast lock
counter starts operation. To set frequency definitely, <Address 0x01> should be written in the state
that {MODE [1:0]} in <Address 0x04> is 0 or 1 or 2 and [PDN] pin is “H”.
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14. Fast Lock mode
The fast lock mode becomes effective when set {FASTEN} of <Address 0x04> to”1”.
○Fast Lock Mode
When writing in <Address0x01> with {FASTEN}=1, Fast Lock Up mode starts after calibration. The
Fast Lock Up mode is valid only during the time period set by the timer according to the counter
value in {FAST [3:0]} in <Address0x04>, and the charge pump current is set to the value specified by
{CP2}. When the specified time period elapses, the Fast Lock Up mode operation is switched to the
normal operation, and the charge pump current returns to {CP1} setting
Fast Lock Up time
specified by the timer
Operation mode
Charge pump current
Normal
Calibration
Fast Lock Up
Normal
CP1
Hi-Z
CP2
CP1
Frequency setting （Write in <Address0x01>）
Fig.7. Fast Lock up Mode Timing Chart
○Timer period
{FAST [3:0]} in <Address0x04> is used to set the time period for this mode. The following formula
is used to calculate the time period
Counter Value =511＋FAST[3:0] × 512
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15. VCO
Calibration
AK1572 has three VCO core in uses several overlapping bands to allow low Phase Noise, low VCO
sensitivity (KVCO) and wide frequency range. The selection which VCO should be used can be done
by the register {VCO[1:0]} in <Address 0x01>. Moreover, the correct band is chosen automatically at
frequency setting, which is called calibration.
The calibration starts when <Address0x01> are written in the condition that {MODE[1]} in <Address
0x04>=”0” and [PDN] pin=“H”. During the calibration, VTUNE of VCO is disconnected from the
output of the loop filter and connected to an internal reference voltage. The charge pump output is
disabled.
The internal bias must be stable so that the calibration is done correctly. Therefore, it is necessary to
wait 500sec at least until <Address0x01> writing after [PDN] rises up.
The register {CALTM [3:0]} determines the calibration time. When {CALTM [3:0]} is larger, the
calibration precision increases, but the required time becomes long as a trade-off. The value
calculated by the following formula is recommended to get enough calibration precision. However,
{CALTM [3:0]} should be set at from 1 to 11. 0 and over 11 is prohibited.
{CALTM[3:0]} ≥ log2(FPFD / 20000)
FPFD : PFD frequency
The calibration time can be estimated as following calculation;
Calibration time = 1 /FPFD × {(6 + 2^ {CALTM [3:0]}) ×8 + 3}
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16. Power up Sequence
min. 500usec
min. 10msec
1)
2)
3)
4)
PDN Pin
VDD1, VDD2, VDD3
VREF1(LDO)
Register writing
Prohibit
PLL/Synth
Power Down
Mixer
Power Down
Active
Unstable
VCO calibration
Fast Lock
Lock
Active
1) Set [PDN] pin to “L” and turn on power supplies (VDD1/VDD2/VDD3)
2) The stabilization time for [VREF1] (LDO) is 10msec. After LDO is stabilized, write the data to
the registers of <Address 0x01, 0x02, 0x03, 0x04>
3) Set [PDN] pin to “H”. In this state, the internal circuits are in an operating state, but PLL/Synth
is unstable yet.
4) The stabilization time of internal BIAS circuits is 500usec. After BIAS circuit is stabilized,
write the data to <Address 0x01>. VCO calibration starts and PLL status will be locked. Refer
to 14.Fast Lock Mode and 15.VCO contents regarding fast Lock mode and VCO calibration.
Note1) The initial register values are not defined. Therefore, it is required to write the data in all
addresses of the register.
Note2) The stabilization time for LDO is required more than 10ms.
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17. Typical Evaluation Board Schematic
1.Evaluation Board schematic and the list of external parts
Fig.9. Typical Evaluation Board Schematic
Ref.
Value
Ref.
Value
Ref.
Value
Ref.
Value
Ref.
Value
C1
100pF
C10
2.7nF
C19
10nF
C28
Loop Filter
L2
Matching
C2
220nF
C11
100pF
C20
100pF
C29
Loop Filter
L3
Matching
C3
10nF
C12
Matching
C21
100pF
C30
Loop Filter
L4
Matching
C4
100pF
C13
Matching
C22
10nF
C31
100pF
L5
Matching
C5
Matching
C14
Matching
C23
100pF
C32
10nF
R1
33k
C6
Matching
C15
Matching
C24
10nF
C33
10nF
R2
27k
C7
10nF
C16
Matching
C25
470nF
C34
100pF
R3
Loop Filter
C8
100pF
C17
Matching
C26
100pF
C35
100pF
R4
Loop Filter
C9
10nF
C18
Matching
C27
10nF
L1
Matching
Note1)
Exposed Pad at the center of the backside is should be connected to ground.
Note2)
[TEST1] and [TEST2] pins should be connected to ground.
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2. External circuit to input the external Local signal to [LOP] and [LON] pins.
Fig 7 Circuit for local input
Ref
Value
C36
100pF
C37
100nF
3. External circuit to output the internal local signal from [LOP] and [LON] pins
Fig 8
Circuit for local output
Example of the external components for this mode
Ref
MS1551-E-00
Value
C38
100pF
C39
100pF
L7
180nH
L8
180nH
R5
50Ω
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18.
Pin
No.
11
12
13
14
Name
I/O
PDN
LE
CLK
DATA
DI
DI
DI
DI
R0()
(typ.)
300
300
300
300
30
31
TEST1
TEST2
DI
DI
300
300
Interface Circuit
Cur(A)
Function
Digital input pin
R0
Digital input pin Pull-Down
R0
100kΩ(typ.)
15
LD
DO
21
32
VCNT
REFIN
I
I
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Digital Output pin
100
300
Analog input pin
R0
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Pin
No.
1
4
Name
I/O
VREF1
MIXBIAS
AO
AO
R0()
(typ.)
300
300
22
VREF2
AI
300
25
CPBIAS
AI
300
23
CP
O
Analog output pin
9
10
MIXOUTN
MIXOUTP
O
O
RF open collector output pin
17
18
LOP
LON
IO
IO
RF open collector input/output pin
5
6
MIXINN
MIXINP
IO
IO
RF input pin
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Cur(A)
Function
Analog input/output pin
R0
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19. Outer Dimensions
QFN32-5X5-0.50
0.85 0.05
B
25
32
24
1
0.10
C0.35
0.10
3.10 0.10
5.00
3.10
0.05 MAX
A
5.00
16
9
0.10 M C A B
0.10
0.05
(0.20)
0.25
0.08 C
C
0.50 Ref
Note) The exposed pad at the center of the backside should be connected to ground.
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0.40 0.10
8
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[AK1572]
20. Marking
(a) Style
:
QFN
(b) Number of pins
:
32
(c) 1 pin marking:
:
○
(d) Product number
:
1572
(e) Date code
:
YWWL (4 digits)
Y: Lower 1 digit of calendar year (Year 2013 → 3, 2014 → 4 ...)
WW: Week
L: Lot identification, given to each product lot which is made in a week
LOT ID is given in alphabetical order (A, B, C…).
1572
YWWL
(d)
(e)
○(c)
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IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this
document without notice. When you consider any use or application of AKM product stipulated in this document
(“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the
Products.
1. All information included in this document are provided only to illustrate the operation and application examples of AKM
Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the
information contained in this document nor grants any license to any intellectual property rights or any other rights of
AKM or any third party with respect to the information in this document. You are fully responsible for use of such
information contained in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR
ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN
YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily high levels
of quality and/or reliability and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious
property damage or serious public impact, including but not limited to, equipment used in nuclear facilities, equipment
used in the aerospace industry, medical equipment, equipment used for automobiles, trains, ships and other
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Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for complying with
safety standards and for providing adequate designs and safeguards for your hardware, software and systems which
minimize risk and avoid situations in which a malfunction or failure of the Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in this
document for any military purposes, including without limitation, for the design, development, use, stockpiling or
manufacturing of nuclear, chemical, or biological weapons or missile technology products (mass destruction weapons).
When exporting the Products or related technology or any information contained in this document, you should comply
with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any products or systems
whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS compatibility of the
Product. Please use the Product in compliance with all applicable laws and regulations that regulate the inclusion or
use of controlled substances, including without limitation, the EU RoHS Directive. AKM assumes no liability for
damages or losses occurring as a result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in this document
shall immediately void any warranty granted by AKM for the Product and shall not create or extend in any manner
whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of
AKM.
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