Dallas DS21FT40 Four x three 12 channel e1 framer Datasheet

DS21FT40
Four x Three 12 Channel E1 Framer
www.dalsemi.com
MULTI-CHIP MODULE FEATURES
•
•
•
•
•
FUNCTIONAL DIAGRAM
Twelve (12) completely independent
E1 Framers in one small 27 mm x 27 mm
Package
Each Multi-Chip Module (MCM) Contains
Three DS21Q44 Quad E1 Framer Die
Each Quad Framer can be concatenated into
a Single 8.192 MHz Backplane Data Stream
300–pin MCM 1.27 mm pitch BGA package
(27 mm X 27 mm)
Low Power 3.3V CMOS with 5V Tolerant
Input & Outputs
•
•
•
•
•
Transmit
Formatter
Elastic
Store
ρρρ
FRAMER #12
Control Port
•
All framers are fully independent; transmit
and receive sections of each framer are fully
independent
Frames to FAS, CAS, CCS, and CRC4
formats
Each framer contains dual two–frame elastic
store slip buffers that can connect to
asynchronous backplanes up to 8.192 MHz
8–bit parallel control port that can be used
directly on either multiplexed or non–
multiplexed buses (Intel or Motorola)
Easy access to Si and Sa bits
Extracts and inserts CAS signaling
Elastic
Store
FRAMER #1
FRAMER #2
FRAMER #3
FRAMER FEATURES
•
Receive
Framer
•
•
•
•
Large counters for bipolar and code
violations, CRC4 code word errors, FAS
word errors, and E-bits
Programmable output clocks for Fractional
E1, per channel loopback, H0 and H12
applications
Integral HDLC controller with 64-byte
buffers. Configurable for Sa bits or DS0
operation
Detects and generates AIS, remote alarm,
and remote multiframe alarms
IEEE 1149.1 support
DESCRIPTION
The DS21FT40 MCM offers a high density packaging arrangement for the DS21Q44 E1 Enhanced Quad
Framer. Three DS21Q44 silicon die are packaged in a Multi-Chip Module (MCM) with the electrical
connections as shown in Figure 1-1. The DS21FT40 is closely related to the DS21FT44. Most of the
functions of the DS21FT44 are available on the DS21FT40. The differences are listed in Table 1-1.
Table 2-1 lists all of the signals on the MCM.
The DS21Q44 E1 Framer is an enhanced version of the DS21Q43 Quad E1 Framer. Each DS21Q44 die
contains four framers that are configured and read through a common microprocessor-compatible parallel
port. Each framer consists of a receive framer, receive elastic store, transmit formatter and transmit
elastic store. All four framers in the DS21Q44 are totally independent, they do not share a common
framing synchronizer. Also, the transmit and receive sides of each framer are totally independent. The
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041400
DS21FT40
dual two-frame elastic stores contained in each of the four framers can be independently enabled and
disabled as required. The device fully meets all of the latest E1 specifications including CCITT/ITU
G.704, G.706, G.962, and I.431 as well as ETS 300 011 and ETS 300 233.
Functional Description
The receive side in each framer locates FAS frame and CRC and CAS multiframe boundaries as well as
detects incoming alarms including, carrier loss, loss of synchronization, AIS and Remote Alarm. If
needed, the receive side elastic store can be enabled in order to absorb the phase and frequency
differences between the recovered E1 data stream and an asynchronous backplane clock which is
provided at the RSYSCLK input. The clock applied at the RSYSCLK input can be either a 2.048 MHz
clock or a 1.544 MHz clock. The RSYSCLK can be a burst clock with speeds up to 8.192 MHz.
The transmit side in each framer is totally independent from the receive side in both the clock
requirements and characteristics. Data off of a backplane can be passed through a transmit side elastic
store if necessary. The transmit formatter will provide the necessary frame/multiframe data overhead for
E1 transmission.
Reader’s Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In
each 125 us frame, there are 32 8–bit timeslots numbered 0 to 31. Timeslot 0 is transmitted first and
received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32.
Timeslot 0 is identical to channel 1, timeslot 1 is identical to Channel 2, and so on. Each timeslot (or
channel) is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted
first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following
abbreviations will be used:
FAS
CAS
MF
Si
CRC4
CCS
Sa
E-bit
Frame Alignment Signal
Channel Associated Signaling
Multiframe
International bits
Cyclical Redundancy Check
Common Channel Signaling
Additional bits
CRC4 Error Bits
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DS21FT40
DS21FT40 Schematic Figure 1-1
DVSS
DVSS
TLINK0/1/2/3
TEST
MUX
BTS
FS0/FS1
2
WR*
RD*
8
A0 to A7
D0 to D7
8
CS*
INT*
DS21Q44 # 1
DVDD
FMS
Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RCLK1/2/3/4
RLCLK
RPOS1/2/3/4
RCHBLK
RNEG1/2/3/4
RCHCLK
RFSYNC
RSER1/2/3/4
TLCLK
RMSYNC1/2/3/4
TCHCLK
RSYNC1/2/3/4
TCHBLK
RSIG
TSIG
RSYSCLK1/2/3/4
8MCLK
TSYSCLK1/2/3/4
CLKSI
JTRST*
TCLK1/2/3/4
JTMS
TPOS1/2/3/4
JTCLK
TNEG1/2/3/4
JTDI
TSER1/2/3/4
JTDO
TSSYNC1/2/3/4
TSYNC1/2/3/4
DVSS
DVSS
TLINK0/1/2/3
TEST
MUX
BTS
FS0/FS1
WR*
RD*
A0 to A7
D0 to D7
CS*
INT*
DS21Q44 # 2
DVDD
FMS
Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RCLK5/6/7/8
RLCLK
RPOS5/6/7/8
RCHBLK
RNEG5/6/7/8
RCHCLK
RFSYNC
RSER5/6/7/8
TLCLK
RMSYNC5/6/7/8
TCHCLK
RSYNC5/6/7/8
TCHBLK
RSIG
TSIG
RSYSCLK5/6/7/8
8MCLK
TSYSCLK5/6/7/8
CLKSI
JTRST*
TCLK5/6/7/8
JTMS
TPOS5/6/7/8
JTCLK
TNEG5/6/7/8
JTDI
TSER5/6/7/8
JTDO
TSSYNC5/6/7/8
TSYNC5/6/7/8
See Connecting Page
3 of 87
DS21FT40
DS21FT40 Schematic Figure 1-1 (continued)
See Connecting Page
DVSS
DVSS
TLINK0/1/2/3
TEST
MUX
BTS
FS0/FS1
WR*
RD*
A0 to A7
D0 to D7
CS*
INT*
DVDD
FMS
DS21Q44 # 3
Signals Not Connected &
Left Open Circuited Include:
RLOS/LOTC
RLINK
RCLK9/10/11/12
RLCLK
RPOS9/10/11/12
RCHBLK
RNEG9/10/11/12
RCHCLK
RFSYNC
RSER9/10/11/12
TLCLK
RMSYNC9/10/11/12
TCHCLK
RSYNC9/10/11/12
TCHBLK
RSIG
TSIG
RSYSCLK9/10/11/12
8MCLK
TSYSCLK9/10/11/12
CLKSI
JTRST*
TCLK9/10/11/12
JTMS
TPOS9/10/11/12
JTCLK
TNEG9/10/11/12
JTDI
TSER9/10/11/12
JTDO
TSSYNC9/10/11/12
TSYNC9/10/11/12
Changes in DS21FT40 compared to DS21FT44 Table 1-1
1.
2.
3.
4.
The SYSCLK pins have been separated into TSYSCLK and RSYSCLK pins.
RMSYNC pins have been added.
FMS tied to Vdd.
The following signals are not available:
RSIG / TSIG / 8MCLK / CLKSI / JTRST* / JTMS / JTCLK / JTDI / JTDO
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DS21FT40
DS21FT40 ENHANCED 12-Channel E1 FRAMER Figure 1-2
64-Byte Buffer
HDLC Engine
DS0 Insertion
Sa Extraction
Timing Control
Signaling
Buffer
Signaling Extraction
SA and SI Extraction
FAS Error Counter
E-BIT Counter
CRC Error Counter
Per-Channel Code Insert
Remote Loopback
Framer Loopback
RNEG
Synchronizer
RCLK
Alarm Detection
RPOS
BPV Counter
HDB3 Decoder
Receive Side Framer
data
RSER
clock
Elastic
Store
sync
RSYSCLK
RSYNC
RMSYNC
TSYNC
Sync Control
Timing Control
Per-Channel Loopback
Per-Channel Code Insert
SI Bit Insertion
FAS Word Insertion
E-Bit Insertion
CRC4 Generation
TNEG
Signaling Insertion
SA Insertion
TPOS
HDB3 Encode
AIS Generation
Transmit Side Formatter
sync
TSSYNC
Elastic
Store
clock
TSYSCLK
data
Hardware
Signaling
Insertion
TSER
LOTC DET
&
MUX
TCLK
64-Byte Buffer
HDLC Engine
DS0 Insertion
Sa Insertion
FR A ME R # 1
F R A ME R # 2
F R A ME R # 3
FRAMER #12
VDD
Power
VSS
Parallel & Test Control Port
(routed to all blocks)
7
TEST
C S*
FS0
FS1
B TS
W R*
(R/W*)
RD*
(DS*)
5 of 87
ALE
(AS)/
A6
8
A0 to A5, M U X D 0 t o D 7 /
A7
AD0 to AD7
INT*
DS21FT40
TABLE OF CONTENTS
DESCRIPTION.......................................................................................................................................................................... 1
1.
DS21FT40 PIN DESCRIPTION....................................................................................................................................... 8
2.
DS21FT44 PIN FUNCTION DESCRIPTION............................................................................................................... 16
3.
DS21FT40 REGISTER MAP.......................................................................................................................................... 19
4.
PARALLEL PORT.......................................................................................................................................................... 24
5.
CONTROL, ID AND TEST REGISTERS..................................................................................................................... 24
6.
STATUS AND INFORMATION REGISTERS ............................................................................................................ 33
7.
ERROR COUNT REGISTERS ...................................................................................................................................... 39
8.
DS0 MONITORING FUNCTION.................................................................................................................................. 41
9.
SIGNALING OPERATION............................................................................................................................................ 44
9.1
9.2
10.
PROCESSOR BASED SIGNALING ........................................................................................................................ 44
HARDWARE BASED SIGNALING ........................................................................................................................ 47
PER–CHANNEL CODE GENERATION AND LOOPBACK................................................................................ 47
10.1 TRANSMIT SIDE CODE GENERATION............................................................................................................... 47
10.1.1 Simple Idle Code Insertion and Per–Channel Loopback................................................................................... 47
10.1.2 Per–Channel Code Insertion ............................................................................................................................. 48
10.2 RECEIVE SIDE CODE GENERATION .................................................................................................................. 49
11.
CLOCK BLOCKING REGISTERS .......................................................................................................................... 50
12.
ELASTIC STORES OPERATION ............................................................................................................................ 50
12.1
12.2
13.
13.1
13.2
14.
14.1
14.2
14.3
14.4
RECEIVE SIDE......................................................................................................................................................... 51
TRANSMIT SIDE ..................................................................................................................................................... 51
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION ................................................................ 51
INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME ..................................................................... 51
INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME................................................................ 53
HDLC CONTROLLER FOR THE SA BITS OR DS0............................................................................................. 55
GENERAL OVERVIEW .................................................................................................................................................. 55
HDLC STATUS REGISTERS ......................................................................................................................................... 56
BASIC OPERATION DETAILS ........................................................................................................................................ 57
HDLC REGISTER DESCRIPTION .................................................................................................................................. 58
15.
INTERLEAVED PCM BUS OPERATION .............................................................................................................. 64
16.
TIMING DIAGRAMS................................................................................................................................................. 67
17.
OPERATING PARAMETERS................................................................................................................................... 75
18.
DS21FT40 MECHANICAL DIMENSIONS.............................................................................................................. 86
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DS21FT40
DOCUMENT REVISION HISTORY
Revision
5-18-99
8-19-99
8-26-99
2-17-00
Notes
Initial Release
Concatenated DS21FT40 and DS21Q44 data sheets
Remove RCHBLK pins.
Corrected error in Figure 1-1 (removed RCHBLK pins).
7 of 87
DS21FT40
1. DS21FT40 PIN DESCRIPTION
Pin Description Sorted by Pin Number Table 2-1
Lead
G20
H20
G19
H19
G18
H18
G17
H17
W15
T8
Y4
Y15
L20
M20
L19
M19
L18
M18
L17
M17
C7
E4
D2
K3
U7
P2
V19
T12
L16
E9
A6
D5
U3
K4
U8
U4
R16
Y20
Y14
W14
G16
P17
Symbols
A0
A1
A2
A3
A4
A5
A6
A7
BTS
CS1*
CS2*
CS3*
D0
D1
D2
D3
D4
D5
D6
D7
DVDD1
DVDD1
DVDD1
DVDD2
DVDD2
DVDD2
DVDD3
DVDD3
DVDD3
DVSS1
DVSS1
DVSS1
DVSS2
DVSS2
DVSS2
DVSS3
DVSS3
DVSS3
FS0
FS1
INT*
MUX
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
I
I
O
I
Description
Address Bus Bit 0 (lsb).
Address Bus Bit 1.
Address Bus Bit 2.
Address Bus Bit 3.
Address Bus Bit 4.
Address Bus Bit 5.
Address Bus Bit 6.
Address Bus Bit 7 (msb).
Bus Timing Select. 0 = Intel / 1 = Motorola.
Chip Select for Quad Framer 1.
Chip Select for Quad Framer 2.
Chip Select for Quad Framer 3.
Data Bus Bit 0 (lsb).
Data Bus Bit 1.
Data Bus Bit 2.
Data Bus Bit 3.
Data Bus Bit 4.
Data Bus Bit 5.
Data Bus Bit 6.
Data Bus Bit 7 (msb).
Digital Positive Supply for Framer 1.
Digital Positive Supply for Framer 1.
Digital Positive Supply for Framer 1.
Digital Positive Supply for Framer 2.
Digital Positive Supply for Framer 2.
Digital Positive Supply for Framer 2.
Digital Positive Supply for Framer 3.
Digital Positive Supply for Framer 3.
Digital Positive Supply for Framer 3.
Digital Signal Ground for Framer 1.
Digital Signal Ground for Framer 1.
Digital Signal Ground for Framer 1.
Digital Signal Ground for Framer 2.
Digital Signal Ground for Framer 2.
Digital Signal Ground for Framer 2.
Digital Signal Ground for Framer 3.
Digital Signal Ground for Framer 3.
Digital Signal Ground for Framer 3.
Framer Select 0 for the Parallel Control Port.
Framer Select 1 for the Parallel Control Port.
Interrupt for all four Quad Framers.
Bus Operation Select. 0 = non-multiplexed bus / 1 =
8 of 87
DS21FT40
Lead
Symbols
I/O
A2
K1
D10
B9
M3
V1
W6
J3
T9
W10
Y18
N17
E18
D3
G2
D4
D8
N2
V4
V6
K5
U10
Y11
W19
U20
B2
H2
D9
A9
M2
V3
V7
P3
U9
W11
W17
T20
A1
H1
H4
C9
M1
W2
V5
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RD*
RMSYNC1
RMSYNC2
RMSYNC3
RMSYNC4
RMSYNC5
RMSYNC6
RMSYNC7
RMSYNC8
RMSYNC9
RMSYNC10
RMSYNC11
RMSYNC12
RNEG1
RNEG2
RNEG3
RNEG4
RNEG5
RNEG6
RNEG7
RNEG8
RNEG9
RNEG10
RNEG11
RNEG12
RPOS1
RPOS2
RPOS3
RPOS4
RPOS5
RPOS6
RPOS7
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
multiplexed bus
Receive Clock for Framer 1
Receive Clock for Framer 2.
Receive Clock for Framer 3.
Receive Clock for Framer 4.
Receive Clock for Framer 5.
Receive Clock for Framer 6.
Receive Clock for Framer 7.
Receive Clock for Framer 8.
Receive Clock for Framer 9.
Receive Clock for Framer 10.
Receive Clock for Framer 11.
Receive Clock for Framer 12.
Read Input.
Receive Multiframe Sync from Framer 1
Receive Multiframe Sync from Framer 2
Receive Multiframe Sync from Framer 3
Receive Multiframe Sync from Framer 4
Receive Multiframe Sync from Framer 5
Receive Multiframe Sync from Framer 6
Receive Multiframe Sync from Framer 7
Receive Multiframe Sync from Framer 8
Receive Multiframe Sync from Framer 9
Receive Multiframe Sync from Framer 10
Receive Multiframe Sync from Framer 11
Receive Multiframe Sync from Framer 12
Receive Negative Data for Framer 1.
Receive Negative Data for Framer 2.
Receive Negative Data for Framer 3.
Receive Negative Data for Framer 4.
Receive Negative Data for Framer 5.
Receive Negative Data for Framer 6.
Receive Negative Data for Framer 7.
Receive Negative Data for Framer 8.
Receive Negative Data for Framer 9.
Receive Negative Data for Framer 10.
Receive Negative Data for Framer 11.
Receive Negative Data for Framer 12.
Receive Positive Data for Framer 1.
Receive Positive Data for Framer 2.
Receive Positive Data for Framer 3.
Receive Positive Data for Framer 4.
Receive Positive Data for Framer 5.
Receive Positive Data for Framer 6.
Receive Positive Data for Framer 7.
9 of 87
DS21FT40
Lead
P4
T10
V11
Y19
R19
C1
H3
C6
C8
P1
W4
T7
N4
U11
Y12
V16
T16
B1
G1
D6
A7
N3
Y2
U5
J4
T11
V13
V15
P18
B5
E2
E5
B8
M4
T2
Y5
W3
T4
Y9
U12
R17
D1
H5
C5
A5
Symbols
RPOS8
RPOS9
RPOS10
RPOS11
RPOS12
RSER1
RSER2
RSER3
RSER4
RSER5
RSER6
RSER7
RSER8
RSER9
RSER10
RSER11
RSER12
RSYNC1
RSYNC2
RSYNC3
RSYNC4
RSYNC5
RSYNC6
RSYNC7
RSYNC8
RSYNC9
RSYNC10
RSYNC11
RSYNC12
RSYSCLK1
RSYSCLK2
RSYSCLK3
RSYSCLK4
RSYSCLK5
RSYSCLK6
RSYSCLK7
RSYSCLK8
RSYSCLK9
RSYSCLK10
RSYSCLK11
RSYSCLK12
TCLK1
TCLK2
TCLK3
TCLK4
I/O
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Description
Receive Positive Data for Framer 8.
Receive Positive Data for Framer 9.
Receive Positive Data for Framer 10.
Receive Positive Data for Framer 11.
Receive Positive Data for Framer 12.
Receive Serial Data from Framer 1.
Receive Serial Data from Framer 2.
Receive Serial Data from Framer 3.
Receive Serial Data from Framer 4.
Receive Serial Data from Framer 5.
Receive Serial Data from Framer 6.
Receive Serial Data from Framer 7.
Receive Serial Data from Framer 8.
Receive Serial Data from Framer 9.
Receive Serial Data from Framer 10.
Receive Serial Data from Framer 11.
Receive Serial Data from Framer 12.
Receive Frame/Multiframe Sync for Framer 1.
Receive Frame/Multiframe Sync for Framer 2.
Receive Frame/Multiframe Sync for Framer 3.
Receive Frame/Multiframe Sync for Framer 4.
Receive Frame/Multiframe Sync for Framer 5.
Receive Frame/Multiframe Sync for Framer 6.
Receive Frame/Multiframe Sync for Framer 7.
Receive Frame/Multiframe Sync for Framer 8.
Receive Frame/Multiframe Sync for Framer 9.
Receive Frame/Multiframe Sync for Framer 10.
Receive Frame/Multiframe Sync for Framer 11.
Receive Frame/Multiframe Sync for Framer 12.
Receive System Clock for Framer 1.
Receive System Clock for Framer 2.
Receive System Clock for Framer 3.
Receive System Clock for Framer 4.
Receive System Clock for Framer 5.
Receive System Clock for Framer 6.
Receive System Clock for Framer 7.
Receive System Clock for Framer 8.
Receive System Clock for Framer 9.
Receive System Clock for Framer 10.
Receive System Clock for Framer 11.
Receive System Clock for Framer 12.
Transmit Clock for Framer 1.
Transmit Clock for Framer 2.
Transmit Clock for Framer 3.
Transmit Clock for Framer 4.
10 of 87
DS21FT40
Lead
R1
Y3
T6
K2
U13
Y13
T18
P16
A13
Symbols
TCLK5
TCLK6
TCLK7
TCLK8
TCLK9
TCLK10
TCLK11
TCLK12
TEST
I/O
I
I
I
I
I
I
I
I
I
C3
J1
F5
A10
L1
V2
V8
P5
U14
V12
W18
T19
B3
J2
J5
B10
L2
W1
W7
R3
T14
Y10
V18
V20
B4
E1
F3
D7
L5
T1
Y6
T3
M16
W9
W16
TNEG1
TNEG2
TNEG3
TNEG4
TNEG5
TNEG6
TNEG7
TNEG8
TNEG9
TNEG10
TNEG11
TNEG12
TPOS1
TPOS2
TPOS3
TPOS4
TPOS5
TPOS6
TPOS7
TPOS8
TPOS9
TPOS10
TPOS11
TPOS12
TSER1
TSER2
TSER3
TSER4
TSER5
TSER6
TSER7
TSER8
TSER9
TSER10
TSER11
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Description
Transmit Clock for Framer 5.
Transmit Clock for Framer 6.
Transmit Clock for Framer 7.
Transmit Clock for Framer 8.
Transmit Clock for Framer 9.
Transmit Clock for Framer 10.
Transmit Clock for Framer 11.
Transmit Clock for Framer 12.
Tri-State. 0 = do not tri-state / 1 = tri-state all outputs & I/O
signals
Transmit Negative Data from Framer 1.
Transmit Negative Data from Framer 2.
Transmit Negative Data from Framer 3.
Transmit Negative Data from Framer 4.
Transmit Negative Data from Framer 5.
Transmit Negative Data from Framer 6.
Transmit Negative Data from Framer 7.
Transmit Negative Data from Framer 8.
Transmit Negative Data from Framer 9.
Transmit Negative Data from Framer 10.
Transmit Negative Data from Framer 11.
Transmit Negative Data from Framer 12.
Transmit Positive Data from Framer 1.
Transmit Positive Data from Framer 2.
Transmit Positive Data from Framer 3.
Transmit Positive Data from Framer 4.
Transmit Positive Data from Framer 5.
Transmit Positive Data from Framer 6.
Transmit Positive Data from Framer 7.
Transmit Positive Data from Framer 8.
Transmit Positive Data from Framer 9.
Transmit Positive Data from Framer 10.
Transmit Positive Data from Framer 11.
Transmit Positive Data from Framer 12.
Transmit Serial Data for Framer 1.
Transmit Serial Data for Framer 2.
Transmit Serial Data for Framer 3.
Transmit Serial Data for Framer 4.
Transmit Serial Data for Framer 5.
Transmit Serial Data for Framer 6.
Transmit Serial Data for Framer 7.
Transmit Serial Data for Framer 8.
Transmit Serial Data for Framer 9.
Transmit Serial Data for Framer 10.
Transmit Serial Data for Framer 11.
11 of 87
DS21FT40
Lead
W20
A3
F2
G5
E8
L4
U1
Y7
R4
T15
W8
Y17
U19
E3
F4
E7
A4
R2
W5
T5
M5
T13
W13
U16
N16
C4
F1
G4
C10
L3
U2
V9
R5
U15
V10
U18
R18
Y16
A11
A12
A14
A15
A16
A17
A18
Symbols
TSER12
TSSYNC1
TSSYNC2
TSSYNC3
TSSYNC4
TSSYNC5
TSSYNC6
TSSYNC7
TSSYNC8
TSSYNC9
TSSYNC10
TSSYNC11
TSSYNC12
TSYNC1
TSYNC2
TSYNC3
TSYNC4
TSYNC5
TSYNC6
TSYNC7
TSYNC8
TSYNC9
TSYNC10
TSYNC11
TSYNC12
TSYSCLK1
TSYSCLK2
TSYSCLK3
TSYSCLK4
TSYSCLK5
TSYSCLK6
TSYSCLK7
TSYSCLK8
TSYSCLK9
TSYSCLK10
TSYSCLK11
TSYSCLK12
WR*
NC
NC
NC
NC
NC
NC
NC
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
–
–
–
–
–
–
–
Description
Transmit Serial Data for Framer 12.
Transmit System Sync for Framer 1.
Transmit System Sync for Framer 2.
Transmit System Sync for Framer 3.
Transmit System Sync for Framer 4.
Transmit System Sync for Framer 5.
Transmit System Sync for Framer 6.
Transmit System Sync for Framer 7.
Transmit System Sync for Framer 8.
Transmit System Sync for Framer 9.
Transmit System Sync for Framer 10.
Transmit System Sync for Framer 11.
Transmit System Sync for Framer 12.
Transmit Sync for Framer 1.
Transmit Sync for Framer 2.
Transmit Sync for Framer 3.
Transmit Sync for Framer 4.
Transmit Sync for Framer 5.
Transmit Sync for Framer 6.
Transmit Sync for Framer 7.
Transmit Sync for Framer 8.
Transmit Sync for Framer 9.
Transmit Sync for Framer 10.
Transmit Sync for Framer 11.
Transmit Sync for Framer 12.
Transmit System Clock for Framer 1.
Transmit System Clock for Framer 2.
Transmit System Clock for Framer 3.
Transmit System Clock for Framer 4.
Transmit System Clock for Framer 5.
Transmit System Clock for Framer 6.
Transmit System Clock for Framer 7.
Transmit System Clock for Framer 8.
Transmit System Clock for Framer 9.
Transmit System Clock for Framer 10.
Transmit System Clock for Framer 11.
Transmit System Clock for Framer 12.
Write Input.
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
12 of 87
DS21FT40
Lead
A19
A20
A8
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B6
B7
C11
C12
C13
C14
C15
C16
C17
C18
C19
C2
C20
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
E10
E11
E12
E13
E14
E15
E16
E17
E19
Symbols
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
13 of 87
DS21FT40
Lead
E20
E6
F16
F17
F18
F19
F20
G3
H16
J16
J17
J18
J19
J20
K16
K17
K18
K19
K20
N1
N18
N19
N20
N5
P19
P20
R20
T17
U17
U6
V14
V17
W12
Y1
Y8
Symbols
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Description
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
14 of 87
DS21FT40
DS21FT40 PCB Land Pattern Figure 2-1
The diagram shown below is the lead pattern that will be placed on the target PCB. This is the same
pattern that would be seen as viewed through the MCM from the top.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
rpos
1
rclk
1
ts
sync1
tsync
4
tclk
4
dvss
1
rsync
4
nc
rneg
4
tneg
4
nc
nc
test
ns
ns
nc
nc
nc
nc
nc
B
rsync
1
rneg
1
tpos
1
tser
1
nc
nc
tpos
4
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
rser
1
nc
tneg
1
rser
3
dvdd
1
rpos
4
nc
nc
nc
ns
nc
nc
nc
nc
nc
tclk
1
dvdd
1
dvss
1
rsync
3
tser
4
rm
sync4
rneg
3
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
E
tser
2
tsync
3
ts
sync
4
dvss
1
nc
nc
nc
nc
nc
nc
nc
nc
rd*
nc
nc
tser
3
tsync
2
nc
nc
nc
nc
nc
G
tsys
clk
2
rsync
2
rsys
clk
3
tneg
3
nc
F
nc
A4
A2
A0
rser
2
ts
sync
3
tclk
2
A6
rpos
2
tsys
clk
3
rpos
3
int*
H
rsys
clk
2
ts
sync
2
rm
sync
2
rneg
2
rm
sync
1
tsync
1
tsys
clk
4
rclk
3
nc
D
tsys
clk
1
rm
sync
3
dvdd
1
rsys
clk
4
rser4
rclk
4
C
rsys
clk
1
tclk
3
nc
A7
A5
A3
A1
J
tneg
2
tpos
2
rclk
8
rsync
8
tpos
3
nc
nc
nc
nc
nc
K
rclk
2
tclk
8
dvdd
2
dvss
2
rm
sync
8
nc
nc
nc
nc
nc
L
tneg
5
tpos
5
dvdd
3
D6
D4
D2
D0
rpos
5
rneg
5
tsync
8
tser
9
D7
D5
D3
D1
N
nc
rsync
5
nc
tsync
12
rclk
12
nc
nc
nc
P
rser
5
rm
sync
5
dvdd
2
ts
sync
5
rsys
clk
5
rser
8
tser
5
M
tsys
clk
5
rclk
5
rneg
8
rpos
8
tneg
8
tclk
12
mux
rsync
12
nc
nc
R
tclk
5
tsync
5
tpos
8
tser
8
tsys
clk
12
tclk
11
nc
tneg
12
rneg
12
U
tsync
11
nc
V
ts
sync
6
rclk
6
rsys
clk
6
tsys
clk
6
tneg
6
rsys
clk
12
nc
rpos
12
tser
6
tsys
clk
8
tsync
7
dvss
3
T
ts
sync
8
rsys
clk
9
dvss
3
rser
11
nc
tsys
clk
11
tpos
11
ts
sync
12
dvdd
3
rm
sync
12
tpos
12
W
tpos
6
rpos
6
tser
12
Y
nc
rsync
6
rm
sync
11
rpos
11
dvss
2
rneg
6
rsys
clk
8
tclk
6
rm
sync
6
rser
6
cs2*
tclk
7
rser
7
cs1*
rclk
9
rpos
9
rsync
9
dvdd
3
tsync
9
tpos
9
rsync
7
nc
dvdd
2
dvss
2
rneg
9
rser
9
tneg
9
rm
sync
7
rclk
7
rneg
7
tneg
7
rsync
10
nc
tpos
7
tser
7
ts
sync
7
ts
sync
10
nc
tsys
clk
7
tser
10
rsys
clk
11
tneg
10
tclk
9
rpos
7
rm
sync
9
tsys
clk
10
rclk
10
tsync
6
rsys
clk
7
rsys
clk
10
tpos
10
rpos
10
ts
sync
9
tsys
clk
9
rsync
11
rser
12
rneg
10
nc
tsync
10
fs1
bts
tser
11
rneg
11
tneg
11
rm
sync
10
rser
10
tclk
10
fs0
cs3*
wr*
ts
sync
11
rclk
11
15 of 87
dvss
3
DS21FT40
2. DS21FT44 PIN FUNCTION DESCRIPTION
TRANSMIT SIDE PINS
Signal Name:
TCLK
Signal Description:
Transmit Clock
Signal Type:
Input
A 2.048 MHz primary clock. Used to clock data through the transmit side formatter.
Signal Name:
TSER
Signal Description:
Transmit Serial Data
Signal Type:
Input
Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is
disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
Signal Name:
TSYSCLK
Signal Description:
Transmit System Clock
Signal Type:
Input
1.544 MHz or 2.048 MHz clock. Only used when the transmit side elastic store function is enabled.
Should be tied low in applications that do not use the transmit side elastic store. Can be burst at rates up
to 8.192 MHz.
Signal Name:
TSYNC
Signal Description:
Transmit Sync
Signal Type:
Input /Output
A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. This pin can
also be programmed to output either a frame or multiframe pulse. Always synchronous with TCLK.
Signal Name:
TSSYNC
Signal Description:
Transmit System Sync
Signal Type:
Input
Only used when the transmit side elastic store is enabled. A pulse at this pin will establish either frame or
multiframe boundaries for the transmit side. Should be tied low in applications that do not use the
transmit side elastic store. Always synchronous with TSYSCLK.
Signal Name:
TPOS
Signal Description:
Transmit Positive Data Output
Signal Type:
Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter. Can be
programmed to source NRZ data via the Output Data Format (TCR1.7) control bit.
Signal Name:
TNEG
Signal Description:
Transmit Negative Data Output
Signal Type:
Output
Updated on the rising edge of TCLK with the bipolar data out of the transmit side formatter.
16 of 87
DS21FT40
RECEIVE SIDE PINS
Signal Name:
RCLK
Signal Description:
Receive Clock Input
Signal Type:
Input
2.048 MHz clock that is used to clock data through the receive side framer.
Signal Name:
RSER
Signal Description:
Receive Serial Data
Signal Type:
Output
Received NRZ serial data. Updated on rising edges of RCLK when the receive side elastic store is
disabled. Updated on the rising edges of RSYSCLK when the receive side elastic store is enabled.
Signal Name:
RSYNC
Signal Description:
Receive Sync
Signal Type:
Input /Output
An extracted pulse, one RCLK wide, is output at this pin which identifies either frame or CAS/CRC
multiframe boundaries. If the receive side elastic store is enabled, then this pin can be enabled to be an
input at which a frame or multiframe boundary pulse synchronous with RSYSCLK is applied.
Signal Name:
RMSYNC
Signal Description:
Receive Multiframe Sync
Signal Type:
Output
An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries. If
the receive side elastic store is disabled, then this output will output multiframe boundaries associated
with RCLK.
Signal Name:
RSYSCLK
Signal Description:
Receive System Clock
Signal Type:
Input
1.544 MHz or 2.048 MHz clock. Only used when the elastic store function is enabled. Should be tied
low in applications that do not use the elastic store. Can be burst at rates up to 8.192 MHz.
Signal Name:
RPOS
Signal Description:
Receive Positive Data Input
Signal Type:
Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
Signal Name:
RNEG
Signal Description:
Receive Negative Data Input
Signal Type:
Input
Sampled on the falling edge of RCLK for data to be clocked through the receive side framer. RPOS and
RNEG can be tied together for an NRZ interface. Connecting RPOS to RNEG disables the bipolar
violation monitoring circuitry.
17 of 87
DS21FT40
PARALLEL CONTROL PORT PINS
Signal Name:
INT*
Signal Description:
Interrupt
Signal Type:
Output
Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2
and the FDL Status Register. Active low, open drain output.
Signal Name:
MUX
Signal Description:
Bus Operation
Signal Type:
Input
Set low to select non–multiplexed bus operation. Set high to select multiplexed bus operation.
Signal Name:
D0 TO D7 / AD0 TO AD7
Signal Description:
Data Bus or Address/Data Bus
Signal Type:
Input /Output
In non–multiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation
(MUX = 1), serves as a 8–bit multiplexed address / data bus.
Signal Name:
A0 TO A5, A7
Signal Description:
Address Bus
Signal Type:
Input
In non–multiplexed bus operation (MUX = 0), serves as the address bus. In multiplexed bus operation
(MUX = 1), these pins are not used and should be tied low.
Signal Name:
ALE (AS) / A6
Signal Description:
Address Latch Enable (Address Strobe) or A6
Signal Type:
Input
In non–multiplexed bus operation (MUX = 0), serves as address bit 6. In multiplexed bus operation
(MUX = 1), serves to demultiplex the bus on a positive–going edge.
Signal Name:
BTS
Signal Description:
Bus Type Select
Signal Type:
Input
Strap high to select Motorola bus timing; strap low to select Intel bus timing. This pin controls the
function of the RD*(DS*), ALE(AS), and WR*(R/W*) pins. If BTS = 1, then these pins assume the
function listed in parenthesis ().
Signal Name:
RD* (DS)
Signal Description:
Read Input (Data Strobe)
Signal Type:
Input
RD* is an active low signal and DS is an active high signal.
Signal Name:
FS0 AND FS1
Signal Description:
Framer Selects
Signal Type:
Input
Selects which of the four framers is to be accessed for a specific DS21Q44 die.
18 of 87
DS21FT40
Signal Name:
CS1* TO CS3*
Signal Description:
Chip Select
Signal Type:
Input
Must be low to read or write to a specific DS21Q44 die. These are active low signals.
Signal Name:
Signal Description:
Signal Type:
WR* is an active low signal.
WR* (R/W*)
Write Input (Read/Write)
Input
TEST ACCESS PORT PINS
Signal Name:
TEST
Signal Description:
3–State Control
Signal Type:
Input
Set high to 3–state all output and I/O pins (including the parallel control port). Set low for normal
operation. Useful in board level testing.
SUPPLY PINS
Signal Name:
Signal Description:
Signal Type:
2.97 to 3.63 volts.
VDD
Positive Supply
Supply
Signal Name:
Signal Description:
Signal Type:
0.0 volts.
VSS
Signal Ground
Supply
3. DS21FT40 REGISTER MAP
Register Map for Each Quad Framer Sorted by Address Table 3-1
ADDRESS
R/W
REGISTER NAME
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
R
R
R
R
R
R
R/W
R/W
R/W
R/W
–
–
–
BPV or Code Violation Count 1
BPV or Code Violation Count 2
CRC4 Error Count 1 / FAS Error Count 1
CRC4 Error Count 2
E-Bit Count 1 / FAS Error Count 2
E-Bit Count 2
Status 1
Status 2
Receive Information
Test 2
Not used
Not used
Not used
19 of 87
REGISTER
ABBREVIATION
VCR1
VCR2
CRCCR1
CRCCR2
EBCR1
EBCR2
SR1
SR2
RIR
TEST2 (set to 00h)
(set to 00H)
(set to 00H)
(set to 00H)
DS21FT40
ADDRESS
R/W
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
–
–
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
–
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
23
R/W
24
R/W
25
R/W
26
27
28
29
2A
2B
2C
2D
2E
2F
30
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
REGISTER NAME
Not used
Not used
Device ID
Receive Control 1
Receive Control 2
Transmit Control 1
Transmit Control 2
Common Control 1
Test 1
Interrupt Mask 1
Interrupt Mask 2
Not used
Not used
Common Control 2
Common Control 3
Transmit Sa Bit Control
Common Control 6
Synchronizer Status
Receive Non-Align Frame
Transmit Align Frame
Transmit Non-Align Frame
Transmit Channel Blocking 1
(Not applicable to DS21FT40 – write to
00H.)
Transmit Channel Blocking 2
(Not applicable to DS21FT40 – write to
00H.)
Transmit Channel Blocking 3
(Not applicable to DS21FT40 – write to
00H.)
Transmit Channel Blocking 4
(Not applicable to DS21FT40 – write to
00H.)
Transmit Idle 1
Transmit Idle 2
Transmit Idle 3
Transmit Idle 4
Transmit Idle Definition
Receive Channel Blocking 1
Receive Channel Blocking 2
Receive Channel Blocking 3
Receive Channel Blocking 4
Receive Align Frame
Receive Signaling 1
20 of 87
REGISTER
ABBREVIATION
(set to 00H)
(set to 00H)
IDR
RCR1
RCR2
TCR1
TCR2
CCR1
TEST1 (set to 00h)
IMR1
IMR2
(set to 00H)
(set to 00H)
CCR2
CCR3
TSaCR
CCR6
SSR
RNAF
TAF
TNAF
TCBR1
TCBR2
TCBR3
TCBR4
TIR1
TIR2
TIR3
TIR4
TIDR
RCBR1
RCBR2
RCBR3
RCBR4
RAF
RS1
DS21FT40
ADDRESS
R/W
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
REGISTER NAME
Receive Signaling 2
Receive Signaling 3
Receive Signaling 4
Receive Signaling 5
Receive Signaling 6
Receive Signaling 7
Receive Signaling 8
Receive Signaling 9
Receive Signaling 10
Receive Signaling 11
Receive Signaling 12
Receive Signaling 13
Receive Signaling 14
Receive Signaling 15
Receive Signaling 16
Transmit Signaling 1
Transmit Signaling 2
Transmit Signaling 3
Transmit Signaling 4
Transmit Signaling 5
Transmit Signaling 6
Transmit Signaling 7
Transmit Signaling 8
Transmit Signaling 9
Transmit Signaling 10
Transmit Signaling 11
Transmit Signaling 12
Transmit Signaling 13
Transmit Signaling 14
Transmit Signaling 15
Transmit Signaling 16
Transmit Si Bits Align Frame
Transmit Si Bits Non-Align Frame
Transmit Remote Alarm Bits
Transmit Sa4 Bits
Transmit Sa5 Bits
Transmit Sa6 Bits
Transmit Sa7 Bits
Transmit Sa8 Bits
Receive Si bits Align Frame
Receive Si bits Non-Align Frame
Receive Remote Alarm Bits
Receive Sa4 Bits
Receive Sa5 Bits
21 of 87
REGISTER
ABBREVIATION
RS2
RS3
RS4
RS5
RS6
RS7
RS8
RS9
RS10
RS11
RS12
RS13
RS14
RS15
RS16
TS1
TS2
TS3
TS4
TS5
TS6
TS7
TS8
TS9
TS10
TS11
TS12
TS13
TS14
TS15
TS16
TSiAF
TSiNAF
TRA
TSa4
TSa5
TSa6
TSa7
TSa8
RSiAF
RSiNAF
RRA
RSa4
RSa5
DS21FT40
ADDRESS
R/W
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
REGISTER NAME
Receive Sa6 Bits
Receive Sa7 Bits
Receive Sa8 Bits
Transmit Channel 1
Transmit Channel 2
Transmit Channel 3
Transmit Channel 4
Transmit Channel 5
Transmit Channel 6
Transmit Channel 7
Transmit Channel 8
Transmit Channel 9
Transmit Channel 10
Transmit Channel 11
Transmit Channel 12
Transmit Channel 13
Transmit Channel 14
Transmit Channel 15
Transmit Channel 16
Transmit Channel 17
Transmit Channel 18
Transmit Channel 19
Transmit Channel 20
Transmit Channel 21
Transmit Channel 22
Transmit Channel 23
Transmit Channel 24
Transmit Channel 25
Transmit Channel 26
Transmit Channel 27
Transmit Channel 28
Transmit Channel 29
Transmit Channel 30
Transmit Channel 31
Transmit Channel 32
Receive Channel 1
Receive Channel 2
Receive Channel 3
Receive Channel 4
Receive Channel 5
Receive Channel 6
Receive Channel 7
Receive Channel 8
Receive Channel 9
22 of 87
REGISTER
ABBREVIATION
RSa6
RSa7
RSa8
TC1
TC2
TC3
TC4
TC5
TC6
TC7
TC8
TC9
TC10
TC11
TC12
TC13
TC14
TC15
TC16
TC17
TC18
TC19
TC20
TC21
TC22
TC23
TC24
TC25
TC26
TC27
TC28
TC29
TC30
TC31
TC32
RC1
RC2
RC3
RC4
RC5
RC6
RC7
RC8
RC9
DS21FT40
ADDRESS
R/W
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
–
–
–
R/W
R/W
R/W
R/W
R/W
REGISTER NAME
Receive Channel 10
Receive Channel 11
Receive Channel 12
Receive Channel 13
Receive Channel 14
Receive Channel 15
Receive Channel 16
Receive Channel 17
Receive Channel 18
Receive Channel 19
Receive Channel 20
Receive Channel 21
Receive Channel 22
Receive Channel 23
Receive Channel 24
Receive Channel 25
Receive Channel 26
Receive Channel 27
Receive Channel 28
Receive Channel 29
Receive Channel 30
Receive Channel 31
Receive Channel 32
Transmit Channel Control 1
Transmit Channel Control 2
Transmit Channel Control 3
Transmit Channel Control 4
Receive Channel Control 1
Receive Channel Control 2
Receive Channel Control 3
Receive Channel Control 4
Common Control 4
Transmit DS0 Monitor
Common Control 5
Receive DS0 Monitor
Test 3
Not used
Not used
Not used
HDLC Control Register
HDLC Status Register
HDLC Interrupt Mask Register
Receive HDLC Information Register
Receive HDLC FIFO Register
23 of 87
REGISTER
ABBREVIATION
RC10
RC11
RC12
RC13
RC14
RC15
RC16
RC17
RC18
RC19
RC20
RC21
RC22
RC23
RC24
RC25
RC26
RC27
RC28
RC29
RC30
RC31
RC32
TCC1
TCC2
TCC3
TCC4
RCC1
RCC2
RCC3
RCC4
CCR4
TDS0M
CCR5
RDS0M
TEST3 (set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
HCR
HSR
HIMR
RHIR
RHFR
DS21FT40
ADDRESS
R/W
REGISTER NAME
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
–
–
–
Interleave Bus Operation Register
Transmit HDLC Information Register
Transmit HDLC FIFO Register
Receive HDLC DS0 Control Register 1
Receive HDLC DS0 Control Register 2
Transmit HDLC DS0 Control Register 1
Transmit HDLC DS0 Control Register 2
Not used
Not used
Not used
Not used
REGISTER
ABBREVIATION
IBO
THIR
THFR
RDC1
RDC2
TDC1
TDC2
(set to 00H)
(set to 00H)
(set to 00H)
(set to 00H)
NOTES:
1. Test Registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all
zeros) on power– up initialization to insure proper operation.
2. Register banks CxH, DxH, ExH, and FxH are not accessible.
4. PARALLEL PORT
The DS21FT40 is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by
an external microcontroller or microprocessor. The DS21FT40 can operate with either Intel or Motorola
bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola
timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in
the A.C. Electrical Characteristics in Section 17 for more details.
5. CONTROL, ID AND TEST REGISTERS
The operation of each framer within the DS21FT40 is configured via a set of ten control registers.
Typically, the control registers are only accessed when the system is first powered up. Once a channel in
the DS21FT40 has been initialized, the control registers will only need to be accessed when there is a
change in the system configuration. There are two Receive Control Register (RCR1 and RCR2), two
Transmit Control Registers (TCR1 and TCR2), and six Common Control Registers (CCR1 to CCR6).
Each of the ten registers are described in this section.
There is a device Identification Register (IDR) at address 0Fh. The MSB of this read–only register is
fixed to a one indicating that the DS21Q44 die is present. The lower 4 bits of the IDR are used to display
the die revision of the chip.
24 of 87
DS21FT40
Power–Up Sequence
The DS21FT40 does not automatically clear its register space on power–up. After the supplies are stable,
each of the four framer’s register space should be configured for operation by writing to all of the internal
registers. This includes setting the Test and all unused registers to 00Hex.
This can be accomplished using a two-pass approach on each quad framer within the DS21FT40.
1. Clear each quad framer’s register space by writing 00H to addresses 00H through 0BFH.
2. Program required registers to achieve desired operating mode.
Finally, after the TSYSCLK and RSYSCLK inputs are stable, the ESR bit should be toggled from a zero
to a one (this step can be skipped if the elastic stores are disabled).
IDR: DEVICE IDENTIFICATION REGISTER (Address=0F Hex)
(MSB)
T1E1
0
0
SYMBOLS
POSITION
T1E1
IDR.7
ID3
IDR.3
ID2
ID1
ID0
IDR.1
IDR.2
IDR.0
0
ID3
ID2
ID1
(LSB)
ID0
NAME AND DESCRIPTION
T1 or E1 Chip Determination Bit.
0=T1 chip
1=E1 chip
Chip Revision Bit 3. MSB of a decimal code that represents
the chip revision.
Chip Revision Bit 2.
Chip Revision Bit 1.
Chip Revision Bit 0. LSB of a decimal code that represents
the chip revision.
RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex)
(MSB)
RSMF
RSM
RSIO
SYMBOLS
POSITION
RSMF
RCR1.7
RSM
RCR1.6
RSIO
RCR1.5
–
–
RCR1.4
RCR1.3
–
–
FRC
SYNCE
(LSB)
RESYNC
NAME AND DESCRIPTION
RSYNC Multiframe Function. Only used if the RSYNC pin
is programmed in the multiframe mode (RCR1.6=1).
0 = RSYNC outputs CAS multiframe boundaries
1 = RSYNC outputs CRC4 multiframe boundaries
RSYNC Mode Select.
0 = frame mode (see the timing in Section 18)
1 = multiframe mode (see the timing in Section 18)
RSYNC I/O Select. (note: this bit must be set to zero when
RCR2.1=0).
0 = RSYNC is an output (depends on RCR1.6)
1 = RSYNC is an input (only valid if elastic store enabled)
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
25 of 87
DS21FT40
SYMBOLS
POSITION
FRC
RCR1.2
SYNCE
RCR1.1
RESYNC
RCR1.0
NAME AND DESCRIPTION
Frame Resync Criteria.
0 = resync if FAS received in error 3 consecutive times
1 = resync if FAS or bit 2 of non–FAS is received in error 3
consecutive times
Sync Enable.
0 = auto resync enabled
1 = auto resync disabled
Resync. When toggled from low to high, a resync is initiated.
Must be cleared and set again for a subsequent resync.
SYNC/RESYNC CRITERIA Table 5–1
FRAME OR
MULTIFRAME
LEVEL
FAS
CRC4
CAS
SYNC CRITERIA
RESYNC CRITERIA
ITU SPEC.
FAS present in frame N and Three consecutive incorrect
N + 2, and FAS not present FAS received
in frame N + 1
Alternate (RCR1.2=1) the
above criteria is met or
three consecutive incorrect
bit 2 of non–FAS received
Two valid MF alignment
915 or more CRC4 code
words found within 8 ms
words out of 1000 received
in error
Valid MF alignment word
Two consecutive MF
found and previous timeslot alignment words received
16 contains code other than in error
all zeros
G.706
4.1.1
4.1.2
G.706
4.2 and 4.3.2
G.732 5.2
RCR2: RECEIVE CONTROL REGISTER 2 (Address=11 Hex)
(MSB)
Sa8S
Sa7S
Sa6S
SYMBOLS
POSITION
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
RCR2.7
RCR2.6
RCR2.5
RCR2.4
RCR2.3
Sa5S
Sa4S
RBCS
RESE
NAME AND DESCRIPTION
Sa8 Bit Select.
Sa7 Bit Select.
Sa6 Bit Select.
Sa5 Bit Select.
Sa4 Bit Select.
Not applicable for DS21FT40.
Not applicable for DS21FT40.
Not applicable for DS21FT40.
Not applicable for DS21FT40.
Not applicable for DS21FT40.
26 of 87
(LSB)
–
DS21FT40
SYMBOLS
POSITION
RBCS
RCR2.2
RESE
RCR2.1
–
RCR2.0
NAME AND DESCRIPTION
Receive Side Backplane Clock Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
Receive Side Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
Not Assigned. Should be set to zero when written.
TCR1: TRANSMIT CONTROL REGISTER 1 (Address=12 Hex)
(MSB)
ODF
TFPT
T16S
SYMBOLS
POSITION
ODF
TCR1.7
TFPT
TCR1.6
T16S
TCR1.5
TUA1
TCR1.4
TSiS
TCR1.3
TSA1
TCR1.2
TSM
CR1.1
TSIO
TCR1.0
TUA1
TSiS
TSA1
TSM
(LSB)
TSIO
NAME AND DESCRIPTION
Output Data Format.
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG=0
Transmit Timeslot 0 Pass Through.
0 = FAS bits/Sa bits/Remote Alarm sourced internally from
the TAF and TNAF registers
1 = FAS bits/Sa bits/Remote Alarm sourced from TSER
Transmit Timeslot 16 Data Select.
0 = sample timeslot 16 at TSER pin
1 = source timeslot 16 from TS0 to TS15 registers
Transmit Unframed All Ones.
0 = transmit data normally
1 = transmit an unframed all one’s code at TPOS and TNEG
Transmit International Bit Select.
0 = sample Si bits at TSER pin
1 = source Si bits from TAF and TNAF registers (in this
mode, TCR1.6 must be set to 0)
Transmit Signaling All Ones.
0 = normal operation
1 = force timeslot 16 in every frame to all ones
TSYNC Mode Select.
0 = frame mode (see the timing in Section 16)
1 = CAS and CRC4 multiframe mode (see the timing in
Section 16)
TSYNC I/O Select.
0 = TSYNC is an input
1 = TSYNC is an output
NOTE:
See Figure 16–15 for more details about how the Transmit Control Registers affect the operation of the
DS21FT40.
27 of 87
DS21FT40
TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex)
(MSB)
Sa8S
Sa7S
Sa6S
SYMBOLS
POSITION
Sa8S
Sa7S
Sa6S
Sa5S
Sa4S
ODM
TCR2.7
TCR2.6
TCR2.5
TCR2.4
TCR2.3
TCR2.2
AEBE
TCR2.1
PF
TCR2.0
Sa5S
Sa4S
ODM
AEBE
(LSB)
PF
NAME AND DESCRIPTION
Sa8 Bit Select. Not applicable for DS21FT40.
Sa7 Bit Select. Not applicable for DS21FT40.
Sa6 Bit Select. Not applicable for DS21FT40.
Sa5 Bit Select. Not applicable for DS21FT40.
Sa4 Bit Select. Not applicable for DS21FT40.
Output Data Mode.
0 = pulses at TPOSO and TNEGO are one full TCLKO period
wide
1 = pulses at TPOSO and TNEGO are 1/2 TCLKO period
wide
Automatic E–Bit Enable.
0 = E–bits not automatically set in the transmit direction
1 = E–bits automatically set in the transmit direction
Function of RLOS/LOTC Pin.
Not applicable for DS21FT40. Should be cleared to zero.
CCR1: COMMON CONTROL REGISTER 1 (Address=14 Hex)
(MSB)
FLB
THDB3
TG802
SYMBOLS
POSITION
FLB
CCR1.7
THDB3
CCR1.6
TG802
CCR1.5
TCRC4
CCR1.4
RSM
CCR1.3
RHDB3
CCR1.2
TCRC4
RSM
RHDB3
RG802
(LSB)
RCRC4
NAME AND DESCRIPTION
Framer Loopback.
0=loopback disabled
1=loopback enabled
Transmit HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
Transmit G.802 Enable. See Section 16 for details.
Not applicable for DS21FT40. Should be cleared to zero.
Transmit CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
Receive Signaling Mode Select.
0=CAS signaling mode
1=CCS signaling mode
Receive HDB3 Enable.
0=HDB3 disabled
1=HDB3 enabled
28 of 87
DS21FT40
SYMBOLS
POSITION
RG802
CCR1.1
RCRC4
CCR1.0
NAME AND DESCRIPTION
Receive G.802 Enable. See Section 16 for details.
Not applicable for DS21FT40. Should be cleared to zero.
Receive CRC4 Enable.
0=CRC4 disabled
1=CRC4 enabled
FRAMER LOOPBACK
When CCR1.7 is set to a one, the framer will enter a Framer LoopBack (FLB) mode. See Figure 1–2 for
more details. This loopback is useful in testing and debugging applications. In FLB, the framer will loop
data from the transmit side back to the receive side. When FLB is enabled, the following will occur:
1. Data will be transmitted as normal at TPOS and TNEG.
2. Data input via RPOS and RNEG will be ignored.
3. The RCLK output will be replaced with the TCLK input.
CCR2: COMMON CONTROL REGISTER 2 (Address=1A Hex)
(MSB)
ECUS
VCRFS
AAIS
SYMBOLS
POSITION
ECUS
CCR2.7
VCRFS
CCR2.6
AAIS
CCR2.5
ARA
CCR2.4
RSERC
CCR2.3
LOTCMC
CCR2.2
RFF
CCR2.1
ARA
RSERC
LOTCMC
RFF
(LSB)
RFE
NAME AND DESCRIPTION
Error Counter Update Select. See Section 7 for details.
0=update error counters once a second
1=update error counters every 62.5 ms (500 frames)
VCR Function Select. See Section 7 for details.
0=count BiPolar Violations (BPVs)
1=count Code Violations (CVs)
Automatic AIS Generation.
0=disabled
1=enabled
Automatic Remote Alarm Generation.
0=disabled
1=enabled
RSER Control.
0=allow RSER to output data as received under all conditions
1=force RSER to one under loss of frame alignment conditions
Loss of Transmit Clock Mux Control. Determines whether the
transmit side formatter should switch to the ever present RCLK
if the TCLK should fail to transition (see Figure 1–2).
0=do not switch to RCLK if TCLK stops
1=switch to RCLK if TCLK stops
Receive Force Freeze. Freezes receive side signaling at RSER
(if CCR3.3=1); will override Receive Freeze Enable (RFE).
See Section 9 for details.
0=do not force a freeze event
1=force a freeze event
29 of 87
DS21FT40
SYMBOLS
POSITION
RFE
CCR2.0
NAME AND DESCRIPTION
Receive Freeze Enable. See Section 9 for details.
0=no freezing of receive signaling data will occur
1=allow freezing of receive signaling data at RSER (if
CCR3.3=1).
AUTOMATIC ALARM GENERATION
The DS21FT40 can be programmed to automatically transmit AIS or Remote Alarm. When automatic
AIS generation is enabled (CCR2.5 = 1), the framer monitors the receive side to determine if any of the
following conditions are present: loss of receive frame synchronization, AIS alarm (all one’s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
framer will transmit an AIS alarm.
When automatic RAI generation is enabled (CCR2.4 = 1), the framer monitors the receive side to
determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm
(all one’s) reception, loss of receive carrier or if CRC4 multiframe synchronization (if enabled) cannot be
found within 128 ms of FAS synchronization. If any one (or more) of the above conditions is present,
then the framer will transmit a RAI alarm. RAI generation conforms to ETS 300 011 specifications and a
constant Remote Alarm will be transmitted if the framer cannot find CRC4 multiframe synchronization
within 400 ms as per G.706.
It is an illegal state to have both CCR2.4 and CCR2.5 set to one at the same time.
CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex)
(MSB)
TESE
TCBFS
TIRFS
SYMBOLS
POSITION
TESE
CCR3.7
TCBFS
CCR3.6
TIRFS
CCR3.5
–
CCR3.4
–
RSRE
THSE
TBCS
(LSB)
RCLA
NAME AND DESCRIPTION
Transmit Side Elastic Store Enable.
0=elastic store is bypassed
1=elastic store is enabled
Transmit Channel Blocking Registers (TCBR) Function Select.
0=TCBRs define the operation of the TCHBLK output pin (not
applicable for DS21FT40)
1=TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select. See Section 10
for details.
0=TIRs define in which channels to insert idle code
1=TIRs define in which channels to insert data from RSER
(i.e., Per Channel Loopback function)
Not Assigned. Should be set to zero when written.
30 of 87
DS21FT40
SYMBOLS
POSITION
RSRE
CCR3.3
THSE
CCR3.2
TBCS
CCR3.1
RCLA
CCR3.0
NAME AND DESCRIPTION
Receive Side Signaling Re–Insertion Enable. See Section 9 for
details.
0=do not re–insert signaling bits into the data stream presented
at the RSER pin
1=re–insert the signaling bits into data stream presented at the
RSER pin
Transmit Side Hardware Signaling Insertion Enable.
Not applicable for DS21FT40. Should be cleared to zero.
Transmit Side Backplane Clock Select.
0=if TSYSCLK is 1.544 MHz
1=if TSYSCLK is 2.048 MHz
Receive Carrier Loss (RCL) Alternate Criteria.
0=RCL declared upon 255 consecutive zeros (125 us)
1=RCL declared upon 2048 consecutive zeros (1 ms)
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
(MSB)
RLB
–
–
SYMBOLS
POSITION
RLB
CCR4.7
–
–
TCM4
CCR4.6
CCR4.5
CCR4.4
TCM3
TCM2
TCM1
TCM0
CCR4.3
CCR4.2
CCR4.1
CCR4.0
TCM4
TCM3
TCM2
TCM1
(LSB)
TCM0
NAME AND DESCRIPTION
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that deter-mines which transmit channel data will appear in the
TDS0M register. See Section 8 for details.
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
31 of 87
DS21FT40
CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
(MSB)
–
RESALGN
TESALGN
SYMBOLS
POSITION
–
RESALGN
CCR5.7
CCR5.6
TESALGN
CCR5.5
RCM4
CCR5.4
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
RCM4
RCM3
RCM2
RCM1
(LSB)
RCM0
NAME AND DESCRIPTION
Not Assigned. Should be set to zero when written
Receive Elastic Store Align. Setting this bit from a zero to a
one may force the receive elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after RSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 12 for details.
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 12 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the
RDS0M register. See Section 8 for details.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)
(MSB)
–
–
–
SYMBOLS
POSITION
–
–
–
–
–
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
–
–
TCLKSRC
RESR
NAME AND DESCRIPTION
Not Assigned.
Not Assigned.
Not Assigned.
Not Assigned.
Not Assigned.
Should be set to zero when written
Should be set to zero when written
Should be set to zero when written
Should be set to zero when written
Should be set to zero when written
32 of 87
(LSB)
TESR
DS21FT40
SYMBOLS
POSITION
TCLKSRC
CCR6.2
RESR
CCR6.1
TESR
CCR6.0
NAME AND DESCRIPTION
Transmit Clock Source Select. This function allows the user to
internally select RCLK as the clock source for the transmit side
formatter.
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
Receive Elastic Store Reset. Setting this bit from a zero to a
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this
bit set high.
Transmit Elastic Store Reset. Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this
bit set high.
6. STATUS AND INFORMATION REGISTERS
There is a set of seven registers per framer that contain information on the current real time status of a
framer in the DS21FT40, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register
(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.
The specific details on the four registers pertaining to the HDLC controller are covered in Section 14 but
they operate the same as the other status registers in the DS21FT40 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The
Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and
a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again (or in the case of the
RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still
present).
The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The byte
written to the register will inform the framer which bits the user wishes to read and have cleared. The
user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and
a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with the latest information. When a zero is
written to a bit position, the read register will not be updated and the previous value will be held. A write
to the status and information registers will be immediately followed by a read of the same register. The
read result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write–read– write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21FT40 with higher–order software languages.
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The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and
HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 14.
The interrupts caused by four of the alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently
than the interrupts caused by other alarms and events in SR1 and SR2 (namely RSA1, RDMA, RSA0,
RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). These four alarm interrupts will force
the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the
set/clear criteria in Table 6-1). The INT* pin will be allowed to return high (if no other interrupts are
present) when the user reads the alarm bit that caused the interrupt to occur. If the alarm is still present,
the register bit will remain set.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
ISR: INTERRUPT STATUS REGISTER
(Any address from 0C0 Hex to 0FF Hex)
(MSB)
F3HDLC
F3SR
F2HDLC
SYMBOLS
POSITION
F3HDLC
ISR.7
F3SR
ISR.6
F2HDLC
ISR.5
F2SR
ISR.4
F1HDLC
ISR.3
F1SR
ISR.2
F0HDLC
ISR.1
F2SR
F1HDLC
F1SR
F0HDLC
(LSB)
F0SR
NAME AND DESCRIPTION
FRAMER 3 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 3 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 2 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 2 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 1 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 1 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 0 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
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SYMBOLS
POSITION
F0SR
ISR.0
NAME AND DESCRIPTION
1 = Interrupt request pending.
FRAMER 0 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex)
(MSB)
TESF
TESE
–
SYMBOLS
POSITION
TESF
RIR.7
TESE
RIR.6
–
RESF
RIR.5
RIR.4
RESE
RIR.3
CRCRC
RIR.2
FASRC
RIR.1
CASRC
RIR.0
RESF
RESE
CRCRC
FASRC
(LSB)
CASRC
NAME AND DESCRIPTION
Transmit Side Elastic Store Full. Set when the transmit side
elastic store buffer fills and a frame is deleted.
Transmit Side Elastic Store Empty. Set when the transmit side
elastic store buffer empties and a frame is repeated.
Not Assigned. Could be any value.
Receive Side Elastic Store Full. Set when the receive side
elastic store buffer fills and a frame is deleted.
Receive Side Elastic Store Empty. Set when the receive side
elastic store buffer empties and a frame is repeated.
CRC Resync Criteria Met. Set when 915/1000 code words are
received in error.
FAS Resync Criteria Met. Set when 3 consecutive FAS words
are received in error.
CAS Resync Criteria Met. Set when 2 consecutive CAS MF
alignment words are received in error.
SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex)
(MSB)
CSC5
CSC4
CSC3
SYMBOLS
POSITION
CSC5
CSC4
CSC3
CSC2
CSC0
SSR.7
SSR.6
SSR.5
SSR.4
SSR.3
FASSA
SSR.2
CASSA
SSR.1
CRC4SA
SSR.0
CSC2
CSC0
FASSA
CASSA
(LSB)
CRC4SA
NAME AND DESCRIPTION
CRC4 Sync Counter Bit 5. MSB of the 6–bit counter.
CRC4 Sync Counter Bit 4.
CRC4 Sync Counter Bit 3.
CRC4 Sync Counter Bit 2.
CRC4 Sync Counter Bit 0. LSB of the 6–bit counter. The next
to LSB is not accessible.
FAS Sync Active. Set while the synchronizer is searching for
alignment at the FAS level.
CAS MF Sync Active. Set while the synchronizer is searching
for the CAS MF alignment word.
CRC4 MF Sync Active. Set while the synchronizer is
searching for the CRC4 MF alignment word.
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CRC4 SYNC COUNTER
The CRC4 Sync Counter increments each time the 8 ms CRC4 multiframe search times out. The counter
is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can
also be cleared by disabling the CRC4 mode (CCR1.0=0). This counter is useful for determining the
amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.706 suggests
that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be
abandoned and proper action taken. The CRC4 Sync Counter will rollover.
SR1: STATUS REGISTER 1 (Address=06 Hex)
(MSB)
RSA1
RDMA
RSA0
SYMBOLS
POSITION
RSA1
SR1.7
RDMA
SR1.6
RSA0
SR1.5
RSLIP
SR1.4
RUA1
SR1.3
RRA
SR1.2
RCL
SR1.1
RLOS
SR1.0
RSLIP
RUA1
RRA
RCL
(LSB)
RLOS
NAME AND DESCRIPTION
Receive Signaling All Ones / Signaling Change. Set when
over a full MF, the content of timeslot 16 contains less than
three zeros. This alarm is not disabled in the CCS signaling
mode. A change in the contents of RS1 through RS16 from
one multiframe to the next will cause RSA1 and RSA0 to be
set.
Receive Distant MF Alarm. Set when bit–6 of timeslot 16 in
frame 0 has been set for two consecutive multiframes. This
alarm is not disabled in the CCS signaling mode.
Receive Signaling All Zeros / Signaling Change. Set when
over a full MF, timeslot 16 contains all zeros. A change in the
contents of RS1 through RS16 from one multiframe to the next
will cause RSA1 and RSA0 to be set.
Receive Side Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
Receive Unframed All Ones. Set when an unframed all ones
code is received at RPOS and RNEG.
Receive Remote Alarm. Set when a remote alarm is received
at RPOS and RNEG.
Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0=1)
consecutive zeros have been detected at RPOS and RNEG.
Receive Loss of Sync. Set when the device is not
synchronized to the receive E1 stream.
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ALARM CRITERIA Table 6-1
ALARM
RSA1 (receive
signaling all ones)
RSA0 (receive
signaling all zeros)
RDMA (receive
distant multiframe
alarm)
RUA1 (receive
unframed all ones)
RRA (receive remote
alarm)
RCL (receive carrier
loss)
SET CRITERIA
CLEAR CRITERIA
over 16 consecutive frames
(one full MF) timeslot 16
contains less than three zeros
over 16 consecutive frames
(one full MF) timeslot 16
contains all zeros
bit 6 in timeslot 16 of frame 0
set to one for two consecutive
MF
less than three zeros in two
frames (512 bits)
bit 3 of non–align frame set
to one for three consecutive
occasions
255 (or 2048) consecutive
zeros received
over 16 consecutive frames
(one full MF) timeslot 16
contains three or more zeros
over 16 consecutive frames
(one full MF) timeslot 16
contains at least a single one
bit 6 in timeslot 16 of frame 0
set to zero for two
consecutive MF
more than two zeros in two
frames (512 bits)
bit 3 of non–align frame set
to zero for three consecutive
occasions
in 255 bit times, at least 32
ones are received
ITU
SPEC.
G.732
4.2
G.732
5.2
O.162
2.1.5
O.162
1.6.1.2
O.162
2.1.4
G.775 / G.962
SR2: STATUS REGISTER 2 (Address=07 Hex)
(MSB)
RMF
RAF
TMF
SYMBOLS
POSITION
RMF
SR2.7
RAF
SR2.6
TMF
SR2.5
SEC
SR2.4
TAF
SR2.3
SEC
TAF
LOTC
RCMF
(LSB)
TSLIP
NAME AND DESCRIPTION
Receive CAS Multiframe. Set every 2 ms (regardless if CAS
signaling is enabled or not) on receive multiframe boundaries.
Used to alert the host that signaling data is available.
Receive Align Frame. Set every 250 s at the beginning of
align frames. Used to alert the host that Si and Sa bits are
available in the RAF and RNAF registers.
Transmit Multiframe. Set every 2 ms (regardless if CRC4 is
enabled) on transmit multiframe boundaries. Used to alert the
host that signaling data needs to be updated.
One Second Timer. Set on increments of one second based on
RCLK. If CCR2.7=1, then this bit will be set every 62.5 ms
instead of once a second.
Transmit Align Frame. Set every 250 s at the beginning of
align frames. Used to alert the host that the TAF and TNAF
registers need to be updated.
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SYMBOLS
POSITION
LOTC
SR2.2
RCMF
SR2.1
TSLIP
SR2.0
NAME AND DESCRIPTION
Loss of Transmit Clock. Set when the TCLK pin has not
transitioned for one channel time (or 3.9 s).
Receive CRC4 Multiframe. Set on CRC4 multiframe
boundaries; will continue to be set every 2 ms on an arbitrary
boundary if CRC4 is disabled.
Transmit Elastic Store Slip. Set when the elastic store has
either repeated or deleted a frame of data.
IMR1: INTERRUPT MASK REGISTER 1 (Address=16 Hex)
(MSB)
RSA1
RDMA
RSA0
SYMBOLS
POSITION
RSA1
IMR1.7
RDMA
IMR1.6
RSA0
IMR1.5
RSLIP
IMR1.4
RUA1
IMR1.3
RRA
IMR1.2
RCL
IMR1.1
RLOS
IMR1.0
RSLIP
RUA1
RRA
RCL
NAME AND DESCRIPTION
Receive Signaling All Ones / Signaling Change.
0=interrupt masked
1=interrupt enabled
Receive Distant MF Alarm.
0=interrupt masked
1=interrupt enabled
Receive Signaling All Zeros / Signaling Change.
0=interrupt masked
1=interrupt enabled
Receive Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
Receive Unframed All Ones.
0=interrupt masked
1=interrupt enabled
Receive Remote Alarm.
0=interrupt masked
1=interrupt enabled
Receive Carrier Loss.
0=interrupt masked
1=interrupt enabled
Receive Loss of Sync.
0=interrupt masked
1=interrupt enabled
38 of 87
(LSB)
RLOS
DS21FT40
IMR2: INTERRUPT MASK REGISTER 2 (Address=17 Hex)
(MSB)
RMF
RAF
TMF
SYMBOLS
POSITION
RMF
IMR2.7
RAF
IMR2.6
TMF
IMR2.5
SEC
IMR2.4
TAF
IMR2.3
LOTC
IMR2.2
RCMF
IMR2.1
TSLIP
IMR2.0
SEC
TAF
LOTC
RCMF
(LSB)
TSLIP
NAME AND DESCRIPTION
Receive CAS Multiframe.
0=interrupt masked
1=interrupt enabled
Receive Align Frame.
0=interrupt masked
1=interrupt enabled
Transmit Multiframe.
0=interrupt masked
1=interrupt enabled
One Second Timer.
0=interrupt masked
1=interrupt enabled
Transmit Align Frame.
0=interrupt masked
1=interrupt enabled
Loss Of Transmit Clock.
0=interrupt masked
1=interrupt enabled
Receive CRC4 Multiframe.
0=interrupt masked
1=interrupt enabled
Transmit Side Elastic Store Slip Occurrence.
0=interrupt masked
1=interrupt enabled
7. ERROR COUNT REGISTERS
There are a set of four counters in each framer that record bipolar or code violations, errors in the CRC4
SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four
counters are automatically updated on either one second boundaries (CCR2.7=0) or every 62.5 ms
(CCR2.7=1) as determined by the timer in Status Register 2 (SR2.4). Hence, these registers contain
performance data from either the previous second or the previous 62.5 ms. The user can use the interrupt
from the one second timer to determine when to read these registers. The user has a full second (or 62.5
ms) to read the counters before the data is lost. All four counters will saturate at their respective
maximum counts and they will not rollover.
BPV or Code Violation Counter
Violation Count Register 1 (VCR1) is the most significant word and VCR2 is the least significant word of
a 16–bit counter that records either BiPolar Violations (BPVs) or Code Violations (CVs). If CCR2.6=0,
then the VCR counts bipolar violations. Bipolar violations are defined as consecutive marks of the same
polarity. In this mode, if the HDB3 mode is set for the receive side via CCR1.2, then HDB3 code words
are not counted as BPVs. If CCR2.6=1, then the VCR counts code violations as defined in ITU O.161.
Code violations are defined as consecutive bipolar violations of the same polarity. In most applications,
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DS21FT40
the framer should be programmed to count BPVs when receiving AMI code and to count CVs when
receiving HDB3 code. This counter increments at all times and is not disabled by loss of sync conditions.
The counter saturates at 65,535 and will not rollover. The bit error rate on a E1 line would have to be
greater than 10** –2 before the VCR would saturate.
VCR1: UPPER BIPOLAR VIOLATION COUNT REGISTER 1 (Address=00 Hex)
VCR2: LOWER BIPOLAR VIOLATION COUNT REGISTER 2 (Address=01 Hex)
(MSB)
V15
V7
V14
V6
SYMBOLS
V15
V0
V13
V5
V12
V4
POSITION
VCR1.7
VCR2.0
V11
V3
V10
V2
V9
V1
(LSB)
V8
V0
VCR1
VCR2
NAME AND DESCRIPTION
MSB of the 16–bit code violation count
LSB of the 10–bit code violation count
CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the
least significant word of a 10–bit counter that records word errors in the Cyclic Redundancy Check 4
(CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate.
The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if
loss of multiframe sync occurs at the CAS level.
CRCCR1: CRC4 COUNT REGISTER 1 (Address=02 Hex)
CRCCR2: CRC4 COUNT REGISTER 2 (Address=03 Hex)
(MSB)
(note 1)
CRC7
(note 1)
CRC6
(note 1)
CRC5
(note 1)
CRC4
(note 1)
CRC3
(note 1)
CRC2
CRC9
CRC1
SYMBOLS
POSITION
NAME AND DESCRIPTION
CRC9
CRC0
CRCCR1.1
CRCCR2.0
MSB of the 10–Bit CRC4 error count
LSB of the 10–Bit CRC4 error count
(LSB)
CRC8
CRC0
CRCCR1
CRCCR2
NOTE:
1. The upper 6 bits of CRCCR1 at address 02 are the most significant bits of the 12–bit FAS error
counter.
E–Bit Counter
E–bit Count Register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of
a 10–bit counter that records Far End Block Errors (FEBE) as reported in the first bit of frames 13 and 15
on E1 lines running with CRC4 multiframe. These count registers will increment once each time the
received E–bit is set to zero. Since the maximum E–bit count in a one second period is 1000, this counter
cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will
continue to count if loss of multiframe sync occurs at the CAS level.
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DS21FT40
EBCR1: E–BIT COUNT REGISTER 1 (Address=04 Hex)
EBCR2: E–BIT COUNT REGISTER 2 (Address=05 Hex)
(MSB)
(note 1)
EB7
(note 1)
EB6
(note 1)
EB5
SYMBOLS
POSITION
EB9
EB0
EBCR1.1
EBCR2.0
(note 1)
EB4
(note 1)
EB3
(note 1)
EB2
EB9
EB1
(LSB)
EB8
EB0
EBCR1
EBCR2
NAME AND DESCRIPTION
MSB of the 10–Bit E–Bit Error Count
LSB of the 10–Bit E–Bit Error Count
NOTE:
The upper 6 bits of EBCR1 at address 04 are the least significant bits of the 12–bit FAS error counter.
FAS Error Counter
FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word
of a 12–bit counter that records word errors in the Frame Alignment Signal in timeslot 0. This counter is
disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS
alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FAS
word error count in a one second period is 4000, this counter cannot saturate.
FASCR1: FAS ERROR COUNT REGISTER 1 (Address=02 Hex)
FASCR2: FAS ERROR COUNT REGISTER 2 (Address=04 Hex)
(MSB)
FAS11
FAS5
FAS10
FAS4
FAS9
FAS3
FAS8
FAS2
FAS7
FAS1
FAS6
FAS0
(note 2)
(note 1)
SYMBOLS
POSITION
NAME AND DESCRIPTION
FAS11
FAS0
FASCR1.7
FASCR2.2
MSB of the 12–Bit FAS Error Count
LSB of the 12–Bit FAS Error Count
(LSB)
(note 2)
(note 1)
FASCR1
FASCR2
NOTES:
1. The lower 2 bits of FASCR1 at address 02 are the most significant bits of the 10–bit CRC4 error
counter.
2. The lower 2 bits of FASCR2 at address 04 are the most significant bits of the 10–bit E–Bit counter.
8. DS0 MONITORING FUNCTION
Each framer in the DS21FT40 has the ability to monitor one DS0 64Kbps channel in the transmit
direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user
will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4
register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set.
The DS0 channel pointed to by the TCM0 to TCM4 bits will appear in the Transmit DS0 Monitor
(TDS0M) register and the DS0 channel pointed to by the RCM0 to RCM4 bits will appear in the Receive
DS0 (RDS0M) register. The TCM4 to TCM0 and RCM4 to RCM0 bits should be programmed with the
decimal decode of the appropriate E1 channel. For example, if DS0 channel 6 (timeslot 5) in the transmit
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DS21FT40
direction and DS0 channel 15 (timeslot 14) in the receive direction needed to be monitored, then the
following values would be programmed into CCR4 and CCR5:
TCM4 = 0
TCM3 = 0
TCM2 = 1
TCM1 = 0
TCM0 = 1
RCM4 = 0
RCM3 = 1
RCM2 = 1
RCM1 = 1
RCM0 = 0
CCR4: COMMON CONTROL REGISTER 4 (Address=A8 Hex)
[Repeated here from section 5 for convenience]
(MSB)
RLB
–
–
TCM4
SYMBOLS
POSITION
RLB
CCR4.7
–
–
TCM4
CCR4.6
CCR4.5
CCR4.4
TCM3
TCM2
TCM1
TCM0
CCR4.3
CCR4.2
CCR4.1
CCR4.0
TCM3
TCM2
TCM1
(LSB)
TCM0
NAME AND DESCRIPTION
Remote Loopback.
0 = loopback disabled
1 = loopback enabled
Not Assigned. Should be set to zero when written.
Not Assigned. Should be set to zero when written.
Transmit Channel Monitor Bit 4. MSB of a channel decode
that deter-mines which transmit channel data will appear in the
TDS0M register. See Section 8 or details.
Transmit Channel Monitor Bit 3.
Transmit Channel Monitor Bit 2.
Transmit Channel Monitor Bit 1.
Transmit Channel Monitor Bit 0. LSB of the channel decode.
TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=A9 Hex)
(MSB)
B1
B2
B3
SYMBOLS
POSITION
B1
TDS0M.7
B2
B3
B4
B5
B6
B7
B8
TDS0M.6
TDS0M.5
TDS0M.4
TDS0M.3
TDS0M.2
TDS0M.1
TDS0M.0
B4
B5
B6
B7
(LSB)
B8
NAME AND DESCRIPTION
Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first
bit to be transmitted).
Transmit DS0 Channel Bit 2.
Transmit DS0 Channel Bit 3.
Transmit DS0 Channel Bit 4.
Transmit DS0 Channel Bit 5.
Transmit DS0 Channel Bit 6.
Transmit DS0 Channel Bit 7.
Transmit DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be transmitted).
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DS21FT40
CCR5: COMMON CONTROL REGISTER 5 (Address=AA Hex)
[Repeated here from section 5 for convenience]
(MSB)
–
RESALGN TESALGN
RCM4
SYMBOLS
POSITION
–
RESALGN
CCR5.7
CCR5.6
TESALGN
CCR5.5
RCM4
CCR5.4
RCM3
RCM2
RCM1
RCM0
CCR5.3
CCR5.2
CCR5.1
CCR5.0
RCM3
RCM2
RCM1
(LSB)
RCM0
NAME AND DESCRIPTION
Not Assigned. Should be set to zero when written
Receive Elastic Store Align. Setting this bit from a zero to a
one may force the receive elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after RSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 12 for details.
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 12 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the
RDS0M register. See Section 8 for details.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
Receive Channel Monitor Bit 0. LSB of the channel decode.
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DS21FT40
RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = AB Hex)
(MSB)
B1
B2
B3
SYMBOLS
POSITION
B1
RDS0M.7
B2
B3
B4
B5
B6
B7
B8
RDS0M.6
RDS0M.5
RDS0M.4
RDS0M.3
RDS0M.2
RDS0M.1
RDS0M.0
B4
B5
B6
B7
(LSB)
B8
NAME AND DESCRIPTION
Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit
to be received).
Receive DS0 Channel Bit 2.
Receive DS0 Channel Bit 3.
Receive DS0 Channel Bit 4.
Receive DS0 Channel Bit 5.
Receive DS0 Channel Bit 6.
Receive DS0 Channel Bit 7.
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit
to be received).
9. SIGNALING OPERATION
Each framer in the DS21FT40 contains provisions for both processor based (i.e., software based)
signaling bit access and for hardware based access. Both the processor based access and the hardware
based access can be used simultaneously if necessary. The processor based signaling is covered in
Section 9.1 and the hardware based signaling is covered in Section 9.2.
9.1
PROCESSOR BASED SIGNALING
The Channel Associated Signaling (CAS) bits embedded in the E1 stream can be extracted from the
receive stream and inserted into the transmit stream by the framer. Each of the 30 voice channels has four
signaling bits (A/B/C/D) associated with it. The numbers in parenthesis () are the voice channel
associated with a particular signaling bit. The voice channel numbers have been assigned as described in
the ITU documents. Please note that this is different than the channel numbering scheme (1 to 32) that is
used in the rest of the data sheet. For example, voice channel 1 is associated with timeslot 1 (Channel 2)
and voice Channel 30 is associated with timeslot 31 (Channel 32). There is a set of 16 registers for the
receive side (RS1 to RS16) and 16 registers on the transmit side (TS1 to TS16). The signaling registers
are detailed below.
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RS1 TO RS16: RECEIVE SIGNALING REGISTERS (Address=30 to 3F Hex)
(MSB)
0
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
0
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
0
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
B(7)
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
SYMBOLS
POSITION
X
Y
A(1)
D(30)
RS1.0/1/3
RS1.2
RS2.7
RS16.0
0
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
B(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
X
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
B(22)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
Y
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
X
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
B(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
(LSB)
X
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
B(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
RS1 (30)
RS2 (31)
RS3 (32)
RS3 (33)
RS5 (34)
RS6 (35)
RS7 (36)
RS8 (37)
RS9 (38)
RS10 (39)
RS11 (3A)
RS12 (3B)
RS13 (3C)
RS14 (3D)
RS15 (3E)
RS16 (3F)
NAME AND DESCRIPTION
Spare Bits.
Remote Alarm Bit (integrated and reported in SR1.6).
Signaling Bit A for Channel 1
Signaling Bit D for Channel 30.
Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two timeslots. The
bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the
Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the
signaling bits. The user has a full 2 ms to retrieve the signaling bits before the data is lost. The RS
registers are updated under all conditions. Their validity should be qualified by checking for
synchronization at the CAS level. In CCS signaling mode, RS1 to RS16 can also be used to extract
signaling information. Via the SR2.7 bit, the user will be informed when the signaling registers have
been loaded with data. The user has 2 ms to retrieve the data before it is lost. The signaling data reported
in RS1 to RS16 is also available at the RSER pin.
Three status bits in Status Register 1 (SR1) monitor the contents of registers RS1 through RS16. Status
monitored includes all zeros detection, all ones detection and a change in register contents. The Receive
Signaling All Zeros status bit (SR1.5) is set when over a full multi-frame, RS1 through RS16 contain all
zeros. The Receive Signaling All Ones status bit (SR1.7) is set when over a full multi-frame, RS1
through RS16 contain less than three zeros. A change in the contents of RS1 through RS16 from one
multiframe to the next will cause RSA1 (SR1.7) and RSA0 (SR1.5) status bits to be set at the same time.
The user can enable the INT* pin to toggle low upon detection of a change in signaling by setting either
the IMR1.7 or IMR1.5 bit. Once a signaling change has been detected, the user has at least 1.75 ms to
read the data out of the RS1 to RS16 registers before the data will be lost.
45 of 87
DS21FT40
TS1 TO TS16: TRANSMIT SIGNALING REGISTERS (Address=40 to 4F Hex)
(MSB)
0
A(1)
A(2)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
0
B(1)
B(2)
B(3)
B(4)
B(5)
B(6)
B(7)
B(8)
B(9)
B(10)
B(11)
B(12)
B(13)
B(14)
B(15)
0
C(1)
C(2)
C(3)
C(4)
C(5)
C(6)
B(7)
C(8)
C(9)
C(10)
C(11)
C(12)
C(13)
C(14)
C(15)
SYMBOLS
POSITION
X
Y
A(1)
D(30)
TS1.0/1/3
TS1.2
TS2.7
TS16.0
0
D(1)
D(2)
D(3)
D(4)
D(5)
D(6)
B(7)
D(8)
D(9)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
X
A(16)
A(17)
A(18)
A(19)
A(20)
A(21)
B(22)
A(23)
A(24)
A(25)
A(26)
A(27)
A(28)
A(29)
A(30)
Y
B(16)
B(17)
B(18)
B(19)
B(20)
B(21)
B(22)
B(23)
B(24)
B(25)
B(26)
B(27)
B(28)
B(29)
B(30)
X
C(16)
C(17)
C(18)
C(19)
C(20)
C(21)
B(22)
C(23)
C(24)
C(25)
C(26)
C(27)
C(28)
C(29)
C(30)
(LSB)
X
D(16)
D(17)
D(18)
D(19)
D(20)
D(21)
B(22)
D(23)
D(24)
D(25)
D(26)
D(27)
D(28)
D(29)
D(30)
TS1 (40)
TS2 (41)
TS3 (42)
TS4 (43)
TS5 (44)
TS6 (45)
TS7 (46)
TS8 (47)
TS9 (48)
TS10 (49)
TS11 (4A)
TS12 (4B)
TS13 (4C)
TS14 (4D)
TS15 (4E)
TS16 (4F)
NAME AND DESCRIPTION
Spare Bits.
Remote Alarm Bit (integrated and reported in SR1.6).
Signaling Bit A for Channel 1
Signaling Bit D for Channel 30.
Each Transmit Signaling Register (TS1 to TS16) contains the CAS bits for two timeslots that will be
inserted into the outgoing stream if enabled to do so via TCR1.5. On multiframe boundaries, the framer
will load the values present in the Transmit Signaling Register into an outgoing signaling shift register
that is internal to the device. The user can utilize the Transmit Multiframe bit in Status Register 2
(SR2.5) to know when to update the signaling bits. The bit will be set every 2 ms and the user has 2 ms to
update the TSR’s before the old data will be retransmitted. ITU specifications recommend that the
ABCD signaling not be set to all zeros because they will emulate a CAS multiframe alignment word.
The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble.
The upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe
synchronization. If the user wishes to transmit a multiframe alarm to the far end, then the TS1.2 bit
should be set to a one. If no alarm is to be transmitted, then the TS1.2 bit should be cleared. The three
remaining bits in TS1 are the spare bits. If they are not used, they should be set to one. In CCS signaling
mode, TS1 to TS16 can also be used to insert signaling information. Via the SR2.5 bit, the user will be
informed when the signaling registers need to be loaded with data. The user has 2 ms to load the data
before the old data will be retransmitted.
Via the CCR3.6 bit, the user has the option to use the Transmit Channel Blocking Registers (TCBRs) to
determine on a channel by channel basis, which signaling bits are to be inserted via the TSRs (the
corresponding bit in the TCBRs=1) and which are to be sourced from the TSER pin. See the Transmit
Data Flow diagram in Section 16 for more details.
46 of 87
DS21FT40
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
CH20
CH24
CH28
CH32
CH4
CH8
CH12
CH16
CH19
CH23
CH27
CH31
CH3
CH7
CH11
CH15
CH18
CH22
CH26
CH30
CH2
CH6
CH10
CH14
CH17*
CH21
CH25
CH29
(LSB)
CH1*
CH5
CH9
CH13
TCBR1(22)
TCBR2(23)
TCBR3(24)
TCBR4(25)
*=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
9.2
HARDWARE BASED SIGNALING
Receive Side
Hardware signaling is supported through a mode called signaling re-insertion which is invoked by setting
the RSRE control bit high (CCR3.3=1). In this mode, the user will provide a multiframe sync at the
RSYNC pin and the signaling data will be re-aligned at the RSER output according to this applied
multiframe boundary. In this mode, the elastic store must be enabled and the backplane clock must be
2.048 MHz.
The signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. To allow this freeze action to occur, the RFE
control bit (CCR2.0) should be set high. The user can force a freeze by setting the RFF control bit
(CCR2.1) high. Setting the RFF bit high causes the same freezing action as if a loss of synchronization,
carrier loss, or slip has occurred.
The 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the
RSER pin (if RSRE=1 via CCR3.3). When freezing is enabled (RFE=1), the signaling data will be held
in the last known good state until the corrupting error condition subsides. When the error condition subsides, the signaling data will be held in the old state for an additional 3 ms to 5 ms before being allowed
to be updated with new signaling data.
10.
PER–CHANNEL CODE GENERATION AND LOOPBACK
Each framer in the DS21FT40 can replace data on a channel–by–channel basis in both the transmit and
receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section
10.1. The receive direction is from the E1 line to the backplane and is covered in Section 10.2.
10.1 TRANSMIT SIDE CODE GENERATION
In the transmit direction there are two methods by which channel data from the backplane can be
overwritten with data generated by the framer. The first method which is covered in Section 10.1.1 was a
feature contained in the original DS21Q43 while the second method which is covered in Section 10.1.2 is
a new feature of the DS21Q44.
10.1.1
Simple Idle Code Insertion and Per–Channel Loopback
The first method involves using the Transmit Idle Registers (TIR1/2/3/4) to determine which of the 32 E1
channels should be overwritten with the code placed in the Transmit Idle Definition Register (TIDR).
47 of 87
DS21FT40
This method allows the same 8–bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per–Channel Loopback]
(MSB)
CH8
CH7
CH6
CH5
CH16
CH15
CH14
CH13
CH24
CH23
CH22
CH21
CH32
CH31
CH30
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
(LSB)
CH1
CH9
CH17
CH25
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
SYMBOLS
POSITIONS
NAME AND DESCRIPTION
CH1 - 32
TIR1.0 - 4.7
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR3.5=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 1–2).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
(MSB)
TIDR7
TIDR6
TIDR5
SYMBOLS
POSITION
TIDR7
TIDR0
TIDR.7
TIDR.0
10.1.2
TIDR4
TIDR3
TIDR2
TIDR1
(LSB)
TIDR0
NAME AND DESCRIPTION
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
Per–Channel Code Insertion
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 32 E1 channels.
48 of 87
DS21FT40
TC1 TO TC32: TRANSMIT CHANNEL REGISTERS (Address=60 to 7F Hex)
(for brevity, only channel one is shown; see Table 3-1 for other register address)
(MSB)
C7
C6
C5
C4
C3
C2
C1
SYMBOLS
POSITION
C7
C0
TC1.7
TC1.0
(LSB)
C0
TC1 (60)
NAME AND DESCRIPTION
MSB of the Code (this bit is transmitted first)
LSB of the Code (this bit is transmitted last)
TCC1/TCC2/TCC3/TCC4: TRANSMIT CHANNEL CONTROL REGISTER
(Address=A0 to A3 Hex)
(MSB)
CH8
CH16
CH24
CH32
CH7
CH15
CH23
CH31
CH6
CH14
CH22
CH30
CH5
CH13
CH21
CH29
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
(LSB)
CH1
CH9
CH17
CH25
TCC1 (A0)
TCC2 (A1)
TCC3 (A2)
TCC4 (A3)
SYMBOLS
POSITION
NAME AND DESCRIPTION
CH1 - 32
TCC1.0 - 4.7
Transmit Code Insertion Control Bits
0 = do not insert data from the TC register into the transmit
data stream
1 = insert data from the TC register into the transmit data
stream
10.2 RECEIVE SIDE CODE GENERATION
On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of
the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code
placed in the Receive Channel Registers (RC1 to RC32). This method allows a different 8–bit code to be
placed into each of the 32 E1 channels.
RC1 TO RC32: RECEIVE CHANNEL REGISTERS (Address=80 to 9F Hex)
(for brevity, only channel one is shown; see Table 3-1 for other register address)
(MSB)
C7
C6
C5
C4
C3
C2
C1
SYMBOLS
C7
C0
POSITION
RC1.7
RC1.0
(LSB)
C0
RC1 (80)
NAME AND DESCRIPTION
MSB of the Code (this bit is sent first to the backplane)
LSB of the Code (this bit is sent last to the backplane)
49 of 87
DS21FT40
RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
(MSB)
CH8
CH7
CH6
CH16
CH15
CH14
CH24
CH23
CH22
CH32
CH31
CH30
SYMBOLS
CH1 - 32
11.
CH5
CH13
CH21
CH29
POSITION
RCC1.0 - 4.7
CH4
CH12
CH20
CH28
CH3
CH11
CH19
CH27
CH2
CH10
CH18
CH26
(LSB)
CH1
CH9
CH17
CH25
RCC1 (A4)
RCC2 (A5)
RCC3 (A6)
RCC4 (A7)
NAME AND DESCRIPTION
Receive Code Insertion Control Bits
0 = do not insert data from the RC register into the receive data
stream
1 = insert data from the RC register into the receive data
stream
CLOCK BLOCKING REGISTERS
The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit
Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins
on the DS21Q44 die, respectively. The RCHBLK and TCHBLK pins are not bonded out on the
DS21FT40 module. However, the Transmit Channel Blocking Registers have an alternate function that is
supported by the module. Via the CCR3.6 bit, the user has the option to use the TCBRs to determine on a
channel by channel basis, which signaling bits are to be inserted via the TSRs and which are to be sourced
from the TSER. If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from
and a one implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS)
registers. See definition below. See the timing in Section 16 for an example. The Receive Channel
Blocking Registers provide no function for the DS21FT40 and should be cleared to zero.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
(MSB)
CH20
CH24
CH28
CH32
CH4
CH8
CH12
CH16
CH19
CH23
CH27
CH31
CH3
CH7
CH11
CH15
CH18
CH22
CH26
CH30
CH2
CH6
CH10
CH14
CH17*
CH21
CH25
CH29
(LSB)
CH1*
CH5
CH9
CH13
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
*=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
12.
ELASTIC STORES OPERATION
Each framer in the DS21FT40 contains dual two–frame (512 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 MHz or
2.048 MHz. The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full
controlled slip capability which is necessary for this second purpose. Both elastic stores within a framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to
them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or
50 of 87
DS21FT40
disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048 MHz
backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset
(CCR6.0 & CCR6.1) function forces the elastic stores to a depth of one frame unconditionally. Data is
lost during the reset. The second method, the Elastic Store Align ( CCR5.5 & CCR5.6) forces the elastic
store depth to a minimum depth of half a frame only if the current pointer separation is already less then
half a frame. If a realignment occurs data is lost. In both mechanisms, independent resets are provided
for both the receive and transmit elastic stores.
12.1 RECEIVE SIDE
If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2 =0) or 2.048 MHz (RCR2.2=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a
pulse on frame/multiframe boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame
boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe
boundary, then RCR1.6 must be set to one. If the elastic store is enabled, then either CAS (RCR1.7=0) or
CRC4 (RCR1.7=1) multiframe boundaries will be indicated via the RMSYNC output. If the user selects
to apply a 1.544 MHz clock to the RSYSCLK pin, then every fourth channel of the received E1 data will
be deleted and a F–bit position (which will be forced to one) will be inserted. Hence Channels 1, 5, 9, 13,
17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received E1 data
stream). See Section 16 for timing details. If the 512–bit elastic buffer either fills or empties, a controlled
slip will occur. If the buffer empties, then a full frame of data (256–bits) will be repeated at RSER and
the SR1.4 and RIR.3 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted
and the SR1.4 and RIR.4 bits will be set to a one.
12.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544 MHz (CCR3.1=0) or 2.048 MHz (CCR3.1=1) clock can be applied
to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192 MHz. If the user
selects to apply a 1.544 MHz clock to the TSYSCLK pin, then the data sampled at TSER will be ignored
every fourth channel. Hence Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and
28) will be ignored. The user must supply a 8 kHz frame sync pulse to the TSSYNC input. See Section
16 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0 bit and the
direction of the slip is reported in the RIR.6 and RIR.7 bits.
13.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
Each framer in the DS21FT40 provides for access to both the Sa and the Si bits via two different
methods. The first method involves using the internal RAF/RNAF and TAF/TNAF registers and is
discussed in Section 13.1. The second method, which is covered in Section 13.2, involves an expanded
version of the first method.
13.1 INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME
On the receive side, the RAF and RNAF registers will always report the data as it received in the
Additional and International bit locations. The RAF and RNAF registers are updated with the setting of
the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when
to read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost.
51 of 87
DS21FT40
On the transmit side, data is sampled from the TAF and TNAF registers with the setting of the Transmit
Align Frame bit in Status Register 2 (SR2.3). The host can use the SR2.3 bit to know when to update the
TAF and TNAF registers. It has 250 us to update the data or else the old data will be retransmitted. Data
in the Si bit position will be overwritten if the framer is programmed: (1) to source the Si bits from the
TSER pin, (2) in the CRC4 mode, or (3) have automatic E–bit insertion enabled. Data in the Sa bit
position will be overwritten if any of the TCR2.3 to TCR2.7 bits are set to one. Please see the register
descriptions for TCR1 and TCR2 and the Transmit Data Flow diagram in Section 16 for more details.
RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex)
(MSB)
Si
0
0
SYMBOLS
POSITION
Si
0
0
1
1
0
1
1
RAF.7
RAF.6
RAF.5
RAF.4
RAF.3
RAF.2
RAF.1
RAF.0
1
1
0
1
(LSB)
1
NAME AND DESCRIPTION
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit
Frame Alignment Signal Bit.
RNAF: RECEIVE NON–ALIGN FRAME REGISTER (Address=1F Hex)
(MSB)
Si
1
A
SYMBOLS
POSITION
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
RNAF.7
RNAF.6
RNAF.5
RNAF.4
RNAF.3
RNAF.2
RNAF.1
RNAF.0
Sa4
Sa5
Sa6
NAME AND DESCRIPTION
International Bit.
Frame Non–Alignment Signal Bit.
Remote Alarm.
Additional Bit 4.
Additional Bit 5.
Additional Bit 6.
Additional Bit 7.
Additional Bit 8.
52 of 87
Sa7
(LSB)
Sa8
DS21FT40
TAF: TRANSMIT ALIGN FRAME REGISTER (Address=20 Hex)
(MSB)
(LSB)
Si
0
0
1
1
0
1
1
[Must be programmed with the 7 bit FAS word; the DS21FT40 does not automatically set these bits]
SYMBOLS
POSITION
Si
0
0
1
1
0
1
1
TAF.7
TAF.6
TAF.5
TAF.4
TAF.3
TAF.2
TAF.1
TAF.0
NAME AND DESCRIPTION
International Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
Frame Alignment Signal Bit.
TNAF: TRANSMIT NON–ALIGN FRAME REGISTER (Address=21 Hex)
(MSB)
Si
1
A
Sa4
Sa5
Sa6
Sa7
[Bit 2 must be programmed to one; the DS21FT40 does not automatically set this bit]
SYMBOLS
POSITION
Si
1
A
Sa4
Sa5
Sa6
Sa7
Sa8
TNAF.7
TNAF.6
TNAF.5
TNAF.4
TNAF.3
TNAF.2
TNAF.1
TNAF.0
(LSB)
Sa8
NAME AND DESCRIPTION
International Bit.
Frame Non–Alignment Signal Bit.
Remote Alarm (used to transmit the alarm).
Additional Bit 4.
Additional Bit 5.
Additional Bit 6.
Additional Bit 7.
Additional Bit 8.
13.2 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME
On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the
Si and Sa bits as they are received. These registers are updated with the setting of the Receive CRC4
Multiframe bit in Status Register 2 (SR2.1). The host can use the SR2.1 bit to know when to read these
registers. The user has 2 ms to retrieve the data before it is lost. The MSB of each register is the first
received. Please see the register descriptions below and the Transmit Data Flow diagram in Section 16
for more details. On the transmit side, there is also a set of eight registers (TSiAF, TSiNAF, TRA, TSa4
to TSa8) that via the Transmit Sa Bit Control Register (TSaCR), can be programmed to insert both Si and
Sa data. Data is sampled from these registers with the setting of the Transmit Multiframe bit in Status
Register 2 (SR2.5). The host can use the SR2.5 bit to know when to update these registers. It has 2 ms to
update the data or else the old data will be retransmitted. The MSB of each register is the first bit
transmitted. Please see the register descriptions below and the Transmit Data Flow diagram in Section 16
for more details.
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DS21FT40
REGISTER
NAME
RSiAF
RSiNAF
RRA
RSa4
RSa5
RSa6
RSa7
RSa8
TSiAF
TSiNAF
TRA
TSa4
TSa5
TSa6
TSa7
TSa8
ADDRESS
(HEX)
58
59
5A
5B
5C
5D
5E
5F
50
51
52
53
54
55
56
57
FUNCTION
The eight Si bits in the align frame.
The eight Si bits in the non–align frame.
The eight reportings of the receive remote alarm (RA).
The eight Sa4 reported in each CRC4 multiframe.
The eight Sa5 reported in each CRC4 multiframe.
The eight Sa6 reported in each CRC4 multiframe.
The eight Sa7 reported in each CRC4 multiframe.
The eight Sa8 reported in each CRC4 multiframe.
The eight Si bits to be inserted into the align frame.
The eight Si bits to be inserted into the non–align frame.
The eight settings of remote alarm (RA).
The eight Sa4 settings in each CRC4 multiframe.
The eight Sa5 settings in each CRC4 multiframe.
The eight Sa6 settings in each CRC4 multiframe.
The eight Sa7 settings in each CRC4 multiframe.
The eight Sa8 settings in each CRC4 multiframe.
TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address=1C Hex)
(MSB)
SiAF
SiNAF
RA
SYMBOLS
POSITION
SiAF
TSaCR.7
SiNAF
TSaCR.6
RA
TSaCR.5
Sa4
TSaCR.4
Sa4
Sa5
Sa6
Sa7
(LSB)
Sa8
NAME AND DESCRIPTION
International Bit in Align Frame Insertion Control Bit.
0=do not insert data from the TSiAF register into the transmit
data stream.
1=insert data from the TSiAF register into the transmit data
stream.
International Bit in Non–Align Frame Insertion Control Bit.
0=do not insert data from the TSiNAF register into the transmit
data stream.
1=insert data from the TSiNAF register into the transmit data
stream.
Remote Alarm Insertion Control Bit.
0=do not insert data from the TRA register into the transmit
data stream.
1=insert data from the TRA register into the transmit data
stream.
Additional Bit 4 Insertion Control Bit.
0=do not insert data from the TSa4 register into the transmit
data stream.
1=insert data from the TSa4 register into the transmit data
stream.
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DS21FT40
SYMBOLS
POSITION
Sa5
TSaCR.3
Sa6
TSaCR.2
Sa7
TSaCR.1
Sa8
TSaCR.0
14.
NAME AND DESCRIPTION
Additional Bit 5 Insertion Control Bit.
0=do not insert data from the TSa5 register into the transmit
data stream.
1=insert data from the TSa5 register into the transmit data
stream.
Additional Bit 6 Insertion Control Bit.
0=do not insert data from the TSa6 register into the transmit
data stream.
1=insert data from the TSa6 register into the transmit data
stream.
Additional Bit 7 Insertion Control Bit.
0=do not insert data from the TSa7 register into the transmit
data stream.
1=insert data from the TSa7 register into the transmit data
stream.
Additional Bit 8 Insertion Control Bit.
0=do not insert data from the TSa8 register into the transmit
data stream.
1=insert data from the TSa8 register into the transmit data
stream.
HDLC CONTROLLER FOR THE SA BITS OR DS0
Each framer in the DS21FT40 has the ability to extract/insert data from/ into the Sa bit positions (Sa4 to
Sa8) or from/to any multiple of DS0 channels Each framer contains a complete HDLC controller and this
operation is covered in Section 14.1.
14.1 GENERAL OVERVIEW
Each framer contains a complete HDLC controller with 64–byte buffers in both the transmit and receive
directions. The HDLC controller performs all the necessary overhead for generating and receiving a
HDLC formatted message.
The HDLC controller automatically generates and detects flags, generates and checks the CRC check
sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to
the HDLC data stream.
There are eleven registers that the host will use to operate and control the operation of the HDLC
controller. A brief description of the registers is shown in Table 14-1.
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DS21FT40
HDLC CONTROLLER REGISTER LIST Table 14-1
NAME
HDLC Control Register (HCR)
FUNCTION
general control over the HDLC and BOC
controllers
HDLC Status Register (HSR)
key status information for both transmit and
receive directions
HDLC Interrupt Mask Register (HIMR)
allows/stops status bits to/from causing an
interrupt
Receive HDLC Information Register
status information on receive HDLC
(RHIR)
controller
Receive HDLC FIFO Register (RHFR)
access to 64–byte HDLC FIFO in receive
direction
Receive HDLC DS0 Control Register 1
controls the HDLC function when used on
(RDC1)
DS0 channels
Receive HDLC DS0 Control Register 2
(RDC2)
Transmit HDLC Information Register
status information on transmit HDLC
(THIR)
controller
Transmit BOC Register (TBOC)
enables/disables transmission of BOC codes
Transmit HDLC FIFO Register (THFR)
access to 64–byte HDLC FIFO in transmit
direction
Transmit HDLC DS0 Control Register 1
controls the HDLC function when used on
(TDC1)
DS0 channels
Transmit HDLC DS0 Control Register 2
(TDC2)
14.2 HDLC STATUS REGISTERS
Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set
to a one. Some of the bits in these three status registers are latched and some are real time bits that are not
latched. Section 14.4 contains register descriptions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred
again. The real time bits report the current instantaneous conditions that are occurring and the history of
these bits is not latched.
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DS21FT40
Like the other status registers in the framer, the user will always proceed a read of any of the three
registers with a write. The byte written to the register will inform the framer which of the latched bits the
user wishes to read and have cleared (the real time bits are not affected by writing to the status register).
The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read
and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with current value and it will be cleared. When
a zero is written to a bit position, the read register will not be updated and the previous value will be held.
A write to the status and information registers will be immediately followed by a read of the same
register. The read result should be logically AND’ed with the mask byte that was just written and this
value should be written back into the same register to insure that bit does indeed clear. This second write
step is necessary because the alarms and events in the status registers occur asynchronously in respect to
their access via the parallel port. This write–read–write (for polled driven access) or write–read (for
interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS21FT40 with higher–order software languages.
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low
when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
14.3 BASIC OPERATION DETAILS
As a basic guideline for interpreting and sending HDLC messages, the following sequences can be
applied:
Receive a HDLC Message
1.
2.
3.
4.
5.
6.
7.
8.
Enable RPS interrupts.
Wait for interrupt to occur.
Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.
Read RHIR to obtain REMPTY status.
A. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
A1. If CBYTE=0 then skip to step 5
A2. If CBYTE=1 then skip to step 7
B. If REMPTY=1, then skip to step 6
Repeat step 4.
Wait for interrupt, skip to step 4.
If POK=0, then discard whole packet, if POK=1, accept the packet.
Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
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DS21FT40
Transmit a HDLC Message
1. Make sure HDLC controller is done sending any previous messages and is current sending flags by
checking that the FIFO is empty by reading the TEMPTY status bit in the THIR register.
2. Enable either the THALF or TNF interrupt.
3. Read THIR to obtain TFULL status.
A. If TFULL=0, then write a byte into the FIFO and skip to next step (special case occurs when
the last byte is to be written, in this case set TEOM=1 before writing the byte and then skip to
step 6)
B. If TFULL=1, then skip to step 5
4. Repeat step 3.
5. Wait for interrupt, skip to step 3.
6. Disable THALF or TNF interrupt and enable TMEND interrupt.
7. Wait for an interrupt, then read TUDR status bit to make sure packet was transmitted correctly.
14.4 HDLC REGISTER DESCRIPTION
HCR: HDLC CONTROL REGISTER (Address=B0 Hex)
(MSB)
–
RHR
TFS
SYMBOLS
POSITION
–
RHR
HCR.7
HCR.6
TFS
HCR.5
THR
HCR.4
TABT
HCR.3
TEOM
HCR.2
TZSD
HCR.1
TCRCD
HCR.0
THR
TABT
TEOM
TZSD
(LSB)
TCRCD
NAME AND DESCRIPTION
Not Assigned. Should be set to zero.
Receive HDLC Reset. A 0 to 1 transition will reset the receive
HDLC controller. Must be cleared and set again for a
subsequent reset.
Transmit Flag/Idle Select.
0 = 7Eh.
1 = FFh.
Transmit HDLC Reset. A 0 to 1 transition will reset the
transmit HDLC controller. Must be cleared and set again for a
subsequent reset.
Transmit Abort. A 0 to 1 transition will cause the FIFO
contents to be dumped and one FEh abort to be sent followed
by 7Eh or FFh flags/idle until a new packet is initiated by
writing new data into the FIFO. Must be cleared and set again
for a subsequent abort to be sent.
Transmit End of Message. Should be set to a one just before
the last data byte of a HDLC packet is written into the transmit
FIFO at THFR. The HDLC controller will clear this bit when
the last byte has been transmitted.
Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation).
1 = disable the zero stuffer.
Transmit CRC Defeat.
0 = enable CRC generation (normal operation).
1 = disable CRC generation.
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DS21FT40
HSR: HDLC STATUS REGISTER (Address=B1 Hex)
(MSB)
–
RPE
RPS
SYMBOLS
POSITION
–
RPE
HSR.7
HSR.6
RPS
HSR.5
RHALF
HSR.4
RNE
HSR.3
THALF
HSR.2
TNF
HSR.1
TMEND
HSR.0
RHALF
RNE
THALF
TNF
(LSB)
TMEND
NAME AND DESCRIPTION
Not Assigned. Should be set to zero.
Receive Packet End. Set when the HDLC controller detects
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as
a CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
Receive Packet Start. Set when the HDLC controller detects
an opening byte. The setting of this bit prompts the user to
read the RHIR register for details.
Receive FIFO Half Full. Set when the receive 64–byte FIFO
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
Receive FIFO Not Empty. Set when the receive 64–byte FIFO
has at least one byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half way point. The setting of this
bit prompts the user to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO
has at least one byte available. The setting of this bit prompts
the user to read the THIR register for details.
Transmit Message End. Set when the transmit HDLC
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
NOTE:
The RPE, RPS, and TMEND bits are latched and will be cleared when read.
HIMR: HDLC INTERRUPT MASK REGISTER (Address=B2 Hex)
(MSB)
–
RPE
RPS
SYMBOLS
POSITION
–
RPE
HIMR.7
HIMR.6
RPS
HIMR.5
RHALF
RNE
THALF
NAME AND DESCRIPTION
Not Assigned. Should be set to zero.
Receive Packet End.
0 = interrupt masked.
1 = interrupt enabled.
Receive Packet Start.
0 = interrupt masked.
1 = interrupt enabled.
59 of 87
TNF
(LSB)
TMEND
DS21FT40
SYMBOLS
POSITION
RHALF
HIMR.4
RNE
HIMR.3
THALF
HIMR.2
TNF
HIMR.1
TMEND
HIMR.0
NAME AND DESCRIPTION
Receive FIFO Half Full.
0 = interrupt masked.
1 = interrupt enabled.
Receive FIFO Not Empty.
0 = interrupt masked.
1 = interrupt enabled.
Transmit FIFO Half Empty.
0 = interrupt masked.
1 = interrupt enabled.
Transmit FIFO Not Full.
0 = interrupt masked.
1 = interrupt enabled.
Transmit Message End.
0 = interrupt masked.
1 = interrupt enabled.
RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=B3 Hex)
(MSB)
RABT
RCRCE
ROVR
SYMBOLS
RABT
POSITION
RHIR.7
RCRCE
ROVR
RHIR.6
RHIR.5
RVM
RHIR.4
REMPTY
RHIR.3
POK
RHIR.2
CBYTE
RHIR.1
OBYTE
RHIR.0
RVM
REMPTY
POK
CBYTE
(LSB)
OBYTE
NAME AND DESCRIPTION
Abort Sequence Detected. Set whenever the HDLC controller
sees 7 or more ones in a row.
CRC Error. Set when the CRC checksum is in error.
Overrun. Set when the HDLC controller has attempted to
write a byte into an already full receive FIFO.
Valid Message. Set when the HDLC controller has detected
and checked a complete HDLC packet.
Empty. A real–time bit that is set high when the receive FIFO
is empty.
Packet OK. Set when the byte available for reading in the
receive FIFO at RHFR is the last byte of a valid message (and
hence no abort was seen, no overrun occurred, and the CRC
was correct).
Closing Byte. Set when the byte available for reading in the
receive FIFO at RFDL is the last byte of a message (whether
the message was valid or not).
Opening Byte. Set when the byte available for reading in the
receive FIFO at RHFR is the first byte of a message.
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
60 of 87
DS21FT40
RHFR: RECEIVE HDLC FIFO REGISTER (Address=B4 Hex)
(MSB)
HDLC7
HDLC6
HDLC5
SYMBOLS
POSITION
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
RHFR.7
RHFR.6
RHFR.5
RHFR.4
RHFR.3
RHFR.2
RHFR.1
RHFR.0
HDLC4
HDLC3
HDLC2
HDLC1
(LSB)
HDLC0
NAME AND DESCRIPTION
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
THIR: TRANSMIT HDLC INFORMATION REGISTER (Address=B6 Hex)
(MSB)
–
–
–
SYMBOLS
POSITION
–
–
–
–
–
TEMPTY
THIR.7
THIR.6
THIR.5
THIR.4
THIR.3
THIR.2
TFULL
THIR.1
UDR
THIR.0
–
–
EMPTY
TFULL
(LSB)
UDR
NAME AND DESCRIPTION
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Transmit FIFO Empty. A real–time bit that is set high when
the FIFO is empty.
Transmit FIFO Full. A real–time bit that is set high when the
FIFO is full.
Underrun. Set when the transmit FIFO unwantedly empties
out and an abort is automatically sent.
NOTE:
The UDR bit is latched and will be cleared when read.
61 of 87
DS21FT40
THFR: TRANSMIT HDLC FIFO REGISTER (Address=B7 Hex)
(MSB)
HDLC7
HDLC6
HDLC5
SYMBOLS
POSITION
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
THFR.7
THFR.6
THFR.5
THFR.4
THFR.3
THFR.2
THFR.1
THFR.0
HDLC4
HDLC3
HDLC2
HDLC1
(LSB)
HDLC0
NAME AND DESCRIPTION
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address=B8 Hex)
(MSB)
RHS
RSaDS
RDS0M
SYMBOLS
POSITION
RHS
RDC1.7
RSaDS
RDC1.6
RDS0M
RDC1.5
RD4
RD3
RD2
RD1
RD0
RDC1.4
RDC1.3
RDC1.2
RDC1.1
RDC1.0
RD4
RD3
RD2
RD1
(LSB)
RD0
NAME AND DESCRIPTION
Receive HDLC source
0 = Sa bits defined by RCR2.3 to RCR2.7.
1 = Sa bits or DS0 channels defined by RDC1 (see bits defined
below).
Receive Sa Bit / DS0 Select.
0 = route Sa bits to the HDLC controller. RD0 to RD4 defines
which Sa bits are to be routed. RD4 corresponds to Sa4, RD3
to Sa5, RD2 to Sa6, RD1 to Sa7 and RD0 to Sa8.
1 = route DS0 channels into the HDLC controller. RDC1.5 is
used to determine how the DS0 channels are selected.
DS0 Selection Mode.
0 = utilize the RD0 to RD4 bits to select which single DS0
channel to use.
1 = utilize the RCHBLK control registers to select which DS0
channels to use. This option is not applicable for the
DS21FT40.
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
DS0 Channel Select Bit 3.
DS0 Channel Select Bit 2.
DS0 Channel Select Bit 1.
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
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DS21FT40
RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address=B9 Hex)
(MSB)
RDB8
RDB7
RDB6
SYMBOLS
POSITION
RDB8
RDC2.7
RDB7
RDC2.6
RDB6
RDC2.5
RDB5
RDC2.4
RDB4
RDC2.3
RDB3
RDC2.2
RDB2
RDC2.1
RDB1
RDC2.0
RDB5
RDB4
RDB3
RDB2
(LSB)
RDB1
NAME AND DESCRIPTION
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to
stop this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to
stop this bit from being used.
TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = BA Hex)
(MSB)
THE
TSaDS
TDS0M
SYMBOLS
POSITION
THE
TDC1.7
TSaDS
TDC1.6
TDS0M
TDC1.5
TD4
TD3
TD2
TD1
(LSB)
TD0
NAME AND DESCRIPTION
Transmit HDLC Enable.
0 = disable HDLC controller (no data inserted by HDLC
controller into the transmit data stream)
1 = enable HDLC controller to allow insertion of HDLC data
into either the Sa position or multiple DS0 channels as defined
by TDC1 (see bit definitions below).
Transmit Sa Bit / DS0 Select. This bit is ignored if TDC1.7 is
set to zero.
0 = route Sa bits from the HDLC controller. TD0 to TD4
defines which Sa bits are to be routed. TD4 corresponds to
Sa4, TD3 to Sa5, TD2 to Sa6, TD1 to Sa7 and TD0 to Sa8.
1 = route DS0 channels from the HDLC controller. TDC1.5 is
used to determine how the DS0 channels are selected.
DS0 Selection Mode.
Not applicable for the DS21FT40. Should be cleared to zero.
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DS21FT40
SYMBOLS
POSITION
TD4
TD3
TD2
TD1
TD0
TDC1.4
TDC1.3
TDC1.2
TDC1.1
TDC1.0
NAME AND DESCRIPTION
DS0 Channel Select Bit 4. MSB of the DS0 channel select.
DS0 Channel Select Bit 3.
DS0 Channel Select Bit 2.
DS0 Channel Select Bit 1.
DS0 Channel Select Bit 0. LSB of the DS0 channel select.
TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address = BB Hex)
(MSB)
TDB8
TDB7
TDB6
SYMBOLS
POSITION
TDB8
TDC2.7
TDB7
TDC2.6
TDB6
TDC2.5
TDB5
TDC2.4
TDB4
TDC2.3
TDB3
TDC2.2
TDB2
TDC2.1
TDB1
TDC2.0
15.
TDB5
TDB4
TDB3
TDB2
(LSB)
TDB1
NAME AND DESCRIPTION
DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to
stop this bit from being used.
DS0 Bit 7 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 6 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 5 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 4 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 3 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 2 Suppress Enable. Set to one to stop this bit from
being used.
DS0 Bit 1 Suppress Enable. LSB of the DS0. Set to one to
stop this bit from being used.
INTERLEAVED PCM BUS OPERATION
In many architectures, the outputs of individual framers are combined into higher speed serial buses to
simplify transport across the system. The DS21FT40 can be configured to allow each framer’s data and
signaling busses to be multiplexed into higher speed data and signaling busses eliminating external
hardware saving board space and cost. In particular, the four framers associated with each DS21Q44 die
can be combined.
The interleaved PCM bus option supports two bus speeds and interleave modes. The 4.096 MHz bus
speed allows two framers to share a common bus. The 8.192 MHz bus speed allows all four of the
framers for each DS21Q44 die to share a common bus. Framers can interleave their data either on byte or
frame boundaries. Framers that share a common bus must be configured through software and require
several device pins to be connected together externally (see figures 15-1 & 15-2). Each framer’s elastic
stores must be enabled and configured for 2.048 MHz operation. The signal RSYNC must be configured
as an input on each framer.
64 of 87
DS21FT40
For all bus configurations, one framer will be configured as the master device and the remaining framers
on the shared bus will be configured as slave devices. Refer to the IBO register description below for
more detail. In the 4.096 MHz bus configuration there is one master and one slave per bus. Figure 15-1
shows the DS21Q44 configured to support two 4.096 MHz buses. Bus 1 consists of framers 0 and 1. Bus
2 consists of framers 2 and 3. Framers 0 and 2 are programmed as master devices. Framers 1 and 3 are
programmed as slave devices. In the 8.192 MHz bus configuration there is one master and three slaves.
Figure 15-2 shows the DS21Q44 configured to support a 8.192 MHz bus. Framer 0 is programmed as the
master device. Framers 1, 2 and 3 are programmed as slave devices. Consult timing diagrams in section
16 for additional information.
When using the frame interleave mode, all framers that share an interleaved bus must have receive signals
(RPOS & RNEG) that are synchronous with each other. The received signals must originate from the
same clock reference. This restriction does not apply in the byte interleave mode.
IBO: INTERLEAVE BUS OPERATION REGISTER (Address = B5 Hex)
(MSB)
–
–
–
SYMBOLS
POSITION
–
–
–
–
IBOEN
IBO.7
IBO.6
IBO.5
IBO.4
IBO.3
INTSEL
IBO.2
MSEL0
MSEL1
IBO.1
IBO.0
–
IBOEN
INTSEL
MSEL0
(LSB)
MSEL1
NAME AND DESCRIPTION
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Not Assigned. Should be set to 0.
Interleave Bus Operation Enable
0 = Interleave Bus Operation disabled.
1 = Interleave Bus Operation enabled.
Interleave Type Select
0 = Byte interleave.
1 = Frame interleave.
Master Device Bus Select Bit 0 See table 15-1.
Master Device Bus Select Bit 1 See table 15-1.
Master Device Bus Select Table 15-1
MSEL1
MSEL0
0
0
1
1
0
1
0
1
Function
Slave device.
Master device with 1 slave device (4.096 MHz bus rate)
Master device with 3 slave devices (8.192 MHz bus rate)
Reserved
65 of 87
DS21FT40
4.096 MHz Interleaved Bus External Pin Connection Example Figure 15-1
FRAMER 0
FRAMER 1
FRAMER 2
FRAMER 3
RSYSCLK0
RSYSCLK1
RSYSCLK2
RSYSCLK3
TSYSCLK0
TSYSCLK1
TSYSCLK2
TSYSCLK3
RSYNC0
RSYNC1
RSYNC2
RSYNC3
TSSYNC0
TSSYNC1
TSSYNC2
TSSYNC3
RSER0
RSER1
RSER2
RSER3
TSER0
TSER1
TSER2
TSER3
SYSCLK
SYNC INPUT
RSER
TSER
SYSCLK
SYNC INPUT
RSER
TSER
Bus 2
Bus 1
8.192 MHz Interleaved Bus External Pin Connection Example Figure 15-2
FRAMER 0
FRAMER 1
FRAMER 2
FRAMER 3
RSYSCLK0
RSYSCLK1
RSYSCLK2
RSYSCLK3
TSYSCLK0
TSYSCLK1
TSYSCLK2
TSYSCLK3
RSYNC0
RSYNC1
RSYNC2
RSYNC3
TSSYNC0
TSSYNC1
TSSYNC2
TSSYNC3
RSER0
RSER1
RSER2
RSER3
TSER0
TSER1
TSER2
TSER3
SYSCLK
SYNC INPUT
RSER
TSER
66 of 87
DS21FT40
16.
TIMING DIAGRAMS
Receive Side Timing Figure 16-1
14
FRAME#
RSYNC1/
RFSYNC
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
RSYNC2
Notes:
1. RSYNC in the frame mode (RCR1.6 = 0)
2. RSYNC in the multiframe mode (RCR1.6 = 1)
3. This diagram assumes the CAS MF begins with the FAS word
RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) Figure 16-2
RCLK
CHANNEL 1
RPOS, RNEG 1
LSB Si
RSER MSB
CHANNEL 2
1
A Sa4 Sa5 Sa6 Sa7 Sa8 MSB
CHANNEL 32
CHANNEL 1
LSB Si
1
A
Sa4 Sa5 Sa6 Sa7 Sa8 MSB
RSYNC
Notes:
1. There is a 6 RCLK delay from RPOS, RNEG to RSER
2. Shown is a non-align frame boundary
67 of 87
LSB
CHANNEL 2
DS21FT40
RECEIVE SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 16-3
RSYSCLK
RSER
1
CHANNEL 23/31
CHANNEL 24/32
LSB MSB
CHANNEL 1/2
LSB
F
MSB
RSYNC2
3
RSYNC
Notes:
1. Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is
mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one)
2. RSYNC is in the output mode (RCR1.5 = 0)
3. RSYNC is in the input mode (RCR1.5 = 1)
RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 16-4
RSYSCLK
CHANNEL 31
RSER
CHANNEL 32
LSB
CHANNEL 1
LSB
MSB
1
RSYNC
2
RSYNC
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0)
2. RSYNC is in the input mode (RCR1.5 = 1)
68 of 87
MSB
DS21FT40
RECEIVE SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING
Figure 16-5
RSYNC
1
RSER
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
FR1 CH32
FR0 CH1
FR1 CH1
FR0 CH2
FR1 CH2
1
RSIG
2
RSER
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
SYSCLK
3
RSYNC
FRAMER 3, CHANNEL 32
RSER
FRAMER 1, CHANNEL 1
FRAMER 0, CHANNEL 1
LSB
LSB
MSB
LSB
MSB
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 1).
RECEIVE SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 16-6
RSYNC
1
RSER
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
2
RSER
FR2 CH1-32 FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
BIT DETAIL
SYSCLK
3
RSYNC
FRAMER 3, CHANNEL 32
RSER
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 1
MSB
LSB
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
3. RSYNC is in the input mode (RCR1.5 = 1).
69 of 87
MSB
LSB
DS21FT40
TRANSMIT SIDE TIMING Figure 16-7
TRANSMIT SIDE TIMING Figure 13.5
14
FRAME#
15 16
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
1
2
3
4
5
6
1
TSYNC
2
TSYNC
Notes:
1. TSYNC in the frame mode (TCR1.1 = 0)
2. TSYNC in the multiframe mode (TCR1.1 = 1)
3. This diagram assumes both the CAS MF and the CRC4 begin with the align frame
TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled)
Figure 16-8
TCLK
CHANNEL 1
TSER
LSB
Si
1
A
Sa4
Sa5
CHANNEL 2
Sa6
Sa7
Sa8
CHANNEL 32
1
TPOS, TNEG
MSB
MSB
LSB
CHANNEL 1
LSB
Si
1
A
Sa4
Sa5
2
TSYNC
TSYNC3
Notes:
1. There is a 5 TCLK delay from TSER to TPOS and TNEG
2. TSYNC is in the input mode (TCR1.0 = 0)
3. TSYNC is in the output mode (TCR1.0 = 1)
4. Shown is a non-align frame boundary
70 of 87
Sa6
Sa7
Sa8
MSB
MSB
DS21FT40
TRANSMIT SIDE 1.544 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 16-9
TSYSCLK
CHANNEL 23
TSER
CHANNEL 1
CHANNEL 24
LSB
LSB
MSB
MSB
F-Bit
TSSYNC
Notes:
1. The F-bit position is ignored by the DS21FT40
TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled)
Figure 16-10
TSYSCLK
CHANNEL 31
TSER
CHANNEL 32
LSB
CHANNEL 1
LSB
MSB
TSSYNC
71 of 87
MSB
DS21FT40
TRANSMIT SIDE INTERLEAVED BUS OPERATION BYTE MODE TIMING
Figure 16-11
TSSYNC
1
TSER
FR1 CH32
FR1 CH1
FR0 CH1
FR1 CH2
FR0 CH2
2
TSER
FR2 CH32
FR3 CH32
FR0 CH1
FR1 CH1
FR2 CH1
FR3 CH1
FR0 CH2
FR1 CH2
FR2 CH2
FR3 CH2
BIT DETAIL
SYSCLK
TSSYNC
FRAMER 3, CHANNEL 32
TSER
FRAMER 1, CHANNEL 1
FRAMER 0, CHANNEL 1
LSB
LSB
MSB
MSB
LSB
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
TRANSMIT SIDE INTERLEAVED BUS OPERATION FRAME MODE TIMING
Figure 16-12
TSSYNC
1
TSER
FR0 CH1-32
FR1 CH1-32
FR1 CH1-32
FR0 CH1-32
FR1 CH1-32
2
TSER
FR2 CH1-32 FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
FR0 CH1-32
FR1 CH1-32
FR2 CH1-32
FR3 CH1-32
BIT DETAIL
SYSCLK
TSSYNC
FRAMER 3, CHANNEL 32
TSER
LSB
FRAMER 0, CHANNEL 2
FRAMER 0, CHANNEL 1
MSB
LSB
Notes:
1. 4.096 MHz bus configuration.
2. 8.192 MHz bus configuration.
72 of 87
MSB
LSB
DS21FT40
DS21FT40 FRAMER SYNCHRONIZATION FLOWCHART Figure 16-13
Power Up
RLOS = 1
FAS Search
FASSA = 1
RLOS = 1
FAS Sync
Criteria Met
FASSA = 0
Resync if
RCR1.0 = 0
Increment CRC4
Sync Counter;
CRC4SA = 0
8ms
Time
Out
CRC4 Multiframe Search
(if enabled via CCR1.0)
CRC4SA = 1
CRC4 Sync Criteria
Met; CRC4SA = 0;
Reset CRC4
Sync Counter
Set FASRC
(RIR.1)
CRC4 Resync
Criteria Met
(RIR.2)
CAS Resync
Criteria Met;
Set CASRC
(RIR.0)
FAS Resync
Criteria Met
Check for FAS
Framing Error
(depends on RCR1.2)
Check for >=915
Out of 1000
CRC4 Word Errors
If CRC4 is on
(CCR1.0 = 1)
Check for CAS
MF Word Error
If CAS is on
(CCR1.3 = 0)
73 of 87
CAS Multiframe Search
(if enabled via CCR1.3)
CASSA = 1
Sync Declared
RLOS = 0
CAS Sync
Criteria Met
CASSA = 0
DS21FT40
DS21FT40 TRANSMIT DATA FLOW Figure 16-14
T SER
&
TD ATA
HDLC
EN GIN E
TSIG
R SER
(note #1)
TLINK
0
1
Hardware
Signaling
Insertion (CCR3.2)
TNAF.0-4
0
0
1
Sa Data Source
MUX
(TDC1)
1
DS0 Data
Source MUX
(TDC1/2)
TAF
TNAF.5-7
0
TC1 to TC32
1
0
1
Per-Channel Code
Generation
(TCC1/2/3/4)
TAF/TNAF Bit
MUX
0
1
Timeslot 0
Pass-Through
(TCR1.6)
1
0
Si Bit Insertion
Control
(TCR1.3)
Receive Side
CRC4 Error
Detector
CRC4 Multiframe
Alignment Word
Generation (CCR.4)
0
1
E-Bit Generation
(TCR2.1)
0
1
Sa Bit Insertion
Control (TCR2.3
thru TCR2.7)
TSiAF
TSiNAF
TIDR
TRA
0
TSa4 to TSa8
Auto Remote Alarm
Generation (CCR2.4)
1
TIR Function Select
(CCR3.5)
0
1
Sa Bit Insertion
Control Register
(TSaCR)
TS1 to TS16
0
1
Idle Code / Channel
Insertion Control via
TIR1/2/3/4
AIS
Generation
0
1
Transmit Signaling
All Ones
(TCR1.2)
T CBR1/2/3/4
0
1
Signaling Bit
Insertion Control
CCR3.6
TCR1.5
Code Word
Generation
0
1
CRC4 Enable
(CCR1.4)
KEY:
= Register
AIS
Generation
DS0 Monitor
= Device Pin
0
1
Transmit Unframed All
Ones (TCR1.4) or
Auto AIS (CCR2.5)
= Selector
NOTES:
1. TCLK should be tied to RCLK and TSYNC should be tied to RFSYNC for
data to be properly sourced from RSER.
2. Auto Remote Alarm if enabled will only overwrite bit 3 of timeslot 0 in the
Not Align Frames if the alarm needs to be sent.
74 of 87
TPOS,
TNEG
DS21FT40
17.
OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Non-Supply Pin Relative to Ground
Supply Voltage
Operating Temperature for DS21FT40
Operating Temperature for DS21FT40N
Storage Temperature
Soldering Temperature
–1.0V to +5.5V
–.3V to +3.63V
0ºC to 70ºC
–40ºC to +85ºC
–55ºC to +125ºC
See J-STD-020A
* This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(0ºC to 70ºC for DS21FT40;
0ºC to +85ºC for DS21FT40N)
PARAMETER
Logic 1
Logic 0
Supply
SYMBOL
VIH
VIL
VDD
MIN
2.0
–0.3
2.97
TYP
MAX
5.5
+0.8
3.63
UNITS
V
V
V
(tA =25ºC)
CAPACITANCE
PARAMETER
Input Capacitance
Output Capacitance
NOTES
SYMBOL
CIN
COUT
MIN
TYP
5
7
MAX
UNITS
pF
pF
NOTES
DC CHARACTERISTICS
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21FT40;
-40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21Q44N)
PARAMETER
Supply Current @ 3.3V
Input Leakage
Output Leakage
Output Current (2.4V)
Output Current (0.4V)
SYMBOL
IDD
IIL
ILO
IOH
IOL
MIN
TYP
75
–1.0
MAX
+1.0
1.0
–1.0
+4.0
NOTES:
1. TCLK=RCLK=TSYSCLK=RSYSCLK=2.048 MHz; outputs open circuited.
2. 0.0V < V IN < V DD .
3. Applied to INT* when 3–stated.
75 of 87
UNITS
mA
µA
µA
mA
mA
NOTES
1
2
3
DS21FT40
AC CHARACTERISTICS – MULTIPLEXED
PARALLEL PORT (MUX=1)
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21FT40
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21FT40N)
PARAMETER
Cycle Time
Pulse Width, DS low or
RD* high
Pulse Width, DS high or
RD* low
Input Rise/Fall times
R/W* Hold Time
R/W* Set Up time
before DS high
CS1*, CS2*, CS3*,
FSO or FS1 Set Up time
before DS, WR* or
RD* active
CS1*, CS2*, CS3*,
FSO or FS1 Hold time
Read Data Hold time
Write Data Hold time
Muxed Address valid to
AS or ALE fall
Muxed Address Hold
time
Delay time DS, WR* or
RD* to AS or ALE rise
Pulse Width AS or ALE
high
Delay time, AS or ALE
to DS, WR* or RD*
Output Data Delay time
from DS or RD*
Data Set Up time
SYMBOL
t CYC
PW EL
MIN
200
100
PW EH
100
TYP
MAX
UNITS
ns
ns
ns
tR,tF
t RWH
t RWS
20
10
50
ns
ns
ns
t CS
20
ns
t CH
0
ns
t DHR
t DHW
t ASL
10
0
15
t AHL
10
ns
t ASD
20
ns
PW ASH
30
ns
t ASED
10
ns
t DDR
20
t DSW
50
50
80
ns
ns
ns
ns
ns
(see Figures 17-1 to 17-3 for details)
76 of 87
NOTES
DS21FT40
AC CHARACTERISTICS – NON–MULTIPLEXED
PARALLEL PORT (MUX=0 )
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21FT40;
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21FT40N)
PARAMETER
Set Up Time for A0 to
A7, FS0 or FS1 Valid to
CS1*, CS2*, CS3*
Active
Set Up Time for CS1*,
CS2*, CS3* Active to
either RD*, WR*, or
DS* Active
Delay Time from either
RD* or DS* Active to
Data Valid
Hold Time from either
RD*, WR*, or DS*
Inactive to CS1*, CS2*,
CS3* Inactive
Hold Time from CS1*,
CS2*, CS3* Inactive to
Data Bus 3–state
Wait Time from either
WR* or DS* Active to
Latch Data
Data Set Up Time to
either WR* or DS*
Inactive
Data Hold Time from
either WR* or DS*
Inactive
Address Hold from
either WR* or DS*
inactive
SYMBOL
t1
MIN
0
t2
0
TYP
MAX
UNITS
ns
ns
t3
75
ns
t4
0
ns
t5
5
t6
75
ns
t7
10
ns
t8
10
ns
t9
10
ns
20
See Figures 17–4 to 17-7 for details.
77 of 87
ns
NOTES
DS21FT40
AC CHARACTERISTICS – RECEIVE SIDE
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21FT40;
–40ºC to +85ºC; VDD = 2.97 to 3.63V for DS21FT40N)
PARAMETER
RCLK Period
RCLK Pulse Width
RSYSCLK Period
RSYSCLK Pulse Width
RSYNC Set Up to
RSYSCLK Falling
RSYNC Pulse Width
RPOS/RNEG Set UP to
RCLK Falling
RPOS/RNEG Hold From
RCLK Falling
RSYSCLK/RCLKI Rise
and Fall Times
Delay RCLK to RSER
Valid
Delay RCLK to RSYNC
Delay RSYSCLK to RSER
Valid
Delay RSYSCLK to
RMSYNC, RSYNC
SYMBOL
t CP
t CH
t CL
t SP
t SP
t SH t SL
MIN
TYP
488
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
t SU
75
75
122
122
50
50
20
t PW
t SU
50
20
ns
ns
t HD
20
ns
648
488
t SH –5
tR,tF
25
ns
t D1
50
ns
t D2
t D3
50
50
ns
ns
t D4
50
ns
See Figures 17-8 to 17-10 for details.
NOTES:
1. RSYSCLK = 1.544 MHz.
2. RSYSCLK = 2.048 MHz.
78 of 87
NOTES
1
2
DS21FT40
AC CHARACTERISTICS – TRANSMIT SIDE
(0ºC to 70ºC; VDD = 2.97 to 3.63V for DS21FT40;
–40ºC to +85ºC; ; VDD = 2.97 to 3.63V for DS21FT40N)
PARAMETER
TCLK Period
TCLK Pulse Width
TCLKI Pulse Width
TSYSCLK Period
TSYSCLK Pulse Width
TSYNC or TSSYNC Set
Up to TCLK or TSYSCLK
falling
TSYNC or TSSYNC Pulse
Width
TSER Set Up to TCLK,
TSYSCLK Falling
TSER Hold from TCLK,
TSYSCLK Falling
TCLK or TSYSCLK Rise
and Fall Times
Delay TCLK to TPOS,
TNEG Valid
Delay TCLK to TSYNC
SYMBOL
t CP
t CH
t CL
t LH
t LL
t SP
t SP
t SH
t SL
t SU
MIN
t PW
50
ns
t SU
20
ns
t HD
20
ns
75
75
75
75
122
122
50
50
20
TYP
488
MAX
648
448
t CH –5
or
t SH –5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tR,tF
25
ns
t DD
50
ns
t D2
50
ns
See Figures 17–11 to 17–13 for details.
NOTES:
1. TSYSCLK = 1.544 MHz.
2. TSYSCLK = 2.048 MHz.
79 of 87
NOTES
1
2
DS21FT40
INTEL BUS READ AC TIMING (BTS=0 / MUX = 1) Figure 17-1
t CYC
ALE
PWASH
t ASD
WR*
t ASD
RD*
PW EL
t ASED
PWEH
t CH
t CS
CS*
t ASL
t DHR
t DDR
AD0-AD7
t AHL
INTEL BUS WRITE TIMING (BTS=0 / MUX=1) Figure 17-2
t CYC
ALE
PW ASH
t ASD
RD*
t ASD
WR*
PW EL
t ASED
PWEH
t CH
t CS
CS*
t ASL
t DHW
AD0-AD7
t AHL
t DSW
80 of 87
DS21FT40
MOTOROLA BUS AC TIMING (BTS = 1 / MUX = 1) Figure 17-3
PWASH
AS
t ASD
DS
PW EH
t ASED
PW EL
t CYC
t RWS
t RWH
R/W*
t DDR
t ASL
AD0-AD7
(read)
t AHL
t DHR
t CH
t CS
CS*
t DSW
t ASL
AD0-AD7
(write)
t DHW
t AHL
INTEL BUS READ AC TIMING (BTS=0 / MUX=0) Figure 17-4
A0 to A7
Address Valid
Data Valid
D0 to D7
5ns min. / 20ns max.
WR*
t5
t1
0ns min.
CS*
0ns min.
t2
t3
t4
75ns max.
RD*
81 of 87
0ns min.
DS21FT40
INTEL BUS WRITE AC TIMING (BTS=0 / MUX=0) Figure 17-5
A0 to A7
Address Valid
D0 to D7
t7
RD*
t8
10ns 10ns
min. min.
t1
0ns min.
CS*
0ns min.
t2
t6
t4
0ns min.
75ns min.
WR*
MOTOROLA BUS READ AC TIMING (BTS=1 / MUX=0) Figure 17-6
MOTOROLA BUS READ AC TIMING (BTS = 1 / MUX = 0) Figure 16.12
A0 to A7
Address Valid
Data Valid
D0 to D7
5ns min. / 20ns max.
R/W*
t5
t1
0ns min.
CS*
0ns min.
t2
t3
t4
75ns max.
DS
82 of 87
0ns min.
DS21FT40
MOTOROLA BUS WRITE AC TIMING (BTS=1 / MUX=0) Figure 17-7
A0 to A7
Address Valid
D0 to D7
10ns
min.
R/W*
t1
CS*
0ns min.
t2
t6
t4
75ns min.
RECEIVE SIDE AC TIMING Figure 17-8
RCLK
tD 1
MSB of
Channel 1
R S E R
D2
RMSYNC
t
t8
10ns
min.
0ns min.
DS*
t
t7
D2
1
R S Y N C
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0).
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0ns min.
DS21FT40
RECEIVE SYSTEM SIDE AC TIMING Figure 17-9
t
tR
t SL
t SH
F
RSYSCLK
t SP
tD 3
R S E R
/
MSB of
Channel 1
RS I G
t
D4
RMSYNC
t
D4
1
R S Y NC
tH D
tS U
2
R S Y NC
Notes:
1. RSYNC is in the output mode (RCR1.5 = 0)
2. RSYNC is in the input mode (RCR1.5 = 1)
RECEIVE LINE INTERFACE AC TIMING Figure 17-10
tC L
tR
t
tC H
F
R C L K
tC P
tS U
R P O S ,
R N E G
tH D
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DS21FT40
TRANSMIT SIDE AC TIMING Figure 17-11
t
t
tR
CP
tC H
tC L
F
TCLK
t SU
TSER
tH D
tD 2
1
TSYNC
tH D
tS U
2
TSYNC
Notes:
1. TSYNC is in the output mode (TCR1.0 = 1).
2. TSYNC is in the input mode (TCR1.0 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
TRANSMIT SYSTEM SIDE AC TIMING Figure 17-12
tS P
tR
t
tS H
tS L
F
TSYSCLK
tS U
TSER
tS U
tH D
TSSYNC
Notes:
1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
TRANSMIT LINE INTERFACE SIDE AC TIMING Figure 17-13
t CP
t CL
tR
tF
TCLK
TPOS, TNEG
t DD
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t CH
DS21FT40
18.
DS21FT40 MECHANICAL DIMENSIONS
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DS21FT40
POWER SUPPLY DE-COUPLING
In a typical PCB layout for the MCM, all of the VDD pins will connect to a common power plane and all
the VSS lines will connect to a common ground plane. The recommended method for de-coupling is
shown below in both schematic and pictorial form. As shown in the pictorial, the capacitors should be
symmetrically located about the device. Figure 18-1 uses standard capacitors, two .47 uf ceramics and
two .01uf ceramics. Since VDD and VSS signals will typically pass vertically to the power and ground
planes of a PCB, the de-coupling caps must be placed as close to the DS21FT40 as possible and routed
vertically to power and ground planes.
De-coupling scheme using standard tantalum caps. Figure 18-1
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