TI1 INA203AID Unidirectional measurement current-shunt monitor with dual comparator Datasheet

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INA203, INA204, INA205
SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
INA20x Unidirectional Measurement Current-Shunt Monitor With Dual Comparators
1 Features
3 Description
•
•
The INA203, INA204, and INA205 are a family of
unidirectional current-shunt monitors with voltage
output, dual comparators, and voltage reference. The
INA203, INA204, and INA205 can sense drops
across shunts at common-mode voltages from –16 V
to 80 V. The INA203, INA204, and INA205 are
available with three output voltage scales: 20 V/V, 50
V/V, and 100 V/V, with up to 500-kHz bandwidth.
1
•
•
•
•
•
•
Complete Current Sense Solution
Three Gain Options Available:
– INA203 = 20 V/V
– INA204 = 50 V/V
– INA205 = 100 V/V
Dual Comparators:
– Comparator 1 With Latch
– Comparator 2 With Optional Delay
Common-Mode Range: –16 V to 80 V
High Accuracy: 3.5% (Maximum) Over
Temperature
Bandwidth: 500 kHz
Quiescent Current: 1.8 mA
Packages: SO-14, TSSOP-14, VSSOP-10
The INA203, INA204, and INA205 also incorporate
two open-drain comparators with internal 0.6-V
references. On 14-pin versions, the comparator
references can be overridden by external inputs.
Comparator 1 includes a latching capability, and
Comparator 2 has a user-programmable delay. 14-pin
versions also provide a 1.2-V reference output.
The INA203, INA204, and INA205 operate from a
single 2.7-V to 18-V supply. They are specified over
the extended operating temperature range of –40°C
to 125°C.
2 Applications
•
•
•
•
•
•
•
Notebook Computers
Cell Phones
Telecom Equipment
Automotive
Power Management
Battery Chargers
Welding Equipment
SPACE
Device Information
PART NUMBER
INA203,
INA204,
INA205
PACKAGE
(1)
BODY SIZE (NOM)
SOIC (14)
8.65 mm × 3.91 mm
VSSOP (10)
3.00 mm × 3.00 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Simplified Schematic
VS
1
OUT
2
14 VIN+
13 VIN1.2V REF
CMP1 IN-/0.6V REF
3
12 1.2V REF OUT
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
INA203, INA204, INA205
SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison ...............................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: Current-Shunt Monitor ..... 6
Electrical Characteristics: Comparator...................... 7
Electrical Characteristics: Reference ........................ 9
Electrical Characteristics: General ............................ 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagrams ..................................... 14
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application ................................................. 22
10 Power Supply Recommendations ..................... 24
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
12.5
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2009) to Revision E
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Moved thermal values from Electrical Characteristics: General to Thermal Information table. Removed duplicate
storage temperature parameter. ............................................................................................................................................. 9
Changes from Revision C (October 2007) to Revision D
•
2
Page
Changed Figure 1................................................................................................................................................................... 8
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SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
5 Device Comparison
Table 1. Device Gain
DEVICE
GAIN
INA203
20 V/V
INA204
50 V/V
INA205
100 V/V
Table 2. Related Products
FEATURES
PRODUCT
Variant of INA203–INA205 Comparator 2 polarity
INA206–INA208
Current-shunt monitor with single Comparator and VREF
INA200–INA202
Current-shunt monitor only
INA193–INA198
Current-shunt monitor with split stages for filter options
INA270–INA271
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6 Pin Configuration and Functions
D and PW Packages
14-Pin SOIC and TSSOP
Top View
DGS Package
10-Pin VSSOP
Top View
VS
1
14 VIN+
OUT
2
13 VIN-
CMP1 IN-/0.6V REF
3
12 1.2V REF OUT
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
VS
1
10 VIN+
OUT
2
9
VIN-
CMP1 IN+
3
8
CMP1 OUT
CMP2 IN+
4
7
CMP2 OUT
GND
5
6
CMP1 RESET
1.2V REF
0.6V REF
Pin Functions
PIN
I/O
DESCRIPTION
SOIC,
TSSOP
VSSOP
Vs
1
1
I
Power Supply
OUT
2
2
O
Output voltage
CMP1 IN-/0.6
V Ref
3
—
I
Comparator 1 negative input, can be used to override the internal 0.6-V
reference
CMP1 IN+
4
3
I
Comparator 1 positive input
CMP2 IN+
5
—
I
Comparator 2 positive input
CMP2 IN–
—
4
I
Comparator 2 negative input
CMP2 IN–/0.6V Ref
6
—
I
Comparator 2 negative input, can be used to override the internal 0.6-V
reference
GND
7
5
I
Ground
CMP1 RESET
8
6
I
Comparator 1 ouput reset, active low
CMP2 DELAY
9
—
I
Connect an optional capacitor to adjust comparator 2 delay
CMP2 OUT
10
7
O
Comparator 2 output
CMP1 OUT
11
8
O
Comparator 1 output
1.2-V REF
OUT
12
—
O
1.2-V reference output
VIN-
13
9
I
Connect to shunt low side
VIN+
14
10
I
Connect to shunt high side
NAME
4
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SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
(1)
See
MIN
Supply Voltage, Vs
MAX
UNIT
18
V
Differential (VIN+) – (VIN–)
–18
18
V
Common-Mode
–16
80
V
Comparator Analog Input and Reset Pins
GND – 0.3
(Vs) + 0.3
V
Analog Output, Out Pin
GND – 0.3
(Vs) + 0.3
V
Comparator Output, Out Pin
GND – 0.3
18
V
VREF and CMP2 Delay Pin
GND – 0.3
10
V
5
mA
Operating Temperature
–55
150
°C
Junction Temperature
–65
150
°C
Storage temperature, Tstg
–65
150
°C
Current-Shunt Monitor Analog
Inputs, VIN+ and VIN–
Input Current Into Any Pin
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
–16
12
80
Vs Operating supply voltage
2.7
12
18
V
TA Operating free-air temperature
–40
25
125
ºC
Vcm Common-mode input voltage
UNIT
V
7.4 Thermal Information
INA20x
THERMAL METRIC
(1)
D (SOIC)
DGS (VSSOP)
PW (TSSOP)
UNIT
14 PINS
10 PINS
14 PINS
84.9
161.3
112.6
°C/W
44
36.8
37.2
°C/W
82.3
55.4
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
39.4
ψJT
Junction-to-top characterization parameter
10.3
1.3
2.7
°C/W
ψJB
Junction-to-board characterization parameter
39.1
80.8
54.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
150
200
150
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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7.5 Electrical Characteristics: Current-Shunt Monitor
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each connected from CMP1 OUT
and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN– = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.15
(VS –
0.25)/Gain
V
80
V
INPUT
Full-Scale Sense Input
Voltage
VSENSE
Common-Mode Input
Range
VCM
VSENSE = VIN+ – VIN–
TA = –40°C to
125°C
Common-Mode Rejection
CMRR
Ratio
VCM = –16 V to 80 V
Over Temperature
VCM = 12 V to 80 V
Offset Voltage, RTI
(1)
TA = –40°C to
125°C
–16
80
100
dB
100
123
dB
±2.5
mV
25°C to 125°C
VOS
±0.5
±3
mV
–40°C to 25°C
±3.5
mV
vs Temperature
dVOS/dT
TMIN to TMAX
TA = –40°C to
125°C
5
vs Power Supply
PSR
VOUT = 2 V,
VCM = 18 V, 2.7 V
TA = –40°C to
125°C
2.5
100
μV/V
TA = –40°C to
125°C
±9
±16
μA
Input Bias Current,
VIN– Pin
IB
μV/°C
OUTPUT (VSENSE ≥ 20 mV)
Gain:
G
INA203
20
V/V
INA204
50
V/V
INA205
100
V/V
Gain
Error
VSENSE = 20 mV to 100 mV
VSENSE = 20 mV to
100 mV
Over Temperature
Total Output Error
TA = –40°C to
125°C
VSENSE = 120 mV,
VS = 16 V
(3)
±0.75%
TA = –40°C to
125°C
±0.002%
RO
Maximum Capacitive Load
OUTPUT (VSENSE < 20 mV)
±2.2%
±3.5%
VSENSE = 20 mV to 100 mV
Output Impedance, Pin 2
±1%
±2%
VSENSE = 120 mV,
VS = 16 V
(2)
Over Temperature
Nonlinearity Error
±0.2%
No Sustained Oscillation
1.5
Ω
10
nF
300
mV
(4)
INA203, INA204, INA205
–16 V ≤ VCM < 0 V
INA203
0 V ≤ VCM ≤ VS, VS = 5 V
0.4
V
INA204
0 V ≤ VCM ≤ VS, VS = 5 V
1
V
INA205
0 V ≤ VCM ≤ VS, VS = 5 V
2
INA203, INA204, INA205
VS < VCM ≤ 80 V
VOLTAGE OUTPUT
Output Swing to GND
(5)
(6)
6
V
mV
(5)
Output Swing to the Positive Rail
(1)
(2)
(3)
(4)
300
(6)
VIN– = 11 V,
VIN+ = 12 V
TA = –40°C to
125°C
(Vs) – 0.15
(Vs) – 0.25
V
VIN– = 0 V,
VIN+ = –0.5 V
TA = –40°C to
125°C
(VGND) + 0.004
(VGND) + 0.05
V
Offset is extrapolated from measurements of the output at 20 mV and 100 mV VSENSE.
Total output error includes effects of gain error and VOS.
Linearity is best fit to a straight line.
For details on this region of operation, see the Accuracy Variations as a Result Of VSENSE and Common-Mode Voltage section in the
Application and Implementation.
See Typical Characteristic curve Positive Output Voltage Swing vs Output Current (Figure 8).
Specified by design; not production tested.
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Electrical Characteristics: Current-Shunt Monitor (continued)
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each connected from CMP1 OUT
and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN– = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
Bandwidth:
BW
INA203
CLOAD = 5 pF
500
kHz
INA204
CLOAD = 5 pF
300
kHz
INA205
CLOAD = 5 pF
200
kHz
CLOAD < 10 nF
40
Phase Margin
Slew Rate
SR
VSENSE = 10 mVPP to 100 mVPP,
CLOAD = 5 pF
Settling Time (1%)
1
V/μs
2
μs
40
nV/√Hz
NOISE, RTI
Output Voltage Noise Density
7.6 Electrical Characteristics: Comparator
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Comparator Common-Mode Voltage = Threshold
Voltage
Offset Voltage
2
mV
Offset Voltage Drift,
Comparator 1
TA = –40°C to 125°C
±2
μV/°C
Offset Voltage Drift,
Comparator 2
TA = –40°C to 125°C
5.4
μV/°C
Threshold
TA = 25°C
Over Temperature
Hysteresis
(1)
Hysteresis
(1)
, CMP1
, CMP2
INPUT BIAS CURRENT
590
TA = –40°C to 125°C
608
586
620
mV
625
mV
TA = –40°C to 85°C
–8
mV
TA = –40°C to 85°C
8
mV
(2)
CMP1 IN+, CMP2 IN+
0.005
vs Temperature
TA = –40°C to 125°C
10
nA
15
nA
INPUT IMPEDANCE
Pins 3 and 6 (14-pin packages
only)
10
kΩ
INPUT RANGE
CMP1 IN+ and CMP2 IN+
0 V to VS – 1.5 V
V
Pins 3 and 6 (14-pin packages
only) (3)
0 V to VS – 1.5 V
V
OUTPUT
Large-Signal Differential Voltage
Gain
CMP VOUT 1 V to 4 V, RL ≥ 15 kΩ Connected to
5V
High-Level Output Current
VID = 0.4 V, VOH = VS
Low-Level Output Voltage
VID = –0.6 V, IOL = 2.35 mA
RESPONSE TIME
(1)
(2)
(3)
(4)
200
V/mV
0.0001
1
μA
220
300
mV
(4)
Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the
noninverting input of the comparator; refer to Figure 1.
Specified by design; not production tested.
See the Comparator Maximum Input Voltage Range section in the Application and Implementation.
The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
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Electrical Characteristics: Comparator (continued)
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Comparator 1
RL to 5 V, CL = 15 pF, 100-mV Input Step with
5-mV Overdrive
1.3
μs
Comparator 2
RL to 5 V, CL = 15 pF, 100-mV Input Step with
5-mV Overdrive, CDELAY Pin Open
1.3
μs
RESET
RESET Threshold
(5)
1.1
Logic Input Impedance
Minimum RESET Pulse Width
Comparator 2 Delay
(5)
(6)
(6)
1.5
μs
3
μs
μF
CDELAY = 0.1 μF
tD
MΩ
CDELAY = tD/5
RESET Propagation Delay
Comparator 2 Delay Equation
V
2
0.5
s
The CMP1 RESET input has an internal 2-MΩ (typical) pulldown. Leaving the CMP1 RESET open results in a LOW state, with
transparent comparator operation.
The Comparator 2 delay applies to both rising and falling edges of the comparator output.
VTHRESHOLD
0.592
VTHRESHOLD
0.6
0.6
0.608
Input Voltage
Input Voltage
Hysteresis = VTHRESHOLD - 8mV
Hysteresis = VTHRESHOLD - 8mV
a) CMP1
b) CMP2
Figure 1. Comparator Hysteresis
8
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7.7 Electrical Characteristics: Reference
At TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, and Rpullup = 5.1 kΩ each connected from CMP1
OUT and CMP2 OUT to VS, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
1.188
1.2
1.212
V
REFERENCE VOLTAGE
1.2-VREFOUT Output Voltage
Reference Drift
dVOUT/dT
TA = –40°C to 85°C
40
0.6-VREF Output Voltage (Pins 3 and 6 of 14pin packages only)
Reference Drift
0.6
dVOUT/dT
LOAD REGULATION
100 ppm/°C
v
TA = –40°C to 85°C
40
100 ppm/°C
0mA < ISOURCE < 0.5mA
0.4
2 mV/mA
0mA < ISINK < 0.5mA
0.4
mV/mA
dVOUT/dILOAD
Sourcing
Sinking
Load Current
ILOAD
Line Regulation
dVOUT/dVS
1
mA
2.7 V < VS < 18 V
30
μV/V
No Sustained Oscillations
10
nF
10
kΩ
CAPACITIVE LOAD
Reference Output Maximum Capacitive Load
OUTPUT IMPEDANCE
Pins 3 and 6 of 14-Pin Packages Only
7.8 Electrical Characteristics: General
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, VSENSE = 100 mV, RL = 10 kΩ to GND, Rpullup = 5.1 kΩ each connected
from CMP1 OUT and CMP2 OUT to VS, and CMP1 IN+ = 1 V and CMP2 IN– = GND, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Operating power supply
VS
Quiescent current
IQ
TA = –40°C to 125°C
VOUT = 2 V
Over temperature
Comparator power-on reset threshold
2.7
1.8
VSENSE = 0 mV
(1)
18
V
2.2
mA
2.8
mA
1.5
V
TEMPERATURE
Specified temperature
–40
125
°C
Operating temperature
–55
150
°C
(1)
The INA203, INA204, and INA205 are designed to power-up with the comparator in a defined reset state as long as CMP1 RESET is
open or grounded. The comparator will be in reset as long as the power supply is below the voltage shown here. The comparator
assumes a state based on the comparator input above this supply voltage. If CMP1 RESET is high at power-up, the comparator output
comes up high and requires a reset to assume a low state, if appropriate.
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7.9 Typical Characteristics
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, and VSENSE = 100 mV, unless otherwise noted.
45
40
G = 50
35
Gain (dB)
30
G = 100
40
G = 50
35
Gain (dB)
45
CLOAD = 1000pF
G = 100
G = 20
25
20
30
20
15
15
10
10
5
G = 20
25
5
10k
100k
10k
1M
100k
Frequency (Hz)
Figure 2. Gain vs Frequency
Figure 3. Gain vs Frequency
20
140
18
130
Common-Mode and
Power-Supply Rejection (dB)
100V/V
16
VOUT (V)
14
50V/V
12
10
8
20V/V
6
4
120
CMR
110
100
90
PSR
80
70
60
50
2
40
0
20
100
200
300
400
500
600
700
800
900
10
100
1k
VDIFFERENTIAL (mV)
100k
Figure 5. Common-Mode and Power-Supply Rejection vs
Frequency
4.0
0.1
3.5
0.09
0.08
3.0
Output Error (% )
Output Error
(% error of the ideal output value)
10k
Frequency (Hz)
Figure 4. Gain Plot
2.5
2.0
1.5
1.0
0.07
0.06
0.05
0.04
0.03
0.02
0.5
0.01
0
0
50
100 150
200
250 300
350 400 450 500
0
-16 -12 -8 -4
VSENSE (mV)
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0
4
8
12 16 20
...
76 80
Common-Mode Voltage (V)
Figure 6. Total Output Error vs VSENSE
10
1M
Frequency (Hz)
Figure 7. Total Output Error vs Common-Mode Voltage
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Typical Characteristics (continued)
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, and VSENSE = 100 mV, unless otherwise noted.
3.5
12
11
VS = 12V
10
9
2.5
+25°C
8
-40°C
+125°C
7
6
VS = 3V
5
Sourcing Current
+25°C
4
-40°C
Output stage is designed
to source current. Current
sinking capability is
approximately 400mA.
3
2
1
+125°C
0
0
IQ (mA)
Output Voltage (V)
3.0
Sourcing Current
2.0
1.5
1.0
0.5
0
5
10
20
15
25
30
0
1
2
3
4
5
7
6
8
9
10
Output Current (mA)
Output Voltage (V)
Figure 8. Positive Output Voltage Swing vs Output Current
Figure 9. Quiescent Current vs Output Voltage
34
VSENSE = 100mV
1.75
Output Short-Circuit Current (mA)
2.00
VS = 2.7V
VS = 12V
IQ (mA)
1.50
1.25
VS = 12V
1.00
VS = 2.7V
VSENSE = 0mV
0.75
0.50
-16 -12 -8 -4
-40°C
30
+25°C
26
+125°C
22
18
14
10
6
0
4
8
12 16 20 24 28 32 36
2.5 3.5
4.5
VCM (V)
5.5 6.5
7.5
8.5
9.5 10.5 11.5 17
18
Supply Voltage (V)
Figure 10. Quiescent Current vs Common-Mode Voltage
Figure 11. Output Short-Circuit Current vs Supply Voltage
G = 20
Output Voltage (50mV/div)
Output Voltage (500mV/div)
G = 20
VSENSE = 20mV to 30mV
VSENSE = 20mV to 110mV
Time (2ms/div)
Time (2ms/div)
Figure 12. Step Response
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Typical Characteristics (continued)
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, and VSENSE = 100 mV, unless otherwise noted.
G = 50
Output Voltage (50mV/div)
Output Voltage (100mV/div)
G = 20
VSENSE = 90mV to 100mV
VSENSE = 20mV to 30mV
Time (2ms/div)
Time (5ms/div)
Figure 14. Step Response
Figure 15. Step Response
G = 50
Output Voltage (1V/div)
Output Voltage (100mV/div)
G = 50
VSENSE = 90mV to 100mV
VSENSE = 20mV to 110mV
Time (5ms/div)
Time (5ms/div)
Figure 16. Step Response
Figure 17. Step Response
600
G = 100
Output Voltage (2V/div)
500
VOL (mV)
400
300
200
100
VSENSE = 20mV to 110mV
0
0
Time (10ms/div)
1
2
3
4
5
6
ISINK (mA)
Figure 18. Step Response
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Figure 19. Comparator VOL vs ISINK
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Typical Characteristics (continued)
All specifications at TA = 25°C, VS = 12 V, VCM = 12 V, and VSENSE = 100 mV, unless otherwise noted.
600
602
Comparator Trip Point (mV)
599
Reset Voltage (mV)
598
597
596
595
594
593
592
601
600
599
598
597
591
596
590
2
4
6
8
10
12
14
16
18
-50
0
-25
Supply Voltage (V)
Figure 20. Comparator Trip Point vs Supply Voltage
50
75
100
125
Figure 21. Comparator Trip Point vs Temperature
200
1.2
175
1.0
Reset Voltage (V)
Propagation Delay (ns)
25
Temperature (°C)
150
125
100
75
0.8
0.6
0.4
0.2
50
0
0
20
40
60
80
100 120 140
160 180
2
200
4
6
8
10
12
14
16
18
Overdrive Voltage (mV)
Supply Voltage (V)
Figure 22. Comparator 1 Propagation Delay vs Overdrive
Voltage
Figure 23. Comparator Reset Voltage vs supply Voltage
300
Propagation Delay (ns)
275
Input
200mV/div
250
225
200
Output
2V/div
175
150
125
-50
VOD = 5mV
-25
0
25
50
75
100
125
2ms/div
Temperature (°C)
Figure 24. Comparator Propagation Delay vs Temperature
Figure 25. Comparator Propagation Delay
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8 Detailed Description
8.1 Overview
The INA203, INA204, and INA205 are a family of unidirectional current-shunt monitors with voltage output, dual
comparators, and voltage reference. The INA203, INA204, and INA205 can sense drops across shunts at
common-mode voltages from –16 V to 80 V. The INA203, INA204, and INA205 are available with three output
voltage scales: 20 V/V, 50 V/V, and 100 V/V, with up to 500-kHz bandwidth. The INA203, INA204, and INA205
also incorporate two open-drain comparators with internal 0.6-V references. On 14-pin versions, the comparator
references can be overridden by external inputs. Comparator 1 includes a latching capability, and Comparator 2
has a user-programmable delay. 14-pin versions also provide a 1.2-V reference output. The INA203, INA204,
and INA205 operate from a single 2.7-V to 18-V supply. They are specified over the extended operating
temperature range of –40°C to 125°C.
8.2 Functional Block Diagrams
VS
1
OUT
2
14 VIN+
13 VIN1.2V REF
CMP1 IN-/0.6V REF
3
12 1.2V REF OUT
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
Figure 26. SO-14, TSSOP-14 Functional Block Diagram
VS
1
10 VIN+
OUT
2
9
VIN-
CMP1 IN+
3
8
CMP1 OUT
CMP2 IN+
4
7
CMP2 OUT
GND
5
6
CMP1 RESET
0.6V REF
Figure 27. VSSOP-10 Functional Block Diagram
8.3 Feature Description
8.3.1 Basic Connections
Figure 28 shows the basic connections of the INA203, INA204, and INA205. The input pins, VIN+ and VIN–, should
be connected as closely as possible to the shunt resistor to minimize any resistance in series with the shunt
resistance.
Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power
supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors
close to the device pins.
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Feature Description (continued)
RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
Current Shunt
Monitor Output
CBYPASS
0.01mF
INA203
x20
OUT
1.2V REF
CMP1 IN-/0.6 REF
VIN+
VIN-
RPULL-UP
4.7kW
RPULL-UP
4.7kW
1.2V REF OUT
CMP1 OUT
CMP1 IN+
CMP2 IN+
CMP2 IN-/0.6 REF
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
Optional Delay
Capacitor
0.2mF
Transparent/Reset
Latch
Figure 28. INA20x Basic Connection
8.3.2 Selecting RSHUNT
The value chosen for the shunt resistor, RSHUNT, depends on the application and is a compromise between smallsignal accuracy and maximum permissible voltage loss in the measurement line. High values of RSHUNT provide
better accuracy at lower currents by minimizing the effects of offset, while low values of RSHUNT minimize voltage
loss in the supply line. For most applications, best performance is attained with an RSHUNT value that provides a
full-scale shunt voltage range of 50 mV to 100 mV. Maximum input voltage for accurate measurements is
(VSHUNT – 0.25) / Gain.
8.3.3 Comparator
The INA203, INA204, and INA205 devices incorporate two open-drain comparators. These comparators typically
have 2 mV of offset and a 1.3-μs (typical) response time. The output of Comparator 1 latches and is reset
through the CMP1 RESET pin, as shown in Figure 30. This configuration applies to both the 10- and 14-pin
versions. Figure 29 illustrates the comparator delay.
The 14-pin versions of the INA203, INA204, and INA205 devices include additional features for comparator
functions. The comparator reference voltage of both Comparator 1 and Comparator 2 can be overridden by
external inputs for increased design flexibility. Comparator 2 has a programmable delay.
8.3.4 Comparator Delay (14-Pin Version Only)
The Comparator 2 programmable delay is controlled by a capacitor connected to the CMP2 Delay Pin; see
Figure 28. The capacitor value (in μF) is selected by using Equation 1:
t
CDELAY (in mF) = D
5
(1)
A simplified version of the delay circuit for Comparator 2 is shown in Figure 29. The delay comparator consists of
two comparator stages with the delay between them. I1 and I2 cannot be turned on simultaneously; I1
corresponds to a U1 low output and I2 corresponds to a U1 high output. Using an initial assumption that the U1
output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies 120 nA to CDELAY. The voltage at U2 +IN
begins to ramp toward a 0.6-V threshold. When the voltage crosses this threshold, the U2 output goes high while
the voltage at U2 +IN continues to ramp up to a maximum of 1.2 V when given sufficient time (twice the value of
the delay specified for CDELAY). This entire sequence is reversed when the comparator outputs go low, so that
returning to low exhibits the same delay.
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Feature Description (continued)
1.2V
I2
120nA
U1
U2
I1
120nA
0.6V
CDELAY
Figure 29. Simplified Model of the Comparator 2 Delay Circuit
0.6V
VIN
0V
CMP Out
RESET
Figure 30. Comparator Latching Capability
Take care to note what will happen if events occur more rapidly than the delay timeout; for example, when the
U1 output goes high (turning on I2), but returns low (turning I1 back on) prior to reaching the 0.6-V transition for
U2. The voltage at U2 +IN ramps back down at a rate determined by the value of CDELAY, and only returns to
zero if given sufficient time.
In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the
model shown in Figure 29.
8.3.5 Comparator Maximum Input Voltage Range
The maximum voltage at the comparator input for normal operation is up to (Vs) – 1.5 V. There are special
considerations when overdriving the reference inputs (pins 3 and 6). Driving either or both inputs high enough to
drive 1 mA back into the reference introduces errors into the reference. Figure 31 shows the basic input
structure. A general guideline is to limit the voltage on both inputs to a total of 20 V. The exact limit depends on
the available voltage and whether either or both inputs are subject to the large voltage. When making this
determination, consider the 20 kΩ from each input back to the comparator. Figure 32 shows the maximum input
voltage that avoids creating a reference error when driving both inputs (an equivalent resistance back into the
reference of 10 kΩ).
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Feature Description (continued)
£ 1mA
1.2V
20kW
20kW
CMP1 IN-
CMP2 IN+
Figure 31. Limit Current Into Reference ≤ 1 mA
RSHUNT
3mW
Load Supply
-18V to +80V
Load
5V Supply
VS
Current Shunt Monitor Output
CMP1 IN-/0.6 REF
CBYPASS
0.01mF
V < 11.2
VIN+
VIN-
INA203
x20
OUT
1.2V REF
RPULL-UP
4.7kW
RPULL-UP
4.7kW
1.2V REF OUT
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
Optional Delay
Capacitor
0.2mF
Transparent/Reset
Latch
Figure 32. Overdriving Comparator Inputs Without Generating a Reference Error
Raychem
Polyswitch
Load
< 18V
Battery
+5V Supply
VS+
CMP1 IN-
x20
1.2V REF
3.3kW
Pull-Up
Resistors
VIN+
INA203
OUT
VIN1.2V REF OUT
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
Overlimit
Warning
(1)
(1)
Reset
Latch
Optional
CDELAY
0.01mF
NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens.
Figure 33. Polyswitch Warning and Fault Detection Circuit
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Feature Description (continued)
RSHUNT
0.02W
Load
Q2
NDS8434A
R1
100kW
+5V Supply
R7
1kW
VS+
R5
100kW
R6
6.04kW
CMP1 IN-
R3
14kW
R4
6.04kW
VIN+
INA203
x20
OUT
1.2V REF
Q1
2N3904
VIN-
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
R2
1kW
1.2V REF OUT
Reset
Latch
Figure 34. Lead-Acid Battery Protection Circuit
8.4 Device Functional Modes
8.4.1 Input Filtering
An obvious and straightforward location for filtering is at the output of the INA203, INA204, and INA205 series;
however, this location negates the advantage of the low output impedance of the internal buffer. The only other
option for filtering is at the input pins of the INA203, INA204, and INA205, which is complicated by the internal 5
kΩ + 30% input impedance; this configuration is illustrated in Figure 35. Using the lowest possible resistor values
minimizes both the initial shift in gain and effects of tolerance. Use Equation 2 to calculate the effect on initial
gain.
Gain Error % = 100 - 100 ´
5kW
5kW + RFILT
(2)
Total effect on gain error can be calculated by replacing the 5-kΩ term with 5 kΩ – 30%, (or 3.5 kΩ) or 5 kΩ +
30% (or 6.5 kΩ). The tolerance extremes of RFILT can also be inserted into the equation. If a pair of 100 Ω 1%
resistors are used on the inputs, the initial gain error will be 1.96%. Worst-case tolerance conditions will always
occur at the lower excursion of the internal 5-kΩ resistor (3.5 kΩ), and the higher excursion of RFILT – 3% in this
case.
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Device Functional Modes (continued)
RSHUNT << RFILTER
3mW
VSUPPLY
Load
RFILTER < 100W
RFILTER <100W
CFILTER
INA203-INA205
VIN+
VS
1
14
OUT
2
13
CMP1 IN-/0.6V REF
3
CMP1 IN+
4
11 CMP1 OUT
CMP2 IN+
5
10 CMP2 OUT
CMP2 IN-/0.6V REF
6
9
CMP2 DELAY
GND
7
8
CMP1 RESET
1.2V REF
VIN-
12 1.2V REF OUT
f-3dB
f-3dB =
1
2p(2RFILTER)CFILTER
SO-14, TSSOP-14
Figure 35. Input Filter (Gain Error: 1.5% to –2.2%)
The specified accuracy of the INA203, INA204, and INA205 must then be combined in addition to these
tolerances. While this discussion treated accuracy worst-case conditions by combining the extremes of the
resistor values, it is appropriate to use geometric mean or root sum square calculations to total the effects of
accuracy variations.
8.4.2 Accuracy Variations as a Result Of VSENSE and Common-Mode Voltage
The accuracy of the INA203, INA204, and INA205 current shunt monitors is a function of two main variables:
VSENSE (VIN+ – VIN–) and common-mode voltage, VCM, relative to the supply voltage, VS. VCM is expressed as
(VIN+ + VIN–) / 2; however, in practice, VCM is seen as the voltage at VIN+ because the voltage drop across VSENSE
is usually small.
This section addresses the accuracy of these specific operating regions:
• Normal Case 1: VSENSE ≥ 20 mV, VCM ≥ VS
• Normal Case 2: VSENSE ≥ 20 mV, VCM < VS
• Low VSENSE Case 1: VSENSE < 20 mV, –16 V ≤ VCM < 0
• Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤ VCM ≤ VS
• Low VSENSE Case 3: VSENSE < 20 mV, VS < VCM ≤ 80 V
8.4.2.1 Normal Case 1: VSENSE ≥ 20 mV, VCM ≥ VS
This region of operation provides the highest accuracy. Here, the input offset voltage is characterized and
measured using a two-step method. First, the gain is determined by Equation 3.
VOUT1 - VOUT2
G=
100mV - 20mV
where
•
•
VOUT1 = Output Voltage with VSENSE = 100 mV.
VOUT2 = Output Voltage with VSENSE = 20 mV.
(3)
Then the offset voltage is measured at VSENSE = 100 mV and referred to the input (RTI) of the current shunt
monitor, as shown in Equation 4.
VOUT1
VOSRTI (Referred-To-Input) =
- 100mV
G
(4)
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Device Functional Modes (continued)
In the Typical Characteristics, Figure 7 shows the highest accuracy for this region of operation. In this plot, VS =
12 V; for VCM ≥ 12 V, the output error is at its minimum. This case is also used to create the VSENSE ≥ 20-mV
output specifications in the Electrical Characteristics: Current-Shunt Monitor table.
8.4.2.2 Normal Case 2: VSENSE ≥ 20 mV, VCM < VS
This region of operation has slightly less accuracy than Normal Case 1 as a result of the common-mode
operating area in which the part functions, as seen in Figure 7. As noted, for this graph VS = 12 V; for VCM < 12
V, the Output Error increases as VCM becomes less than 12 V, with a typical maximum error of 0.005% at the
most negative VCM = –16 V.
8.4.2.3 Low VSENSE Case 1
• VSENSE < 20 mV, –16 V ≤ VCM< 0;
• Low V SENSE Case 3:
• VSENSE < 20 mV, VS < VCM ≤ 80 V
Although the INA203 family of devices are not designed for accurate operation in either of these regions, some
applications are exposed to these conditions; for example, when monitoring power supplies that are switched on
and off while VS is still applied to the INA203, INA204, or INA205. Take care to know what the behavior of the
devices will be in these regions.
As VSENSE approaches 0 mV, in these VCM regions, the device output accuracy degrades. A larger-than-normal
offset can appear at the current shunt monitor output with a typical maximum value of VOUT = 300 mV for VSENSE
= 0 mV. As VSENSE approaches 20 mV, VOUT returns to the expected output value with accuracy as specified in
the Electrical Characteristics: Current-Shunt Monitor. Figure 36 illustrates this effect using the INA205 (Gain =
100).
2.0
1.8
1.6
VOUT (V)
1.4
1.2
Actual
1.0
0.8
Ideal
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
VSENSE (mV)
Figure 36. Example for Low VSENSE Cases 1 and 3 (INA205, Gain = 100)
8.4.2.4 Low VSENSE Case 2: VSENSE < 20 mV, 0 V ≤ VCM ≤ VS
This region of operation is the least accurate for the INA203 family. To achieve the wide input common-mode
voltage range, these devices use two op amp front ends in parallel. One operational amplifier front end operates
in the positive input common-mode voltage range, and the other in the negative input region. For this case,
neither of these two internal amplifiers dominates and overall loop gain is very low. Within this region, VOUT
approaches voltages close to linear operation levels for Normal Case 2. This deviation from linear operation
becomes greatest the closer VSENSE approaches 0 V. Within this region, as VSENSE approaches 20 mV, device
operation is closer to that described by Normal Case 2. Figure 37 illustrates this behavior for the INA205. The
VOUT maximum peak for this case is tested by maintaining a constant VS, setting VSENSE = 0 mV, and sweeping
VCM from 0 V to VS. The exact VCM at which VOUT peaks during this test varies from part to part, but the VOUT
maximum peak is tested to be less than the specified VOUT Tested Limit.
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Device Functional Modes (continued)
2.4
2.2 INA205 VOUT Tested Limit
(1)
VCM1
2.0
Ideal
1.8
VCM2
VOUT (V)
1.6
1.4
VCM3
1.2
1.0
0.8
VOUT Tested Limit at
VSENSE = 0mV, 0 £ VCM1 £ VS.
VCM4
0.6
VCM2, VCM3, and VCM4 illustrate the variance
from part to part of the VCM that can cause
maximum VOUT with VSENSE < 20mV.
0.4
0.2
0
0
2
4
6
8
10
12
14
16
18
20
22
24
VSENSE (mV)
NOTE: (1) INA203 VOUT Tested Limit = 0.4V. INA204 VOUT Tested Limit = 1V.
Figure 37. Example For Low VSENSE Case 2 (INA205, Gain = 100)
8.4.3 Transient Protection
The –16 V to 80 V common-mode range of the INA203, INA204, and INA205 is ideal for withstanding automotive
fault conditions ranging from 12-V battery reversal up to 80-V transients, since no additional protective
components are needed up to those levels. In the event that the INA203, INA204, and INA205 are exposed to
transients on the inputs in excess of their ratings, then external transient absorption with semiconductor transient
absorbers (Zeners or Transzorbs) are necessary. Use of metal oxide varistors (MOVs) or video disk recorders
(VDRs) is not recommended except when they are used in addition to a semiconductor transient absorber.
Select the transient absorber such that it will never allow the INA203, INA204, and INA205 to be exposed to
transients greater than 80 V (that is, allow for transient absorber tolerance, as well as additional voltage because
of transient absorber dynamic impedance). Despite the use of internal Zener-type ESD protection, the INA203,
INA204, and INA205 do not lend themselves to using external resistors in series with the inputs because the
internal gain resistors can vary up to ±30% but are closely matched. (If gain accuracy is not important, then
resistors can be added in series with the INA203, INA204, and INA205 inputs with two equal resistors on each
input.)
8.4.4 Output Voltage Range
The output of the INA203, INA204, and INA205 is accurate within the output voltage swing range set by the
power-supply pin, Vs. This performance is best illustrated when using the INA205 (a gain of 100 version), where
a 100-mV full-scale input from the shunt resistor requires an output voltage swing of 10 V, and a power-supply
voltage sufficient to achieve 10 V on the output.
8.4.5 Reference
The INA203, INA204, and INA205 include an internal voltage reference that has a load regulation of 0.4 mV/mA
(typical), and not more than 100 ppm/°C of drift. Only the 14-pin package allows external access to reference
voltages, where voltages of 1.2 V and 0.6 V are both available. Output current versus output voltage is illustrated
in the Typical Characteristics section.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The INA203, INA204, and INA205 series is designed to enable easy configuration for detecting overcurrent
conditions and current monitoring in an application. This device is also incorporate two open-drain comparators
with internal 0.6-V references. On 14-pin versions, the comparator references can be overridden by external
inputs. Comparator 1 includes a latching capability, and Comparator 2 has a user-programmable delay. 14-pin
versions also provide a 1.2-V reference output. This device can also be paired with minimum additional devices
to create more sophisticated monitoring functional blocks.
9.2 Typical Application
Raychem
Polyswitch
Load
< 18V
Battery
+5V Supply
VS+
x20
OUT
CMP1 IN-
1.2V REF
3.3kW
Pull-Up
Resistors
VIN+
INA203
VIN1.2V REF OUT
CMP1 IN+
CMP1 OUT
CMP2 IN+
CMP2 IN-
CMP2 OUT
CMP2 DELAY
GND
CMP1 RESET
CBYPASS
0.01mF
Overlimit
Warning
(1)
(1)
Reset
Latch
Optional
CDELAY
0.01mF
NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens.
Figure 38. Polyswitch Warning and Fault Detection Circuit
9.2.1 Design Requirements
The device measures current through a resistive shunt with current flowing in one direction, thus enabling
detection of an overlimit or warning event only when the differential input voltage exceeds the corresponding
threshold limits. When the current reaches the warning limit of 0.6 V, the output of CMP2 will transition high
indicating a warning condition. When the current futher increases to or past the overlimit limit of 1.2 V, the output
of CMP1 will transition high indicating an overlimit condition. Optional CDELAY can be sized to add delay to CMP1.
9.2.2 Detailed Design Procedure
Figure 38 shows the basic connections of the device. The input terminals, IN+ and IN–, should be connected as
closely as possible to the current-sensing resistor or polymeric switch to minimize any resistance in series with
the shunt resistance. Additional resistance between the current-sensing resistor and input terminals can result in
errors in the measurement. When input current flows through this external input resistance, the voltage
developed across the shunt resistor can differ from the voltage reaching the input terminals.
22
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Product Folder Links: INA203 INA204 INA205
INA203, INA204, INA205
www.ti.com
SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
Typical Application (continued)
9.2.3 Application Curves
6
6
RESET(V)
COMP1(V)
VOUT(V)
COMP2(V)
5.5
5
5
4.5
4.5
4
4
3.5
3.5
3
3
2.5
2.5
2
2
1.5
1.5
1
1
0.5
0.5
0
0
-0.5
-0.5
0
100
200
COMP1(V)
VOUT(V)
COMP2_No_Delay(V)
COMP2_Delay(V)
5.5
300
400
500
Time(mS)
600
700
800
900
1000
Figure 39. Polyswitch Warning and Fault Detection Circuit
Response
0
25
50
75
100
125
150
175
200
225 250 275
Time(mS)
300
325
350
375
400
425
450
475
500
Figure 40. Polyswitch Warning and Fault Detection Circuit
With Delay Response
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: INA203 INA204 INA205
Submit Documentation Feedback
23
INA203, INA204, INA205
SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
www.ti.com
10 Power Supply Recommendations
The input circuitry of the INA203, INA204, and INA205 can accurately measure beyond the power-supply
voltage, Vs. For example, the Vs power supply can be 5 V, whereas the load power-supply voltage is up to 80 V.
The output voltage range of the OUT terminal, however, is limited by the voltages on the power-supply pin.
11 Layout
11.1 Layout Guidelines
•
•
Connect the input pins to the sensing resistor using a Kelvin or 4-wire connection. This connection technique
ensures that only the current-sensing resistor impedance is detected between the input pins. Poor routing of
the current-sensing resistor commonly results in additional resistance present between the input pins. Given
the very low ohmic value of the current resistor, any additional high-current carrying impedance can cause
significant measurement errors.
The power-supply bypass capacitor should be placed as closely as possible to the supply and ground pins.
The recommended value of this bypass capacitor is 0.1 μF. Additional decoupling capacitance can be added
to compensate for noisy or high-impedance power supplies.
11.2 Layout Example
Via to Power or Ground Plane
Via to Internal Layer
Supply Voltage
Vs
VIN+
OUT
VIN-
Shunt Resistor
Supply Bypass
Capacitor
CMP1 IN/0.6V Ref
1.2V REF
OUT
CMP1
IN+
CMP1 OUT
CMP2
IN+
CMP2 OUT
CMP2 IN/0.6V Ref
CMP2
DELAY
GND
CMP1
RESET
Pull-ups
Figure 41. Layout Recommendation
24
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Product Folder Links: INA203 INA204 INA205
INA203, INA204, INA205
www.ti.com
SBOS393E – MARCH 2007 – REVISED NOVEMBER 2015
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
INA203
Click here
Click here
Click here
Click here
Click here
INA204
Click here
Click here
Click here
Click here
Click here
INA205
Click here
Click here
Click here
Click here
Click here
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2007–2015, Texas Instruments Incorporated
Product Folder Links: INA203 INA204 INA205
Submit Documentation Feedback
25
PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA203AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA203A
INA203AIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQN
INA203AIDGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQN
INA203AIDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQN
INA203AIDGSTG4
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQN
INA203AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA203A
INA203AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA203A
INA203AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA203A
INA204AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA204A
INA204AIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQO
INA204AIDGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQO
INA204AIDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQO
INA204AIDGSTG4
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQO
INA204AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA204A
INA204AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA204A
INA204AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA204A
INA205AID
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA205A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2015
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
INA205AIDGSR
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQP
INA205AIDGSRG4
ACTIVE
VSSOP
DGS
10
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BQP
INA205AIDGST
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
BQP
INA205AIDR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA205A
INA205AIPW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA205A
INA205AIPWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
INA205A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Nov-2015
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF INA203 :
• Automotive: INA203-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Nov-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
INA203AIDGSR
VSSOP
DGS
10
INA203AIDGST
VSSOP
DGS
INA203AIDR
SOIC
D
INA203AIPWR
TSSOP
INA204AIDGSR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA204AIDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA204AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
INA204AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
INA205AIDGSR
VSSOP
DGS
10
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA205AIDGST
VSSOP
DGS
10
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
INA205AIDR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
INA205AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Nov-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
INA203AIDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
INA203AIDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
INA203AIDR
SOIC
D
14
2500
367.0
367.0
38.0
INA203AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
INA204AIDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
INA204AIDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
INA204AIDR
SOIC
D
14
2500
367.0
367.0
38.0
INA204AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
INA205AIDGSR
VSSOP
DGS
10
2500
367.0
367.0
35.0
INA205AIDGST
VSSOP
DGS
10
250
210.0
185.0
35.0
INA205AIDR
SOIC
D
14
2500
367.0
367.0
38.0
INA205AIPWR
TSSOP
PW
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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