Cypress CY7C1354A-133ACI 256k x 36/512k x 18 pipelined sram with nobl architecture Datasheet

CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
256K x 36/512K x 18 Pipelined SRAM
with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Fast clock speed: 200, 166, 133, 100 MHz
• Fast access time: 3.2, 3.6, 4.2, 5.0 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 3.3V –5% and +5% power supply VCC
• Separate VCCQ for 3.3V or 2.5V I/O
• Single WEN (Read/Write) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear four-word burst capability
• Individual byte Write (BWa–BWd) control (may be tied
LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
•Automatic power-down feature available using ZZ mode
or CE select
• JTAG boundary scan
• Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid
Array), and 100-pin TQFP packages
Functional Description
The
CY7C1354A/GVT71256ZC36
and
CY7C1356A/
GVT71512ZC18 SRAMs are designed to eliminate dead
cycles when transitioning from Read to Write or vice versa.
These SRAMs are optimized for 100% bus utilization and
achieve Zero Bus Latency (ZBL)/No Bus Latency
(NoBL). They integrate 262,144 × 36 and 524,288 × 18
SRAM cells, respectively, with advanced synchronous
peripheral circuitry and a two-bit counter for internal burst
operation. These employ high-speed, low-power CMOS
designs using advanced triple-layer polysilicon, double-layer
metal technology. Each memory cell consists of four
transistors and two high-valued resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered clock input (CLK). The synchronous
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD),
Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc,
and BWd), and Read-Write Control (WEN). BWc and BWd
apply to CY7C1354A/GVT71256ZC36 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A clock enable (CEN) pin allows operation of the
CY7C1354A/GVT71256ZC36/CY7C1356A/GVT71512ZC18
to be suspended as long as necessary. All synchronous inputs
are ignored when (CEN) is HIGH and the internal device
registers will hold their previous values.
There are three chip enable pins (CE, CE2, CE3) that allow the
user to deselect the device when desired. If any one of these
three are not active when ADV/LD is LOW, no new memory
operation can be initiated and any burst cycle in progress is
stopped. However, any pending data transfers (Read or Write)
will be completed. The data bus will be in high-impedance
state two cycles after chip is deselected or a Write cycle is
initiated.
The
CY7C1354A/GVT71256ZC36
and
CY7C1356A/
GVT71512ZC18 have an on-chip two-bit burst counter. In the
burst mode, the CY7C1354A/GVT71256ZC36 and
CY7C1356A/GVT71512ZC18 provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE), Sleep Enable (ZZ) and burst sequence
select (MODE) are the asynchronous signals. OE can be used
to disable the outputs at any given time. ZZ may be tied to
LOW if it is not used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Selection Guide
7C1354A-200
71256ZC36-5
7C1356A-200
71512ZC18-5
7C1354A-166
71256ZC36-6
7C1356A-166
71512ZC18-6
7C1354A-133
71256ZC36-7.5
7C1356A-133
71512ZC18-7.5
7C1354A-100
71256ZC36-10
7C1356A-100
71512ZC18-10
Unit
3.2
3.6
4.2
5.0
ns
Commercial
560
480
410
350
mA
Maximum CMOS Standby Current Commercial
30
30
30
30
mA
Maximum Access Time
Maximum Operating Current
Cypress Semiconductor Corporation
Document #: 38-05161 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised April 25, 2002
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
.
Functional Block Diagram—256K × 36[1]
256K x 9 x 4
SRAM Array
Address
CKE#
CEN
ADV/LD#
ADV/LD
R/W#
WEN
Control
BWa#,
BWb#
BWa, BWb,
BWc#,
BWd#
BWc, BWd
CE#,
CE2
CE , CE
CE, CE2#,
2
DI
Input
Registers
DO
ZZ
MODE
3
SA0, SA1,
CENSA
Control Logic
A0, A1, A
Sel
Mux
Output Registers
CLK
Output Buffers
OE#
OE
DQa-DQd
Functional Block Diagram—512K × 18[1]
1M x 9 x 2
SRAM Array
Address
CKE#
CEN
BWa,BWb#
BWb
BWa#,
CE#,
CE2
CE,CE2#,
CE2, CE
3
SA0, SA1,
CENSA
A0, A1, A
Control
Input
Registers
DI
WEN
R/W#
Input Registers
ADV/LD
ADV/LD#
Control Logic
Mux
CLK
OE#
OE
DO
ZZ
MODE
Sel
Output Registers
Output Buffers
DQa, DQb
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
Document #: 38-05161 Rev. *B
Page 2 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
VCC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
NC
NC
NC
VCCQ
VSS
NC
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
VCC
VCC
VCC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DPb
NC
VSS
VCCQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1356A/
GVT71512ZC18
(512K × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VCCQ
VSS
NC
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
VCC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
VSS
VCCQ
NC
NC
NC
A
A
TDO
TCK
A
A
A
A
A
A
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
Document #: 38-05161 Rev. *B
DQb
DQb
DQb
VCCQ
VSS
TDO
TCK
A
A
A
A
A
A
CY7C1354A/
GVT71256ZC36
(256K × 36)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
VCC
VCC
VCC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQd
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
DQc
DQc
DQc
VCCQ
A
A
A
A
CE
CE2
NC
NC
BWb
BWa
CE3
VCC
VSS
CLK
WEN
CEN
OE
ADV/LD
NC
A
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE3
VCC
VSS
CLK
WEN
CEN
OE
ADV/LD
NC
A
100-lead TQFP Packages
Page 3 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Configurations (continued)
119-ball Bump BGA
CY7C1354A/GVT71256ZC36 (256K × 36)–7 × 17 BGA
1
2
3
4
5
6
7
A
VCCQ
A
A
NC
A
A
VCCQ
B
NC
CE2
A
ADV/LD
A
CE3
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
A
BWb
DQb
DQb
H
DQc
DQc
VSS
WEN
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
CEN
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
VSS
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
CY7C1356A/GVT71512ZC18 (512K × 18)–7 × 17 BGA
1
2
3
4
5
6
7
A
VCCQ
A
A
NC
A
A
VCCQ
B
NC
CE2
A
ADV/LD
A
CE3
NC
C
NC
A
A
VCC
A
A
NC
D
DQb
NC
VSS
NC
VSS
DQa
NC
E
NC
DQb
VSS
CE
VSS
NC
DQa
F
VCCQ
NC
VSS
OE
VSS
DQa
VCCQ
G
NC
DQb
BWb
A
VSS
NC
DQa
H
DQb
NC
VSS
WEN
VSS
DQa
NC
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
VSS
NC
BWa
DQa
NC
M
VCCQ
DQb
VSS
CEN
VSS
NC
VCCQ
N
DQb
NC
VSS
A1
VSS
DQa
NC
P
NC
DQb
VSS
A0
VSS
NC
DQa
R
NC
A
MODE
VCC
VCC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05161 Rev. *B
Page 4 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Descriptions—256K × 36
256K × 36
TQFP Pins
256K × 36
PBGA Pins
Pin
Name
37,
36,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 81,
82, 83, 99, 100
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 4G, 2R,
6R, 3T, 4T, 5T
A0,
A1,
A
93,
94,
95,
96
5L
5G
3G
3L
InputSynchronous Byte Write Enables: Each nine-bit byte has its own
BWa,
BWb, Synchronous active LOW byte Write enable. On load Write cycles (when WEN and
BWc,
ADV/LD are sampled LOW), the appropriate byte Write signal (BWx)
BWd
must be valid. The byte Write signal must also be valid on each cycle of
a burst Write. Byte Write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device two
cycles later. BWa controls DQa pins; BWb controls DQb pins; BWc
controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW if
always doing Writes to the entire 36-bit word.
87
4M
CEN
InputSynchronous Clock Enable Input: When CEN is sampled HIGH, all
Synchronous other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
88
4H
WEN
InputRead Write: WEN signal is a synchronous input that identifies whether
Synchronous the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the
current cycle takes place two clock cycles later.
89
4K
CLK
InputClock: This is the clock input to CY7C1354A/GVT71256ZC36. Except
Synchronous for OE, ZZ and MODE, all timing references for the device are made
with respect to the rising edge of CLK.
98, 92
4E, 6B
CE,
CE3
InputSynchronous Active LOW Chip Enable: CE and CE3 are used with
Synchronous CE2 to enable the CY7C1354A/GVT71256ZC36. CE or CE3 sampled
HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge
of clock, initiates a deselect cycle. The data bus will be High-Z two clock
cycles after chip deselect is initiated.
97
2B
CE2
InputSynchronous Active High Chip Enable: CE2 is used with CE and CE3
Synchronous to enable the chip. CE2 has inverted polarity but otherwise is identical
to CE and CE3.
86
4F
OE
85
4B
ADV/
InputAdvance/Load: ADV/LD is a synchronous input that is used to load the
LD Synchronous internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected. When
ADV/LD is sampled HIGH, then the internal burst counter is advanced
for any burst that was in progress. The external addresses and WEN
are ignored when ADV/LD is sampled HIGH.
31
3R
MOD
E
64
7T
ZZ
Document #: 38-05161 Rev. *B
Type
Pin Description
InputSynchronous Address Inputs: The address register is triggered by a
Synchronous combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and
true chip enables. A0 and A1 are the two least significant bits (LSBs) of
the address field and set the internal burst counter if burst cycle is
initiated.
Input
InputStatic
Asynchronous Output Enable: OE must be LOW to Read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for Read and Write cycles. In normal operation,
OE can be tied LOW.
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst sequence
is selected. MODE is a static DC input.
InputSleep Enable: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input has to be
either LOW or NC.
Page 5 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Descriptions—256K × 36 (continued)
256K × 36
TQFP Pins
51, 52, 53, 5659, 62, 63
68, 69, 72-75,
78, 79, 80
1, 2, 3, 6-9, 12,
13
18, 19, 22-25,
28, 29, 30
256K × 36
PBGA Pins
Pin
Name
(a) 6P, 7P, 7N, DQa
6N, 6M, 6L, 7L, DQb
6K, 7K,
DQc
(b) 7H, 6H, 7G, DQd
6G, 6F, 6E, 7E,
7D, 6D,
(c) 2D, 1D, 1E,
2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
Type
Pin Description
Input/
Output
Data Inputs/Outputs: Both the data input path and data output path are
registered and triggered by the rising edge of CLK. Byte “a” is DQa pins;
Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins.
38
39
43
2U
3U
4U
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or be
connected to VCC.
42
5U
TDO
Output
IEEE 1149.1 Test Output: LVTTL-level output. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect).
14, 15, 16, 41, 4C, 2J, 4J, 6J,
65, 66, 91
4R, 5R
VCC
Supply
Power Supply: +3.3V –5% and +5%.
5, 10, 17, 21, 3D, 5D, 3E, 5E,
26, 40, 55, 60, 3F, 5F, 3H, 5H,
67, 71, 76, 90
3K, 5K, 3M,
5M, 3N, 5N, 3P,
5P
VSS
Ground
Ground: GND.
4, 11, 20, 27, 1A, 7A, 1F, 7F, VCCQ
54, 61, 70, 77 1J, 7J, 1M, 7M,
1U, 7U
84
4A, 1B, 7B, 1C,
7C, 4D, 3J, 5J,
4L, 1R, 7R, 1T,
2T, 6T, 6U
NC
I/O Supply
Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O. +2.5V
–0.125V and +0.4V for 2.5V I/O.
–
No Connect: These signals are not internally connected. It can be left
floating or be connected to VCC or to GND.
Type
Pin Description
Pin Descriptions—512K × 18
512K × 18
TQFP Pins
512K × 18
PBGA Pins
Pin
Name
37,
36,
32, 33, 34, 35,
44, 45, 46, 47,
48, 49, 50, 80,
81, 82, 83, 99,
100
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C,
3C, 5C, 6C, 4G,
2R, 6R, 2T, 3T,
5T, 6T
A0,
A1,
A
93,
94,
5L
3G
BWa,
InputSynchronous Byte Write Enables: Each nine-bit byte has its own
BWb Synchronous active LOW byte Write enable. On load Write cycles (when WEN and
ADV/LD are sampled LOW), the appropriate byte Write signal (BWx)
must be valid. The byte Write signal must also be valid on each cycle of
a burst Write. Byte Write signals are ignored when WEN is sampled
HIGH. The appropriate byte(s) of data are written into the device two
cycles later. BWa controls DQa pins; BWb controls DQb pins. BWx can
all be tied LOW if always doing Write to the entire 18-bit word.
87
4M
CEN
Document #: 38-05161 Rev. *B
InputSynchronous Address Inputs: The address register is triggered by a
Synchronous combination of the rising edge of CLK, ADV/LD LOW, CEN LOW, and
true chip enables. A0 and A1 are the two least significant bits of the
address field and set the internal burst counter if burst cycle is initiated.
InputSynchronous Clock Enable Input: When CEN is sampled HIGH, all
Synchronous other synchronous inputs, including clock are ignored and outputs
remain unchanged. The effect of CEN sampled HIGH on the device
outputs is as if the LOW-to-HIGH clock transition did not occur. For
normal operation, CEN must be sampled LOW at rising edge of clock.
Page 6 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Descriptions—512K × 18 (continued)
512K × 18
TQFP Pins
512K × 18
PBGA Pins
Pin
Name
88
4H
WEN
InputRead Write: WEN signal is a synchronous input that identifies whether
Synchronous the current loaded cycle and the subsequent burst cycles initiated by
ADV/LD is a Read or Write operation. The data bus activity for the current
cycle takes place two clock cycles later.
89
4K
CLK
InputClock: This is the clock input to CY7C1356A/GVT71512ZC18. Except
Synchronous for OE, ZZ, and MODE, all timing references for the device are made
with respect to the rising edge of CLK.
98,
92
4E, 6B
CE,
CE3
InputSynchronous Active LOW Chip Enable: CE and CE3 are used with
Synchronous CE2 to enable the CY7C1356A/GVT71512ZC18. CE or CE3 sampled
HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge
of clock, initiates a deselect cycle. The data bus will be High-Z two clock
cycles after chip deselect is initiated.
97
2B
CE2
InputSynchronous Active HIGH Chip Enable: CE2 is used with CE and CE3
Synchronous to enable the chip. CE2 has inverted polarity but otherwise is identical to
CE and CE3.
86
4F
OE
85
4B
ADV
InputAdvance/Load: ADV/LD is a synchronous input that is used to load the
/LD Synchronous internal registers with new address and control signals when it is
sampled LOW at the rising edge of clock with the chip is selected. When
ADV/LD is sampled HIGH, then the internal burst counter is advanced
for any burst that was in progress. The external addresses and WEN are
ignored when ADV/LD is sampled HIGH.
31
3R
MOD
E
64
7T
ZZ
58, 59, 62, 63,
68, 69, 72, 73,
74
8, 9, 12, 13, 18,
19, 22, 23, 24
(a) 6D, 7E, 6F,
7G, 6H, 7K, 6L,
6N, 7P
(b) 1D, 2E, 2G,
1H, 2K, 1L, 2M,
1N, 2P
DQa
DQb
Input/
Output
Data Inputs/Outputs: Both the data input path and data output path are
registered and triggered by the rising edge of CLK. Byte “a” is DQa pins;
Byte “b” is DQb pins.
38
39
43
2U
3U
4U
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs: LVTTL-level inputs. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect) or be
connected to VCC.
42
5U
TDO
Output
IEEE 1149.1 Test Inputs: LVTTL-level output. If Serial Boundary Scan
(JTAG) is not used, these pins can be floating (i.e., No Connect).
14, 15, 16, 41, 4C, 2J, 4J, 6J,
65, 66, 91
4R, 5R
VCC
Supply
Power Supply: +3.3V –5% and +5%.
5, 10, 17, 21, 3D, 5D, 3E, 5E,
26, 40, 55, 60, 3F, 5F, 5G, 3H,
67, 71, 76, 90 5H, 3K, 5K, 3L,
3M, 5M, 3N,
5N, 3P, 5P
VSS
Ground
Ground: GND.
Document #: 38-05161 Rev. *B
Type
Input
InputStatic
Pin Description
Asynchronous Output Enable: OE must be LOW to Read data. When
OE is HIGH, the I/O pins are in high-impedance state. OE does not need
to be actively controlled for Read and write cycles. In normal operation,
OE can be tied LOW.
Burst Mode: When MODE is HIGH or NC, the interleaved burst
sequence is selected. When MODE is LOW, the linear burst sequence
is selected. MODE is a static DC input.
InputSleep Enable: This active HIGH input puts the device in low power
Asynchronou consumption standby mode. For normal operation, this input has to be
s
either LOW or NC.
Page 7 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Pin Descriptions—512K × 18 (continued)
512K × 18
TQFP Pins
512K × 18
PBGA Pins
Pin
Name
4, 11, 20, 27, 1A, 7A, 1F, 7F, VCCQ
54, 61, 70, 77 1J, 7J, 1M, 7M,
1U, 7U
1-3, 6, 7, 25,
28-30,
51-53, 56, 57,
75, 78, 79, 84,
95, 96
4A, 1B, 7B, 1C,
7C, 2D, 4D, 7D,
1E, 6E, 2F, 1G,
6G, 2H, 7H, 3J,
5J, 1K, 6K, 2L,
4L, 7L, 6M, 2N,
7N, 1P, 6P, 1R,
7R, 1T, 4T, 6U
Type
Pin Description
I/O Supply
Output Buffer Supply: +3.3V –0.165V and +0.165V for 3.3V I/O. +2.5V
–0.125V and +0.4V for 2.5V I/O.
–
No Connect: These signals are not internally connected. It can be left
floating or be connected to VCC or to GND.
NC
Partial Truth Table for Read/Write[2]
Function
Read
No Write
WEN
BWa
BWb
BWc[4]
BWd[4]
H
X
X
X
X
L
H
H
H
H
Write Byte a (DQa)
[3]
L
L
H
H
H
Write Byte b (DQb)
[3]
L
H
L
H
H
Write Byte c (DQc)[3]
L
H
H
L
H
[3]
Write Byte d (DQd}
L
H
H
H
L
Write all bytes
L
L
L
L
L
Interleaved Burst Address Table
(MODE = VCC or NC)
Linear Burst Address Table
(MODE = VSS)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)[5]
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)[5]
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A11
A...A00
A...A01
A...A10
Notes:
2. L means logic LOW. H means logic HIGH. X means Don’t Care.
3. Multiple bytes may be selected during the same cycle.
4. BWc and BWd apply to 256K × 36 device only.
5. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting.
Document #: 38-05161 Rev. *B
Page 8 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs must remain inactive for the duration of
tZZREC after the ZZ input returns LOW. CEN needs to active
before going into the ZZ mode and before you want to come
back out of the ZZ mode.
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max.
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2V
10
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Truth Table[9, 10, 11, 12, 13, 14, 15, 16, 17]
Operation
Deselect Cycle
Continue Deselect/NOP[18]
Read Cycle (Begin Burst)
Read Cycle (Continue Burst)[18]
Dummy Read (Begin Burst)[19]
Dummy Read (Continue Burst)[18, 19]
Write Cycle (Begin Burst)
Write Cycle (Continue Burst)[18]
Abort Write (Begin Burst)[19]
Abort Write (Continue Burst)[18, 19]
Ignore Clock Edge/NOP
[20]
Previous
Cycle
Address
Used
WEN ADV/LD
CE
CEN
BWx
DQ
OE (2 cycles later)
X
X
X
L
H
L
X
X
High-Z
Deselect
X
X
H
X
L
X
X
High-Z
X
External
H
L
L
L
X
X
Q
Read
Next
X
H
X
L
X
X
Q
X
External
H
L
L
L
X
H
High-Z
Read
Next
X
H
X
L
X
H
High-Z
X
External
L
L
L
L
L
X
D
Write
Next
X
H
X
L
L
X
D
X
External
L
L
L
L
H
X
High-Z
Write
Next
X
H
X
L
H
X
High-Z
X
X
X
H
X
H
X
X
–
Notes:
6. This assumes that CEN, CE, CE2 and CE3 are all True.
7. All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data
delay from the rising edge of clock.
8. DQc and DQd apply to 256K × 36 device only.
9. L means logic LOW. H means logic HIGH. X means Don’t Care. High-Z means High Impedance. BWx = L means [BWa*BWb*BWc*BWd] = LOW. BWx = H
means [BWa*BWb*BWc*BWd] = HIGH. BWc and BWd apply to 256K × 36 device only.
10. CE = H means CE and CE3 are LOW along with CE2 HIGH. CE = L means CE or CE3 are HIGH or CE2 is LOW. CE = X means CE, CE3, and CE2 are Don’t Care.
11. BWa enables Write to byte “a” (DQa pins). BWb enables Write to byte “b” (DQb pins). BWc enables Write to byte “c” (DQc pins). BWd enables Write to byte “d”
(DQd pins). DQc, DQd, BWc, and BWd apply to 256K × 36 device only.
12. The device is not in Sleep Mode, i.e., the ZZ pin is LOW.
13. During Sleep Mode, the ZZ pin is HIGH and all the address pins and control pins are “Don’t Care.” The SNOOZE MODE can only be entered two cycles after
the Write cycle, otherwise the Write cycle may not be completed.
14. All inputs, except OE, ZZ, and MODE pins, must meet set-up time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge.
15. OE may be tied to LOW for all the operation. This device automatically turns off the output driver during Write cycle.
16. Device outputs are ensured to be in High-Z during device power-up.
17. This device contains a two-bit burst counter. The address counter is incremented for all Continue Burst cycles. Address wraps to the initial address every fourth
burst cycle.
18. Continue Burst cycles, whether Read or Write, use the same control signals. The type of cycle performed, Read or Write, depends upon the WEN control signal
at the Begin Burst cycle. A Continue Deselect cycle can only be entered if a DESELECT cycle is executed first.
19. Dummy Read and Abort Write cycles can be entered to set up subsequent Read or Write cycles or to increment the burst counter.
20. When an Ignore Clock Edge cycle enters, the output data (Q) will remain the same if the previous cycle is Read cycle or remain High-Z if the previous cycle is
Write or DESELECT cycle.
Document #: 38-05161 Rev. *B
Page 9 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been
modified or eliminated because their implementation places
extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls
the TAPs operation) and can be expected to function in a
manner that does not conflict with the operation of devices with
IEEE Standard 1149.1 compliant TAPs. The TAP operates
using LVTTL/LVCMOS logic level signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port
TCK–Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS–Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI–Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the
instruction that is currently loaded in the TAP instruction
register (refer to Figure 1, TAP Controller State Diagram). It is
allowable to leave this pin unconnected if it is not used in an
application. The pin is pulled up internally, resulting in a logic
HIGH level. TDI is connected to the most significant bit (MSB)
of any register (see Figure 2).
TDO–Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed
between TDI and TDO. TDO is connected to the LSB of any
register (see Figure 2).
Document #: 38-05161 Rev. *B
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction
register with the IDCODE command. This type of reset does
not affect the operation of the system logic. The reset affects
test logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
TAP Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAP registers is a serial shift register
that captures serial input data on the rising edge of TCK and
pushes serial data out on subsequent falling edge of TCK.
When a register is selected, it is connected between the TDI
and TDO pins.
Instruction Register
The instruction register holds the instructions that are
executed by the TAP controller when it is moved into the run
test/idle or the various data register states. The instructions
are three bits long. The register can be loaded when it is
placed between the TDI and TDO pins. The parallel outputs of
the instruction register are automatically preloaded with the
IDCODE instruction upon power-up or whenever the controller
is placed in the test-logic reset state. When the TAP controller
is in the Capture-IR state, the two least significant bits of the
serial instruction register are loaded with a binary “01” pattern
to allow for fault isolation of the board-level serial test data
path.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The Boundary Scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the
device. This also includes a number of NC pins that are
reserved for future needs. There are a total of 70 bits for x36
device and 51 bits for x18 device. The boundary scan register,
under the control of the TAP controller, is loaded with the
contents of the device I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and
TDO pins when the controller is moved to Shift-DR state. The
EXTEST, SAMPLE/ PRELOAD and SAMPLE-Z instructions
can be used to capture the contents of the I/O ring.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s
position in the boundary scan register. The MSB of the register
is connected to TDI, and LSB is connected to TDO. The
second column is the signal name and the third column is the
bump number. The third column is the TQFP pin number and
the fourth column is the BGA bump number.
Page 10 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
There are two classes of instructions defined in the IEEE
Standard 1149.1-1990; the standard (public) instructions and
device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST,
INTEST, or the preload portion of the SAMPLE/PRELOAD
command.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the
instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in
Document #: 38-05161 Rev. *B
Capture-DR mode and places the ID register between the TDI
and TDO pins in Shift-DR mode. The IDCODE instruction is
the default instruction loaded in the instruction upon power-up
and at any time the TAP controller is placed in the test-logic
reset state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded in the
instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture set-up plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the
boundary scan register between the TDI and TDO pins.
Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR
state with the SAMPLE/PRELOAD instruction loaded in the
instruction register has the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP controller is in the Shift-DR state, the
bypass register is placed between TDI and TDO. This allows
the board level scan path to be shortened to facilitate testing
of other devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
Page 11 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
1
TEST-LOGIC
RESET
0
0
REUN-TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-DR
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Figure 1. TAP Controller State Diagram[21]
Note:
21.The “0”/”1” next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05161 Rev. *B
Page 12 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register [22]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
VIH
Description
Min.
Max.
Unit
[23, 24]
Test Conditions
2.0
VCC + 0.3
V
[23, 24]
–0.3
0.8
V
Input High (Logic 1) Voltage
VIl
Input Low (Logic 0) Voltage
ILI
Input Leakage Current
0V < VIN < VCC
–5.0
5.0
µA
ILI
TMS and TDI Input Leakage Current
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[23, 25]
IOLC = 100 µA
0.2
V
VOHC
[23, 25]
IOHC = 100 µA
VOLT
VOHT
LVCMOS Output High Voltage
LVTTL Output Low Voltage
[23]
IOLT = 8.0 mA
[23]
IOHT = 8.0 mA
LVTTL Output High Voltage
VCC – 0.2
V
0.4
2.4
V
V
Notes:
22. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
23. All voltage referenced to VSS (GND).
24. Overshoot: VIH(AC) < VCC + 1.5V for t < tKHKH/2; undershoot: VIL(AC) <–0.5V for t < tKHKH/2; power-up: VIH < 3.6V and VCC < 3.135V and VCCQ < 1.4V for
t < 200 ms. During normal operation, VCCQ must not exceed VCC. Control input signals (such as WEN and ADV/LD) may not have pulse widths less than
tKHKL (min.).
25. This parameter is sampled.
Document #: 38-05161 Rev. *B
Page 13 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
TAP AC Switching Characteristics Over the Operating Range[26, 27]
Parameter
Description
Min.
Max.
Unit
Clock
tTHTH
Clock Cycle Time
20
ns
fTF
Clock Frequency
tTHTL
Clock HIGH Time
8
ns
tTLTH
Clock LOW Time
8
ns
tTLQX
TCK LOW to TDO Unknown
0
ns
tTLQV
TCK LOW to TDO Valid
tDVTH
TDI Valid to TCK HIGH
5
ns
tTHDX
TCK HIGH to TDI Invalid
5
ns
50
MHz
Output Times
10
ns
Set-up Times
tMVTH
TMS Set-up
5
ns
tTDIS
TDI Set-up
5
ns
tCS
Capture Set-up
5
ns
Hold Times
tTHMX
TMS Hold
5
ns
tTDIH
TDI Hold
5
ns
tCH
Capture Hold
5
ns
Notes:
26. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
27. Test conditions are specified using the load in TAP AC test conditions.
Document #: 38-05161 Rev. *B
Page 14 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
TAP Timing and Test Conditions
1.5V
50Ω
ALL INPUT PULSES
TDO
3.0V
Z0 = 50Ω
1.5V
CL = 20 pF
VSS
1.5 ns
1.5 ns
GND
(a)
t
tTHTH
THTL
t
TLTH
TEST CLOCK
(TCK)
t
MVTH
t
t
tTHDX
THMX
TEST MODE SELECT
(TMS)
DVTH
TEST DATA IN
(TDI)
t
TLQV
tTLQX
TEST DATA OUT
(TDO)
Identification Register Definitions
Instruction Field
256K x 36
512K x 18
Revision Number(31:28)
XXXX
XXXX
Reserved for revision number.
Device Depth (27:23)
00110
00111
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
Device Width (22:18)
Reserved (17:12)
Cypress Jedec ID Code (11:1)
ID Register Presence Indicator (0)
00100
00011
XXXXXX
XXXXXX
00011100100
00011100100
1
1
Description
Reserved for future use.
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x36)
Bit Size (x18)
Instruction
3
3
Bypass
1
1
ID
32
32
Boundary Scan
70
51
Document #: 38-05161 Rev. *B
Page 15 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
010
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
101
Do not use these instructions; they are reserved for future use.
RESERVED
110
Do not use these instructions; they are reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This instruction does
not affect device operations.
Document #: 38-05161 Rev. *B
Page 16 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Boundary Scan Order (256K × 36)
Boundary Scan Order (256K × 36)
Bit#
Signal
Name
TQFP
Bump ID
Bit#
Signal
Name
TQFP
Bump ID
1
A
44
2R
36
CE3
92
6B
2
A
45
3T
37
BWa
93
5L
3
A
46
4T
38
BWb
94
5G
BWc
95
3G
4
A
47
5T
39
5
A
48
6R
40
BWd
96
3L
6
A
49
3B
41
CE2
97
2B
7
A
50
5B
42
CE
98
4E
A
99
3A
8
DQa
51
6P
43
9
DQa
52
7N
44
A
100
2A
10
DQa
53
6M
45
DQc
1
2D
11
DQa
56
7L
46
DQc
2
1E
DQc
3
2F
12
DQa
57
6K
47
13
DQa
58
7P
48
DQc
6
1G
14
DQa
59
6N
49
DQc
7
2H
15
DQa
62
6L
50
DQc
8
1D
DQc
9
2E
16
DQa
63
7K
51
17
ZZ
64
7T
52
DQc
12
2G
18
DQb
68
6H
53
DQc
13
1H
19
DQb
69
7G
54
NC
14
5R
DQd
18
2K
20
DQb
72
6F
55
21
DQb
73
7E
56
DQd
19
1L
22
DQb
74
6D
57
DQd
22
2M
23
DQb
75
7H
58
DQd
23
1N
DQd
24
2P
24
DQb
78
6G
59
25
DQb
79
6E
60
DQd
25
1K
26
DQb
80
7D
61
DQd
28
2L
27
A
81
6A
62
DQd
29
2N
DQd
30
1P
28
A
82
5A
63
29
A
83
4G
64
MODE
31
3R
30
NC
84
4A
65
A
32
2C
31
ADV/LD
85
4B
66
A
33
3C
A
34
5C
32
OE
86
4F
67
33
CEN
87
4M
68
A
35
6C
34
WEN
88
4H
69
A1
36
4N
35
CLK
89
4K
70
A0
37
4P
Document #: 38-05161 Rev. *B
Page 17 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Boundary Scan Order (512K × 18)
Boundary Scan Order (512K × 18)
Bit#
Signal
Name
TQFP
Bump ID
Bit#
Signal
Name
TQFP
Bump ID
1
A
44
2R
27
CLK
89
4K
2
A
45
2T
28
CE3
92
6B
3
A
46
3T
29
BWa
93
5L
BWb
94
3G
4
A
47
5T
30
5
A
48
6R
31
CE2
97
2B
6
A
49
3B
32
CE
98
4E
7
A
50
5B
33
A
99
3A
A
100
2A
8
DQa
58
7P
34
9
DQa
59
6N
35
DQb
8
1D
10
DQa
62
6L
36
DQb
9
2E
11
DQa
63
7K
37
DQb
12
2G
DQb
13
1H
12
ZZ
64
7T
38
13
DQa
68
6H
39
NC
14
5R
14
DQa
69
7G
40
DQb
18
2K
15
DQa
72
6F
41
DQb
19
1L
DQb
22
2M
16
DQa
73
7E
42
17
DQa
74
6D
43
DQb
23
1N
18
A
80
6T
44
DQb
24
2P
19
A
81
6A
45
MODE
31
3R
A
32
2C
20
A
82
5A
46
21
A
83
4G
47
A
33
3C
22
NC
84
4A
48
A
34
5C
23
ADV/LD
85
4B
49
A
35
6C
A1
36
4N
A0
37
4P
24
OE
86
4F
50
25
CEN
87
4M
51
26
WEN
88
4H
Document #: 38-05161 Rev. *B
Page 18 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
VIN ...........................................................–0.5V to VCC+0.5V
Storage Temperature (plastic) ...................... –55°C to +125°
Junction Temperature ..................................................+125°
Power Dissipation .........................................................2.0W
Electrical Characteristics Over the Operating Range
Parameter
VIHD
Short Circuit Output Current ....................................... 50 mA
Static Discharge Voltage ......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ................................................... > 200 mA
Operating Range
Range
Ambient Temperature[28] VCC
VCCQ
Commercial
0°C to +70°C
3.3V ± 2.5V-5%/
5%
3.3V+10%
Industrial
-40°C to +85°C
Description
Test Conditions
[23, 29]
Input High (Logic 1) Voltage
VIH
[23, 29]
Min.
Max.
Unit
All other Inputs
2.0
VCC + 0.3
V
3.3V I/O
2.0
V
2.5V I/O
1.7
V
3.3V I/O
–0.3
0.8
2.5V I/O
VIL
Input Low (Logic 0) Voltage
–0.3
0.7
V
ILI
Input Leakage Current
0V < VIN < VCC
-
5
µA
ILI
MODE and ZZ Input Leakage Current[30] 0V < VIN < VCC
-
30
µA
ILO
Output Leakage Current
-
5
µA
VOH
VOL
[23]
Output High Voltage
[23]
Output Low Voltage
[23]
Output(s) disabled, 0V < VOUT < VCC
V
I0H = –5.0 mA for 3.3V I/O
2.4
V
I0H = –1.0 mA for 2.5V I/O
2.0
V
I0L=8.0 mA for 3.3V I/O
0.4
V
I0L = 1.0 mA for 2.5V I/O
0.4
V
VCC
Supply Voltage
I0H=1.0 mA
3.135
3.465
V
VCCQ
I/O Supply Voltage[23]
3.3V I/O
3.135
3.465
V
2.5V I/O
2.375
2.9
V
Parameter
Description
Conditions
Typ.
200
MHz/
-5
166
MHz/
-6
133
MHz/
-7.5
100
MHz/
-10
Unit
560
480
410
350
mA
ICC
Power Supply Current:
Operating[31, 32, 33, 34]
Device selected; all inputs < VILor > 200
VIH; cycle time > tKC min.; VCC =Max.;
outputs open, ADV/LD = X, f = fMAX2
ISB1
Automatic CE
Power-Down
Current—TTL Inputs
Device deselected;
all inputs < VIL or > VIH; VCC = Max.;
CLK cycle time > tKC Min.
ISB2
CMOS Standby[32, 33, 34] Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or > VCC – 0.2;
all inputs static; CLK frequency = 0
15
30
30
30
30
mA
ISB3
TTL Standby[32, 33, 34]
20
50
50
50
50
mA
ISB4
Clock Running[32, 33, 34] Device deselected;
all inputs < VIL or > VIH; VCC = MAX;
CLK cycle time > tKC Min.
50
230
200
190
170
mA
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = Max.; CLK frequency = 0
mA
Notes:
28. TA is the case temperature.
29. Overshoot: VIH < +6.0V for t < tKC /2; undershoot: VIL < –2.0V for t < tKC /2.
30. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±50 µA.
31. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
32. “Device Deselected” means the device is in power-down mode as defined in the truth table. “Device Selected” means the device is active.
33. Typical values are measured at 3.3V, 25°C, and 20-ns cycle time.
34. At f = fMAX, inputs are cycling at the maximum frequency of Read cycles of 1/tCYC; f = 0 means no input lines are changing.
Document #: 38-05161 Rev. *B
Page 19 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Capacitance[25]
Parameter
Description
Test Conditions
CI
Input Capacitance
CI/O
Input/Output Capacitance (DQ)
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Typ.
Max.
Unit
4
4
pF
7
6.5
pF
Thermal Resistance
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Unit
25
°C/W
9
°C/W
Still Air, soldered on a 4.25 x 1.125 inch,
4-layer PCB
AC Test Loads and Waveforms
317Ω
VCCQ
DQ
ALL INPUT PULSES
VCCQ
DQ
Z0 = 50Ω
TQFP Typ.
50Ω
5 pF
351Ω
0V
≤ 1.0 ns
≤ 1.0 ns
Vt = 1.5V
(a)
90%
10%
90%
10%
(c)
(b)
[17]
Switching Characteristics Over the Operating Range
-5/
200 MHz
Parameter
Description
Min.
Max.
-6/
166 MHz
Min.
Max.
-7.5/
133 MHz
Min.
Max.
-10/
100 MHz
Min.
Max.
Unit
Clock
tKC
Clock Cycle Time
5.0
6.0
7.5
10
ns
tKH
Clock HIGH Time
1.8
2.1
2.6
3.5
ns
tKL
Clock LOW Time
1.8
2.1
2.6
3.5
ns
Output Times
tKQ
Clock to Output Valid
3.2
tKQX
Clock to Output Invalid
1.0
tKQLZ
[25, 36, 37]
Clock to Output in Low-Z
1.0
tKQHZ
Clock to Output in High-Z[25, 36, 37]
1.0
tOEQ
OE to Output Valid
tOELZ
tOEHZ
3.6
1.0
1.0
3.2
[25, 36, 37]
OE to Output in Low-Z
0
[25, 36, 37]
OE to Output in High-Z
1.0
1.0
3.0
4.2
1.0
3.6
0
3.5
1.0
1.0
3.0
5.0
1.0
4.2
0
3.5
ns
1.0
3.0
ns
3.0
ns
5.0
ns
0
3.5
ns
ns
3.5
ns
Set-up Times
tS
tSD
Address and Controls[38]
1.5
1.5
1.8
2.0
ns
Data In
1.5
1.5
1.8
2.0
ns
Address and Controls[38]
0.5
0.5
0.5
0.5
ns
0.5
0.5
0.5
0.5
ns
[38]
Hold Times
tH
tHD
[38]
Data In
Notes:
35. Test conditions as specified with the output loading as shown in (a) of AC Test Loads unless otherwise noted.
36. Output loading is specified with CL=5 pF as in (a) of AC Test Loads.
37. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
38. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t care” as defined in the truth table.
Document #: 38-05161 Rev. *B
Page 20 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Switching Waveforms
Read Timing[39, 40, 41, 42, 43]
tKC
tKH
tKL
CLK
tS
tH
CKE#
CEN
tS
tH
R/W#
WEN
tS
ADDRESS
A1
tH
A2
BWa, BWb,
BWa#,
BWb#
BWc, BWd
tS
tH
tS
tH
CE#
CE
ADV/LD#
ADV/LD
OE#
OE
tKQ
tKQLZ
DQ
Q(A1)
tKQX
Q(A2)
Pipeline Read
Q(A2+1)
(CKE#HIGH
, eliminates
current L-H clock edge)
Q(A2+2)
(Burst Wraps around
to initial state)
Q(A2+3)
tKQHZ
Q(A2)
BURST PIPELINE READ
Pipeline Read
Notes:
39. Q(A1) represents the first output from the external address A1. Q(A2) represents the first output from the external address A2; Q(A2+1) represents the next output
data in the burst sequence of the base address A2, etc., where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the
state of the MODE input.
40. CE3 timing transitions are identical to the CE signal. For example, when CE is LOW on this waveform, CE3 is LOW. CE2 timing transitions are identical but
inverted to the CE signal. For example, when CE is LOW on this waveform, CE2 is HIGH.
41. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
42. WEN is “Don’t Care” when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the WEN signal
when new address and control are loaded into the SRAM.
43. BWc and BWd apply to 256K × 36 device only.
Document #: 38-05161 Rev. *B
Page 21 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Switching Waveforms (continued)
Write Timing[40, 41, 42, 43, 44, 45]
tKC
tKH
tKL
CLK
tS
tH
CKE#
CEN
tS
tH
R/W#
WEN
tS
ADDRESS
A1
BWa, BWb,
BWa#,
BWb#
BWc, BWd
BW(A1)
tH
A2
tS
tH
BW(A2)
BW(A2+1)
tS
tH
tS
tH
BW(A2+2)
BW(A2+3)
BW(A2)
CE#
CE
ADV/LD#
ADV/LD
OE#
OE
tHD
tSD
DQ
D(A1)
Pipeline Write
(CKE#HIGH
, eliminates
current L-H clock edge)
D(A2)
D(A2+1)
(Burst Wraps around
to initial state)
D(A2+2)
D(A2+3)
D(A2)
Burst Pipeline Write
Pipeline Write
Notes:
44. D(A1) represents the first input to the external address A1. D(A2) represents the first input to the external address A2; D(A2 + 1) represents the next input data
in the burst sequence of the base address A2, etc., where address bits A0 and A1 are advancing for the four-word burst in the sequence defined by the state of
the MODE input.
45. Individual Byte Write signals (BWx) must be valid on all Write and burst-Write cycles. A Write cycle is initiated when WEN signal is sampled LOW when ADV/LD
is sampled LOW. The byte Write information comes in one cycle before the actual data is presented to the SRAM.
Document #: 38-05161 Rev. *B
Page 22 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Switching Waveforms (continued)
Read/Write Timing[40, 43, 45, 46]
tKC
tKH
tKL
CLK
tS
tH
CKE#
CEN
tS
tH
R/W#
WEN
tS
ADDRESS
A1
tH
A2
tS
BWa,BWb#
BWb,
BWa#,
BWc, BWd
A3
A4
A5
BW(A4)
BW(A5)
A6
A7
A8
A9
tH
BW(A2)
tS
tH
tS
tH
CE#
CE
ADV/LD#
ADV/LD
OE#
OE
tKQ
DATA Out (Q)
tKQHZ
tKQLZ
Q(A1)
Read
tKQX
Q(A3)
Q(A6)
Read
DATA In (D)
Read
D(A2)
Write
Q(A7)
D(A4)
D(A5)
Write
Note:
46. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2.
Document #: 38-05161 Rev. *B
Page 23 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Switching Waveforms (continued)
CEN Timing[40, 43, 45, 46, 47]
tKC
tKH
tKL
CLK
tS
tH
CKE#
CEN
tS
tH
tS
tH
R/W#
WEN
ADDRESS
A1
A2
A3
tS
tH
tS
tH
tS
tH
BWa, BWb,
BWa#,
BWb#
BWc, BWd
A4
A5
CE#
CE
ADV/LD#
ADV/LD
OE#
OE
tKQ
DATA Out (Q)
Q(A1)
tKQLZ
DATA In (D)
tKQHZ
Q(A3)
tKQX
tSD tHD
D(A2)
Note:
47. CEN when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the
L-H clock transition did not occur. All internal registers in the SRAM will retain their previous states.
Document #: 38-05161 Rev. *B
Page 24 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Switching Waveforms (continued)
CE Timing[40, 43, 45, 48, 49]
tKC
tKH
tKL
CLK
tS
tH
CKE#
CEN
tS
tH
R/W#
WEN
tS
ADDRESS
A1
tH
A2
A3
tS
tH
tS
tH
BWa, BWb,
BWa#, BWb#
BWc, BWd
tS
A4
A5
tH
CE#
CE
ADV/LD#
ADV/LD
tOEQ
OE#
OE
tKQHZ
tOELZ
DATA Out (Q)
Q(A1)
tKQLZ
tKQ
DATA In (D)
tOEHZ
Q(A2)
Q(A4)
tKQX
tSD tHD
D(A3)
Notes:
48. Q(A1) represents the first output from the external address A1. D(A3) represents the input data to the SRAM corresponding to address A3, etc.
49. When either one of the Chip Enables (CE, CE2, or CE3) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z one
cycle after t
Document #: 38-05161 Rev. *B
Page 25 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Switching Waveforms (continued)
ZZ Mode Timing [ 50, 51]
CLK
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
I/Os
IDDZZ
tZZREC
Three-state
Notes:
50.Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device.
51. I/Os are in three-state when exiting ZZ sleep mode
Document #: 38-05161 Rev. *B
Page 26 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Ordering Information
Speed
(MHz)
200
Ordering Code
CY7C1354A-200AC/
GVT71256ZC36-5
CY7C1354A-200BGC/
GVT71256ZC36B-5
166
CY7C1354A-166AC/
GVT71256ZC36-6
CY7C1354A-166BGC/
GVT71256ZC36B-6
133
CY7C1354A-133AC/
GVT71256ZC36-7.5
CY7C1354A-133BGC/
GVT71256ZC36B-7.5
100
CY7C1354A-100AC/
GVT71256ZC36-10
CY7C1354A-100BGC/
GVT71256ZC36B-10
200
CY7C1356A-200AC/
GVT71512ZC18-5
CY7C1356A-200BGC/
GVT71512ZC18B-5
166
CY7C1356A-166AC/
GVT71512ZC18-6
CY7C1356A-166BGC/
GVT71512ZC18B-6
133
CY7C1356A-133AC/
GVT71512ZC18-7.5
CY7C1356A-133BGC/
GVT71512ZC18B-7.5
100
CY7C1356A-100AC/
GVT71512ZC18-10
CY7C1356A-100BGC/
GVT71512ZC18B-10
Document #: 38-05161 Rev. *B
Package
Name
Package Type
Operating
Range
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
Page 27 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Ordering Information
Speed
(MHz)
166
Ordering Code
CY7C1354A-166ACI/
GVT71256ZC36-6
CY7C1354A-166BGCI/
GVT71256ZC36B-6I
133
CY7C1354A-133ACI/
GVT71256ZC36-7.5I
CY7C1354A-133BGCI/
GVT71256ZC36B-7.5I
100
CY7C1354A-100ACI/
GVT71256ZC36-10I
CY7C1354A-100BGCI/
GVT71256ZC36B-10I
200
CY7C1356A-200ACI/
GVT71512ZC18-5I
CY7C1356A-200BGCI/
GVT71512ZC18B-5I
166
CY7C1356A-166ACI/
GVT71512ZC18-6I
CY7C1356A-166BGCI/
GVT71512ZC18B-6I
133
CY7C1356A-133ACI/
GVT71512ZC18-7.5I
CY7C1356A-133BGCI/
GVT71512ZC18B-7.5I
100
CY7C1356A-100ACI
GVT71512ZC18-10I
CY7C1356A-100BGCI/
GVT71512ZC18B-10I
Document #: 38-05161 Rev. *B
Package
Name
Package Type
Operating
Range
A101
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Industrial
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
A101
BG119
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
100-lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-ball BGA (14 x 22 x 2.4 mm)
Page 28 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Package Diagrams
100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05161 Rev. *B
Page 29 of 31
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Package Diagrams (continued)
119-Lead BGA (14 x 22 x 2.4) BG119
51-85115-*A
No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.
Document #: 38-05161 Rev. *B
Page 30 of 31
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1354A/GVT71256ZC36
CY7C1356A/GVT71512ZC18
Document Title: CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM
with NoBL™ Architecture
Document Number: 38-05161
REV.
ECN No.
Issue
Date
Orig. of
Change
**
3000
4/21/00
CXV
New Data Sheet
*A
114095
03/12/02
GLC
1) Updated VIH, VIL, separate VIH and VIL for 3.3V and 2.5V I/O.
*B
114095
05/30/02
GLC
1) Added “I” temp
2) Added automatic power down to features.
3) Added ZZ mode to characteristics.
4) Added ZZ mode timing waveform.
5) Changed nomenclature for ISB.
6) Updated latch-up current.
7) Added static discharge voltage.
Document #: 38-05161 Rev. *B
Description of Change
Page 31 of 31

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