A8837 Photoflash Capacitor Charger with IGBT Driver Features and Benefits Description ▪ Power with 1 Li+ or 2 Alkaline/NiMH/NiCAD batteries ▪ Eight-level, digitally-programmable current limits from 700 mA to 2 A ▪ Voltage sensing feedback before output diode for low leakage ▪ Adjustable output voltage ▪ No primary-side Schottky diode needed ▪ Integrated IGBT driver with trigger ▪ Charge complete indication ▪ >75% efficiency ▪ Low-profile (0.75 mm high) 3 mm × 3 mm MLP/TDFN 10-contact package The A8837 is a highly integrated IC that charges photoflash capacitors for digital and film cameras. An integrated MOSFET switch drives the transformer in a flyback topology. It also features an integrated IGBT driver that facilitates the flash discharge function and saves board space. Package: 10-contact TDFN/MLP (suffix EJ) The CHARGE pin enables the A8837 and starts the charging of the output capacitor. When the designated output voltage is reached, the A8837 stops the charging until the CHARGE pin ¯ pin is an open-drain indicator of is toggled again. The D̄¯¯ Ō¯¯N̄¯Ē when the designated output voltage is reached. The peak current limit can be adjusted to eight different levels between 700 mA and 2 A, by clocking the CHARGE pin. This allows the user to operate the flash even at low battery voltages. The A8837 can be used with two Alkaline/NiMH/NiCAD or one single-cell Li+ battery connected to the transformer primary. Connect the VIN pin to a 3.0 to 5.5 V supply, which can be either the system rail or the Li+ battery, if used. The A8837 is available in a very low profile (0.75 mm) 10-contact 3 mm × 3 mm MLP/TDFN package, making it ideal for space-constrained applications. It is lead (Pb) free, with 100% matte-tin leadframe plating. Applications include the following: Approximate Scale ▪ Digital camera flash ▪ Film camera flash ▪ Cell phone flash ▪ Emergency strobe light Typical Applications VBATT 1.5 to 5.5 V + VBIAS 3.0 to 5.5 V N =10.2 T1 D1 R1 R4 150 k7 1% C1 0.1 μF 100 k7 VOUT COUT 100 μF 330 V R2 VIN CHARGE R5 C1 0.1 μF R3 1.20 k7 1% TRIGGER IGBTDRV GND To IGBT Gate R5 Figure 1. Typical circuit with separate power supply to transformer A8837-DS 150 k7 SW A8837 10 k7 FB R3 1.20 k7 DONE C1, C2: X5R or X7R, 10 V 10 k7 R1 150 k7 R2 VIN CHARGE FB C2 4.7 μF D1 100 k7 DONE R6 T1 R4 150 k7 1% SW A8837 10 k7 VBIAS 3.0 to 5.5 V TRIGGER R6 IGBTDRV GND To IGBT Gate 10 k7 Figure 2. Typical circuit with single power supply VOUT COUT A8837 Photoflash Capacitor Charger with IGBT Driver Selection Guide Part Number A8837EEJTR-T Package Packing* 10-pin TDFN/MLP *Contact Allegro for additional packing options 1500 pieces/ 7-in. reel Absolute Maximum Ratings Characteristic Symbol SW pin Notes Rating Units V VSW –0.3 to 40 VIGBTDRV –0.3 to VIN + 0.3 V FB pin VFB –0.3 to VIN V All other pins VX Operating Ambient Temperature TA Maximum Junction Temperature TJ(max) 150 ºC Tstg –55 to 150 ºC IGBTDRV pin Storage Temperature Range E –0.3 to 7 V –40 to 85 ºC Package Thermal Characteristics Characteristic Package Thermal Resistance Symbol RθJA Test Conditions* 4layer PCB, based on JEDEC standard Rating Units 45 ºC/W *Additional information is available on the Allegro website. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 2 A8837 Photoflash Capacitor Charger with IGBT Driver Functional Block Diagram SW VIN Control Logic DCM Detector (dV/dt = 0) 18 μs HmL Triggered Timer 40 V DMOS Q S SET Q R CMP2 CLR Q ILIM Comparator CHARGE Adjustable Reference ILIM Decoder Enable Q Q SET CLR S FB R CMP1 1.2 V DONE VIN TRIGGER One-Shot GND IGBTDRV Device Pin-out Diagram Terminal List Table Number 1,10 Name NC Function No connection NC 1 10 NC IGBTDRV 2 9 FB VIN 3 8 DONE 3 VIN Power supply input GND 4 7 TRIGGER CHARGE 5 6 SW 4 GND Device ground 5 CHARGE 6 SW 2 7 IGBTDRV IGBT driver gate drive output Charging enable and ISWLIM code input; set to low to power-off the A8837 Switch, internally connected to the DMOS power FET drain TRIGGER Strobe signal input 8 ¯N̄¯Ē¯ D̄¯Ō 9 FB Open drain, when pulled low by internal MOSFET, indicates that charging target level has been reached Output voltage feedback Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 3 A8837 Photoflash Capacitor Charger with IGBT Driver ELECTRICAL CHARACTERISTICS TA = 25°C and VIN = 3.3 V (unless otherwise noted) Characteristics Symbol Min. Typ. 3 – – – 1.8 – – – – – – – – – – – – 2 – 20 0.2 – 1.5 1 0.01 2.0 1.8 1.6 1.4 1.2 1 0.86 0.7 0.27 – 18 18 – – – – – 5.5 – 10 1 2.2 – – – – – – – – 1 – – 1 – 0.8 – – V mA μA μA A A A A A A A A Ω μA μs μs μA V V μs μs tILIM(L) 0.2 – – μs tILIM(SU) – 54 – μs D̄¯Ō ¯N̄¯Ē ¯ Output Leakage Current* IDONELKG – – 1 μA D̄¯Ō ¯N̄¯Ē ¯ Output Low Voltage* FB Voltage Threshold* FB Input Current UVLO Enable Threshold UVLO Hysteresis IGBT Driver IGBTDRV On Resistance to VIN IGBTDRV On Resistance to GND TRIGGER Input Current VDONE(L) – – 100 mV Supply Voltage* VIN Supply Current IIN Primary Side Current Limit (ILIM clock input at CHARGE pin) SW On Resistance SW Leakage Current* SW Maximum Off-Time SW Maximum On-Time CHARGE Input Current CHARGE Input Voltage* ILIM Clock High Time at CHARGE Pin ILIM Clock Low Time at CHARGE Pin Total ILIM Setup Time TRIGGER Input Voltage* ISWLIM1 ISWLIM2 ISWLIM3 ISWLIM4 ISWLIM5 ISWLIM6 ISWLIM7 ISWLIM8 RDS(On)SW ISWLKG tOFF(Max) tON(Max) ICHARGE VCHARGE(H) VCHARGE(L) tILIM1(H) tILIM(H) VFB IFB VUVLO Test Conditions Charging Charging done Shutdown (VCHARGE = 0 V, VTRIGGER = 0 V) VIN = 3.3 V, ID = 800 mA VSW = 35 V VCHARGE = VIN Initial pulse Subsequent pulses 32 μA into D̄¯Ō ¯N̄¯Ē¯ pin 1.187 – 2.55 – VFB = 1.205 V VIN rising VUVLOHYS RDS(On)I-V RDS(On)I-G ITRIGGER VTRIGGER(H) VTRIGGER(L) tDr tDf tr tf VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = VIN VIN = 3.3 V, VIGBTDRV = 1.5 V, VTRIGGER = 0 V VTRIGGER = VIN Propagation Delay, Rising Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V Propagation Delay, Falling Output Rise Time Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V Output Fall Time Rgate=12 Ω, CLOAD = 6500 pF, VIN = 3.3 V Minimum dV/dt for dV/dt Measured at SW pin ZVS Comparator *Guaranteed by design and characterization over operating temperature range, –40°C to 85°C. Max. Units 1.205 1.223 –120 – 2.65 2.75 150 – V nA V mV – – – 2 – – – – – 5 6 – – – 30 30 70 70 – – 1 – 0.8 – – – – Ω Ω μA V V ns ns ns ns – 30 – V/μs Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 4 A8837 Photoflash Capacitor Charger with IGBT Driver Operation Timing Diagram VUVLO VIN CHARGE SW Target VOUT VOUT DONE TRIGGER IGBTDRV A C B D E F Explanation of Events: A. Start charging by pulling CHARGE to high, provided that VIN is above the VUVLO level. B. Charging stops when VOUT reaches the target voltage. D̄¯Ō ¯N̄¯Ē¯ goes low, to signal the completion of the charging process. C. Start a new charging process with a low-to-high transition at the CHARGE pin. D. Pull CHARGE to low, to put the controller in low-power standby mode. E. Charging does not start, because VIN is below VUVLO level when CHARGE goes high. F. After VIN goes above VUVLO, another low-to-high transition at the CHARGE pin is required to start charging. IGBT Drive Timing Definition TRIGGER 50% tDr IGBTDRV 10% 50% tr tDf 90% 90% tf 10% Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 5 A8837 Photoflash Capacitor Charger with IGBT Driver Performance Characteristics IGBT Drive waveforms are measured with R-C load (12 Ω, 6800 pF) IGBT Drive Performance tr Rising Signal VIGBTDRV Symbol C2 C3 t Conditions Parameter VIGBTDRV VTRIGGER time Parameter tDr tr CLOAD Rgate Units/Division 1V 1V 50 ns Value 22.881 ns 63.125 ns 6800 pF 12 Ω C2 VTRIGGER C3 t tf Falling Signal Symbol C2 C3 t Conditions Parameter VIGBTDRV VTRIGGER time Parameter tDf tf CLOAD Rgate Units/Division 1V 1V 50 ns Value 27.427 ns 65.529 ns 6800 pF 12 Ω C2 VIGBTDRV C3 VTRIGGER t Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 6 A8837 Photoflash Capacitor Charger with IGBT Driver Functional Description Overview The A8837 is a photoflash capacitor charger control IC with adjustable input current limiting. It also integrates an IGBT driver for strobe operation of the flash tube, dramatically saving board space in comparison to discrete solutions for strobe flash operation. The control logic is shown in the functional block diagram. The charging operation of the A8837 is started by a low-to-high signal on the CHARGE pin, provided that VIN is above VUVLO level. If CHARGE is already high before VIN reaches VUVLO , another low-to-high transition on the CHARGE pin is required to start the charging. The primary peak current is set by input clock signals from the CHARGE pin. When a charging cycle is initiated, the transformer primary side current, IPrimary, ramps up linearly at a rate determined by the combined effect of the battery voltage, VBATT , and the primary side inductance, LPrimary. When IPrimary reaches the current limit, ISWLIM , the internal MOSFET is turned off immediately, allowing the energy to be pushed into the photoflash capacitor, COUT, from the secondary winding. The secondary side current drops linearly as COUT charges. The switching cycle starts again, either after the transformer flux is reset, or after a predetermined time period, tOFF(Max) (18 μs), whichever occurs first. The output voltage, VOUT, is sensed by a resistor string, R1, R2 , and R3 (see application circuit diagrams), connected across the transformer secondary winding. This resistor string forms a voltage divider that feeds back to the FB pin. The resistors must be sized to achieve a desired output voltage level based on a typical value of 1.205 V at the FB pin. As soon as VOUT reaches the desired value, the charging process is terminated. Toggling the CHARGE pin can start a refresh operation. input voltages. The battery life can be effectively extended by setting a lower current limit at low battery voltages. Figure 4 shows the ILIM clock timing scheme protocol. The total ILIM setup time, tILIM(SU) , denotes the time needed for the decoder circuit to receive ILIM inputs and set ISWLIM . Apply current limit pulses during tILIM(SU) (54 μs) period. Figure 5 shows the timing definition of the primary current limiting circuit. At the end of the setup period, tILIM(SU) , primary t ILIM(H) ≥ 0.2 μs t ILIM(L) ≥ 0.2 μs Clock input at CHARGE pin t ILIM1(H) = min. first pulse width t ILIM(SU) = ILIM setup time Subsequent rising edges (0 to 7) First rising edge 0 μs Switching starts 54 μs 20 μs Figure 4. ILIM Clock Timing Definition Start ILIM counter Reset ILIM counter CHARGE Four rising edges within t ILIM(SU) ISWLIM4 = 1.4 A I SW Switching starts Input Current Limiting The peak current limit can be adjusted to eight different levels, from 700 mA to 2.0 A, by clocking the CHARGE pin. An internal digital circuit decodes the input clock signals to a counter, which sets the charging time. This flexible scheme allows the user to operate the flash circuit according to different battery 0 μs 20 μs Switching stops 54 μs Figure 5. Current Limit Programming Example (ISWLIM4 selected). Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 7 A8837 Photoflash Capacitor Charger with IGBT Driver current starts to ramp up to the set ISWLIM. The ISWLIM setting remains in effect as long as the CHARGE pin is high. To reset the ILIM counter, pull the CHARGE pin low before clocking in the new setting. After the first start-up or an ILIM counter reset, each new current limit can be set by sending a burst of pulses to the CHARGE pin. The first rising edge starts the ILIM counter, and up to 8 rising edges will be counted to set the ISWLIM level. The first pulse width, tILIM1(H), must be at least 20 μs long. Subsequent pulses (up to 7 more) can be as short as 0.2 μs. The last low-to-high edge must arrive within 54 μs from the first edge. The CHARGE pin will stay high afterwards. Figure 6 shows the last charging cycle, when the CHARGE pin is forced low before charging has been completed. The A8837 implements an adaptive off-time, tOFF , control. After the switch is turned off, a sensing circuit tracks the flyback voltage at the SW node. A special dV/dt detection circuit is used to allow minimum-voltage switching, even if the SW voltage does not drop to zero volts. This enables fast-charging to start earlier than previously possible, thereby reducing the overall charging time. However, when the photoflash capacitor charger circuit starts up at low output voltage, a timeout may be triggered to limit the maximum switch off-time to 18 μs. VCHARGE VSW ISWLIM = 2.0 A ISW VCHARGE VSW ISWLIM = 1.8 A ISW VCHARGE VSW ISWLIM = 1.6 A VCHARGE ISW VSW VCHARGE VSW ISWLIM = 1.4 A ISW ISW Figure 6. Last charging cycle, when the CHARGE pin is forced low before charging is complete. Figure 7. ILIM programming waveforms for various ISWLIM; VIN = 3.3 V, VBAT = 2.0 V, VCHARGE 5 V/div, VSW 2 V/div, ISW 500 mA/div, time scale 10 μs/div. Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 8 A8837 Photoflash Capacitor Charger with IGBT Driver Applications Information Transformer Design Turns Ratio. The minimum transformer turns ratio, N, (Second- ary : Primary) should be chosen based on the following formula: VOUT + VD_Drop N≥ 40 − VBATT (1) where: VOUT (V) is the required output voltage level, VD_Drop (V) is the forward voltage drop of the output diode(s), VBATT (V) is the transformer battery supply, and 40 (V) is the rated voltage for the internal MOSFET switch, representing the maximum allowable reflected voltage from the output to the SW pin. For example, if VBATT is 3.5 V and VD_Drop is 1.7 V (which could be the case when two high voltage diodes were in series), and the desired VOUT is 320 V, then the turns ratio should be at least 8.9. In a worst case, when VBATT is highest and VD_Drop and VOUT are at their maximum tolerance limit, N will be higher. Taking VBATT = 5.5 V, VD_Drop = 2 V, and VOUT = 320 V × 102 % = 326.4 V as the worst case condition, N can be determined to be 9.5. In practice, always choose a turns ratio that is higher than the calculated value to give some safety margin. In the worst case example, a minimum turns ratio of N = 10 is recommended. Primary Inductance. As a loose guideline when choosing the primary inductance, LPrimary (μH), use the following formula: 300 × 10−9 × VOUT N × ISWLIM LPrimary ≥ . (2) Ideally, the charging time is not affected by transformer primary inductance. In practice, however, it is recommended that a primary inductance be chosen between 10 μH and 20 μH. When LPrimary is lower than 10 μH, the converter operates at higher frequency, which increases switching loss proportionally. This leads to lower efficiency and longer charging time. When LPrimary is greater than 20 μH, the rating of the transformer must be dramatically increased to handle the required power density, and the series resistances are usually higher. A design that is optimized to achieve a small footprint solution would have an LPrimary of 12 to 14 μH, with minimized leakage inductance and secondary capacitance, and minimized primary and secondary series resistance. See the table Recommended Components for more information. Recommended Components Component C1, Input Capacitor C2, Input Capacitor Rating 0.1 μF, ±10%, 16 V X7R ceramic capacitor (0603) 4.7 μF, ±10%, 10 V, X5R ceramic capacitor (0805) Part Number Source GRM188R71C104KA01D Murata LMK212BJ475KG Taiyo Yuden COUT, Photoflash Capacitor 330 V 100 μF (or 19 to 180 μF) EPH-331ELL101B131S Chemi-Con D1, Output Diode 2 x 250 V, 225 mA, 5 pF Philips Semiconductor, Fairchild Semiconductor BAV23S Instead of two resistors, a single 300 kΩ resistor with 350 V rating can be used 150 kΩ each 1/4 W, ± 1%; R1, R2, FB Resistors 1206, 0805, or 0603 resistors rated for 150 V R3, FB Resistor T1, Transformer Remarks 10 V minimum rating can be used 1.2 kΩ 1/10 W ±1% (0603 or 0402) LP = 14.2 μH, IP = 2 A, N = 10 T-15-154M Tokyo Coil Suitable for ILIM from 0.7 to 2.0 A LP = 7.4 μH, IP = 2 A, N = 10 T-16-103A Tokyo Coil Suitable for ILIM from 1.2 to 2.0 A only LP = 14 μH, IP = 1.5 A, N=10 ST-652956A Asatech Suitable for ILIM from 0.7 to 1.4 A only Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com 9 A8837 Photoflash Capacitor Charger with IGBT Driver Leakage Inductance and Secondary Capacitance. The trans- Output Diode Selection former design should minimize the leakage inductance to ensure the turn-off voltage spike at the SW node does not exceed the 40 V limit. An achievable minimum leakage inductance for this application, however, is usually compromised by an increase in parasitic capacitance. Furthermore, the transformer secondary capacitance should be minimized. Any secondary capacitance is multiplied by N 2 when reflected to the primary, leading to high initial current swings when the switch turns on, and to reduced efficiency. Choose the rectifying diode(s), D1, to have small parasitic capacitance (short reverse recovery time) while satisfying the reverse voltage and forward current requirements. The peak reverse voltage of the diode, VD_Peak , occurs when the internal MOSFET switch is closed, and the primary-side current starts to ramp-up. It can be calculated as: VD_ Peak = VOUT + N × VBATT . (4) The peak current of the rectifying diode, ID_Peak, is calculated as: Adjusting Output Voltage The A8436 senses output voltage during switch off-time. This allows the voltage divider network, R1 through R3, to be connected at the anode of the high voltage output diode, D1, eliminating power loss due to the feedback network when charging is complete. The output voltage can be adjusted by selecting proper values of the voltage divider resistors. Use the following equation to calculate values for Rx (Ω): R1 + R2 VOUT = −1 . R3 VFB (3) R1 and R2 together need to have a breakdown voltage of at least 300 V. A typical 1206 surface mount resistor has a 150 V breakdown voltage rating. It is recommended that R1 and R2 have similar values to ensure an even voltage stress between them. Recommended values are: R1 = R2 = 150 kΩ (1206) R3 = 1.2 kΩ (0603) which together yield a stop voltage of 303 V. Using higher resistance values for R1, R2, and R3 does not offer significant efficiency improvement, because the power loss of the feedback network occurs mainly during switch off-time, and because the off-time is only a small fraction of each charging cycle. ID_ Peak = IPrimary_Peak / N . (5) Input Capacitor Selection Ceramic capacitors with X5R or X7R dielectrics are recommended for the input capacitor, C2. It should be rated at least 4.7 μF / 6.3 V to decouple the battery input, VBATT , at the primary of the transformer. When using a separate bias, VBIAS , for the A8837 VIN supply, connect at least a 0.1 μF / 6.3 V bypass capacitor to the VIN pin. Layout Guidelines Key to a good layout for the photoflash capacitor charger circuit is to keep the parasitics minimized on the power switch loop (transformer primary side) and the rectifier loop (secondary side). Use short, thick traces for connections to the transformer primary and SW pin. Output voltage sensing circuit elements must be kept away from switching nodes such as SW pin. Make sure that there is no ground plane underneath R1 and R2, because parasitic capacitance to ground will affect sensing accuracy. It is important that the D̄¯Ō¯N̄¯Ē¯ signal trace and other signal traces be routed away from the transformer and other switching traces, in order to minimize noise pickup. In addition, high voltage isolation rules must be followed carefully to avoid breakdown failure of the circuit board. 10 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com A8837 Photoflash Capacitor Charger with IGBT Driver Package EJ, 10-Contact TDFN/MLP 0.30 3.00 ±0.15 0.85 0.50 10 10 3.00 ±0.15 1.65 3.10 A 1 2 1 11X D SEATING PLANE 0.08 C +0.05 0.25 –0.07 C C 2.38 PCB Layout Reference View 0.75 ±0.05 0.50 1 For Reference Only (reference JEDEC MO-229WEED) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 2 0.40 ±0.10 1.65 B 10 2.38 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 SON50P300X300X80-11WEED3M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) Copyright ©2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com