ON NB3N551DR2G 3.3 v / 5.0 v ultra-low skew 1:4 clock fanout buffer Datasheet

NB3N551
3.3 V / 5.0 V
Ultra−Low Skew
1:4 Clock Fanout Buffer
Description
The NB3N551 is a low skew 1−to 4 clock fanout buffer, designed
for clock distribution in mind. The NB3N551 specifically guarantees
low output−to−output skew. Optimal design, layout and processing
minimize skew within a device and from device to device.
The output enable (OE) pin three−states the outputs when low.
Features
MARKING
DIAGRAMS*
8
SOIC−8
D SUFFIX
CASE 751
8
1
3N551
ALYW
G
1
Input/Output Clock Frequency up to 180 MHz
Low Skew Outputs (50 ps typical)
Output goes to Three−State Mode via OE
Operating Range: VDD = 3.0 V to 5.5 V
Ideal for Networking Clocks
Packaged in 8−pin SOIC
Industrial Temperature Range
These are Pb−Free Devices
3N551
A
L
Y
W
G
DFN8
MN SUFFIX
CASE 506AA
1
6K
M
G
Q1
Q2
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
6K MG
G
•
•
•
•
•
•
•
•
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1
4
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
CLK
*For additional marking information, refer to
Application Note AND8002/D.
Q3
Q4
PIN CONNECTIONS
ICLK
OE
Q1
Figure 1. Block Diagram
Q2
Q3
1
8
2
7
3
6
4
5
OE
VDD
GND
Q4
ORDERING INFORMATION
Device
Package
Shipping†
NB3N551DG
SOIC−8
(Pb−Free)
98 Units/Rail
NB3N551DR2G
SOIC−8
(Pb−Free)
2500/Tape & Reel
NB3N551MNR4G
DFN−8
(Pb−Free)
1000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2006
October, 2006 − Rev. 2
1
Publication Order Number:
NB3N551/D
NB3N551
OE
Function
0
Disable
1
Enable
Table 1. OE, Output Enable Function
PIN DESCRIPTION
Pin #
Name
Type
Description
1
ICLK
(LV)CMOS/(LV)TTL Input
2
Q1
(LV)CMOS/(LV)TTL Output
Clock Output 1
3
Q2
(LV)CMOS/(LV)TTL Output
Clock Output 2
4
Q3
(LV)CMOS/(LV)TTL Output
Clock Output 3
5
Q4
(LV)CMOS/(LV)TTL Output
Clock Output 4
6
GND
Power
Negative supply voltage; Connect to ground, 0 V
7
VDD
Power
Positive supply voltage (3.0 V to 5.5 V)
8
OE
(LV)CMOS/(LV)TTL Input
Clock Input. Internal pull−up resistor.
Output Enable for the clock outputs. Outputs are enabled when HIGH or when left
open; OE pin has internal pull−up resistor. Three−states outputs when LOW.
MAXIMUM RATINGS
Symbol
VDD
VI/VO
Parameter
Positive Power Supply
Input/Output Voltage
Condition 1
Condition 2
Rating
Units
GND = 0 V
−
7.0
V
t ≤ 1.5 ns
−
GND–1.5 ≤ VI/VO ≤ VDD+1.5
V
TA
Operating Temperature Range, Industrial
−
−
≥ −40 to ≤ +85
_C
Tstg
Storage Temperature Range
−
−
−65 to +150
_C
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
SOIC−8
190
130
_C/W
_C/W
qJC
Thermal Resistance (Junction−to−Case)
(Note 1)
SOIC−8
41 to 44
_C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 LFPM
500 LFPM
DFN−8
DFN−8
129
84
_C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
ATTRIBUTES
Characteristic
ESD Protection
Value
Human Body Model
Machine Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 2)
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
Level 1
UL−94 code V−0 @ 0.125 in
531 Devices
Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test
2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
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2
NB3N551
DC CHARACTERISTICS (VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Characteristic
Symbol
IDD
Power Supply Current @ 135 MHz, No Load, VDD = 3.3 V
VOH
Output HIGH Voltage – IOH = −25 mA, VDD = 3.3 V
VOL
Output LOW Voltage – IOL = 25 mA
VOH
Output HIGH Voltage – IOH = −12 mA (CMOS level)
Min
Typ
Max
Unit
−
20
40
mA
2.4
−
−
V
−
−
0.4
V
VDD − 0.4
−
−
V
VIH, ICLK
Input HIGH Voltage, ICLK
(VDD/2)+0.7
−
3.8
V
VIL, ICLK
Input LOW Voltage, ICLK
−
−
(VDD/2)−0.7
V
VIH, OE
Input HIGH Voltage, OE
2.0
−
VDD
V
VIL, OE
Input LOW Voltage, OE
0
−
0.8
V
ZO
Nominal Output Impedance
−
20
−
W
RPU
Input Pull−up Resistor, OE
−
220
−
kW
CIN
Input Capacitance, OE
−
5.0
−
pF
IOS
Short Circuit Current
−
± 50
−
mA
Min
Typ
Max
Unit
−
50
95
mA
2.4
−
−
V
−
−
0.4
V
VDD – 0.4
−
−
V
DC CHARACTERISTICS (VDD = 4.5 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Characteristic
Symbol
IDD
Power Supply Current @ 135 MHz, No Load, VDD = 5.0 V
VOH
Output HIGH Voltage – IOH = −35 mA
VOL
Output LOW Voltage – IOL = 35 mA
VOH
Output HIGH Voltage – IOH = −12 mA (CMOS level)
VIH, ICLK
Input HIGH Voltage, ICLK
(VDD/2) + 1
−
5.5
V
VIL, ICLK
Input LOW Voltage, ICLK
−
−
(VDD/2) − 1
V
VIH, OE
Input HIGH Voltage, OE
2.0
−
VDD
V
VIL, OE
Input LOW Voltage, OE
0
−
0.8
V
ZO
Nominal Output Impedance
−
20
−
W
RPU
Input Pull−up Resistor, OE
−
220
−
kW
CIN
Input Capacitance, OE
−
5.0
−
pF
IOS
Short Circuit Current
−
±80
−
mA
AC CHARACTERISTICS (VDD = 3.0 V to 5.5 V, GND = 0 V, TA = −40°C to +85°C) (Note 3)
Symbol
Min
Typ
Max
Unit
Input Frequency
−
−
180
MHz
Period Jitter (RMS, 1σ)
−
2.0
−
ps
tr/tf
Output rise and fall times; 0.8 V to 2.0 V
−
0.5
1.0
ns
tpd
Propagation Delay, CLK to Qn, 0 − 180 MHz, (Note 4)
1.5
3.0
6.0
ns
−
50
160
ps
fin
tjitter (pd)
tskew
Characteristic
Output−to−output skew; (Note 5)
3. Outputs loaded with external RL = 33−W series resistor and CL = 15 pF to GND for proper operation. Duty cycle out = duty in. A 0.01 mF
decoupling capacitor should be connected between VDD and GND. A 33 W series terminating resistor may be used on each clock output
if the trace is longer than 1 inch.
4. Measured with rail−to−rail input clock.
5. Measured on rising edges at VDD ÷ 2.
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3
NB3N551
PACKAGE DIMENSIONS
−X−
SOIC−8 NB
CASE 751−07
ISSUE AG
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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4
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NB3N551
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
TOP VIEW
0.08 C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.20
−−−
0.25
0.35
A
0.10 C
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
(A3)
SIDE VIEW
A1
C
D2
e
e/2
4
1
8X
L
E2
K
8
5
8X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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NB3N551/D
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