AD AD9154-FMC-EBZ Quad, 16-bit, 2.4 gsps, txdac digital-to-analog converter Datasheet

Quad, 16-Bit, 2.4 GSPS, TxDAC+®
Digital-to-Analog Converter
AD9154
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
QUAD MOD
ADRF6720-27
DAC
RF
OUTPUT
0°/90° PHASE
SHIFTER
JESD204B
LPF
SYNCOUTx±
DAC
LO_IN
SYSREF
QUAD DAC
MOD_SPI
QUAD MOD
ADRF6720-27
DAC
RF
OUTPUT 1
0°/90° PHASE
SHIFTER
JESD204B
LPF
SYNCOUTx±
DAC
AD9154
LO_IN
MOD_SPI
DAC DAC
CLOCK SPI
APPLICATIONS
11389-101
Supports input data rates up to 1 GSPS
Proprietary, low spurious and distortion design
Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc at
180 MHz IF
Six carrier GSM IMD = 78 dBc, 600 kHz carrier spacing at
180 MHz IF
SFDR = 72 dBc at 180 MHz IF, −6 dBFS single tone
Flexible 8-lane JESD204B interface
Multiple chip synchronization
Fixed latency
Data generator latency compensation
Input signal power detection
High performance, low noise phase-locked loop (PLL) clock
multiplier
Digital inverse sinc filter
Digital quadrature modulation using a numerically
controlled oscillator (NCO)
Nyquist band selection—mix mode
Selectable 1×, 2×, 4×, and 8× interpolation filters
Low power: 2.11 W at 1.6 GSPS, full operating conditions
88-lead, exposed pad LFCSP
Figure 1.
Wireless communications
Multicarrier LTE and GSM base stations
Wideband repeaters
Software defined radios
Wideband communications
Point to point microwave radio
Transmit diversity, multiple input/multiple output (MIMO)
Instrumentation
Automated test equipment
GENERAL DESCRIPTION
The AD9154 is a quad, 16-bit, high dynamic range digital-toanalog converter (DAC) that provides a maximum sample rate
of 2.4 GSPS, permitting multicarrier generation up to the Nyquist
frequency in baseband mode. The AD9154 includes features
optimized for direct conversion transmit applications, including
complex digital modulation, input signal power detection, and
gain, phase, and offset compensation. The DAC outputs are
optimized to interface seamlessly with the ADRF6720-27 radio
frequency quadrature modulator (AQM) from Analog Devices,
Inc. In mix mode, the AD9154 DAC can reconstruct carriers in
the second and third Nyquist zones. A serial port interface (SPI)
provides the programming/readback of internal parameters.
The full-scale output current can be programmed over a range
Rev. B
of 4 mA to 20 mA. The AD9154 is available in two different
88-lead LFCSP packages.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
Ultrawide signal bandwidth enables emerging wideband
and multiband wireless applications.
Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
JESD204B Subclass 1 support simplifies multichip
synchronization.
Small package size with a 12 mm × 12 mm footprint.
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Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9154
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Link Latency Setup ..................................................................... 30
Applications ....................................................................................... 1
Crossbar Setup ............................................................................ 32
Functional Block Diagram .............................................................. 1
JESD204B Serial Data Interface .................................................... 33
General Description ......................................................................... 1
JESD204B Overview .................................................................. 33
Product Highlights ........................................................................... 1
Physical Layer ............................................................................. 34
Revision History ............................................................................... 3
Data Link Layer .......................................................................... 37
Detailed Functional Block Diagram .............................................. 4
Transport Layer .......................................................................... 45
Specifications..................................................................................... 5
JESD204B Test Modes ............................................................... 58
DC Specifications ......................................................................... 5
JESD204B Error Monitoring..................................................... 59
Digital Specifications ................................................................... 6
Digital Datapath ............................................................................. 62
Maximum DAC Update Rate Speed Specifications by Supply .... 7
Dual Paging ................................................................................. 62
JESD204B Serial Interface Speed Specifications ...................... 7
Data Format ................................................................................ 62
SYSREF to DAC Clock Timing Specifications ......................... 8
Interpolation Modes .................................................................. 62
Digital Input Data Timing Specifications ................................. 8
Digital Modulation ..................................................................... 63
Latency Variation Specifications ................................................ 9
Inverse Sinc ................................................................................. 64
JESD204B Interface Electrical Specifications ........................... 9
Digital Gain, Phase Adjust, DC Offset, and Group Delay .... 64
AC Specifications........................................................................ 10
I to Q Swap .................................................................................. 65
Absolute Maximum Ratings .......................................................... 11
NCO Alignment ......................................................................... 65
Thermal Resistance .................................................................... 11
Downstream Protection ............................................................ 66
ESD Caution ................................................................................ 11
Datapath PRBS ........................................................................... 68
Pin Configuration and Function Descriptions ........................... 12
DC Test Mode ............................................................................. 69
Typical Performance Characteristics ........................................... 14
Interrupt Request Operation ........................................................ 70
Terminology .................................................................................... 20
Interrupt Service Routine .......................................................... 70
Theory of Operation ...................................................................... 21
DAC Input Clock Configurations ................................................ 72
Serial Port Operation ..................................................................... 22
Driving the CLK± Inputs .......................................................... 72
Data Format ................................................................................ 22
DAC PLL Fixed Register Writes ............................................... 72
Serial Port Pin Descriptions ...................................................... 22
Condition Specific Register Writes .......................................... 72
Serial Port Options ..................................................................... 22
Starting the PLL .......................................................................... 73
Chip Information ............................................................................ 24
Analog Outputs............................................................................... 75
Device Setup Guide ........................................................................ 25
Transmit DAC Operation.......................................................... 75
Step 1: Start Up the DAC ........................................................... 25
Normal and Mix Modes of Operation ..................................... 76
Step 2: Digital Datapath ............................................................. 26
Temperature Sensor ....................................................................... 77
Step 3: Transport Layer .............................................................. 26
Example Start-Up Sequence .......................................................... 78
Step 4: Physical Layer ................................................................. 27
Step 1: Start Up the DAC ........................................................... 78
Step 5: Data Link Layer .............................................................. 28
Step 2: Digital Datapath ............................................................. 78
Step 6: Error Monitoring ........................................................... 28
Step 3: Transport Layer .............................................................. 79
DAC PLL Setup ............................................................................ 28
Step 4: Physical Layer ................................................................. 79
Interpolation ............................................................................... 29
Step 5: Data Link Layer.............................................................. 80
JESD204B Setup .......................................................................... 29
Step 6: Error Monitoring ........................................................... 80
Equalization Mode Setup .......................................................... 30
Board Level Hardware Considerations ........................................ 81
Rev. B | Page 2 of 124
Data Sheet
AD9154
Power Supply Recommendations .............................................81
Register Details ................................................................................ 91
JESD204B Serial Interface Inputs (SERDIN0± to SERDIN7±) .81
Outline Dimensions ......................................................................123
Register Summary ...........................................................................84
Ordering Guide .............................................................................124
REVISION HISTORY
7/15—Rev. A to Rev. B
Changes to General Description Section ....................................... 1
Changes to Figure 33 ......................................................................19
Added Figure 34; Renumbered Sequentially ...............................19
Changes to Figure 43 ......................................................................35
Changes to SERDES PLL Fixed Register Writes Section ...........36
Change to Table 87 ..........................................................................79
Change to ERRWINDOW, Table 93 ............................................95
Updated Outline Dimensions ......................................................123
Changes to Ordering Guide .........................................................123
3/15—Rev. 0 to Rev. A
Changes to Figure 1 and General Description Section ................ 1
2/15—Revision 0: Initial Version
Rev. B | Page 3 of 124
AD9154
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
DACCLK
SERDES
PLL
HB1
OUT3+
COMPLEX
MODULATION
HB3
HB2
I GAIN
PHASE
ADJUST
DACCLK
I OFFSET
OUT2+
÷4, ÷8
HB3
HB2
FSC
HB1
OUT2–
COMPLEX
MODULATION
HB3
HB2
OUT1+
FSC
PDP0
SERDIN0±
HB1
INV SINC
SERDIN7±
NCO
MODE CONTROL
OUT3–
Q OFFSET
fDAC
CLOCK DATA RECOVERY
AND CLOCK FORMATTER
VTT
INV SINC
PDP1
FSC
Q GAIN
NCO
MODE CONTROL
Q GAIN
I GAIN
OUT1–
Q OFFSET
PHASE
ADJUST
DACCLK
I OFFSET
fDAC
HB1
PDP OUT0
PDP OUT1
FSC
SERIAL
I/O PORT
POWER-ON
RESET
DAC
ALIGN
DETECT
CLK_SEL
CONFIG
REGISTERS
CLOCK DISTRIBUTION
AND
CONTROL LOGIC
DACCLK
OUT0–
REF
AND
BIAS
SYSREF
RCVR
CLK
RCVR
I120
SYSREF+
SYSREF–
CLK+
CLK–
11389-001
DAC PLL
TXEN1
IRQ
TXEN0
PLL_LOCK
RESET
SYNCOUT1+
SYNCOUT1–
OUT0+
÷4, ÷8
HB3
SYNCHRONIZATION
LOGIC
SDO
SDIO
SCLK
CS
SYNCOUT0+
SYNCOUT0–
HB2
Figure 2. Detailed Functional Block Diagram
Rev. B | Page 4 of 124
Data Sheet
AD9154
SPECIFICATIONS
DC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Gain Error
Offset Error1
I/Q Gain Mismatch
Full-Scale Output Current
Maximum Setting
Minimum Setting
Output Compliance Range
Output Resistance
Output Capacitance
Full-Scale Current DAC Monotonicity
MAIN DAC TEMPERATURE DRIFT
Gain2
REFERENCE
Internal Reference Voltage
ANALOG SUPPLY VOLTAGES
AVDD33
PVDD12
CVDD12
DIGITAL SUPPLY VOLTAGES
SIOVDD33
VTT
DVDD12
SVDD12
IOVDD
POWER CONSUMPTION
2× Interpolation Mode, JESD204B
Mode 4, Dual Link, 8 SERDES Lanes
AVDD33
PVDD12
CVDD12
SVDD12
DVDD12
SIOVDD33 + IOVDD
1
2
Test Conditions/Comments
Min
Typ
16
Max
±4.3
±8.2
With internal reference
−8.0
−3.0
Unit
Bits
LSB
LSB
−3.01
2322
+0.54
+8.0
20.85
4.17
2.8
15
3.0
Guaranteed
21.3
4.4
3.37
+3.0
% FSR
ppm
% FSR
Based on a 4 kΩ external resistor between I120 and ground
19.9
3.9
2.0
mA
mA
V
MΩ
pF
−114
ppm/°C
1.2
V
5%
5%
2%
5%
2%
3.13
1.14
1.274
1.14
1.274
3.3
1.2
1.3
1.2
1.3
3.47
1.26
1.326
1.26
1.326
V
V
V
V
V
5%
3.13
1.1
1.14
1.274
1.14
1.274
1.71
3.3
1.2
1.2
1.3
1.2
1.3
1.8
3.47
1.37
1.26
1.326
1.26
1.326
3.47
V
V
V
V
V
V
V
2.11
2.63
W
159
152
355
541.9
264.5
10.6
185
174
397
682
442
11.4
mA
mA
mA
mA
mA
mA
5%
2%
5%
2%
5%
fDAC = 1.6 GSPS, NCO on, IFOUT = 40 MHz, PLL on, DAC
full-scale current = 20 mA
Includes VTT
Offset error is a measure of how far from full-scale range (FSR) the DAC output current is at 25°C (in ppm).
Gain drift is a measure of the slope of the DAC output current across its full temperature range (in ppm/°C).
Rev. B | Page 5 of 124
AD9154
Data Sheet
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
Low
Symbol
CMOS OUTPUT LOGIC LEVEL
Output Voltage (VOUT) Logic
High
Low
MAXIMUM DAC UPDATE RATE1
ADJUSTED DAC UPDATE RATE
INTERFACE4
Number of JESD204B Lanes
JESD204B Serial Interface Speed
Minimum
Maximum
DAC CLOCK INPUT (CLK±)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Maximum Clock Rate, DAC Clock
Sourced Directly from CLK±
PLL Multiplier Mode Clock Input
Frequency5
SYSREF INPUT (SYSREF±)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
SYSREF± Frequency6
SYSREF± TO DAC CLOCK7
Setup Time
Hold Time
SPI
Maximum Clock Rate
Minimum SCLK Pulse Width
High
Low
SDIO to SCLK
Setup Time
Hold Time
SDO to SCLK
Data Valid Window
Test Conditions/Comments
Min
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
0.7 × IOVDD
1.8 V ≤ IOVDD ≤ 3.3 V
1.8 V ≤ IOVDD ≤ 3.3 V
1× interpolation2 (see Table 4)
2× interpolation3
4× interpolation
8× interpolation
1× interpolation
2× interpolation
4× interpolation
8× interpolation
0.7 × IOVDD
Typ
Max
Unit
0.3 × IOVDD
V
V
0.3 × IOVDD
V
V
1096
2192
2400
2400
1096
1096
600
300
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
MSPS
8
Per lane
Per lane, SVDD12 = 1.3 V ± 2%
Lanes
1.44
Gbps
Gbps
2000
mV
mV
MHz
1000
MHz
2000
2000
fDATA/(K × (F/S))
mV
mV
Hz
10.96
400
Self biased input, ac-coupled
1000
600
2400
6.0 GHz ≤ fVCO ≤ 12.0 GHz
35
400
0
1000
SYSREF± differential swing = 0.4 V,
slew rate = 1.3 V/ns, (ac-coupled, and
0 V, 0.6 V, 1.25 V, 2.0 V dc-coupled
common-mode voltages)
tSSD
tHSD
SCLK
See timing diagrams shown in
Figure 39 and Figure 40
IOVDD = 1.8 V
111
145
ps
ps
10
MHz
tPWH
tPWL
8
12
tDS
tDH
tDV
Rev. B | Page 6 of 124
ns
ns
5
2
ns
ns
25
ns
Data Sheet
Parameter
CS to SCLK
Setup Time
Hold Time
AD9154
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
5
2
tSCS
tHCSCS
ns
ns
1
See Table 3 for detailed specifications for DAC update rate conditions.
Maximum speed for 1× interpolation is limited by the JESD204B interface. See Table 4 for details.
3
Maximum speed for 2× interpolation is limited by the JESD204B interface. See Table 4 for details.
4
See Table 4 for detailed specifications for JESD204B speed conditions.
5
CLK+/CLK− serve as a reference oscillator input for the on-chip PLL clock multiplier when in use.
6
K, F, and S are JESD204B transport layer parameters. See Table 42 for the full definitions.
7
See Table 5 for detailed specifications for SYSREF to DAC clock timing conditions.
2
MAXIMUM DAC UPDATE RATE SPEED SPECIFICATIONS BY SUPPLY
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,
VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
MAXIMUM DAC UPDATE RATE
Test Conditions/Comments
DVDD12, CVDD12, PVDD12 = 1.2 V ± 5%
DVDD12, CVDD12, PVDD12 = 1.2 V ± 2%
DVDD12, CVDD12, PVDD12 = 1.3 V ± 2%
Min
1.93
2.07
2.4
Typ
Max
Unit
GSPS
GSPS
GSPS
JESD204B SERIAL INTERFACE SPEED SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 4.
Parameter
CLOCK AND DATA RECOVERY
(CDR) HALF RATE MODE
CDR FULL RATE MODE
CDR OVERSAMPLING MODE
Test Conditions/Comments
SVDD12 = 1.2 V ± 5%
Min
5.74
SVDD12 = 1.2 V ±2%
SVDD12 = 1.3 V ± 2%
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ±2%
SVDD12 = 1.3 V ± 2%
SVDD12 = 1.2 V ± 5%
SVDD12 = 1.2 V ±2%
SVDD12 = 1.3 V ± 2%
5.74
5.74
2.87
2.87
2.87
1.44
1.44
1.44
Rev. B | Page 7 of 124
Typ
Max
9.04
Unit
Gbps
9.65
10.96
4.79
4.93
5.73
2.39
2.50
2.93
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
Gbps
AD9154
Data Sheet
SYSREF TO DAC CLOCK TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, SYSREF± common-mode voltages = 0.0 V, 0.6 V, 1.25 V, and 2.0 V, unless otherwise noted.
Table 5.
Parameter
SYSREF
Setup Time
Hold Time
Setup Time
Hold Time
Setup Time
Hold Time
Test Conditions/Comments
Differential swing = 0.4 V, slew rate = 1.3 V/ns
AC-coupled
DC-coupled
AC-coupled
DC-coupled
Differential swing = 0.7 V, slew rate = 2.28 V/ns
AC-coupled
DC-coupled
AC-coupled
DC-coupled
Differential swing = 1.0 V, slew rate = 3.26 V/ns
AC-coupled
DC-coupled
AC-coupled
DC-coupled
Min
Typ
Max
Unit
89
111
105
145
ps
ps
ps
ps
71
81
97
118
ps
ps
ps
ps
58
64
92
108
ps
ps
ps
ps
DIGITAL INPUT DATA TIMING SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,
VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 6.
Parameter
LATENCY
Interface, Excluding Transport
Layer Delay Buffer
Interpolation
1×
2×
4×
8×
Inverse Sinc
Fine Modulation
Coarse Modulation
fS/8
fS/4
Digital Phase Adjust
Digital Gain Adjust
Power-Up Time
Dual A Only
Dual B Only
All DACs
1
Test Conditions/Comments
Min
Typ
Max
Unit
17
PClock1 cycles
94
130
250
474
17
20
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
8
4
12
12
DAC clock cycles
DAC clock cycles
DAC clock cycles
DAC clock cycles
30
30
30
µs
µs
µs
With or without modulation
Register 0x011 from 0x60 to 0x00
Register 0x011 from 0x18 to 0x00
Register 0x011 from 0x78 to 0x00
PClock is the AD9154 internal processing clock running at the JESD204B lane rate ÷ 40.
Rev. B | Page 8 of 124
Data Sheet
AD9154
LATENCY VARIATION SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,
VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 7.
Parameter
DAC LATENCY VARIATION
Subclass 1
PLL Off
PLL On
Test Conditions/Comments
Min
Typ
Max
Unit
0
1
+1
DACCLK cycles
DACCLK cycles
−1
JESD204B INTERFACE ELECTRICAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,
VTT = 1.2 V, TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 8.
Parameter
JESD204B DATA INPUTS
Input Leakage Current
Logic High
Logic Low
Unit Interval
Common-Mode Voltage
Symbol
Differential Voltage
VTT Source Impedance
Differential Impedance
Differential Return Loss
Common-Mode Return Loss
DIFFERENTIAL OUTPUTS (SYNCOUT±)2
Output Offset Voltage
DETERMINISTIC LATENCY
Fixed
Variable
SYSREF± TO LOCAL MULTIFRAME
CLOCK (LMFC) DELAY
R_VDIFF
ZTT
ZRDIFF
RLRDIF
RLRCM
1
2
3
Test Conditions/Comments
Min
Max
Unit
94
−0.05
714
+1.85
µA
µA
ps
V
110
1050
30
120
mV
Ω
Ω
dB
dB
1.27
V
17
2
PClock3 cycles
PClock3 cycles
DAC clock cycles
TA = 25°C
Input level = 1.2 V ± 0.25 V, VTT = 1.2 V
Input level = 0 V
UI
VRCM
AC-coupled
VTT = SVDD121
At dc
At dc
10
−4
80
VOS
Typ
100
8
6
1.19
4
As measured on the input side of the ac coupling capacitor.
IEEE Standard 1596.3 LVDS compatible.
PClock is the AD9154 internal processing clock; its frequency is equal to the JESD204B lane rate ÷ 40.
Rev. B | Page 9 of 124
AD9154
Data Sheet
AC SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V,
VTT = 1.2 V, TA = 25°C, IOUTFS = 20 mA, unless otherwise noted.
Table 9.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
TWO-TONE THIRD INTERMODULATION DISTORTION (IMD)
fDAC = 983.04 MSPS
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
NOISE SPECTRAL DENSITY (NSD), SINGLE TONE
fDAC = 983.04 MSPS
fDAC = 1966.08 MSPS
5 MHz BW LTE FIRST ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
5 MHz BW LTE SECOND ACLR, SINGLE CARRIER
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
fDAC = 1966.08 MSPS
Test Conditions/Comments
−6 dBFS single tone
fOUT = 20 MHz
fOUT = 150 MHz
fOUT = 180 MHz
−6 dBFS
fOUT = 30 MHz
fOUT = 150 MHz
fOUT = 30 MHz
fOUT = 180 MHz
0 dBFS
fOUT = 150 MHz
fOUT = 180 MHz
0 dBFS, PLL off
fOUT = 50 MHz
fOUT = 150 MHz
fOUT = 180 MHz
0 dBFS, PLL off
fOUT = 50 MHz
fOUT = 150 MHz
fOUT = 180 MHz
Rev. B | Page 10 of 124
Min
Typ
Max
Unit
76
73
72
dBc
dBc
dBc
87
77
86
78
dBc
dBc
dBc
dBc
−164
−163
dBm/Hz
dBm/Hz
79
77
77
dBc
dBc
dBc
82
81
81
dBc
dBc
dBc
Data Sheet
AD9154
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 10.
Parameter
I120 to Ground
SERDINx±, VTT, SYNCOUTx±, and
TXENx
OUTx±
SYSREF±
CLK± to Ground
RESET, IRQ, CS, SCLK, SDIO, SDO,
and PDP OUTx to Ground
LDO_BYP1
LDO_BYP2
Ambient Operating Temperature (TA)
Junction Temperature
Storage Temperature
Rating
−0.3 V to AVDD33 + 0.3 V
−0.3 V to SIOVDD33 + 0.3 V
−0.3 V to AVDD33 + 0.3 V
GND − 0.5 V
−0.3 V to PVDD12 + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to SVDD12 + 0.3 V
−0.3 V to PVDD12 + 0.3 V
−40°C to +85°C
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The exposed pad (EPAD) must be soldered to the ground plane
for the 88-lead LFCSP. The EPAD provides an electrical,
thermal, and mechanical connection to the board.
Typical θJA, θJB, and θJC values are specified for a 4-layer, JESD51-7
high effective thermal conductivity test board for leaded
surface-mount packages. θJA is obtained in still air conditions
(JESD51-2). Airflow increases heat dissipation, effectively reducing
θJA. θJB is obtained following double-ring cold plate test conditions
(JESD51-8). θJC is obtained with the test case temperature monitored at the bottom of the exposed pad.
ΨJT and ΨJB are thermal characteristic parameters obtained with
θJA in still air test conditions.
Junction temperature (TJ) can be estimated using the following
equations:
TJ = TT + (ΨJT × P),
or
TJ = TB + (ΨJB × P)
where:
TT is the temperature measured at the top of the package.
P is the total device power dissipation.
TB is the temperature measured at the board.
Table 11. Thermal Resistance
Package
88-Lead LFCSP1
1
θJA
22.6
θJB
5.59
θJC
1.17
ΨJT
0.1
ΨJB
5.22
The exposed pad must be securely connected to the ground plane.
ESD CAUTION
Rev. B | Page 11 of 124
Unit
°C/W
AD9154
Data Sheet
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
LDO_BYP2
CVDD12
I120
AVDD33
OUT+
OUT0–
AVDD33
CVDD12
AVDD33
OUT1–
OUT1+
AVDD33
CVDD12
AVDD33
OUT2+
OUT2–
AVDD33
CVDD12
AVDD33
OUT3–
OUT3+
AVDD33
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
AD9154
TOP VIEW
(Not to Scale)
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
IOVDD
CS
SCLK
SDIO
SDO
RESET
IRQ
PDP OUT0
PDP OUT1
PVDD12
PVDD12
DNC
DNC
DVDD12
SERDIN7+
SERDIN7–
SVDD12
SERDIN6+
SERDIN6–
SVDD12
VTT
SVDD12
NOTES
1. THE EXPOSED PAD MUST BE SECURELY CONNECTED TO THE GROUND PLANE.
2. DNC = DO NOT CONNECT.
11389-002
SYNCOUT0+
SYNCOUT0–
VTT
SERDIN2+
SERDIN2–
SVDD12
SERDIN3+
SERDIN3–
SVDD12
SVDD12
SVDD12
LDO_BYP1
SIOVDD33
SVDD12
SERDIN4–
SERDIN4+
SVDD12
SERDIN5–
SERDIN5+
VTT
SYNCOUT1–
SYNCOUT1+
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
PVDD12
CLK+
CLK–
PVDD12
SYSREF+
SYSREF–
PVDD12
PVDD12
PVDD12
PVDD12
TXEN0
TXEN1
DVDD12
DVDD12
SERDIN0+
SERDIN0–
SVDD12
SERDIN1+
SERDIN1–
SVDD12
VTT
SVDD12
Figure 3. Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
1, 4, 7, 8, 9, 10,
56, 57
2
Mnemonic
PVDD12
Description
1.2 V Clock Supplies.
CLK+
3
CLK−
5
SYSREF+
6
SYSREF−
11
12
13, 14, 53
15
TXEN0
TXEN1
DVDD12
SERDIN0+
16
SERDIN0−
17, 20, 22, 28,
31, 32, 33, 36,
39, 45, 47, 50
18
SVDD12
PLL Reference/Clock Input, Positive. When the PLL is used, this pin is the positive reference clock input.
When the PLL is not used, this pin is the positive device clock input. This pin is self biased and must be
ac-coupled.
PLL Reference/Clock Input, Negative. When the PLL is used, this pin is the negative reference clock input.
When the PLL is not used, this pin is the negative device clock input. This pin is self biased and must be
ac-coupled.
Timing Reference Input, Positive. This pin is used in JESD204B Subclass 1 systems and is self biased,
ac-coupled, or dc-coupled.
Timing Reference Input, Negative. This pin is used in JESD204B Subclass 1 systems and is self biased,
ac-coupled, or dc-coupled.
Transmit enable for DAC0 and DAC1. CMOS levels are determined with respect to IOVDD.
Transmit Enable for DAC2 and DAC3. CMOS levels are determined with respect to IOVDD.
1.2 V Digital Supplies.
Serial Channel Input 0, Positive. CML compliant. SERDIN0+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 0, Negative. CML compliant. SERDIN0− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V JESD204B Receiver Supplies.
19
SERDIN1−
21, 25, 42, 46
VTT
SERDIN1+
Serial Channel Input 1, Positive. CML compliant. SERDIN1+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 1, Negative. CML compliant. SERDIN1− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
1.2 V Termination Voltage Pins.
Rev. B | Page 12 of 124
Data Sheet
AD9154
Pin No.
23
24
26
Mnemonic
SYNCOUT0+
SYNCOUT0−
SERDIN2+
27
SERDIN2−
29
SERDIN3+
30
SERDIN3−
34
35
37
LDO_BYP1
SIOVDD33
SERDIN4−
38
SERDIN4+
40
SERDIN5−
41
SERDIN5+
43
44
48
SYNCOUT1−
SYNCOUT1+
SERDIN6−
49
SERDIN6+
51
SERDIN7−
52
SERDIN7+
54, 55
58
59
60
61
62
63
64
65
66
67, 70, 72, 75,
77, 80, 82, 85
68
69
71, 76, 81, 87
73
74
78
79
83
84
86
88
DNC
PDP OUT1
PDP OUT0
IRQ
RESET
SDO
SDIO
SCLK
CS
IOVDD
AVDD33
Description
Positive LVDS Synchronization Output Signal for Channel Link 0.
Negative LVDS Synchronization Output Signal for Channel Link 0.
Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 2, Negative. CML compliant. SERDIN2− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 3, Negative. CML compliant. SERDIN3− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
LDO SERDES Bypass. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground.
SERDES Ports Input/Output Supply.
Serial Channel Input 4, Negative. CML compliant. SERDIN4− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 4, Positive. CML compliant. SERDIN4+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 5, Negative. CML compliant. SERDIN5− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 5, Positive. CML compliant. SERDIN5+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Negative LVDS Synchronization Output Signal for Channel Link 1.
Positive LVDS Synchronization Output Signal for Channel Link 1.
Serial Channel Input 6, Negative. CML compliant. SERDIN6− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 6, Positive. CML compliant. SERDIN6+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 7, Negative. CML compliant. SERDIN7− is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Serial Channel Input 7, Positive. CML compliant. SERDIN7+ is internally terminated to the VTT pin voltage
using a calibrated 50 Ω resistor. This pin is ac-coupled only.
Do Not Connect. Do not connect to this pin.
Power Detection and Protection (PDP) Indicator for DAC2 and DAC3.
PDP Indicator for DAC0 and DAC1.
Interrupt Request (Active Low, Open Drain).
Reset (Active Low). CMOS levels with are determined with respect to IOVDD.
Serial Port Data Output. CMOS levels with are determined with respect to IOVDD.
Serial Port Data Input/Output. CMOS levels with are determined with respect to IOVDD.
Serial Port Clock Input. CMOS levels with are determined with respect to IOVDD.
Serial Port Chip Select (Active Low). CMOS levels with are determined with respect to IOVDD.
CMOS Input/Output and SPI Pin Supply.
3.3 V Analog Supplies for the DAC Cores.
OUT3+
OUT3−
CVDD12
OUT2−
OUT2+
OUT1+
OUT1−
OUT0−
OUT0+
I120
LDO_BYP2
EPAD
DAC3 Positive Current Output.
DAC3 Negative Current Output.
1.2 V Clock Supplies.
DAC2 Negative Current Output.
DAC2 Positive Current Output.
DAC1 Positive Current Output.
DAC1 Negative Current Output.
DAC0 Negative Current Output.
DAC0 Positive Current Output.
Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 kΩ resistor from this pin to ground.
LDO Clock Bypass for the DAC PLL. Tie a 1 Ω resistor in series with a 1 µF capacitor from this pin to ground.
Exposed Pad. The exposed pad must be securely connected to the ground plane.
Rev. B | Page 13 of 124
AD9154
Data Sheet
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–80
–80
–90
–90
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 4. Single Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over
fDAC = 1966.08 MHz and 1228.80 MHz, All Four DAC Outputs
–100
0
–10
IN-BAND SECOND HARMONIC (dBc)
–10
–40
–50
–60
–70
–80
200
300
400
500
600
700
800
900
1000
Figure 7. Single Tone SFDR vs. fOUT in the First Nyquist Zone over Digital Back Off,
fDAC = 1966.08 MHz
0
–30
100
fOUT (MHz)
0
–20
0dBFS
–6dBFS
–12dBFS
–15dBFS
–30
–40
–50
–60
–70
–80
–90
0
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
–100
11389-105
–100
Figure 5. Single Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over
fDAC = 1474.56 MHz and 983.04 MHz, All Four DAC Outputs
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
11389-108
–90
–20
Figure 8. In-Band Second Harmonic vs. fOUT in the First Nyquist Zone over
Digital Back Off, fDAC = 1966.08 MHz
0
0
–10
–10
–30
IN-BAND THIRD HARMONIC (dBc)
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1474.56MHz
fDAC = 1966.08MHz
–20
–40
–50
–60
–70
–80
–20
–40
–50
–60
–70
–80
–90
–100
100
200
300
400
500
600
fOUT (MHz)
700
800
900
1000
11389-106
–90
–100
0
Figure 6. Single Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over
fDAC = 1966.08 MHz, 1474.56 MHz, 1228.8 MHz, and 983.04 MHz
Rev. B | Page 14 of 124
0dBFS
–6dBFS
–12dBFS
–15dBFS
–30
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 9. In-Band Third Harmonic vs. fOUT in the First Nyquist Zone,
fDAC = 1966.08 MHz
11389-109
SFDR (dBc)
–50
–70
0
SFDR (dBc)
–40
–70
–100
0dBFS
–6dBFS
–12dBFS
–15dBFS
11389-107
SFDR (dBc)
0
11389-104
SFDR (dBc)
TYPICAL PERFORMANCE CHARACTERISTICS
AD9154
0
0
–10
–10
–20
20mA
10mA
4mA
–40
–50
–60
–60
–70
–80
–90
–90
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
Figure 10. In-Band Second Harmonic vs. fOUT in the
First Nyquist Zone over Analog Full-Scale Current, fDAC = 1966.08 MHz
–100
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 13. Two-Tone Third Harmonic (IMD3) vs. fOUT over Digital Backoff
0
0
–10
–10
–20
–20
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
–100
0
100
200
300
20mA
10mA
4mA
–30
IMD3 (dBc)
–30
400
500
600
700
800
900
1000
fOUT (MHz)
Figure 11. In-Band Third Harmonic vs. fOUT in the First Nyquist Zone over
Analog Full-Scale Current, fDAC = 1966.08 MHz
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
11389-114
20mA
10mA
4mA
11389-111
IN-BAND THIRD HARMONIC (dBc)
–50
–80
–100
Figure 14. Two-Tone Third Harmonic (IMD3) vs. fOUT over Analog Full-Scale
Current, fDAC = 1966.08 MHz
0
–130
–10
–135
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1474.56MHz
fDAC = 1966.08MHz
–30
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1474.56MHz
fDAC = 1966.08MHz
–140
NSD (dBm/Hz)
–20
IMD3 (dBc)
–40
–70
0
0dBFS
–6dBFS
–12dBFS
–15dBFS
–30
IMD3 (dBc)
–30
11389-113
–20
11389-110
IN-BAND SECOND HARMONIC (dBc)
Data Sheet
–40
–50
–60
–145
–150
–155
–70
–160
–80
0
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
–170
11389-112
–100
Figure 12. Two-Tone Third Harmonic (IMD3) vs. fOUT, fDAC = 1966.08 MHz,
1474.56 MHz, 1228.8 MHz, and 983.04 MHz
0
100
200
300
400
500
600
fOUT (MHz)
700
800
900
1000
11389-115
–165
–90
Figure 15. Single Tone (0 dBFS) NSD vs. fOUT over fDAC = 1966.08 MHz,
1474.56 MHz, 1228.8 MHz, and 983.04 MHz at 70 MHz
Rev. B | Page 15 of 124
AD9154
Data Sheet
–130
–40
–45
–135
–145
–150
–155
–160
–165
–55
PLL OFF
PLL ON
–60
–65
–70
–75
–80
100
200
300
400
–90
11389-116
0
500
fOUT (MHz)
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
11389-119
–85
–170
Figure 19. 1-Channel (1C) 5 MHz BW LTE, First Adjacent ACLR vs. fOUT,
PLL On and Off
Figure 16. Single Tone (0 dBFS) NSD vs. fOUT over fDAC,
20 MHz Offset from Carrier
–40
–130
–45
–135
–145
SECOND ADJACENT ACLR (dBc)
0dBFS
–6dBFS
–12dBFS
–15dBFS
–140
NSD (dBm/Hz)
–50
–150
–155
–160
–165
–50
–55
PLL OFF
PLL ON
–60
–65
–70
–75
–80
–85
0
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
–90
11389-117
–170
Figure 17. Single Tone NSD vs. fOUT over Digital Back Off, fDAC = 1966.08 MHz,
Measured at 70 MHz
0
100
200
300
400
500
600
700
800
900
1000
fOUT (MHz)
11389-120
NSD (dBm/Hz)
–140
FIRST ADJACENT ACLR (dBc)
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1474.56MHz
fDAC = 1966.08MHz
Figure 20. 1C 5 MHz BW LTE, Second Adjacent ACLR vs. fOUT, PLL On and Off
–130
0
–10
–135
–20
–140
(10dB/DIV)
NSD (dBm/Hz)
–30
PLL OFF
PLL ON
–145
–150
–40
–50
–60
–155
–70
–160
–80
0
100
200
300
400
500 600
fOUT (MHz)
700
800
900
1000
11389-118
–100
–170
Figure 18. Single Tone NSD vs. fOUT, fDAC = 1966.08 MHz, Measured at 70 MHz,
PLL On and Off
Rev. B | Page 16 of 124
CENTER 180.550MHz
#RES BW 3.0kHz
VBW 3.0kHz
SPAN 10.00MHz
SWEEP 22.80ms (1001PTS)
Figure 21. Two-Tone, Third IMD Performance, IF = 180 MHz,
fDAC = 1966.08 MHz
11389-121
–90
–165
–85
–115
–115
–125
SPAN 44.5MHz
SWEEP 144.3ms
11389-122
–105
VBW 300kHz
CENTER 175MHz
#RES BW 30kHz
–77.2dBc
–77.2dBc
–75.8dBc
–13.1dBm
–76.2dBc
–20
–77.4dBc
–10
–45
–77.3dBc
–73.3dBc
–73.5dBc
–61.4dBc
0.0dBc
–61.4dBc
–24.0dBm
VBW 300kHz
SPAN 54.5MHz
SWEEP 2s
Figure 25. 2-Channel (2C) 5 MHz BW with 5 MHz Gap,
LTE ACLR Performance, IF = 180 MHz, fDAC = 1966.08 MHz
(Total LTE Carrier Power is 20.982 dBm)
–35
–30
–40
(10dB/DIV)
–75
–85
–95
–50
–60
–70
–90
–100
–110
–25
–20
–35
–30
–45
–40
–55
–50
–65
–75
Figure 24. Single Tone fDAC = 1966.08 MHz, fOUT = 280 MHz, −14 dBFS
–125
CENTER 180MHz
#RES BW 10kHz
#VBW 100kHz
SPAN 10MHz
#SWEEP 1s
11389-127
STOP 2.0GHz
SWEEP 54.20ms (1001PTS)
–83.86dBc
–115
–82.59dBc
–100
–78.51dBc
–105
11389-124
–95
–90
–22.864dBm
–85
–80
VBW 30kHz
STOP 2.000GHz
SWEEP 54.20ms (1001PTS)
–23.146dBm
–70
–22.658dBm
–60
–22.899dBm
(10dB/DIV)
–10
START 0Hz
#RES BW 30kHz
VBW 30kHz
Figure 26. Single Tone SFDR fDAC = 1966.08 MHz, 4× Interpolation,
fOUT = 10 MHz, −14 dBFS
Figure 23. 1C 20 MHz BW LTE ACLR Performance, IF = 180 MHz,
fDAC = 1966.08 MHz
–110
START 0Hz
#RES BW 30kHz
–22.809dBm
SPAN 140MHz
SWEEP 454.1ms
–23.093dBm
VBW 300kHz
–79.05dBc
CENTER 180MHz
#RES BW 30kHz
–82.27dBc
–135
11389-123
–115
–125
11389-126
–80
–105
–83.26dBc
–65
–65.3dBc
–135
Figure 22. 1C 5 MHz BW LTE ACLR Performance, IF = 180 MHz,
fDAC = 1966.08 MHz
–55
–73.2dBc
–95
–95
CENTER 180MHz
#RES BW 30kHz
(10dB/DIV)
–85
–105
–125
(10dB/DIV)
–75
11389-125
(10dB/DIV)
–75
–73.4dBc
–65
–65
–73.4dBc
–82.1dBc
–81.7dBc
–81.1dBc
–78.5dBc
–12.9dBm
–55
–78.8dBc
–45
–45
–81.3dBc
–35
–81.3dBc
–35
–81.6dBc
–25
–55
(10dB/DIV)
AD9154
–73.4dBc
Data Sheet
Figure 27. 6-Channel (6C) Spaced by 600 kHz GSM, Enhanced Data Rates for
GSM Evolution (EDGE) Adjacent Channel Power (ACP) IMD Performance,
IF = 180 MHz, fDAC = 1966.08 MHz
Rev. B | Page 17 of 124
AD9154
Data Sheet
140
2.4
2.2
2.0
1.8
1× INTERPOLATION
2× INTERPOLATION
4× INTERPOLATION
8× INTERPOLATION
1.6
1.4
1.0
0
500
1000
1500
2000
2500
fDAC (MHz)
80
60
40
20
0
450
400
400
SUPPLY CURRENT (mA)
500
450
350
300
250
200
1× INTERPOLATION
2× INTERPOLATION
4× INTERPOLATION
8× INTERPOLATION
100
1000
1500
2000
2500
fDAC (MHz)
500
150
500
Figure 30. Additive DVDD12 Supply Current vs. fDAC over Digital Functions
Figure 28. Total Power Consumption vs. fDAC over Interpolation
AVDD33
CVDD12
PVDD12
350
300
250
200
150
100
50
50
0
0
500
1000
1500
2000
2500
fDAC (MHz)
11389-129
DVDD12 SUPPLY CURRENT (mA)
100
0
11389-128
1.2
NCO
fDAC /4
fDAC /8
INVERSE SINC
DIGITAL GAIN,
PHASE ASDJUST,
GROUP DELAY
120
Figure 29. DVDD12 Supply Current vs. fDAC over Interpolation
0
0
500
1000
1500
2000
2500
fDAC (MHz)
Figure 31. AVDD33, CVDD12, and PVDD12 Supply Current vs. fDAC
Rev. B | Page 18 of 124
11389-131
TOTAL POWER CONSUMPTION (W)
2.6
11389-130
ADDITIVE DVDD12 SUPPLY CURRENT (mA)
2.8
Data Sheet
AD9154
60
700
80
PHASE NOISE (dBc/Hz)
600
500
400
300
200
1.3V, 8 LANES
1.3V, 4 LANES
1.3V, 2 LANES
5
6
8
7
9
LANE RATE (Gbps)
100
1k
10k
1M
100k
10M
OFFSET FREQUENCY (Hz)
120
140
–82.0dBc
–81.9dBc
–81.5dBc
–80.7dBc
–77.3dBc
–77.8dBc
–60
100
–80.3dBc
–50
–80.8dBc
–40
–13.3dBm
–30
51MHz FALSE
101MHz FALSE
201MHz FALSE
401MHz FALSE
51MHz SMA100A
(10dB/DIV)
PHASE NOISE (dBc/Hz)
80
180
10
Figure 34. Single Tone Phase Noise vs. Offset Frequency at Four Different fOUT
Rates, fDAC = 2.0 GHz, PLL On
Figure 32. Total SERDES Supply Current (SVDD12) vs. Lane Rate:
2, 4, and 8 Lanes
60
140
–81.1dBc
4
3
120
–81.3dBc
2
100
160
0
1
51MHz TRUE
101MHz TRUE
201MHz TRUE
401MHz TRUE
51MHz SMA100A
11389-234
1.2V, 8 LANES
1.2V, 4 LANES
1.2V, 2 LANES
100
11389-132
TOTAL SERDES SUPPLY CURRENT (mA)
800
–70
–80
–90
–100
–110
160
–130
100
1k
10k
100k
OFFSET FREQUENCY (Hz)
1M
10M
CENTER 180MHz
#RES BW 30kHz
11389-233
180
10
Figure 33. Single Tone Phase Noise vs. Offset Frequency at Four Different fOUT
Rates, fDAC = 2.0 GHz, PLL Off
#VBW 300kHz
SPAN 65.4MHz
SWEEP 212.1ms
11389-135
–120
Figure 35. 1C 256 Point Quadrature Amplitude Modulation (QAM) Signal
ACLR Performance, IF = 180 MHz, fDAC = 1966.08 MHz
Rev. B | Page 19 of 124
AD9154
Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Offset Error
Offset error is a measure of how far from full-scale range (FSR)
the DAC output current is at 25°C (in ppm).
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when the input is at its minimum code and the
output when the input is at its maximum code.
Output Compliance Range
The output compliance range is the range of allowable voltages
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient value (25°C) to the value at either TMIN or TMAX. For offset
and gain drift, the drift is reported in ppm of FSR per degree
Celsius.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, energy in this band
is rejected by the interpolation filters. This specification,
therefore, defines how well the interpolation filters work and
the effect of other parasitic coupling paths on the DAC output.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc)
between the measured power within a channel relative to
its adjacent channel.
Complex Image Rejection
In a single sideband upconversion, two images are created
around the second IF frequency; the desired signal is on one of
these images. The other signal is unwanted, and a complex
modulator rejects this unwanted image.
Adjusted DAC Update Rate
The adjusted DAC update rate the DAC update rate divided by
the selected interpolation factor.
Physical Lane
Physical Lane x refers to SERDINx±.
Logical Lane
Logical Lane x refers to physical lanes after optionally being
remapped by the crossbar block (Register 0x308 to
Register 0x30B).
Link Lane
Link Lane x refers to logical lanes considered per link. When
paging Link 0 (Register 0x300, Bit 2 = 0), Link Lane x = Logical
Lane x. When paging Link 1 (Register 0x300, Bit 2 = 1, dual link
only), Link Lane x = Logical Lane x + 4.
Rev. B | Page 20 of 124
Data Sheet
AD9154
THEORY OF OPERATION
The AD9154 is a 16-bit, quad DAC with a SERDES interface.
Figure 2 shows a detailed functional block diagram of the AD9154.
Eight high speed serial lanes carry data into the AD9154.
The clock for the input data is derived from the device clock (as
called out in the JESD204B specification). This device clock can
be sourced with a phase-locked loop (PLL) reference clock used
by the on-chip PLL to generate a DAC clock or a high fidelity
direct external DAC sampling clock. The device can be configured
to operate in one-, two-, four-, or eight-lane modes, depending on
the required input data rate. The quad DAC can be configured as a
dual link device with each JESD204B link providing data for a dual
DAC pair to add application flexibility.
The signal processing datapath of the AD9154 offers four
interpolation modes (1×, 2×, 4×, and 8×) through three halfband filters. An inverse sinc filter compensates for DAC output sinc
roll-off. A digital inphase and quadrature modulator upcoverts a
pair of DAC input signals to an IF frequency within the first
Nyquist zone of the DAC programmed into an NCO. Gain, phase,
dc offset, and group delay adjustments can programmably
predistort the DAC input signals to improve LO feedthrough
and unwanted sideband cancellation performance of an analog
quadrature modulator following the AD9154 in a transmitter
signal chain.
The AD9154 DAC cores provide a differential current output
with a nominal full-scale current of 20 mA. The differential
current outputs are optimized for integration with the Analog
Devices ADRF6720-27 wideband quadrature modulator. The
AD9154 has a mechanism for multichip synchronization, as
well as a mechanism for achieving deterministic latency
(latency locking). The latency for each DAC remains constant
from link establishment to link establishment. The AD9154
makes use of the JESD204B Subclass 1 SYSREF signal to
establish multichip synchronization.
The various functional blocks and the data interface must be set
up in a specific sequence for proper operation (see the Device
Setup Guide section). This data sheet describes the various
blocks of the AD9154 in detail, including descriptions of the
JESD204B interface, the control parameters, and the various
registers used to set up and monitor the device. The
recommended start-up routine reliably sets up the data link.
Rev. B | Page 21 of 124
AD9154
Data Sheet
SERIAL PORT OPERATION
The serial port interface (SPI) is a flexible, synchronous serial
communications port that allows easy interfacing with many
industry-standard microcontrollers and microprocessors. The
interface facilitates read/write access to all registers that configure
the AD9154. MSB first or LSB first transfer formats are supported.
The SPI is configurable as a 4-wire interface or a 3-wire interface
in which the input and output share a single-pin I/O, SDIO.
SDO 62
SCLK 64
SPI
PORT
11389-027
SDIO 63
CS 65
Figure 36. SPI Pins
There are two phases to a communication cycle with the AD9154.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first 16 SCLK rising
edges. The instruction word provides the serial port controller
with information regarding the data transfer cycle, Phase 2 of
the communication cycle. The Phase 1 instruction word defines
whether the upcoming data transfer is a read or write, along
with the starting register address for the following data transfer.
A logic high on the CS pin, followed by a logic low, resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next 16 rising SCLK edges represent the
instruction bits of the current input/output (I/O) operation.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the device and the system controller. Phase 2 of the
communication cycle is a transfer of one or more data bytes.
Eight × N SCLK cycles are needed to transfer N bytes during
the transfer cycle. Registers change immediately upon writing to
the last bit of each transfer byte, except for the frequency tuning
word (FTW) and numerically controlled oscillator (NCO)
phase offsets, which change only when the frequency tuning
word FTW_UPDATE_REQ bit is set.
DATA FORMAT
The instruction byte contains the information shown in Table 13.
Table 13. Serial Port Instruction Word
I15 (MSB)
R/W
I[14:0]
A[14:0]
R/W, Bit 15 of the instruction word, determines whether a read
or a write data transfer occurs after the instruction word write.
Logic 1 indicates a read operation, and Logic 0 indicates a write
operation.
A14 to A0, Bit 14 to Bit 0 of the instruction word, determine the
register accessed during the data transfer portion of the
communication cycle. For multibyte transfers, A[14:0] is the
starting address. The device generates the remaining register
addresses based on the address increment bits. If the address
increment bits are set high (Register 0x000, Bit 5 and Bit 2),
multibyte SPI writes start on A[14:0] and increment by 1 every
eight bits sent/received. If the address increment bits are set to 0,
the address decrements by 1 every eight bits.
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin synchronizes data to and from the device
and runs the internal state machines. The maximum frequency
of SCLK is specified in Table 2. All data input is registered on the
rising edge of SCLK. All data is driven out on the falling edge of
SCLK.
Chip Select (CS)
An active low input starts and gates a communication cycle.
It allows the use of more than one device on the same serial
communications lines. The SDIO pin goes to a high impedance
state when this input is high. During the communication cycle,
chip select must stay low.
Serial Data I/O (SDIO)
This pin is a bidirectional data line. In 4-wire mode, this pin
acts as the data input and SDO acts as the data output.
SERIAL PORT OPTIONS
The serial port can support both MSB first and LSB first data
formats. The LSB first bits (Register 0x000, Bit 6 and Bit 1)
control this functionality. The default is MSB first (the LSB first
bits = 0).
When the LSB first bits = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. R/W is followed by
A[14:0] as the instruction word, and D[7:0] is the data-word.
When the LSB first bits = 1 (LSB first), the opposite is true.
A[0:14] is followed by R/W, which is subsequently followed by
D[0:7].
The serial port supports a 3-wire or 4-wire interface. When the
SDO active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire
interface with a separate input pin (SDIO) and output pin
(SDO) is used. When the SDO active bits = 0, the SDO pin is
unused and the SDIO pin is used for both input and output.
Rev. B | Page 22 of 124
Data Sheet
AD9154
bits = 1, the multicycle addresses are incremented. When the
address increment bits = 0, the addresses are decremented. A
new write cycle can always be initiated by bringing CS high and
then low again.
Multibyte data transfers can be performed as well. Hold the CS
pin low for multiple data transfer cycles (eight SCLKs) after the
first data transfer word following the instruction cycle. The first
eight SCLKs following the instruction cycle read from or write
to the register provided in the instruction cycle. For each
additional eight SCLK cycles, the address is either incremented
or decremented and the read/write occurs on the new register.
Set the direction of the address using the address increment bits
(Register 0x000, Bit 5 and Bit 2). When the address increment
During writes to Register 0x0000 only, the chip tests the first
nibble following the address phase, ignoring the second nibble.
This is completed independently from the LSB first bit and
ensures that there are extra clock cycles following the soft reset
bits (Register 0x000, Bit 0 and Bit 7).
DATA TRANSFER CYCLE
INSTRUCTION CYCLE
CS
SDIO
R/W A14 A13
A3
A2 A1
A0 D7N D6N D5N
D30 D20 D10 D00
11389-028
SCLK
Figure 37. Serial Register Interface Timing, MSB First, Address Increment Bits = 0
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SDIO
A0
A1 A2
A12 A13 A14 R/W D00 D10 D20
D4N D5N D6N D7N
11389-029
SCLK
Figure 38. Serial Register Interface Timing, LSB First, Address Increment Bits = 1
CS
SCLK
SDIO
DATA BIT n
11389-139
tDV
DATA BIT n – 1
Figure 39. Timing Diagram for Serial Port Register Read
tSCS
tHCS
CS
tPWH
tPWL
tDS
SDIO
tDH
INSTRUCTION BIT 15
INSTRUCTION BIT 14
INSTRUCTION BIT 0
Figure 40. Timing Diagram for Serial Port Register Write
Rev. B | Page 23 of 124
11389-140
SCLK
AD9154
Data Sheet
CHIP INFORMATION
Register 0x003 to Register 0x006 contain chip information, as shown in Table 14.
Table 14. Chip Information
Information
Chip Type
Product ID
Product Grade
Device Revision
Description
The product is a high speed DAC represented by a code of 0x04 in Register 0x003.
8 MSBs in Register 0x005 and 8 LSBs in Register 0x004. The product ID is 0x9154.
Register 0x006, Bits[7:4]. The product grade is 0x8.
Register 0x006, Bits[3:0]. The device revision is 0x9.
Rev. B | Page 24 of 124
Data Sheet
AD9154
DEVICE SETUP GUIDE
Follow these steps to properly set up the AD9154:
STEP 1: START UP THE DAC
1.
This section describes how to set up the SPI interface, power up
necessary circuit blocks, as well as the required writes to the
configuration registers, and how to set up the DAC clocks.
2.
3.
4.
5.
6.
7.
Set up the SPI interface, power up necessary circuit blocks,
make required writes to the configuration registers, and set
up the DAC clocks (see Step 1: Start Up the DAC).
Set the digital features of the AD9154 (see Step 2: Digital
Datapath).
Set up the JESD204B links (see Step 3: Transport Layer).
Set up the physical layer of the SERDES interface (see Step 4:
Physical Layer).
Set up the data link layer of the SERDES interface (see Step 5:
Data Link Layer).
Check for errors (see Step 6: Error Monitoring).
Enable any additional datapath features needed as
described in Table 19.
A specific working start-up sequence example is given in the
Example Start-Up Sequence section.
The register writes listed in Table 15 to Table 22 are necessary
writes to set up the AD9154. Consider printing out this setup
guide and filling in the Value column with appropriate variable
values for the conditions of the desired application.
The value notation 0x without a specified value setting indicates
register settings that must be filled in by the user. To fill in the
unknown register values, select the correct settings for each
variable listed in the Variable column of Table 15 to Table 22.
The Description column describes how to set variables, or
provides a link to a section where this procedure is described.
Register settings with specified values are fixed settings to be
used in all cases.
A variable is noted by concatenating multiple terms. For
example, PdDACs is a variable corresponding to the value that
is determined for Register 0x011[6:3] in the Device Setup Guide
section.
Table 15. Power-Up and DAC Initialization Settings
Addr.
0x000
0x000
0x011
Bit
No.
7
[6:3]
0x080
1
Variable
PdDACs
[7:6]
PdClocks
0x1
0x
0x081
1
Value1
0xBD
0x3C
0x
0
DUTY_EN
PdSysref
Description
Soft reset.
Deassert reset, set 4-wire SPI.
Power-up band gap.
PdDACs = 0 if all four DACs are
being used. If not, see the DAC
Power-Down Setup section.
PdClocks = 0 if all four DACs are
being used. If not, see the DAC
Power-Down Setup section.
Always set DUTY_EN = 1
PdSysref = 0x00 for Subclass 1.
PdSysref = 0x10 for Subclass 0.
See the Subclass Setup section
for details on subclass.
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
The registers in Table 16 must be written to and the values changed
from default for the device to work correctly. These registers must
be written to after any soft reset, hard reset, or on a power-up.
Table 16. Required Device Configurations
Addr.
0x12D
0x146
0x333
Rev. B | Page 25 of 124
Value
0x8B
0x01
0x01
Description
Digital datapath configuration
Digital datapath configuration
JESD interface configuration
AD9154
Data Sheet
If using the optional DAC PLL, also set the registers in Table 17.
Table 17. Optional DAC PLL Configuration Procedure
Addr.
0x087
Value1
0x62
0x088
0xC9
0x089
0x0E
0x08A
0x08D
0x12
0x7B
0x1B0
0x00
0x1B5
0x1B9
0xC9
0x24
0x1BC
0x0D
0x1BE
0x02
0x1BF
0x8E
0x1C0
0x2A
0x1C1
0x2A
0x1C4
0x7E
0x1C5
0x08B
0x08C
0x085
Various
0x083
0x06
0x
0x
0x
0x
0x10
Variable
LODivMode
RefDivMode
BCount
LookUpVals
Description
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL CP settings
Optimal DAC LDO settings for
DAC PLL
Power DAC PLL blocks when
power machine disabled
Optimal DAC PLL VCO settings
Optimal DAC PLL calibration
options settings
Optimal DAC PLL block control
settings
Optimal DAC PLL VCO power
control settings
Optimal DAC PLL VCO calibration
settings
Optimal DAC PLL lock counter
length setting
Optimal DAC PLL charge pump
setting
Optimal DAC PLL varactor
settings
Optimal DAC PLL VCO settings
See the DAC PLL Setup section
See the DAC PLL Setup section
See the DAC PLL Setup section
See the DAC PLL Setup section
Enable DAC PLL2
Table 19. Digital Datapath Signal Processing Functions
Feature
Digital
Modulation
Inverse Sinc
Default
Off
On
Digital Gain
0 dB
Phase Adjust
Off
DC Offset
Off
Group Delay
0
Downstream
Protection
Off
Description
Modulates the data with a desired IF carrier.
See the Digital Datapath section.
Improves pass-band flatness. See the Digital
Datapath section.
Multiplies data by a factor to compensate
inverse sinc usage or balance I/Q amplitude.
See the Digital Datapath section.
Used to balance I/Q phase. See the Digital
Datapath section.
Used to cancel LO leakage. See the Digital
Datapath section.
Used to control overall latency. See the
Digital Datapath section.
Used to protect downstream components.
See the Digital Datapath section.
STEP 3: TRANSPORT LAYER
This section describes how to set up the JESD204B links. The
desired JESD204B operating mode determines the parameters.
See the JESD204B Setup section for details.
Table 20. Transport Layer Settings
Addr.
0x200
0x201
Bit
No.
0x300
Value1
0x00
0x
Variable
UnusedLanes
0x
6
CheckSumMode
3
DualLink
2
CurrentLink
1
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
2
Verify that Register 0x084[1] reads back 1 after enabling the DAC PLL to
indicate that the DAC PLL has locked.
STEP 2: DIGITAL DATAPATH
The digital datapath selects interpolation mode and the data
format. Additional digital datapath capabilities are shown in
Table 19.
0x450
0x
DID
0x451
0x
BID
0x452
0x
LID
0x453
Table 18. Digital Datapath Settings
Addr.
0x112
Bit No.
0x110
Variable
InterpMode
Description
Select the interpolation
mode; see the Interpolation
section.
0x
7
1
Value1
0x
DataFmt
DataFmt = 0 if twos
complement; DataFmt = 1
if unsigned binary.
Scrambling
[4:0]
L − 12
0x
F − 12
0x455
0x
K − 12
0x456
0x
M − 12
0x457
0x458
0x
0x
N − 12
There are a number of signal processing functions to be enabled
if needed; these are in addition to the interpolation mode.
Rev. B | Page 26 of 124
See the JESD204B Setup
section.
See the JESD204B Setup
section.
See the JESD204B Setup
section.
Set DID to match the device ID
sent by the transmitter.
Set BID to match the bank ID
sent by the transmitter.
Set LID to match the lane ID
sent by the transmitter.
0x
7
0x454
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
Description
Power up the interface.
See the JESD204B Setup
section.
5
Subclass
[4:0]
Np − 12
See the JESD204B Setup
section.
See the JESD204B Setup
section.
See the JESD204B Setup
section.
See the JESD204B Setup
section.
See the JESD204B Setup
section.
N = 16.
See the JESD204B Setup
section.
Np = 16.
Data Sheet
Addr.
0x459
Bit
No.
Value1
0x
AD9154
Variable
[7:5]
JESDVer
[4:0]
S − 12
0x45A 7
0x
HD
0x45D
0x
CF
Lane0Checksum
0x46C
0x476
0x
0x
Lanes
F
0x47D
0x
Lanes
[4:0]
Table 21. Device Configurations and Physical Layer Settings
Description
JESDVer = 1 for JESD204B,
JESDVer = 0 for JESD204A.
See the JESD204B Setup
section.
See the JESD204B Setup
section.
CF = 0
See the JESD204B Setup
section.
Deskew lanes.
See the JESD204B Setup
section.
Enable lanes. See the
JESD204B Setup section.
Addr.
0x2A7
0x2AE
0x314
0x230
If using dual link, perform writes from Register 0x300 to
Register 0x47D with CurrentLink = 0, and then repeat the same
set of register writes with CurrentLink = 1. Write to Register 0x200
and Register 0x201 only once.
STEP 4: PHYSICAL LAYER
This section describes how to set up the physical layer of the
SERDES interface. In this section, the input termination
settings are configured along with the CDR sampling and
SERDES PLL.
Value1
0x01
0x01
0x01
0x
5
[4:2]
[2:1]
0x206
0x206
0x289
2
[1:0]
1
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
2
This JESD204B link parameter is programmed in n − 1 notation as noted. For
example, if the setup requires L = 8 (8 lanes per link), program L − 1 or 7 into
Register 0x453, Bits[4:0].
Bit
No.
Halfrate
Set up the CDR; see the
SERDES Clocks Setup section
OvSmp
Set up the CDR; see the
SERDES Clocks Setup section
Reset the CDR
Release the CDR reset
0x00
0x01
0x
1
PLLDiv
0x62
0x285
0xC9
0x286
0x0E
0x287
0x28A
0x12
0x7B
0x28B
0x290
0x291
0x294
0x296
0x297
0x299
0x29A
0X29C
0x29F
0x2A0
0x280
0x268
0x00
0x89
0x4C
0x24
0x1B
0x0D
0x02
0x8E
0x2A
0x7E
0x06
0x01
0x
[7:6]
1
Description
Autotune PHY setting
Autotune PHY setting
SERDES SPI configuration
0x2
0x284
[5:0]
Variable
EqMode
0x22
SERDES PLL configuration
Set the CDR oversampling
for PLL; see the SERDES
Clocks Setup section
Optimal SERDES PLL loop
filter
Optimal SERDES PLL loop
filter
Optimal SERDES PLL loop
filter
Optimal SERDES PLL CP
Optimal SERDES PLL VCO
LDO
Optimal SERDES PLL PD
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL CP
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL PD
Optimal SERDES PLL VCO
Optimal SERDES PLL CP
Optimal SERDES PLL VCO
Configure SERDES PLL VCO
Enable SERDES PLL2
See the Equalization Mode
Setup section
Required value (default)
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register
value.
2
Verify that Register 0x281, Bit 0 reads back 1 after enabling the SERDES PLL
to indicate that the SERDES PLL has locked.
Rev. B | Page 27 of 124
AD9154
Data Sheet
STEP 5: DATA LINK LAYER
STEP 6: ERROR MONITORING
This section describes how to set up the data link layer of the
SERDES interface. This section deals with SYSREF processing,
setting deterministic latency, and establishing the link.
For JESD204B error monitoring, see the JESD204B Error
Monitoring section. For other error checks, see the Interrupt
Request Operation section.
Table 22. Data Link Layer Settings
DAC PLL SETUP
Address
0x301
Bit No.
1
Value
0x
Variable
Subclass
0x304
0x
LMFCDel
0x305
0x
LMFCDel
0x306
0x
LMFCVar
0x307
0x
LMFCVar
0x03A
0x01
0x03A
0x81
0x03A
SYSREF±
0xC1
0x308 to
0x30B
0x
XBarVals
0x334
0x
InvLanes
0x300
0x
3
CheckSum
Mode
DualLink
[1:0]
EnLinks
6
1
2
Description
See the JESD204B
Setup section.
See the Link Latency
Setup section.
See the Link Latency
section.
See the Link Latency
Setup section.
See the Link Latency
Setup section.
Set sync mode = oneshot sync; see the
Syncing LMFC Signals
section for other sync
options.
Enable the sync
machine.
Arm the sync machine.
If Subclass = 1, ensure
that at least one
SYSREF± edge is sent
to the device.2
If remapping lanes, set
up crossbar; see the
Crossbar Setup section.
Invert the polarity of
desired logical lanes.
Bit x of InvLanes must
be a 1 for each Logical
Lane x to invert.
Enable the links.
See the JESD204B
Setup section.
See the JESD204B
Setup section.
EnLinks = 3 if DualLink
= 1 (enables Link 0 and
Link 1); EnLinks = 1 if
DualLink = 0 (enables
Link 0 only).
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
Verify that Register 0x03B, Bit 3 reads back 1 after sending at least one
SYSREF± edge to the device to indicate that the LMFC sync machine has properly
locked.
This section explains how to select appropriate LODivMode,
RefDivMode, and BCount in the Step 1: Start Up the DAC
section. These parameters depend on the desired DAC clock
frequency (fDACCLK) and DAC reference clock frequency (fREF).
When using the DAC PLL, the reference clock signal is applied
to the CLK± differential pins, Pin 2 and Pin 3.
Table 23. DAC PLL LODivMode Settings
DAC Frequency Range (MHz)
1500 to 2400
750 to 1500
420 to 750
LODIVMODE,
Register 0x08B[1:0]
1
2
3
Table 24. DAC PLL RefDivMode Settings
DAC PLL Reference
Frequency (fREF) (MHz)
35 to 80
80 to 160
160 to 320
320 to 640
640 to 1000
Divide by
(RefDivFactor)
1
2
4
8
16
REFDIVMODE,
Register 0x08C[2:0]
0
1
2
3
4
The VCO frequency (fVCO) is related to the DAC clock
frequency according to the following equation:
fVCO = fDACCLK × 2LODivMode + 1
where 6 GHz ≤ fVCO ≤ 12 GHz.
BCount must be between 6 and 127 and is calculated based on
fDACCLK and fREF as follows:
BCount = floor((fDACCLK)/(2 × fREF/RefDivFactor))
where RefDivFactor = 2RefDivMode (see Table 24).
Finally, to finish configuring the DAC PLL, set the VCO control
registers up as described in Table 80 based on the VCO
frequency (fVCO).
For more information on the DAC PLL, see the DAC Input
Clock Configurations section.
Rev. B | Page 28 of 124
Data Sheet
AD9154
INTERPOLATION
The transmit path can use zero to three cascaded interpolation
filters, which each provide a 2× increase in output data rate and
a low-pass function. Table 25 shows the different interpolation
modes and the respective usable bandwidth, along with the
maximum fDATA rate attainable.
Table 25. Interpolation Modes and Their Usable Bandwidth
Interpolation Mode
1× (bypass)
2×
4×
8×
InterpMode
0x00
0x01
0x03
0x04
Usable Bandwidth
0.5× fDATA
0.4 × fDATA
0.4 × fDATA
0.4 × fDATA
The usable bandwidth is defined for 1×, 2×, 4×, and 8× modes
as the frequency band over which the filters have a pass-band
ripple of less than ±0.001 dB and an image rejection of greater
than 85 dB. For more information, see the Interpolation section.
JESD204B SETUP
This section explains how to select a JESD204B operating mode
for a desired application. This in turn defines appropriate values
for CheckSumMode, UnusedLanes, DualLink, CurrentLink,
Scrambling, L, F, K, M, N, Np, Subclass, S, HD, Lane0Checksum,
and Lanes needed for the Step 3: Transport Layer section.
Note that DualLink, Scrambling, L, F, K, M, N, Np, S, HD, and
Subclass must have the same settings on the transmit side.
For a summary of how a JESD204B system works and what
each parameter means, see the JESD204B Serial Data Interface
section.
Available Operating Modes
Table 26. JESD204B Operating Modes (Single Link Only)
Parameter
M (Converter Count)
L (Lane Count)
S ((Samples per Converter) per Frame)
F ((Octets per Frame) per Lane)
0
4
8
1
1
1
4
8
2
2
Mode
2
4
4
1
2
3
4
2
1
4
For a particular application, the number of converters to use
(M) and the fDATA (DataRate) are known. The LaneRate and
number of lanes (L) can be traded off as follows:
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
where LaneRate is specified in Table 4.
Octets per frame per lane (F) and samples per convertor per
frame (S) define how the data is packed. If F = 1, the high density
(HD) setting must be set to 1 (HD = 1). Otherwise, set HD = 0.
Both the converter resolution (N) and the bits per sample (Np)
must be set to 16. K must be set to 32 for Mode 0, Mode 4 and
Mode 9. Other modes may use either K = 16 or K = 32.
DualLink
DualLink sets up two independent JESD204B links; each link
can be reset independently. If DualLink is desired, set it to 1; if a
single link is desired, set DualLink to 0. Note that Link 0 and
Link 1 must have identical parameters. The operating modes
available when using dual link mode are shown in Table 26. In
addition to these operating modes, the modes in Table 27 may
also be used when using single link mode.
Scrambling
Scrambling is a feature that makes the spectrum of the link data
independent. This avoids spectral peaking and provides some
protection against data dependent errors caused by frequency
selective effects in the electrical interface. Set Scrambling to 1 if
scrambling is being used, or to 0 if it is not.
Subclass
Subclass determines whether the latency of the device is
deterministic, meaning it requires an external synchronization
signal. See the Subclass Setup section for more information.
CurrentLink
To configure Link 0 or Link 1, set CurrentLink to either 0 or 1,
respectively.
Lanes
Lanes enables and deskews particular lanes in two thermometer
coded registers.
Table 27. JESD204B Operating Modes (Single or Dual Link)
Parameter
M (Converter Count)
L (Lane Count)
S ((Samples per Converter) per Frame)
F ((Octets per Frame) per Lane)
4
2
4
1
1
5
2
4
2
2
Mode
6 7
2 2
2 1
1 1
2 4
9
1
2
1
1
10
1
1
1
2
Lanes = (2L) − 1
UnusedLanes
UnusedLanes turns off unused circuit blocks to save power.
Each physical lane not being used (SERDINx±) must be
powered off by writing a 1 to the corresponding bit of
Register 0x201.
For example, if using Mode 6 in dual link mode and sending
data on SERDIN0±, SERDIN1±, SERDIN4±, and SERDIN5±,
set UnusedLanes = 0xCC to power off Physical Lane 2, Physical
Lane 3, Physical Lane 6, and Physical Lane 7.
Rev. B | Page 29 of 124
AD9154
Data Sheet
CheckSumMode
Table 29. SERDES Lane Rate Configuration Settings
CheckSumMode must match the checksum mode used on the
transmit side. If the checksum used is the sum of fields in the
link configuration table, CheckSumMode = 0. If summing the
registers containing the packed link configuration fields,
CheckSumMode = 1. For more information on the how to
calculate the two checksum modes, see the Lane0Checksum
section.
Lane Rate (Gbps) (see Table 4)
CDR Oversampling Mode
CDR Full Rate Mode
CDR Half Rate Mode
Lane0Checksum
Lane0Checksum is used for error checking purposes to ensure
that the transmitter is set up as expected.
If CheckSumMode = 0, the checksum is the lower 8 bits of the
sum of the L − 1, M − 1, K − 1, N − 1, Np − 1, S − 1, Scrambling,
HD, Subclass, and JESDVer variables.
If CheckSumMode = 1, Lane0Checksum is the lower 8 bits of
the sum of Register 0x450 to Register 0x45A. Select whether to
sum by fields or by registers, matching the setting on the
transmitter.
DAC Power-Down Setup
As described in the Step 1: Start Up the DAC section, PdDACs
must be set to 0 if all four converters are being used. If fewer
than four converters are in use, the unused converters can be
powered down. Use Table 28 determine which DACs are powered
down based on the number of converters per link (M) and
whether the device is in DualLink mode.
Table 28. DAC Power-Down Configuration Settings
M (Converters
per Link)
1
1
2
2
4
DualLink
0
1
0
1
0
DACs to Power Down
0
1
2
3
0
1
1
1
0
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
Halfrate
0
0
1
OvSmp
1
0
0
PLLDiv
2
1
0
Halfrate and OvSmp set how the clock detect and recover
(CDR) circuit samples. See the SERDES PLL section for an
explanation of how this circuit blocks works and the role of
PLLDiv in the block.
EQUALIZATION MODE SETUP
Set EqMode = 1 for a low power setting. Select this mode if the
insertion loss in the printed circuit board (PCB) is less than
12 dB. For insertion losses greater than 12 dB but less than
17.5 dB, set EqMode = 0. See the Equalization section for more
information.
LINK LATENCY SETUP
This section describes the steps necessary to guarantee
multichip deterministic latency in Subclass 1 and guarantee
synchronization of links within a device in Subclass 0. Use this
section to fill in LMFCDel, LMFCVar, and Subclass in the Step 5:
Data Link Layer section. For more information, see the Syncing
LMFC Signals section.
Subclass Setup
The AD9154 supports JESD204B Subclass 0 and Subclass 1
operation.
Subclass 1
PdDACs
0b0111
0b0110
0b0011
0b0000
0b0000
When using M = 1 in DualLink mode, set the I_TO_Q bit high
to ensure data entering DAC Dual B is sent to the DAC 3 output.
PdClocks
If both DACs in DAC Dual B (DAC2 and DAC3) are powered
down, the clock for DAC Dual B can be powered down. In this
case, Register 0x080, Bits[7:6] = 0x1; otherwise, Register 0x080,
Bits[7:6] = 0x0.
SERDES Clocks Setup
This section describes how to select the appropriate Halfrate,
OvSmp, and PLLDiv settings in the Step 4: Physical Layer
section. These parameters depend solely on the lane rate. The
lane rate is established in the JESD204B Setup section.
Subclass 1 mode achieves deterministic latency and allows the
synchronization of links to within the limits called out in Table 7.
It requires an external SYSREF± signal accurately phase aligned to
the DAC clock.
Subclass 0
Subclass 0 mode does not require any signal on the SYSREF± pins;
leave these pins disconnected.
Subclass 0 still requires that all lanes arrive within the same
LMFC cycle and the dual DACs must be synchronized to each
other (they are synchronized to an internal clock instead of the
SYSREF± signal when in Subclass 0 mode).
Set Subclass to 0 or 1 as desired.
Link Delay Setup
LMFCVar and LMFCDel impose delays such that all lanes in a
system arrive in the same LMFC cycle.
The unit used internally for delays is the period of the internal
processing clock (PClock), with a rate 1/40th of the lane rate.
Delays that are not in PClock cycles must be converted before
they are used.
Some useful internal relationships are defined below:
PClockPeriod = 40/LaneRate
Rev. B | Page 30 of 124
Data Sheet
AD9154
For Subclass 1,
The PClockPeriod is used to convert from time to PClock
cycles when needed.
LMFCDel = ((MinDelay − 1) × PClockFactor) % K
PClockFactor = 4/F (Frames per PClock)
For Subclass 0,
The PClockFactor is used to convert from units of PClock
cycles to frame clock cycles, which is required to set LMFCDel
in Subclass 1.
PClocksPerMF= K/PClockFactor (PClocks per LMFC Cycle)
where PClocksPerMF is the number of PClock cycles in a
multiframe cycle.
The values for PClockFactor and PClockPerMF are given per
JESD204B mode in Table 30 and Table 31.
Table 30. PClockFactor and PClockPerMF Per LMFC
JESD204B Mode ID
PClockFactor
PClockPerMF (K = 32)
PClockPerMF (K = 16)
0
4
8
Not applicable
1
2
16
8
2
2
16
8
3
1
32
16
9
4
8
N/A1
10
2
16
8
Table 31. PClockFactor and PClockPerMF Per LMFC
JESD204B Mode ID
PClockFactor
PClockPerMF (K = 32)
PClockPerMF (K = 16)
1
4
4
8
N/A1
5
2
16
8
6
2
16
8
7
1
32
16
N/A means not applicable.
LMFCDel = (MinDelay − 1) % PClockPerMF
Program the same LMFCDel and LMFCVar across all links and
devices.
See the Link Delay Setup Example, With Known Delays section
for an example calculation.
Without Known Delays
If comprehensive delay information is not available or known,
the AD9154 can read back the link latency between the LMFCRX
and the last arriving LMFC boundary in PClock cycles. Use this
information to calculate LMFCVar and LMFCDel.
For each link on each device,
1.
2.
3.
4.
5.
With Known Delays
LMFCVar and LMFCDel can be calculated directly with
information about all the system delays.
RxFixed (the fixed receiver delay in PClock cycles) and RxVar (the
variable receiver delay in PClock cycles) are found in Table 8.
TxFixed (the fixed transmitter delay in PClock cycles) and
TxVar (the variable receiver delay in PClock cycles) can be
found in the data sheet of the transmitter used. PCBFixed (the
fixed PCB trace delay in PClock cycles) is extracted from the
software. Because PCBFixed is generally much smaller than a
PClock cycle, it can be omitted. For both the PCB and
transmitter delays, convert the delays into PClock cycles.
For each lane,
Power up the board.
Follow the steps in Table 15 through Table 22 in the Device
Setup Guide section.
Set the subclass and perform a sync. For a one-shot sync,
perform the writes in Table 32. See the Syncing LMFC
Signals section for alternate sync modes.
Record DYN_LINK_LATENCY_0 (Register 0x302) as a
value of Delay for that link and power cycle.
Record DYN_LINK_LATENCY_1 (Register 0x303) as a
value of Delay for that link and power cycle.
Repeat Step 1 through Step 5 twenty times for each device in the
system. Keep a single list of the Delay values across all runs and
devices.
Table 32. Register Configuration and Procedure for
One-Shot Sync
Addr.
0x301
0x03A
Bit.
No.
0x03A
0x03A
Value1
0x
0x01
Variable
Subclass
0x81
0xC1
SYSREF±
MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)
FALL_COUNT_DelayLane = ceiling(RxFixed + RxVar +
TxFixed + TxVar + PCBFixed))
0x300
where, across lanes, links, and devices:
MinDelayLane is the minimum of all MinDelayLane values.
FALL_COUNT_Delay is the maximum of all
FALL_COUNT_DelayLane values.
For safety, add a guard band of 1 PClock cycle to each end of
the link delay, as shown in the following equations:
LMFCVar = (FALL_COUNT_Delay + 1) − (MinDelay − 1)
1
0x
6
ChkSmMd
3
Dual Link
[1:0]
EnLinks
Description
Set subclass
Set sync mode = one-shot
sync
Enable the sync machine
Arm the sync machine
If Subclass = 1, ensure
that at least one SYSREF±
edge is sent to the device
Enable the links
See the JESD204B Setup
section
See the JESD204B Setup
section
EnLinks = 3 if in DualLink
mode to enable Link 0
and Link 1; EnLinks = 1 if
not in DualLink mode to
enable Link 0
0x denotes a register value that the user must fill in. See the Variable and
Description columns for information on selecting the appropriate register value.
Note that if LMFCVar must be more than 10, the AD9154
cannot tolerate the variable delay in the system.
Rev. B | Page 31 of 124
AD9154
Data Sheet
Use the list of delay values to calculate LMFCDel and LMFCVar,
but note that some of the delay values may need to be remapped
first.
The maximum possible value for DYN_LINK_LATENCY_x is
one less than the number of PClocks in a multiframe
(PClocksPerMF). A rollover condition may be encountered,
meaning the set of recorded delay values may roll over the edge
of a multiframe. If so, Delay values may be near both 0 and
PClocksPerMF. If this occurs, add PClocksPerMF to the set of
values near 0.
For example, for Delay value readbacks of 6, 7, 0, and 1, the 0
and 1 Delay values must be remapped to 8 and 9, making the
new set of Delay values 6, 7, 8, and 9.
Across power cycles, links, and devices,
•
•
MinDelay is the minimum of all delay measurements.
FALL_COUNT_Delay is the maximum of all delay
measurements.
For safety, add a guard band of 1 PClock cycle to each end of
the link delay and calculate LMFCVar and LMFCDel with the
following equation:
LMFCVar = (FALL_COUNT_Delay + 1) − (MinDelay − 1)
CROSSBAR SETUP
Registers 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx±) to logical lanes used by the SERDES
deframers.
Table 33. Crossbar Registers
Address
0x308
0x308
0x309
0x309
0x30A
0x30A
0x30B
0x30B
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
Logical Lane
XBARVAL0
XBARVAL1
XBARVAL2
XBARVAL3
XBARVAL4
XBARVAL5
XBARVAL6
XBARVAL7
Write each XBARVALy with the number (x) of the desired
physical lane (SERDINx±) from which to get data. By default, all
logical lanes use the corresponding physical lane as their data
source. For example, by default, XBARVAL0 = 0, meaning Logical
Lane 0 receives data from Physical Lane 0 (SERDIN0±). If
instead the user wants to use SERDIN4± as the source for
Logical Lane 0, the user must write XBARVAL0 = 4.
Note that if LMFCVar must be more than 10, the AD9154
cannot tolerate the variable delay in the system.
For Subclass 1,
LMFCDel = ((MinDelay − 1) × PClockFactor) % K
For Subclass 0
LMFCDel = (MinDelay − 1) % PClockPerMF
Program the same LMFCDel and LMFCVar across all links and
devices.
See the Link Delay Setup Example, Without Known Delay
section for an example calculation.
Rev. B | Page 32 of 124
Data Sheet
AD9154
JESD204B SERIAL DATA INTERFACE
JESD204B OVERVIEW
Only certain combinations of parameters are supported. Each
supported combination is called a JESD204B operating mode.
In total, there are 10 single link modes supported by the
AD9154, as described in Table 34. In dual link mode, there are
six supported modes, as described in Table 35.
The JESD204B Setup section explains how to select a JESD204B
operating mode. This section presents an overview of the inner
workings of the AD9154 JESD204B receiver implementation.
The AD9154 has eight JESD204B data ports that receive data.
The eight JESD204B ports can be configured as part of a single
JESD204B link or as part of two separate JESD204B links (dual
link mode) that share a single system reference (SYSREF±) and
device clock (CLK±).
Each of these tables shows the associated clock rates when the
lane rate is 10 Gbps.
For a particular application, the number of converters to use
(M) and the DataRate are known. The LaneRate and number of
lanes (L) can be traded off as follows:
The JESD204B hardware protocol stack consists of three layers:
the physical layer, the data link layer, and the transport layer.
These sections of the hardware are described in subsequent
sections, including information for configuring every aspect of
the interface. Figure 41 shows the communication layers
implemented in the AD9154 serial data interface to recover the
clock and deserialize, descramble, and deframe the data before it
is sent to the digital signal processing section of the device.
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
where LaneRate must be between 1.42 Gbps and 10.64 Gbps.
Achieving and recovering synchronization of the lanes is very
important. To simplify the interface to the transmitter, the
AD9154 designates a master synchronization signal for each
JESD204B link. In single link mode, SYNCOUT0± is the master
signal for all lanes; in dual link mode, SYNCOUT0± is the master
signal for Link 0, and SYNCOUT1± is used as the master signal for
Link 1. If any lane in a link loses synchronization, a resynchronization request is sent to the transmitter via the SYNCOUT signal
of the link. The transmitter stops sending data and instead sends
synchronization characters to all lanes in that link until
resynchronization is achieved.
The physical layer establishes a reliable channel between the
transmitter and the receiver, the data link layer unpacks the data
into frames of octets and descrambles the data, and the
transport layer receives the descrambled JESD204B frames and
converts them to DAC input samples.
A number of JESD204B parameters (L, F, K, M, N, Np, S, and
HD) define how the data is packed and instruct the device on
how to turn the serial data into samples. These parameters are
defined in detail in the Transport Layer section.
SYNCOUT0±
SYNCOUT1±
PHYSICAL
LAYER
SERDIN0±
DATA LINK
LAYER
TRANSPORT
LAYER
DUAL A Q DATA[15:0]
DESERIALIZER
TO
DAC
FRAME TO
SAMPLES
QBD/
DESCRAMBLER
SERDIN7±
DUAL A I DATA[15:0]
DUAL B I DATA[15:0]
DESERIALIZER
11389-003
DUAL B Q DATA[15:0]
SYSREF±
Figure 41. Functional Block Diagram of Serial Link Receiver
Table 34. Single Link JESD204B Operating Modes
Parameter
M (Converter Counts)
L (Lane Counts)
S (Samples per Converter per Frame)
F (Octets per Frame per Lane)
Example Clocks for 10 Gbps Lane Rate
PClock (MHz)
Frame Clock (MHz)
Sample Clock (MHz)
0
4
8
1
1
1
4
8
2
2
2
4
4
1
2
3
4
2
1
4
4
2
4
1
1
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
Rev. B | Page 33 of 124
Mode
5
2
4
2
2
250
500
1000
6
2
2
1
2
7
2
1
1
4
9
1
2
1
1
10
1
1
1
2
250
500
500
250
250
250
250
1000
1000
250
500
500
AD9154
Data Sheet
Table 35. Dual Link JESD204B Operating Modes for Link 0 and Link 1
Mode
Parameter
M (Converter Counts)
L (Lane Counts)
S (Samples per Converter per Frame)
F (Octets/Frame per Lane)
Example Clock for 10 Gbps Lane Rate
PClock (MHz)
Frame Clock (MHz)
Sample Clock (MHz)
4
2
4
1
1
5
2
4
2
2
6
2
2
1
2
7
2
1
1
4
9
1
2
1
1
10
1
1
1
2
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
250
500
500
DESERIALIZER
SERDINx±
TERMINATION
EQUALIZER
CDR
1:40
11389-
SPI CONTROL
FROM SERDES PLL
Figure 42. Deserializer Block Diagram
PHYSICAL LAYER
Table 36. PHY Termination Autocalibration Routine
The physical layer of the JESD204B interface, hereafter referred
to as the deserializer, has eight identical channels. Each channel
consists of the terminators, an equalizer, a CDR circuit, and the
1:40 demux function (see Figure 42).
Address
0x2A7
0x2AE
JESD204B data is input to the AD9154 via the SERDINx± 1.2 V
differential input pins as per the JESD204B specification.
The input termination voltage of the DAC is sourced externally
via the VTT pins (Pin 21, Pin 25, Pin 42, and Pin 46). Set VTT by
connecting it to SVDD12. It is recommended that the JESD204B
inputs be ac-coupled to the JESD204B transmit device using
100 nF capacitors.
Note that any unused and enabled lanes unnecessarily consume
extra power. Each lane that is not in use (SERDINx±) must be
powered off by writing a 1 to the corresponding bit of PHY_PD
(Register 0x201).
Interface Power-Up and Input Termination
Before using the JESD204B interface, it must be powered up by
setting Register 0x200[0] = 0. In addition, each physical lane that is
not being used (SERDINx±) must be powered down. To do so,
set the corresponding Bit x for Physical Lane x in Register 0x201 to
0 if the physical lane is being used, and to 1 if it is not being used.
Description
Autotune PHY terminations
Autotune PHY terminations
Receiver Eye Mask
The AD9154 complies with the JESD204B specification
regarding the receiver eye mask and can capture data that
complies with this mask without equalization. With equalization
enabled, the AD9154 can reliably capture from signals with
much smaller eye openings. Figure 43 shows the receiver eye
mask normalized to the data rate interval with a 600 mV VTT
swing. See the JESD204B specification for more information
regarding the eye mask and permitted receiver eye opening.
The AD9154 autocalibrates the input termination to 50 Ω.
Register 0x2A7 controls autocalibration for PHY 0, PHY 1,
PHY 6, and PHY 7. Register 0x2AE controls autocalibration for
PHY 2, PHY 3, PHY 4, and PHY 5. The PHY termination
autocalibration routine is shown in Table 36.
LV-OIF-11G-SR TX EYE MASK
(3.125Mbps ≥ UI ≤ 12.5Gbps)
525
AMPLITUDE (mV)
Power-Down Unused PHYs
Value
0x01
0x01
55
0
–55
0
0.35
0.5
0.65
TIME (UI)
Figure 43. Receiver Eye Mask
Rev. B | Page 34 of 124
1.00
11389-006
–525
Data Sheet
AD9154
Equalization
0
To compensate for signal integrity distortions for each PHY
channel due to insertion loss caused by PCB trace characteristics,
the AD9154 employs an easy to use, low power equalizer on each
JESD204B channel. The AD9154 equalizers can compensate for
insertion losses far greater than required by the JESD204B
specification. The equalizers have two modes of operation
determined by the EQ_POWER_MODE register setting in
Register 0x268, Bits[7:6]. In low power mode (Register 0x268,
Bits[7:6] = 2b’01) and operating at the maximum lane rate, the
equalizer can compensate for up to 12 dB of insertion loss. In
normal mode (Register 0x268, Bits[7:6] = 2b’00), the equalizer can
compensate for up to 17.5 dB of insertion loss. This performance is
shown in Figure 44 as an overlay to the JESD204B specification for
insertion loss. Figure 44 shows the equalization performance at
10.0 Gbps, near the maximum baud rate for the AD9154.
2
AD9154 ALLOWED
CHANNEL LOSS
(LOW POWER MODE)
INSERTION LOSS (dB)
6
EXAMPLE OF
AD9154
COMPATIBLE
CHANNEL (LOW
POWER MODE)
8
10
12
EXAMPLE OF
AD9154
COMPATIBLE
CHANNEL
(NORMAL MODE)
AD9154 ALLOWED
CHANNEL LOSS
(NORMAL MODE)
14
16
18
20
22
2.5
5.0
11389-339
24
7.5
FREQUENCY (GHz)
Figure 44. Insertion Loss Allowed
0
–5
–10
–15
–20
STRIPLINE = 6”
STRIPLINE = 10”
STRIPLINE = 15”
STRIPLINE = 20”
STRIPLINE = 25”
STRIPLINE = 30”
–25
–30
–35
–40
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (GHz)
11389-008
Low power mode is recommended if the insertion loss of the
JESD204B PCB channels is less than that of the most lossy
supported channel for lower power mode (shown in Figure 44).
If the insertion loss is greater than that, but still less than that of
the most lossy supported channel for normal mode (shown in
Figure 44), use normal mode. At 10 Gbps operation, the equalizer
in normal mode consumes about 4 mW more power per lane
used than in low power equalizer mode. Note that either mode
can be used in conjunction with transmitter preemphasis to
ensure functionality and/or to optimize for power.
EXAMPLE OF
JESD204B
COMPLIANT
CHANNEL
4
ATTENUATION (dB)
Figure 45 and Figure 46 are provided as points of reference for
hardware designers and show the insertion loss for various
lengths of well laid out stripline and microstrip transmission
lines on FR-4 material.
JESD204B SPEC ALLOWED
CHANNEL LOSS
Figure 45. Insertion Loss of 50 Ω Striplines on FR-4
0
–5
–15
–20
6” MICROSTRIP
10” MICROSTRIP
15” MICROSTRIP
20” MICROSTRIP
25” MICROSTRIP
30” MICROSTRIP
–25
–30
–35
–40
0
1
2
3
4
5
6
7
8
9
FREQUENCY (GHz)
Figure 46. Insertion Loss of 50 Ω Microstrips on FR-4
Rev. B | Page 35 of 124
10
11389-009
ATTENUATION (dB)
–10
AD9154
Data Sheet
Clock Multiplication Relationships
Table 37. SERDES PLL Divider Settings
The following clocks rates are used throughout the rest of the
JESD204B section. The relationship between any of the clocks
can be derived from the following equations:
LaneRate (Gbps)
(see Table 4)
CDR
Oversampling
Mode
CDR Full Rate
Mode
CDR Half Rate
Mode
DataRate = (DACRate)/(InterpolationFactor)
LaneRate = (20 × DataRate × M)/L
ByteRate = LaneRate/10
where:
M is the JESD204B parameter for converters per link.
L is the JESD204B parameter for lanes per link.
F is the JESD204B parameter for octets per frame per lane.
Divide by
(DivFactor)
1
SPI_CDR_OVERSAMP
Register 0x289, Bits[1:0]
2
2
1
4
0
Register 0x280 controls the synthesizer enable and recalibration.
To enable the SERDES PLL, first set the PLL divider register
according to Table 37, then enable the SERDES PLL by writing
Register 0x280, Bit 0 to 1.
This comes from 8-bit/10-bit encoding, where each byte is
represented by 10 bits.
Confirm that the SERDES PLL is working by reading
Register 0x281. If Register 0x281, Bit 0 = 1, the SERDES PLL is
locked. If Register 0x281, Bit 3 = 1, the SERDES PLL is successfully
calibrated. If Register 0x281, Bit 4 or Register 0x281, Bit 5 are high,
the PLL hits the upper or lower end of its calibration band and
must be recalibrated by writing 0 and then 1 to Register 0x280,
Bit 2.
PClockRate = ByteRate/4
The processing clock is used for a quad-byte decoder.
FrameRate = ByteRate/F
where F is defined as (bytes per frame) per lane.
PClockFactor = FrameRate/PClockRate = 4/F
SERDES PLL
Functional Overview of the SERDES PLL
SERDES PLL Fixed Register Writes
To optimize the SERDES PLL across all operating conditions,
the following register writes to the following locations are
recommended: 0x284, 0x285, 0x286, 0x287, 0x28A, 0x28B,
0x290, 0x291, 0x294, 0x296, 0x297, 0x299, 0x29A, 0x29C,
0x29F, and 0x2A0 as shown in Table 21.
The independent SERDES PLL uses integer-N techniques to
achieve clock synthesis. The entire SERDES PLL is integrated
on chip, including the VCO and the loop filter. The SERDES
PLL VCO operates over the range of 5.65 GHz to 12 GHz.
In the SERDES PLL, a VCO divider block divides the VCO
clock by 2 to generate a 2.825 GHz to 6 GHz quadrature clock
for the deserializer cores. This clock is the input to the CDR
block described in the Clock and Data Recovery section.
SERDES PLL IRQ
SERDES PLL lock and lost signals are available as IRQ events.
Use Register 0x01F, Bit 3 and Bit2 to enable these signals, and then
use Register 0x023, Bit 3 and Bit 2 to read back their statuses and
reset the IRQ signals. See the Interrupt Request Operation
section for more information.
The reference clock to the SERDES PLL is always running at a
frequency of fREF = 1/40 of the lane rate = PClockRate. This
clock is divided by a DivFactor to deliver a clock to the PFD
block that is between 35 MHz and 80 MHz. Table 37 includes
the respective SERDES_PLL_DIV_MODE register settings for
each of the desired DivFactor options available.
2.825GHz TO 6GHz
OUTPUT
VCO
LDO
CHARGE
PUMP
I Q
PFD
80MHz
MAX
BIT RATE ÷ 40
DivFactor
(1, 2, 4)
C1
R1
UP
C2
C3
LC VCO
5.65GHz TO 12GHz
÷2
DOWN
÷80
R3
CALIBRATION
CONTROL
BITS
3.2mA
Figure 47. SERDES PLL Synthesizer Block Diagram Including VCO Divider Block
Rev. B | Page 36 of 124
11389-144
fREF
Data Sheet
AD9154
Clock and Data Recovery
DATA LINK LAYER
The deserializer is equipped with a CDR circuit. Instead of
recovering the clock from the JESD204B serial lanes, the CDR
recovers the clocks from the SERDES PLL. The 2.825 GHz to
6 GHz output from the SERDES PLL, shown in Figure 47, is
the input to the CDR.
The data link layer of the AD9154 JESD204B interface accepts
the deserialized data from the PHYs and deframes and descrambles
them so that data octets are presented to the transport layer to
be put into DAC samples. The architecture of the data link layer
is shown in Figure 48. It consists of a synchronization FIFO for
each lane, a crossbar switch, a deframer, and descrambler.
Select a CDR sampling mode to generate the lane rate clock
inside the device. If the desired lane rate is greater than
5.65 GHz, half rate CDR operation must be used. If the desired
lane rate is less than 5.65 GHz, disable half rate operation. If the
lane rate is less than 2.825 GHz, disable half rate and enable 2×
oversampling to recover the appropriate lane rate clock. Table 38
breaks down the CDR sampling settings that must be set
dependent on the LaneRate.
The AD9154 can operate as a single link or dual link, high speed
JESD204B serial data interface. When operating in dual link mode,
configure both links with the same JESD204B parameters because
they share a common device clock and system reference. All eight
lanes of the JESD204B interface handle link layer communications
such as code group synchronization, frame alignment, and frame
synchronization.
The AD9154 decodes 8-bit/10-bit control characters, allowing
marking of the start and end of the frame and alignment
between serial lanes. Each AD9154 serial interface link can issue
a synchronization request by setting its SYNCOUT0±/
SYNCOUT1± signal low. The synchronization protocol follows
Section 4.9 of the JESD204B standard. When a stream of four
consecutive /K/ symbols is received, the AD9154 deactivates the
synchronization request by setting the SYNCOUT0±/
SYNCOUT1± signal high at the next internal LMFC rising
edge. Then, it waits for the transmitter to issue a lane alignment
sequence (ILAS). During the ILAS sequence, all lanes are
aligned using the /A/ to /R/ character transition as described in
the JESD204B Serial Link Establishment section. Elastic buffers
hold early arriving lane data until the alignment character of the
latest lane arrives. At this point, the buffers for all lanes are
released and all lanes are aligned (see Figure 49).
Table 38. CDR Operating Modes
HALFRATE,
Register 0x230,
Bit 5
0
CDR_OVERSAMP,
Register 0x230,
Bit 1
1
0
1
0
0
The CDR circuit synchronizes the phase used to sample the data on
each serial lane independently. This independent phase adjustment
per serial interface ensures accurate data sampling and eases the
implementation of multiple serial interfaces on a PCB.
After configuring the CDR circuit, reset it and then release the
reset by writing 1 and then 0 to Register 0x206, Bit 0.
DATA LINK LAYER
SYNCOUTx±
LANE 0 DATA CLOCK
SERDIN0
FIFO
CROSS
BAR
SWITCH
LANE 7 DATA CLOCK
SYSREF
SERDIN7
FIFO
LANE0 OCTETS
LANE7 OCTETS
SYSTEM CLOCK
PHASE DETECT
11389-011
LANE 7 DESERIALIZED
AND DESCRAMBLED DATA
DESCRAMBLE
QUAD BYTE
DEFRAMER
(QBD)
LANE 0 DESERIALIZED
AND DESCRAMBLED DATA
10-BIT/8-BIT DECODE
LaneRate (Gbps)
(See Table 4)
CDR Oversampling
Mode
CDR Full Rate Mode
CDR Half Rate Mode
PCLK
SPI CONTROL
Figure 48. Data Link Layer Block Diagram
Rev. B | Page 37 of 124
AD9154
Data Sheet
L RECEIVE LANES
(EARLIEST ARRIVAL) K K K R D D
D D A R Q C
L RECEIVE LANES
(LATEST ARRIVAL) K K K K K K K R D D
C
D D A R Q C
D D A R D D
C
D D A R D D
0 CHARACTER ELASTIC BUFFER DELAY OF LATEST ARRIVAL
4 CHARACTER ELASTIC BUFFER DELAY OF EARLIEST ARRIVAL
L ALIGNED
RECEIVE LANES K K K K K K K R D D
D D A R Q C
C
D D A R D D
11389-149
K = K28.5 CODE GROUP SYNCHRONIZATION COMMA CHARACTER
A = K28.3 LANE ALIGNMENT SYMBOL
F = K28.7 FRAME ALIGNMENT SYMBOL
R = K28.0 START OF MULTIFRAME
Q = K28.4 START OF LINK CONFIGURATION DATA
C = JESD204 LINK CONFIGURATION PARAMETERS
D = Dx.y DATA SYMBOL
Figure 49. Lane Alignment During ILAS
JESD204B Serial Link Establishment
A brief summary of the high speed serial link establishment
process for Subclass 1 is provided. See Section 5.3.3 of the
JESD204B specifications document for complete details.
After the last /A/ character of the last ILAS, the multiframe data
begins streaming. The receiver adjusts the position of the /A/
character such that it aligns with the internal LMFC of the
receiver at this point.
Step 1: Code Group Synchronization
Step 3: Data Streaming
Each receiver must locate K (K28.5) characters in its input data
stream. After four consecutive K characters are detected on all
link lanes, the receiver block deasserts the SYNCOUTx± signal
to the transmitter block at the LMFC edge.
In this phase, data is streamed from the transmitter block to the
receiver block.
The transmitter captures the change in the SYNCOUTx± signal,
and at a future transmitter LMFC rising edge, starts the initial
ILAS.
The receiver block processes and monitors the data it receives
for errors, including
Step 2: Initial Lane Alignment Sequence
The main purposes of this phase are to align all the lanes of the
link and verify the parameters of the link.
Before the link is established, write each of the link parameters
to the receiver device to designate how data is sent to the
receiver block.
The ILAS consists of four or more multiframes. The last character
of each multiframe is a multiframe alignment character, /A/.
The first, third, and fourth multiframes are populated with
predetermined data values. Note that Section 8.2 of the
JESD204B specifications document describes the data ramp
expected during ILAS. By default, the AD9154 does not require
this ramp. Register 0x47E[0] can be set high to require the data
ramp. The deframer uses the final /A/ of each lane to align the
ends of the multiframes within the receiver. The second
multiframe contains an R (K.28.0), Q (K.28.4), and then data
corresponding to the link parameters. Additional multiframes
can be added to the ILAS if needed by the receiver. By default,
the AD9154 uses four multiframes in the ILAS (this can be
changed in Register 0x478). If using Subclass 1, exactly four
multiframes must be used.
Optionally, data can be scrambled. Scrambling does not start
until the very first octet following the ILAS.
•
•
•
•
•
Bad running disparity (8-bit/10-bit error)
Not in table (8-bit/10-bit error)
Unexpected control character
Bad ILAS
Interlane skew error (through character replacement)
If any of these errors exist, they are reported back to the
transmitter in one of a few ways (see the JESD204B Error
Monitoring section for details):
•
•
•
Signal assertion. Resynchronization (SYNCOUTx± signal
pulled low) is requested at each error for the last two errors.
For the first three errors, an optional resynchronization
request can be asserted when the error counter reaches a
set error threshold.
For the first three errors, each multiframe with an error in
it causes a small pulse of programmable width
on SYNCOUTx±.
Errors can optionally trigger an IRQ event, which can be
sent to the transmitter.
See to the JESD204B Test Modes section for various test modes
for verifying the link integrity.
Rev. B | Page 38 of 124
Data Sheet
AD9154
Lane FIFO
The FIFOs in front of the crossbar switch and deframer
synchronize the samples sent on the high speed serial data
interface with the deframer clock by adjusting the phase of the
incoming data. The FIFO absorbs timing variations between the
data source and the deframer; this allows up to two PClock
cycles of drift from the transmitter. The FIFO_STATUS_REG_0
register and FIFO_STATUS_REG_1 register (Register 0x30C
and Register 0x30D, respectively) can be monitored to identify
whether the FIFOs are full or empty.
Lane FIFO IRQ
An aggregate lane FIFO error bit is also available as an IRQ
event. Use Register 0x01F[1] to enable the FIFO error bit, and
then use Register 0x023[1] to read back its status and reset the
IRQ signal. See the Interrupt Request Operation section for
more information.
Crossbar Switch
Register 0x308 to Register 0x30B allow arbitrary mapping of
physical lanes (SERDINx±) to logical lanes used by the SERDES
deframers.
Table 39. Crossbar Registers
Address
0x308
0x308
0x309
0x309
0x30A
0x30A
0x30B
0x30B
Bits
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
[2:0]
[5:3]
In single link mode, Deframer 0 is used exclusively and Deframer 1
remains inactive. In dual link mode, both QBDs are active and
must be configured separately using the SEL_REG_MAP_1 bit
(Register 0x300[2]) to select the link to be configured. The
DUALLINK bit (Register 0x300[3]) =1 for dual link, or 0 for
single link.
Each deframer uses the JESD204B parameters that the user has
programmed into the register map to identify how the data has
been packed and how to unpack it. The JESD204B parameters
are discussed in detail in the Transport Layer section; many of
the parameters are also needed in the transport layer to convert
JESD204B frames into samples.
Descrambler
The AD9154 provides an optional descrambler block using a
self synchronous descrambler with a polynomial: 1 + x14 + x15.
Enabling data scrambling reduces the spectral peaks produced
when the same data octets repeat from frame to frame. It also
makes the spectrum data independent so that possible
frequency selective effects on the electrical interface do not
cause data dependent errors. Descrambling of the data is
enabled by setting the SCR bit (Register 0x453[7]) to 1.
Syncing LMFC Signals
Logical Lane
XBARVAL0
XBARVAL1
XBARVAL2
XBARVAL3
XBARVAL4
XBARVAL5
XBARVAL6
XBARVAL7
The first step in guaranteeing synchronization across links and
devices begins with syncing the LMFC signals. Each DAC dual
(DAC Dual A = DAC0/DAC1 and DAC Dual B = DAC2/DAC3)
has its own LMFC signal. In Subclass 0, the LMFC signals for
each of the two links are synchronized to an internal processing
clock. In Subclass 1, all LMFC signals (for all duals and devices)
are synchronized to an external SYSREF signal.
SYSREF Signal
Write each XBARVALx with the number (x) of the desired
physical lane (SERDINx±) from which to get data. By default,
all logical lanes use the corresponding physical lane as their data
source. For example, by default XBARVALx = 0, so Logical Lane 0
gets data from Physical Lane 0 (SERDIN0±). If instead the user
wants to use SERDIN4± as the source for Logical Lane 0, the user
must write XBARVALx = 4.
Lane Inversion
Register 0x334 allows the inversion of desired logical lanes,
which can be used to ease routing of the SERDINx± signals. For
each Logical Lane x, set Bit x of Register 0x334 to 1 to invert the
lane.
Deframers
The AD9154 consists of two quad byte deframers (QBDs). Each
deframer takes in the 8-bit/10-bit encoded data from the
deserializer (via the crossbar switch), decodes it, and descrambles it
into JESD204B frames before passing it to the transport layer to be
converted to DAC samples. The deframer processes four symbols
(or octets) per processing clock (PClock) cycle.
The SYSREF± signal is a differential source synchronous input that
synchronizes the LMFC signals in both the transmitter and receiver
in a JESD204B Subclass 1 system to achieve deterministic latency.
The SYSREF± signal is an active high signal sampled by the
device clock rising edge. It is best practice that the device clock and
the SYSREF± signals be generated by the same source, such as a
device from the AD9516-0, AD9516-1, AD9516-2, AD9516-3,
AD9516-4, and AD9516-5 family of clock generators, so that
the phase alignment between the signals is fixed. When designing
for optimum deterministic latency operation, consider the
timing distribution skew of the SYSREF± signal in a multipoint
link system (multichip).
The AD9154 supports a single pulse or step, or a periodic
SYSREF± signal. The periodicity can be continuous, strobed, or
gapped periodic.
Rev. B | Page 39 of 124
AD9154
Data Sheet
To avoid this common-mode current draw, use a 50% dutycycle periodic SYSREF± signal with ac coupling capacitors. If
ac-coupled, the ac coupling capacitors combine with the
resistors shown in Figure 50 to create a high-pass filter with an
RC time constant of τ = RC. Select C such that τ > 4/SYSREF
frequency. In addition, the edge rate must be sufficiently fast—
at least 1.3 V/ns is recommended per Table 5.
1.2V
3kΩ
SYSREF–
3kΩ
For debug purposes, SYNCARM (Register 0x03A, Bit 6)
informs the user that alignment edges are being received in
continuous mode. Because the SYNCARM bit is self cleared
after an alignment edge is received, the user can arm the sync
(SYNCARM (Register 0x03A, Bit 6) = 1), and then read back
SYNCARM. If SYNCARM = 0, the alignment edges are being
received and phase checks are occurring. Arming the sync
machine in this mode does not affect the operation of the device.
~600mV
11389-014
SYSREF+
check occurs on every SYSREF± pulse, but an alignment occurs
only if the phase error is greater than the specified error
window tolerance. If the jitter of the SYSREF± signal violates
the setup and hold time specifications given in Table 5, and
therefore causes phase error uncertainty, the error tolerance can
be increased to avoid constant clock rotations. Note that this
means that the latency is less deterministic by the size of the
window. If the error window tolerance must be set above 3,
Subclass 0 with a one-shot sync is recommended.
Figure 50. SYSREF± Input Circuit
LMFC Synchronization Modes Overview
One-Shot Then Monitor Sync Mode (SYNCMODE = 0x9)
The AD9154 supports various LMFC sync processing modes.
These modes are one-shot, continuous, windowed continuous,
and monitor modes. All sync processing modes perform a
phase check to see that the LMFC is phase aligned to an
alignment edge. In Subclass 1, the SYSREF± pulse acts as the
alignment edge; in Subclass 0, an internal processing clock acts
as the alignment edge. If the signals are not in phase, a clock
rotation occurs to align the signals. The sync modes are described
in the following sections. See the LMFC Synchronization
Procedure section for details on the procedure for syncing the
LMFC signals.
In one-shot then monitor mode, the user can monitor the phase
error in real time. Use this sync mode with a periodic SYSREF±
signal. A phase check and alignment occurs on the first alignment
edge received after the sync machine is armed. On all subsequent
alignment edges, the phase is monitored and reported, but no
clock phase adjustment occurs.
One-Shot Sync Mode (SYNCMODE = 0x1)
In one-shot sync mode, a phase check occurs on only the first
alignment edge received after the sync machine is armed. If the
phase error is larger than a specified window error tolerance, a
phase adjustment occurs. Though an LMFC synchronization
occurs only once, the SYSREF± signal can still be continuous.
Continuous Sync Mode (SYNCMODE = 0x2)
Continuous mode must only be used in Subclass 1 with a
periodic SYSREF± signal. In continuous mode, a phase
check/alignment occurs on every alignment edge.
Continuous mode differs from the one-shot mode in two ways.
First, no SPI cycle is required to arm the device; the alignment
edge seen after continuous mode is enabled results in a phase
check. Second, a phase check (and when necessary, clock rotation)
occurs on every alignment edge in continuous mode. The one
caveat to the previous statement is that when a phase rotation cycle
is underway, subsequent alignment edges are ignored until the
logic lane is ready again.
The maximum acceptable phase error (in DAC clock cycles)
between the alignment edge and the LMFC edge is set in the
error window tolerance register. If continuous sync mode is
used with a nonzero error window tolerance, then a phase
The phase error can be monitored on the CURRERR_L register,
(Register 0x03C, Bits[7:0]). Immediately after an alignment
occurs, CURRERRx = 0 to indicate that there is no difference
between the alignment edge and the LMFC edge. On every
subsequent alignment edge, the phase is checked. If the alignment
is lost, the phase error is reported in the CURRERR_L register in
DAC clock cycles. If the phase error is beyond the selected window
tolerance (Register 0x034, Bits[2:0]), one bit of Register 0x03D,
Bits[7:6] is set high, depending on whether the phase error is on
low or high side.
When an alignment occurs, snapshots of the last phase error
(Register 0x03C, Bits[3:0]) and the corresponding error flags
(Register 0x03D, Bit 7 and Bit 6]) are placed into readable
registers for reference (Register 0x038 and Register 0x039,
respectively).
LMFC Synchronization Procedure
The procedure for enabling the LMFC sync is as follows:
1.
2.
3.
4.
Rev. B | Page 40 of 124
Set Register 0x008 to 0x03 to sync the LMFC for both DAC
duals (DAC0/DAC1 and DAC2/DAC3)
Set the desired sync processing mode. The sync processing
mode settings are listed in Table 40.
For Subclass 1, set the error window according to the
uncertainty of the SYSREF± signal relative to the DAC
clock and the tolerance of the application for deterministic
latency uncertainty. The sync window tolerance settings
are given in Table 41.
Enable sync by writing 1 to SYNCENABLE
(Register 0x03A, Bit 7).
Data Sheet
5.
6.
7.
AD9154
If in one-shot mode, arm the sync machine by writing 1 to
SYNCARM (Register 0x03A, Bit 6).
If in Subclass 1, ensure that at least one SYSREF± pulse is
sent to the device.
Check the status by reading the following bit fields:
a) REF_BUSY (Register 0x03B, Bit 7) = 0 to indicate that
the sync logic is no longer busy.
b) REF_LOCK (Register 0x03B, Bit 3) = 1 to indicate that
the signals are aligned. This bit updates on every
phase check.
c) REF_WLIM (Register 0x03B, Bit 1) = 0 to indicate
that the phase error is not beyond the specified error
window. This bit updates on every phase check.
d) REFROTA (Register 0x03B, Bit 2) = 1 if the phases
were not aligned before the sync and an alignment
occurred, this indicates that a clock alignment occurred.
This bit is sticky and can be cleared only by writing to
the SYNCCLRSTKY control bit (Register 0x03A, Bit 5).
e) REF_TRIP (Register 0x03B, Bit 0) = 1 to indicate
alignment edge received and phase check occurred.
This bit is sticky and can be cleared only by writing to the
SYNCCLRSTKY control bit (Register 0x03A, Bit 5).
Table 40. Sync Processing Modes
Sync Processing
Mode
One-shot
Continuous
One-shot then monitor
JESD204B systems contain various clock domains distributed
throughout each system. Data traversing from one clock
domain to a different clock domain can lead to ambiguous
delays in the JESD204B link. These ambiguities lead to
nonrepeatable latencies across the link from power cycle to
power cycle with each new link establishment. Section 6 of the
JESD204B specification addresses the issue of deterministic
latency with mechanisms defined as Subclass 1 and Subclass 2.
The AD9154 supports JESD204B Subclass 0 and Subclass 1
operation, but not Subclass 2. Write the subclass to Register 0x301,
Bits[2:0] and once per link to Register 0x458, Bits[7:5].
Subclass 0
This mode does not require any signal on the SYSREF± pins,
which can be left disconnected.
Subclass 0 still requires that all lanes arrive within the same LMFC
cycle and the dual DACs must be synchronized to each other.
Minor Subclass 0 Caveats
Because the AD9154 requires an ILAS, the nonmultiple
converter single lane (NMCDA-SL) case from the JESD204A
specification is only supported when using the optional ILAS.
Error reporting using SYNCOUTx± is not supported when
using Subclass 0 with F = 1.
SYNCMODE (Register 0x03A,
Bits[3:0])
0x01
0x02
0x09
Subclass 1
This mode gives deterministic latency and allows links to be
synced to within ½ a DAC clock period. It requires an external
SYSREF± signal that is accurately phase aligned to the DAC clock.
Table 41. Sync Window Tolerance
Sync Error Window
Tolerance
±1/2 DAC clock cycles
±1 DAC clock cycles
±2 DAC clock cycles
±3 DAC clock cycles
Deterministic Latency
Deterministic Latency Requirements
ERRWINDOW (Register 0x034,
Bits[2:0])
0x00
0x01
0x02
0x03
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system.
•
•
LMFC Sync IRQ
•
The sync status bits (REFLOCK, REFROTA, REFTRIP, and
REFWLIM) are available as IRQ events.
Use Register 0x021, Bits[3:0] to enable the sync status bits for
DAC Dual A (DAC0 and DAC1), and then use Register 0x025,
Bits[3:0] to read back their statuses and reset the IRQ signals.
Use Register 0x022, Bits[3:0] to enable the sync status bits for
DAC Dual B (DAC2 and DAC3), and then use Register 0x026,
Bits[3:0] read back their statuses and reset the IRQ signals.
Rev. B | Page 41 of 124
The SYSREF± signal distribution skew within the system
must be less than the desired uncertainty.
The SYSREF± setup and hold time requirements must be
met for each device in the system.
The total latency variation across all lanes, links and
devices must be ≤10 PClock periods. This includes both
variable delays and the variation in fixed delays from lane
to lane, link to link, and device to device in the system.
AD9154
Data Sheet
Link Delay
For the AD9154, this is not necessarily the case; instead, the
AD9154 uses a local LMFC for each link (LMFCRx) that can be
delayed from the SYSREF aligned LMFC. Because the LMFC is
periodic, this can account for any amount of fixed delay. As a
result, the LMFC period must only be larger than the variation in
the link delays, and the AD9154 can achieve proper performance
with a smaller total latency. Figure 51 and Figure 52 show a case
where the link delay is larger than an LMFC period. Note that it
can be accommodated by delaying LMFCRx.
The link delay of a JESD204B system is the sum of fixed and
variable delays from the transmitter, channel and receiver, as
shown in Figure 53.
For proper functioning, all lanes on a link must be read during
the same LMFC period. Section 6.1 of the JESD204B
specification states that the LMFC period must be larger than
the maximum link delay.
POWER CYCLE
VARIANCE
ILAS
ALIGNED DATA
DATA
LATE ARRIVING
LMFC REFERENCE
EARLY ARRIVING
LMFC REFERENCE
11389-151
LMFC
Figure 51. Link Delay > LMFC Period Example
POWER CYCLE
VARIANCE
LMFC
ILAS
ALIGNED DATA
DATA
LMFC_DELAY
LMFC REFERENCE FOR ALL POWER CYCLES
FRAME CLOCK
11389-152
LMFCRX
Figure 52. LMFC DELAY to Compensate for Link Delay > LMFC
LINK DELAY = DELAYFIXED + DELAYVARIABLE
LOGIC DEVICE
(JESD204B Tx)
CHANNEL
JESD204B Rx
DSP
DAC
POWER CYCLE
VARIANCE
LMFC
ALIGNED DATA
AT Rx OUTPUT
ILAS
DATA
ILAS
DATA
FIXED DELAY
VARIABLE
DELAY
Figure 53. JESD204B Link Delay = Fixed Delay + Variable Delay
Rev. B | Page 42 of 124
11389-153
DATA AT
Tx INPUT
Data Sheet
AD9154
1.
The method for setting the LMFCDel and LMFCVar is
described in the Link Delay Setup section.
Setting LMFCDel appropriately ensures that all the corresponding
data samples arrive in the same LMFC period. Then LMFCVar
is written into the receive buffer delay (RBD) to absorb all link
delay variation. This ensures that all data samples have arrived
before reading. By setting these to fixed values across runs and
devices, deterministic latency is achieved.
2.
The RBD described in the JESD204B specification takes values
from 1 to K frame clock cycles, while the RBD of the AD9154
takes values from 0 PClock cycles to 10 PClock cycles. As a
result, up to 10 PClock cycles of total delay variation can be
absorbed. Because LMFCVar is in PClock cycles, and LMFCDel
is in frame clock cycles, a conversion between these two units is
needed. The PClockFactor, or number of frame clock cycles per
PClock cycle, is equal to 4/F. For more information on this
relationship, see the Clock Multiplication Relationships section.
Two examples follow that show how to determine LMFCVar
and LMFCDel. After they are calculated, write LMFCDel into
both Register 0x304 and Register 0x305 for all devices in the
system, and write LMFCVar to both Register 0x306 and
Register 0x307 for all devices in the system.
3.
4.
5.
Link Delay Setup Example, With Known Delays
All the known system delays can be used to calculate LMFCVar
and LMFCDel as described in the Link Delay Setup section.
The example shown in Figure 54 is demonstrated in the
following steps according to the procedure outlined in the Link
Delay Setup section. Note that this example is in Subclass 1 to
achieve deterministic latency, which has a PClockFactor (4/F)
of 2 frame clock cycles per PClock cycle, and uses K = 32
(frames per multiframe). Because PCBFixed < PClockPeriod,
PCBFixed is negligible in this example and is not included in
the calculations.
6.
7.
Find the receiver delays using Table 8.
RxFixed = 17 PClock cycles
RxVar = 2 PClock cycles
Find the transmitter delays. The equivalent table in the
example JESD204B core (implemented on a GTH or GTX
transceiver on a Virtex-6 FPGA) states that the delay is
56 ± 2 byte clock cycles.
Because the PClockRate = ByteRate/4 as described in the
Clock Multiplication Relationships section, the transmitter
delays in PClock cycles are:
TxFixed = 54/4 = 13.5 PClock cycles
TxVar = 4/4 = 1 PClock cycle
Calculate MinDelayLane as follows:
MinDelayLane = floor(RxFixed + TxFixed + PCBFixed)
= floor(17 + 13.5 + 0)
= floor(30.5)
MinDelayLane = 30
Calculate FALL_COUNT_DelayLane as follows:
FALL_COUNT_DelayLane = ceiling(RxFixed + RxVar +
TxFixed + TxVar + PCBFixed))
= ceiling(17 + 2 + 13.5 + 1 + 0)
= ceiling(33.5)
FALL_COUNT_DelayLane = 34
Calculate LMFCVar as follows:
LMFCVar = (FALL_COUNT_DelayLane + 1) − (MinDelay −
1)
= (34 + 1) − (30 − 1) = 35 − 29
LMFCVar = 6 PClock cycles
Calculate LMFCDel as follows:
LMFCDel = ((MinDelay − 1) × PClockFactor) % K
= ((30 − 1) × 2) % 32 = (29 × 2) % 32
= 58 % 32
LMFCDel = 26 frame clock cycles
Write LMFCDel to both Register 0x304 and Register 0x305
for all devices in the system. Write LMFCVar to both
Register 0x306 and Register 0x307 for all devices in the
system.
LMFC
PCLOCK
FRAME CLOCK
DATA AT Tx FRAMER
ALIGNED LANE DATA
AT Rx DEFRAMER OUTPUT
DATA
ILAS
ILAS
Tx VAR
DELAY
Rx VAR
DELAY
DATA
PCB FIXED
DELAY
LMFCRX
TOTAL FIXED LATENCY = 30 PCLOCK CYCLES
Figure 54. LMFC_DELAY Calculation Example
Rev. B | Page 43 of 124
TOTAL VARIABLE
LATENCY = 4
PCLOCK CYCLES
11389-154
LMFC DELAY = 26 FRAME CLOCK CYCLES
AD9154
Data Sheet
Link Delay Setup Example, Without Known Delay
variation in the link latency over the 20 runs is shown in
Figure 56 in gray.
If the system delays are not known, the AD9154 can read back
the link latency between LMFCRX for each link and the SYSREF
aligned LMFC. This information is used to calculate LMFCVar
and LMFCDel, as shown in the Without Known Delays section.
•
Figure 56 shows how DYN_LINK_LATENCY_x (Register 0x302
and Register 0x303) provides a readback showing the delay (in
PClock cycles) between LMFCRX and the transition from ILAS
to the first data sample. By repeatedly power-cycling and taking
this measurement, the minimum and maximum delays across
power cycles can be determined and used to calculate LMFCVar
and LMFCDel.
•
•
2.
The example shown in Figure 56 is demonstrated in the following
steps according to the procedure outlined in the Without Known
Delays section. Note that this example is in Subclass 1 to
achieve deterministic latency, which has a PClockFactor
(FrameClockRate/ PClkRate) of 2 and uses K = 16; therefore
PClocksPerMF = 8.
3.
4.
In Figure 56, for Link A, Link B, and Link C, the system
containing the AD9154 (including the transmitter) is
power cycled and configured 20 times. The AD9154 is
configured as described in the Device Setup Guide section.
As the point of this exercise is to determine LMFCDel and
LMFCVar, the LMFCDel is programmed to 0 and the
DYN_ LINK_LATENCY_x is read from Register 0x302
and Register 0x303 for Link 0 and Link 1, respectively. The
5.
6.
Calculate the minimum of all Delay measurements across
all power cycles, links, and devices:
MinDelay = min(all Delay values) = 4
Calculate the maximum of all Delay measurements across
all power cycles, links, and devices:
FALL_COUNT_Delay = max(all Delay values) = 9
Calculate the total Delay variation (with guard band)
across all power cycles, links, and devices:
LMFCVar = (FALL_COUNT_Delay + 1) − (MinDelay − 1)
= (9 + 1) − (4 − 1) = 10 − 3 = 7 PClock cycles
Calculate the minimum delay in frame clock cycles (with
guard band) across all power cycles, links, and devices:
LMFCDel = ((MinDelay − 1) × PClockFactor) % K
= ((4 − 1) × 2) % 16 = (3 × 2) % 16
= 6 % 16 = 6 frame clock cycles
Write LMFCDel to both Register and Register 0x305 for all
devices in the system. Write LMFCVar to both Register 0x306
and Register 0x307 for all devices in the system.
SYSREF±
LMFCRX
ILAS
ALIGNED DATA
DATA
11389-155
DYN_LINK_LATENCY
Figure 55. DYN_LINK_LATENCY Illustration
LMFC
PCLOCK
FRAME CLOCK
DYN_LINK_LATENCY_CNT
0
1
2
ALIGNED DATA (LINK A)
ALIGNED DATA (LINK B)
ALIGNED DATA (LINK C)
3
4
5
6
7
0
1
2
3
ILAS
4
5
6
7
DATA
ILAS
DATA
ILAS
DATA
LMFCRX
DETERMINISTICALLY
DELAYED DATA
ILAS
LMFC_DELAY = 6
(FRAME CLOCK CYCLES)
DATA
LMFCVARx = 7
(PCLOCK CYCLES)
Figure 56. Multilink Synchronization Settings, Derived Method Example
Rev. B | Page 44 of 124
11389-156
1.
Link A gives readbacks of 6, 7, 0, and 1. Note that the
set of recorded delay values rolls over the edge of a
multiframe at the boundary K/PClockFactor = 8. Add
PClocksPerMF = 8 to low set. Delay values range from
6 to 9.
Link B gives Delay values from 5 to 7.
Link C gives Delay values from 4 to 7.
Data Sheet
AD9154
TRANSPORT LAYER
TRANSPORT LAYER
(QBD)
LANE 0 OCTETS
DAC 1_I0[15:0]
DELAY
BUFFER 0
F2S_0
DAC 2_Q0[15:0]
LANE 3 OCTETS
PCLK_0
SPI CONTROL
LANE 4 OCTETS
DAC 3_I0[15:0]
DELAY
BUFFER 1
F2S_1
DAC 4_Q0[15:0]
11389-157
LANE 7 OCTETS
PCLK_1
SPI CONTROL
Figure 57. Transport Layer Block Diagram
The transport layer receives the descrambled JESD204B frames
and converts them to DAC samples based on the programmed
JESD204B parameters shown in Table 42. A number of device
parameters are defined in Table 43.
Table 43. JESD204B Device Parameters
Parameter
CF
Table 42. JESD204B Transport Layer Parameters
CS
Parameter
F
K
HD
L
M
S
Description
Number of octets per frame per lane: 1, 2, or 4.
Number of frames per multiframe.
K = 32 if F = 1, K = 16 or 32 otherwise.
Number of lanes per converter device (per link), as
follows.
1, 2, 4, or 8 (single link mode).
1, 2, or 4 (dual link mode).
Number of converters per device (per link), as follows.
1, 2, or 4 (single link mode).
1 or 2 (dual link mode).
Number of samples per converter, per frame: 1 or 2.
N
N Prime (Nʹ)
Description
Number of control words per device clock per link.
Not supported, must be 0.
Number of control bits per conversion sample. Not
supported, must be 0.
High density user data format. Used when samples
must be split across lanes. Set to 1 when F = 1,
otherwise 0.
Converter resolution = 16.
Total number of bits per sample = 16.
Certain combinations of these parameters, called JESD204B
operating modes, are supported by the AD9154. See Table 44
and Table 45 for a list of supported modes, along with their
associated clock relationships.
Rev. B | Page 45 of 124
AD9154
Data Sheet
Table 44. Single Link JESD204B Operating Modes
Parameter
M (Converter Count)
L (Lane Count)
S (Samples per Converter per Frame)
F (Octets per Frame, per Lane)
K1 (Frames per Multiframe)
HD (High Density)
N (Converter Resolution)
NP (Bits per Sample)
Example Clocks for 10 Gbps Lane Rate
PClock Rate (MHz)
Frame Clock Rate (MHz)
Data Rate (MHz)
1
0
4
8
1
1
32
1
16
16
1
4
8
2
2
16/32
0
16
16
2
4
4
1
2
16/32
0
16
16
3
4
2
1
4
16/32
0
16
16
4
2
4
1
1
32
1
16
16
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
Mode
5
2
4
2
2
16/32
0
16
16
250
500
1000
6
2
2
1
2
16/32
0
16
16
7
2
1
1
4
16/32
0
16
16
9
1
2
1
1
32
1
16
16
10
1
1
1
2
16/32
0
16
16
250
500
500
250
250
250
250
1000
1000
250
500
500
K must be 32 in Mode 0, Mode 4, and Mode 9. K can be 16 or 32 in all other modes.
Table 45. Dual Link JESD204B Operating Modes for Link 0 and Link 1
Parameter
M (Converter Count)
L (Lane Count)
S (Samples per Converter per Frame)
F (Octets per Frame per Lane)
K1 (Frames per Multiframe)
HD (High Density)
N (Converter Resolution)
NP (Bits per Sample)
Example Clocks for 10 Gbps Lane Rate
PClock Rate (MHz)
Frame Clock Rate (MHz)
Data Rate (MHz)
1
4
2
4
1
1
32
1
16
16
5
2
4
2
2
16/32
0
16
16
Mode
6
2
2
1
2
16/32
0
16
16
7
2
1
1
4
16/32
0
16
16
9
1
2
1
1
32
1
16
16
10
1
1
1
2
16/32
0
16
16
250
1000
1000
250
500
1000
250
500
500
250
250
250
250
1000
1000
250
500
500
K must be 32 in Mode 4 and Mode 9. K can be 16 or 32 in all other modes.
Rev. B | Page 46 of 124
Data Sheet
AD9154
Configuration Parameters
Data Flow Through the JESD204B Receiver
The AD9154 modes refer to the link configuration parameters
for L, K, M, N, NP, S, and F. Table 46 provides the description
and addresses for these settings.
The link configuration parameters determine how the serial bits
on the JESD204B receiver interface are deframed and passed on
to the DACs as data samples. Figure 58 shows a detailed flow of
the data through the various hardware blocks for Mode 4 (L = 4,
M = 2, S = 1, F = 1). Simplified flow diagrams for all other modes
are provided in Figure 59 through Figure 67.
Table 46. Configuration Parameters
JESD204B
Setting
L−1
F1 − 1
K−1
M−1
N−1
NP − 1
S−1
HD
F1
DID
BID
LID0
JESDVER
1
Description
Number of lanes − 1.
Number of ((octets per frame) per
lane) − 1.
Number of frames per multiframe − 1.
Number of converters − 1.
Converter bit resolution − 1.
Bit packing per sample − 1.
Number of ((samples per converter)
per frame) − 1.
High density format. Set to 1 if F = 1.
Leave at 0 if F ≠ 1.
F parameter, in ((octets per frame) per
lane).
Device ID. Match the device ID sent
by the transmitter.
Bank ID. Match the bank ID sent by
the transmitter.
Lane ID for Lane 0. Match the lane ID
sent by the transmitter on Logical
Lane 0.
JESD Version. Match the version sent
by the transmitter (0x0 = JESD204A,
0x1 = JESD204B).
Address
[Bits]
0x453[4:0]
0x454[7:0]
0x455[4:0]
0x456[7:0]
0x457[4:0]
0x458[4:0]
0x459[4:0]
Single and Dual Link Configuration
The AD9154 uses the settings contained in Table 44 and Table 45.
Mode 0 to Mode 10 can be used for single link operation.
Mode 4 to Mode 10 can also be used for dual link operation.
To use dual link mode, set DUALLINK (Register 0x300, Bit 3) to 1.
In dual link mode, Link 1 must be programmed with identical
parameters to Link 0. To write to Link 1, set SEL_REG_MAP_1
(Register 0x300, Bit 2) to 1.
0x476[7:0]
If single link mode is being used, a small amount of power can
be saved by powering down the output buffer for SYNCOUT1±,
which can be done by setting Register 0x203, Bit 0 = 1.
0x450[7:0]
Checking Proper Configuration
0x45A[7]
0x451[3:0]
0x452[4:0]
0x459[7:5]
F must be programmed in two places: Register 0x454, Bits[7:0] and
Register 0x459, Bits[7:0].
As a convenience, the AD9154 provides some quick configuration
checks. Register 0x030, Bit 5 is high if an illegal LMFCDELx is
used. Register 0x030, Bit 3 is high if an unsupported combination
of L, M, F, or S is used. Register 0x030, Bit 2 is high if an illegal
K is used. Register 0x030, Bit 1 is high if an illegal SUBCLASSV
is used.
Deskewing and Enabling Logical Lanes
After proper configuration, the logical lanes must be deskewed and
enabled to capture data.
Set Bit x in Register 0x46C to 1 to deskew Logical Lane x and to 0 if
that logical lane is not being used. Then, set Bit x in Register 0x47D
to 1 to enable Logical Lane x and to 0 if that logical lane is not
being used.
Rev. B | Page 47 of 124
AD9154
Data Sheet
J0
DESERIALIZER
SERDIN2±
DESERIALIZER
J19 J18
J11 J10
SERDIN3±
J9
J8
J1
J0
DESERIALIZER
SERIAL JESD204B DATA (L = 4)
SAMPLES SPLIT ACROSS LANES
(HD = 1)
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
LANE 0, OCTET 0
10-BIT/8-BIT
DECODE
DAC0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC1
DESCRAMBLER
40 BITS PARALLEL DATA
(ENCODED AND SCRAMBLED)
2 CONVERTERS
(M = 2)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
16-BIT NIBBLE GROUP
(N = 16)
1 OCTET PER LANE
(F = 1)
Figure 58. JESD204B Mode 4 Data Deframing
Rev. B | Page 48 of 124
11389-158
J1
CONVERTER 0, SAMPLE 0
J8
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CONVERTER 1, SAMPLE 0
J9
NIBBLE GROUP 0
SERDIN1±
LANE 1, OCTET 0
DESERIALIZER
LANE 2, OCTET 0
J11 J10
TRANSPORT
LAYER
NIBBLE GROUP 1
J19 J18
DATA LINK LAYER
LANE 3, OCTET 0
PHYSICAL
LAYER
SERDIN0±
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Data Sheet
AD9154
Mode Configuration Maps
to Mode 10 also apply to dual link operation. Register 0x300 must
be set accordingly for single or dual link operation.
Table 47 through Table 56 contain the SPI configuration maps
for each mode shown in Figure 59 through Figure 67. Figure 59
through Figure 67 show the associated data flow through the
deframing process of the JESD204B receiver for each of the
modes. Mode 0 to Mode 10 apply to single link operation. Mode 4
Additional details regarding all the SPI registers can be found in
the Register Summary and Register Details sections.
Table 47. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 0
J1
J9
LANE 6,
OCTET 0
J8
SERDIN7±
J0
J11 J10
SERDIN6±
J19 J18
J1
LANE 5,
OCTET 0
J8
LANE 4,
OCTET 0
J9
SERDIN3±
J0
J11 J10
SERDIN2±
LANE 3,
OCTET 0
J8
J19 J18
LANE 2,
OCTET 0
J1
SERDIN3±
J0
J11 J10
SERDIN2±
J19 J18
J0
J1
J8
LANE 1,
OCTET 0
LANE 7,
OCTET 0
NIBBLE GROUP 0
NIBBLE GROUP 1
NIBBLE GROUP 2
NIBBLE GROUP 3
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
CONVERTER 2, SAMPLE 0
CONVERTER 3, SAMPLE 0
D15 ... D0
D15 ... D0
D15 ... D0
D15 ... D0
DAC1
DAC2
DAC0
DAC3
11389-159
4 CONVERTERS
(M = 4)
LANE 0,
OCTET 0
J9
1 OCTET PER LANE
(F = 1)
16-BIT NIBBLE GROUP
(N = 16)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
J9
SERIAL JESD204B DATA (L = 8)
SAMPLES SPLIT ACROSS LANES
(HD = 1)
SERDIN1±
0x80
0xFF
0x01
0xFF
J11 J10
0x45A
0x46C
0x476
0x47D
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453[4:0] = 0x7: L = 8 lanes per link
Register 0x454, Bits[7:0] = 0x00: F = 1 octet per frame
Register 0x455, Bits[4:0] = 0x1F: K = 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x03: M = 4 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0xF: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1; Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: JESD204B version; Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per
frame
Register 0x45A, Bit 7 = 1: HD = 1; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: Deskew Link Lane 0 to Link Lane 7
Register 0x476, Bits[7:0] = 0x01: F = 1 octet per frame
Register 0x47D, Bits[7:0] = 0xFF: Enable Link Lane 0 to Link Lane 7
SERDIN0±
Setting
0x07 or 0x87
0x00
0x1F
0x03
0x0F
0x0F or 0x2F
0x20
J19 J18
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Figure 59. JESD204B Mode 0 Data Deframing
Rev. B | Page 49 of 124
AD9154
Data Sheet
Table 48. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 1
16-BIT NIBBLE GROUP
(N = 16)
2 SAMPLES PER
CONVERTER PER FRAME
(S = 2)
4 CONVERTERS
(M = 4)
L 0,
O1
L 1,
O0
NIBBLE
GROUP 0
CONV 0,
SMPL 0
NIBBLE
GROUP 1
CONV 0,
SMPL 1
L 2,
O0
L 3,
O0
NIBBLE
GROUP 2
CONV 1,
SMPL 0
L 3,
O1
NIBBLE
GROUP 3
CONV 1,
SMPL 1
NIBBLE
GROUP 4
CONV 2,
SMPL 0
NIBBLE
GROUP 5
CONV 2,
SMPL 1
L 6,
O0
J0
L 7,
O0
NIBBLE
GROUP 6
CONV 3,
SMPL 0
J1
SERDIN7±
L 6,
O1
J19 J18
J19 J18
SERDIN6±
L 5,
O1
J1
J0
J0
L 5,
O0
J1
SERDIN3±
L 4,
O1
J19 J18
J1
J0
L 4,
O0
J19 J18
SERDIN2±
J19 J18
SERDIN3±
L 2,
O1
J1
J0
J0
L 1,
O1
J1
J1
J19 J18
SERDIN1±
J1
SERDIN0±
L 0,
O0
L 7,
O1
NIBBLE
GROUP 7
CONV 3,
SMPL 1
D15 ... D0 (0) D15 ... D0 (1)
D15 ... D0 (0) D15 ... D0 (1)
D15 ... D0 (0) D15 ... D0 (1)
D15 ... D0 (0) D15 ... D0 (1)
DAC0
DAC1
DAC2
DAC3
11389-160
2 OCTETS PER LANE
(F = 2)
J19 J18
SERIAL JESD204B DATA (L = 8)
SAMPLES NOT SPLIT
ACROSS LANES
(HD = 0)
J19 J18
0x00
0xFF
0x02
0xFF
SERDIN2±
0x45A
0x46C
0x476
0x47D
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x7: L = 8 lanes per link
Register 0x454, Bits[7:0] = 0x01: F = 2 octets per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x03: M = 4 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x1: S = 2 samples per converter per
frame
Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 to Link Lane 7
Register 0x476, Bits[7:0] = 0x02: F = 2 octets per frame
Register 0x47D, Bits[7:0] = 0xFF: 8 lanes enabled, set one bit per lane to enable
J0
Setting
0x07 or 0x87
0x01
0x0F or 0x1F
0x03
0x0F
0x0F or 0x2F
0x21
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Figure 60. JESD204B Mode 1 Data Deframing
Rev. B | Page 50 of 124
Data Sheet
AD9154
Table 49. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 2
4 CONVERTERS
(M = 4)
J0
J1
J19 J18
SERDIN3±
J0
J1
J19 J18
SERDIN2±
SERDIN1±
J1
SERDIN0±
LANE 0,
LANE 0,
OCTET 0
OCTET 1
NIBBLE GROUP 0
LANE 1,
LANE 1,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 11
LANE 2,
LANE 2,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 22
LANE 3,
LANE 3,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 33
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
CONVERTER 2, SAMPLE 0
CONVERTER 3, SAMPLE 0
D15 ... D0 (0)
D15 ... D0 (0)
D15 ... D0 (0)
D15 ... D0 (0)
DAC1
DAC2
DAC0
DAC3
11389-161
2 OCTETS PER LANE
(F = 2)
16-BIT NIBBLE GROUP
(N = 16)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
J19 J18
SERIAL JESD204B DATA (L = 4)
SAMPLES NOT SPLIT
ACROSS LANES
(HD = 0)
J0
0x00
0x0F
0x02
0x0F
J1
0x45A
0x46C
0x476
0x47D
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x3: L = 4 lanes per link
Register 0x454, Bits[7:0] = 0x01: F = 2 octets per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x03: M = 4 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per
frame
Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: Deskew Link Lane 0 to Link Lane 3
Register 0x476, Bits[7:0] = 0x02: F = 2 octets per frame
Register 0x47D, Bits[7:0] = 0x0F: enable Link Lane 0 to Link Lane 3
J19 J18
Setting
0x03 or 0x83
0x01
0x0F or 0x1F
0x03
0x0F
0x0F or 0x2F
0x20
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Figure 61. JESD204B Mode 2 Data Deframing
Rev. B | Page 51 of 124
AD9154
Data Sheet
Table 50. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 3
0x00
0x03
0x04
0x03
J0
0x45A
0x46C
0x476
0x47D
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x1: L = 2 lanes per link
Register 0x454, Bits[7:0] = 0x03: F = 4 octets per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x03: M = 4 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] =0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per
frame
Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 and Link Lane 1
Register 0x476, Bits[7:0] = 0x04: F = 4 octets per frame
Register 0x47D, Bits[7:0] = 0x03: enable Link Lane 0 and Link Lane 1
J1
J1
SERDIN1±
J39 J38
LANE 0,
LANE 0,
OCTET 0
OCTET 1
NIBBLE GROUP 0
LANE 0,
LANE 0,
OCTET 2
OCTET 3
NIBBLE
NIBBLE GROUP
GROUP 11
LANE 1,
LANE 1,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 22
LANE 1,
LANE 1,
OCTET 2
OCTET 3
NIBBLE
NIBBLE GROUP
GROUP 33
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
CONVERTER 2, SAMPLE 0
CONVERTER 3, SAMPLE 0
D15 ... D0 (0)
D15 ... D0 (0)
D15 ... D0 (0)
D15 ... D0 (0)
DAC1
DAC2
DAC0
DAC3
11389-162
4 CONVERTERS
(M = 4)
J21 J20 J19 J18
SERDIN0±
4 OCTETS PER LANE
(F = 4)
16-BIT NIBBLE GROUP
(N = 16)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
J39 J38
SERIAL JESD204B DATA (L = 2)
SAMPLES NOT SPLIT
ACROSS LANES
(HD = 0)
J21 J20 J19 J18
Setting
0x01 or 0x81
0x03
0x0F or 0x1F
0x03
0x0F
0x0F or 0x2F
0x20
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Figure 62. JESD204B Mode 3 Data Deframing
Table 51. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 4
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Setting
0x03 or 0x83
0x00
0x0F or 0x1F
0x01
0x0F
0x0F or 0x2F
0x20
0x45A
0x46C
0x476
0x47D
0x01
0x0F
0x01
0x0F
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x3: L = 4 lanes per link
Register 0x454, Bits[7:0] = 0x00: F = 1 octet per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K =16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x01: M = 2 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per
frame
Register 0x45A, Bit 7 = 1: HD = 1; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 to Link Lane 3
Register 0x476, Bits[7:0] = 0x01: F = 1 octet per frame
Register 0x47D, Bits[7:0] = 0x0F: Enable Link Lane 0 to Link Lane 3
Rev. B | Page 52 of 124
Data Sheet
AD9154
See Figure 58 for an illustration of the AD9154 JESD204B Mode 4 data deframing process.
Table 52. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 5
2 CONVERTERS
(M = 2)
J0
J1
SERDIN3±
J19 J18
J0
J1
SERDIN2±
J19 J18
J0
J1
J19 J18
LANE 0,
LANE 0,
OCTET 0
OCTET 1
NIBBLE GROUP 0
LANE 1,
LANE 1,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 11
LANE 2,
LANE 2,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 22
LANE 3,
LANE 3,
OCTET 0
OCTET 1
NIBBLE
NIBBLE GROUP
GROUP 33
CONVERTER 0, SAMPLE 0
CONVERTER 0, SAMPLE 1
CONVERTER 1, SAMPLE 0
CONVERTER 1, SAMPLE 1
D15 ... D0 (0)
D15 ... D0 (1)
D15 ... D0 (0)
D15 ... D0 (1)
DAC0
DAC1
11389-163
2 OCTETS PER LANE
(F = 2)
16-BIT NIBBLE GROUP
(N = 16)
2 SAMPLES PER
CONVERTER PER FRAME
(S = 2)
SERDIN1±
SERIAL JESD204B DATA (L = 4)
SAMPLES NOT SPLIT
ACROSS LANES
(HD = 0)
J1 J0
0x21
0x00
0x0F
0x02
0x0F
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled; Register 0x453, Bits[4:0] = 0x3: L = 4 lanes per link
Register 0x454, Bits[7:0] = 0x01: F = 2 octets per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x01: M = 2 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x1: S = 2 samples per converter per
frame
Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 to Link Lane 3
Register 0x476, Bits[7:0] = 0x02: F = 2 octets per frame
Register 0x47D, Bits[7:0] = 0x0F: Enable Link Lane 0 to Link Lane 3
SERDIN0±
0x45A
0x46C
0x476
0x47D
Setting
0x03 or 0x83
0x01
0x0F or 0x1F
0x01
0x0F
0x0F or 0x2F
J19 J18
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Figure 63. JESD204B Mode 5 Data Deframing
Rev. B | Page 53 of 124
AD9154
Data Sheet
Table 53. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 6
DAC0
D0
D1
D2
D4
D5
D6
D7
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
CONVERTER 1, SAMPLE 0
D10
CONVERTER 0, SAMPLE 0
D3
SERDIN1±
J1
SERDIN0±
J19 J18
LANE 1, OCTET 1
NIBBLE GROUP 1
D11
D12
D13
D14
LANE 1, OCTET 0
LANE 0, OCTET 1
NIBBLE GROUP 0
DAC1
11389-164
2 CONVERTERS
(M = 2)
LANE 0, OCTET 0
D15
2 OCTETS PER LANE
(F = 2)
16-BIT NIBBLE GROUP
(N = 16)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
J19 J18
SERIAL JESD204B DATA (L = 2)
SAMPLES NOT SPLIT
ACROSS LANES
(HD = 0)
J1
J0
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled, Register 0x453, Bits[4:0] = 0x1: L = 2 lanes per link
Register 0x454, Bits[7:0] = 0x01: F = 2 octets per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x01: M = 2 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per frame
Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: deskew Link Lane 0 and Link Lane 1
Register 0x476, Bits[7:0] = 0x02: F = 2 octets per frame
Register 0x47D, Bits[7:0] = 0x03: Enable Link Lane 0 and Link Lane 1
D8
Setting
0x01 or 0x81
0x01
0x0F or 0x1F
0x01
0x0F
0x0F or 0x2F
0x20
0x00
0x03
0x02
0x03
J0
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x46C
0x476
0x47D
Figure 64. JESD204B Mode 6 Data Deframing
Rev. B | Page 54 of 124
Data Sheet
AD9154
Table 54. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 7
J0
J1
SERIAL JESD204B DATA (L = 1)
SAMPLES NOT SPLIT
ACROSS LANES
(HD = 0)
4 OCTETS PER LANE
(F = 4)
16-BIT NIBBLE GROUP
(N = 16)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
2 CONVERTERS
(M = 2)
LANE 0,
LANE 0,
OCTET 0
OCTET 1
NIBBLE GROUP 0
LANE 0,
LANE 0,
OCTET 2
OCTET 3
NIBBLE
NIBBLE GROUP
GROUP 12
CONVERTER 0, SAMPLE 0
CONVERTER 1, SAMPLE 0
D15 ... D0
D15 ... D0
DAC0
DAC1
11389-165
0x00
0x01
0x04
0x01
SERDIN0±
0x45A
0x46C
0x476
0x47D
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled, Register 0x453, Bits[4:0] = 0x0: L = 1 lane per link
Register 0x454, Bits[7:0] = 0x03: F = 4 octets per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x01: M = 2 converters per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per
frame
Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: Deskew Link Lane 0
Register 0x476, Bits[7:0] = 0x04: F = 4 octets per frame
Register 0x47D, Bits[7:0] = 0x01: Enable Link Lane 0
J21 J20 J19 J18
Setting
0x00 or 0x80
0x03
0x0F or 0x1F
0x01
0x0F
0x0F or 0x2F
0x20
J39 J38
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Figure 65. JESD204B Mode 7 Data Deframing
Rev. B | Page 55 of 124
AD9154
Data Sheet
Table 55. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 9
J0
J1
SERDIN1±
LANE 0,
OCTET 0
LANE 1,
OCTET 0
NIBBLE GROUP 0
CONVERTER 0, SAMPLE 0
1 CONVERTER
(M = 1)
D15 ... D0
DAC0
Figure 66. JESD204B Mode 9 Data Deframing
Rev. B | Page 56 of 124
11389-166
1 OCTET PER LANE
(F = 1)
16-BIT NIBBLE GROUP
(N = 16)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
J8
SERIAL JESD204B DATA (L = 2)
SAMPLES SPLIT ACROSS LANES
(HD = 1)
J9
0x01
0x03
0x01
0x03
J11 J10
0x45A
0x46C
0x476
0x47D
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled, Register 0x453, Bits[4:0] = 0x1: L = 2 lanes per link
Register 0x454, Bits[7:0] = 0x00: F = 1 octet per frame
Register 0x455, Bits[4:0] = 0x1F: K = 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x00: M = 1 converter per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: Set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per
frame
Register 0x45A, Bit 7 = 1: HD = 1; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0xFF: Deskew Link Lane 0 and Link Lane 1
Register 0x476, Bits[7:0] = 0x01: F = 1 octet per frame
Register 0x47D, Bits[7:0] = 0x03: Enable Link Lane 0 and Link Lane 1
SERDIN0±
Setting
0x01 or 0x81
0x00
0x1F
0x00
0x0F
0x0F or 0x2F
0x20
J19 J18
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Data Sheet
AD9154
Table 56. SPI Configuration Map—Register Settings for JESD204B Parameters for Mode 10
J0
SERIAL JESD204B DATA (L = 1)
SAMPLES SPLIT ACROSS LANES
(HD = 0)
2 OCTETS PER LANE
(F = 2)
16-BIT NIBBLE GROUP
(N = 16)
1 SAMPLE PER
CONVERTER PER FRAME
(S = 1)
LANE 0,
OCTET 0
LANE 1,
OCTET 0
NIBBLE GROUP 0
CONVERTER 0, SAMPLE 0
D15 ... D0
1 CONVERTER
(M = 1)
DAC0
11389-167
0x00
0x01
0x02
0x01
J1
0x45A
0x46C
0x476
0x47D
Description
Register 0x453, Bit 7 = 0 or 1: scrambling disabled or enabled, Register 0x453, Bits[4:0] = 0x0: L = 1 lane per link
Register 0x454, Bits[7:0] = 0x01: F = 2 octets per frame
Register 0x455, Bits[4:0] = 0x0F or 0x1F: K = 16 or 32 frames per multiframe
Register 0x456, Bits[7:0] = 0x00: M = 1 converter per link
Register 0x457, Bits[7:6] = 0x0: always set CS = 0; Register 0x457, Bits[4:0] = 0x0F: N = 16, always set to 16-bit resolution
Register 0x458, Bits[7:5] = 0x0 or 0x1: Subclass 0 or Subclass 1, Register 0x458, Bits[4:0] = 0xF: NP = 16 bits per sample
Register 0x459, Bits[7:5] = 0x1: set to JESD204B version, Register 0x459, Bits[4:0] = 0x0: S = 1 sample per converter per
frame
Register 0x45A, Bit 7 = 0: HD = 0; Register 0x45A, Bits[4:0] = 0x00: always set CF = 0
Register 0x46C, Bits[7:0] = 0x01: Deskew Link Lane 0 to Link Lane 7
Register 0x476, Bits[7:0] = 0x02: F = 2 octets per frame
Register 0x47D, Bits[7:0] = 0x01: Enable Link Lane 0
J19 J18
Setting
0x00 or 0x80
0x01
0x0F or 0x1F
0x00
0x0F
0x0F or 0x2F
0x20
SERDIN0±
Address
0x453
0x454
0x455
0x456
0x457
0x458
0x459
Figure 67. JESD204B Mode 10 Data Deframing
Rev. B | Page 57 of 124
AD9154
Data Sheet
JESD204B TEST MODES
Transport Layer Testing
PHY PRBS Testing
The JESD204B receiver in the AD9154 supports the short
transport layer (STPL) test as described in the JESD204B
standard. Use this test to verify the data mapping between the
JESD204B transmitter and receiver.
The JESD204B receiver on the AD9154 includes a pseudorandom
binary sequence (PRBS) pattern checker on the back end of its
physical layer. This functionality enables bit error rate (BER)
testing of each physical lane of the JESD204B link. The PHY
PRBS pattern checker does not require that the JESD204B link be
established. It can synchronize with a PRBS7, PRBS15, or PRBS31
data pattern. PRBS pattern verification can be performed on
multiple lanes at once. The error counts for failing lanes are
reported for one JESD204B lane at a time. The process for
performing PRBS testing on the AD9154 is as follows:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Start sending a PRBS7, PRBS15, or PRBS31 pattern from
the JESD204B transmitter.
Select and write the appropriate PRBS pattern to
Register 0x316, Bits[3:2], as shown in Table 57.
Enable the PHY test for all lanes being tested by writing to
PHY_TEST_EN (Register 0x315). Each bit of Register 0x315
enables the PRBS test for the corresponding lane. For
example, writing a 1 to Bit 0 enables the PRBS test for
Physical Lane 0.
Toggle PHY_TEST_RESET (Register 0x316, Bit 0) from 0
to 1, then back to 0.
Set PHY_PRBS_ERROR_THRESHOLD (Register 0x319 to
Register 0x317) as desired.
Write a 0 and then a 1 to PHY_TEST_START
(Register 0x316, Bit 1). The rising edge of
PHY_TEST_START starts the test.
Wait 500 ms.
Stop the test by writing 0 to PHY_TEST_START
(Register 0x316, Bit 1).
Read the PRBS test results.
a. Each bit of PHY_PRBS_TEST_STATUS (Register
0x31D) corresponds to one SERDES lane. 0 = fail,
1 = pass.
b. The number of PRBS errors seen on each failing lane
can be read by writing the lane number to check (0 to
7) in the PHY_SRC_ERR_CNT (Register 0x316,
Bits[6:4]) and reading PHY_PRBS_ERR_COUNT
(Register 0x31A to Register 0x31C). The maximum
error count is 224 − 1. If all bits of Register 0x31A to
Register 0x31C are high, the maximum error count on
the selected lane has been exceeded.
Table 57. PHY PRBS Pattern Selection
PHY_PRBS_PAT_SEL Setting
(Register 0x316[3:2])
0b00 (default)
0b01
0b10
PRBS Pattern
PRBS7
PRBS15
PRBS31
The STPL test ensures that each sample from each converter is
mapped appropriately according to the number of converters
(M) and the number of samples per converter (S). As specified
in the JESD204B standard, the converter manufacturer specifies
what test samples are transmitted. Each sample must have a
unique value. For example, if M = 2 and S = 2, four unique
samples are transmitted repeatedly until the test is stopped. The
expected sample must be programmed into the device and the
expected sample is compared to the received sample one sample
at a time until all have been tested. The process for performing
this test on the AD9154 is described as follows:
1.
2.
3.
4.
5.
6.
7.
8.
Synchronize the JESD204B link.
Enable the STPL test at the JESD204B Tx.
Select Converter 0 Sample 0 for testing. Write
SHORT_TPL_M_SEL (Register 0x32C, Bits[3:2]) = 0 and
SHORT_TPL_SP_SEL (Register 0x32C, Bits[5:4]) = 0.
Set the expected test sample for Converter 0, Sample 0.
Program the expected 16-bit test sample into the
SHORT_TPL_REF_SP_x registers (Register 0x32E and
Register 0x32D).
Enable the STPL test. Write 1 to SHORT_TPL_TEST_EN
(Register 0x32C, Bit 0).
Toggle the STPL reset, SHORT_TPL_TEST_RESET
(Register 0x32C, Bit 1), from 0 to 1, then back to 0.
Check for failures. Read SHORT_TPL_FAIL
(Register 0x32F, Bit 0), 0 = pass, 1 = fail.
Repeat Steps 3 to Step 7 for each sample of each converter.
Conv0Sample0 through ConvM − 1SampleS − 1.
Repeated CGS and ILAS Test
As per Section 5.3.3.8.2 of the JESD204B specification, the
AD9154 can check that a constant stream of /K28.5/ characters
is being received, or that a CGS followed by a constant stream of
ILAS is being received.
To run a repeated CGS test, send a constant stream of /K28.5/
characters to the AD9154 SERDES inputs. Next, set up the
device and enable the links as described in the Device Setup
Guide section. Ensure that the /K28.5/ characters are being
received by verifying that the SYNCOUTx± signal has been
deasserted and that CGS has passed for all enabled link lanes by
reading Register 0x470. Program Register 0x300, Bit 2 = 0 to
monitor the status of lanes on Link 0, and Register 0x300, Bit 2 = 1
to monitor the status of lanes on Link 1 for dual link mode.
To run the CGS followed by a repeated ILAS sequence test,
follow the Device Setup Guide section, but before performing
the last write (enabling the links), enable the ILAS test mode by
writing a 1 to Register 0x477, Bit 7. Then, enable the links.
When the device recognizes 4 CGS characters on each lane, it
Rev. B | Page 58 of 124
Data Sheet
AD9154
Read Register 0x473 to verify that initial lane synchronization has
passed for all enabled link lanes. Program Register 0x300, Bit 2 = 0
to monitor the status of lanes on Link 0, and Register 0x300, Bit 2 =
1 to monitor the status of lanes on Link 1 for dual link mode.
JESD204B ERROR MONITORING
Disparity, Not in Table, and Unexpected Control
Character Errors
Per Section 7.6 of the JESD204B specification, the AD9154 can
detect disparity errors, not in table errors, and unexpected
control character errors, and can optionally issue a sync request
and reinitialize the link when errors occur.
Note that the disparity error counter counts all characters with
invalid disparity, regardless of whether they are in the 8-bit/10-bit
decoding table. This is a minor deviation from the JESD204B
specification, which only counts disparity errors when they are
in the 8-bit/10-bit decoding table.
Check for Error Count Over Threshold
In addition to reading the error count per lane and error type as
described in the Checking Error Counts section, the user can
check a register to see if the error count for a given error type
has reached a programmable threshold.
The same error threshold is used for the three error types:
disparity, not in table, and unexpected control character. The
error counters are on a per error type basis. To use this feature,
complete the following steps:
1.
2.
Checking Error Counts
The error count can be checked for disparity errors, not in table
errors, and unexpected control character errors. The error
counts are on a per lane and per error type basis. Note that the
lane select and counter select are programmed into Register 0x46B
and the error count is read back from the same address. To
check the error count, complete the following steps:
1.
2.
Select the desired link lane and error type of the counter to
view. Write these to Register 0x46B according to Table 58.
To select a link lane, first select a link (Register 0x300, Bit 2
= 0 to select Link 0 or Register 0x300, Bit 2 = 1 to select
Link 1 [dual link only]). Note that, when using Link 1,
Link Lane x refers to Logical Lane x + 4.
Read the error count from Register 0x46B. Note the
maximum error count is equal to the error threshold set in
Register 0x47C.
Error Counter and IRQ Control
Write to Register 0x46D and Register 0x46F to reset or disable
the error counts and to reset the IRQ for a given lane. Note that
these are the same registers that are used to report error count
over threshold (see the Check for Error Count Over Threshold
section); thus, the readback is not the value that was written.
For each error type,
1.
2.
3.
Table 58. Error Counters
Addr.
0x46B
Bits
[6:4]
[1:0]
Variable
LaneSel
CntrSel
Description
LaneSel = x to monitor the error
count of Link Lane x. See the notes
on link lane in Step 1 of the Checking
Error Counts section.
CntrSel = 0b00 for bad running
disparity counter.
CntrSel = 0b01 for not in table error
counter.
CntrSel = 0b10 for unexpected control
character counter.
Program the desired error count threshold into
ERRORTHRES (Register 0x47C).
Read back the error status for each error type to see if the
error count has reached the error threshold.
Disparity errors are reported in Register 0x46D.
Not in table errors are reported in Register 0x46E.
Unexpected control character errors are reported in
Register 0x46F.
Select the link lane to access. To select a link lane, first
select a link (Register 0x300, Bit 2 = 0 to select Link 0,
Register 0x300, Bit 2 = 1 to select Link 1 [dual link only]).
Note that, when using Link 1, Link Lane x refers to Logical
Lane x + 4.
Decide whether to reset the IRQ, disable the error count,
and/or reset the error count for the given lane and error type.
Write the link lane and desired reset or disable action to
Register 0x46D to Register 0x46F according to Table 59.
Table 59. Error Counter and IRQ Control: Disparity
(Register 0x46D), Not In Table (Register 0x46E), Unexpected
Control Character (Register 0x46F)
Bits
7
Variable
RstIRQ
6
Disable_ErrCnt
5
RstErrCntr
[2:0]
LaneAddr
Rev. B | Page 59 of 124
Description
RstIRQ = 1 to reset IRQ for the lane
selected in Bits[2:0].
Disable_ErrCnt = 1 to disable the error
count for the lane selected in Bits[2:0].
RsteErrCntr = 1 to reset the error
count for the lane selected in Bits[2:0].
LaneAddr = x to monitor the error
count of Link Lane x. See the notes on
link lane in Step 1 of the Checking
Error Counts section.
AD9154
Data Sheet
Table 61. Sync Assertion Mask
Monitoring Errors via SYNCOUTx±
When one or more disparity, not in table, or unexpected
control character error occurs, the error is reported on the
SYNCOUTx± pins as per Section 7.6 of the JESD204B
specification. The JESD204B specification states that the
SYNCOUTx± signal is asserted for exactly 2 frame periods when
an error occurs. For the AD9154, the width of the SYNCOUTx±
pulse can be programmed. The settings to achieve a SYNCOUTx±
pulse of 2 frame clock cycles are given in Table 60.
Addr.
0x47B
Table 60. Setting SYNCOUTx± Error Pulse Duration
JESD204B
Mode IDs
0, 4, 9
1, 2, 5, 6, 10
3, 7
1
PClockFactor
(Frames/PClock)
4
2
1
SYNCB_ERR_DUR
(Register 0x312[5:4]) Setting1
0 (default)
1
2
These register settings assert the SYNCOUTx± signal for 2 frame clock cycles
pulse widths.
Disparity, NIT, Unexpected Control Character IRQs
For disparity, not in table, and unexpected control character
errors, error count over the threshold events are available as
IRQ events. Enable these events by writing to Register 0x47A,
Bits[7:5]. The IRQ event status can be read at the same address
(Register 0x47A, Bits[7:5]) after the IRQs are enabled.
Errors Requiring Reinitializing
A link reinitialization automatically occurs when four invalid
disparity characters are received as per Section 7.1 of the JESD
specification. When a link reinitialization occurs, the resync
request is 5 frames and 9 octets long.
The user can optionally reinitialize the link when the error
count for disparity errors, not in table errors, or unexpected
control characters reaches a programmable error threshold. The
process to enable the reinitialization feature for certain error
types is as follows:
1.
2.
3.
4.
Set THRESHOLD_MASK_EN (Register 0x477, Bit 3) = 1.
Note that when this bit is set, unmasked errors do not
saturate at either threshold or maximum value.
Enable the sync assertion mask for each type of error by
writing to the SYNC_ASSERTION_MASK register
(Register 0x47B, Bits[7:5]) according to Table 61.
Program the desired error counter threshold into
ERRORTHRES (Register 0x47C).
For each error type enabled in the SYNC_ASSERTION_
MASK register, if the error counter on any lane reaches the
programmed threshold, SYNCOUTx± falls, issuing a sync
request. Note that all error counts are reset when a link
reinitialization occurs. The IRQ does not reset and must be
reset manually.
Bit No.
7
Bit Name
BADDIS_S
6
NIT_S
5
UCC_S
Description
Set to 1 to assert SYNCOUTx±
if the disparity error count
reaches the threshold
Set to 1 to assert SYNCOUTx±
if the not in table error count
reaches the threshold
Set to 1 to assert SYNCOUTx±
if the unexpected control
character count reaches the
threshold
CGS, Frame Sync, Checksum, and ILAS Monitoring
Register 0x470 to Register 0x473 can be monitored to verify
that each stage of JESD204B link establishment has occurred.
Program Register 0x300, Bit 2 = 0 to monitor the status of the
lanes on Link 0, and Register 0x300, Bit 2 = 1 to monitor the
status of the lanes on Link 1.
Bit x of CODEGRPSYNCFLAG (Register 0x470) is high if
Link Lane x received at least 4 K28.5 characters and passed code
group synchronization.
Bit x of FRAMESYNCFLAG (Register 0x471) is high if
Link Lane x completed initial frame synchronization.
Bit x of GOODCHKSUMFLG (Register 0x472) is high if the
checksum sent over the lane matches the sum of the JESD204B
parameters sent over the lane during ILAS for Link Lane x. The
parameters can be added either by summing the individual fields
in registers or summing the packed register. If Register 0x300,
Bit 6 = 0 (default), the calculated checksums are the lower 8 bits
of the sum of the following fields: DID, BID, LID, SCR, L − 1, F − 1,
K − 1, M − 1, N − 1, SUBCLASSV, NP − 1, JESDV, S − 1, and
HD. If Register 0x300, Bit 6 = 1, the calculated checksums are
the lower 8 bits of the sum of Register 0x400 to Register 0x40C
and LID.
Bit x of INITIALLANESYNC (Register 0x473) is high if
Link Lane x passed the initial lane alignment sequence.
CGS, Frame Sync, Checksum, and ILAS IRQs
Fail signals for CGS, frame sync, checksum, and ILAS are available
as IRQ events. Enable them by writing to Register 0x47A,
Bits[3:0]. The IRQ event status can be read at the same address
(Register 0x47A, Bits[3:0]) after the IRQs are enabled. Write a 1
to Register 0x470, Bit 7 to reset the CGS IRQ. Write a 1 to
Register 0x471 to reset the frame sync IRQ. Write a 1 to
Register 0x472 to reset the checksum IRQ. Write a 1 to
Register 0x473 to reset the ILAS IRQ.
Rev. B | Page 60 of 124
Data Sheet
AD9154
Configuration Mismatch IRQ
The AD9154 has a configuration mismatch flag that is available
as an IRQ event. Use Register 0x47B, Bit 3 to enable the
mismatch flag (it is enabled by default), and then use
Register 0x47B, Bit 4 to read back its status and reset the IRQ
signal. See the Interrupt Request Operation section for more
information.
Register 0x40D). All these registers are paged per link (in
Register 0x300).
Note that this function is different from the good checksum
flags in Register 0x472. The good checksum flags ensure that
the transmitted checksum matches a calculated checksum based
on the transmitted settings. The configuration mismatch event
ensures that the transmitted settings match the configured settings.
The configuration mismatch event flag is high when the link
configuration settings (in Register 0x450 to Register 0x45D) do
not match the JESD204B transmitted settings (Register 0x400 to
Rev. B | Page 61 of 124
AD9154
Data Sheet
INPUT
POWER
DETECTION
AND
PROTECTION
COARSE
AND
FINE
MODULATION
DIGITAL GAIN
AND PHASE
AND OFFSET
ADJUSTMENT
INV
SINC
11389-032
DIGITAL DATAPATH
Figure 68. Block Diagram of the Digital Datapath
Figure 68 shows a block diagram of the signal processing digital
datapath. The digital processing includes an input power
detection block, three half-band interpolation filters, a quadrature
modulator consisting of a fine resolution NCO modulator and
fDAC/4 and fDAC/8 coarse modulator blocks, an inverse sinc filter,
and gain, phase, offset, and group delay adjustment blocks.
The datapath is organized into two identical paths. Each path
processes a pair of digital signals input from the JESD204B
transport layer block. The digital signals are processed by a
datapath and input to a pair of DAC cores. Interpolation modes
process the pair of signals as independent data streams. The
coarse and fine modulation block requires that a data stream to
be upconverted be an I/Q pair of signals
DUAL PAGING
The digital datapath registers are paged to allow configuration
of either DAC dual independently or both simultaneously. Table 62
shows how to use the dual paging register.
Table 62. Paging Modes
PAGEINDX
Reg. 0x008[1:0]
1
2
3 (default)
Duals
Paged
A
B
A and B
DACs Updated
DAC0 and DAC1
DAC2 and DAC3
DAC0, DAC1, DAC2, and DAC3
INTERPOLATION MODES
Interpolation increases the sampling rate of a digital signal and
can be bypassed. The transmit path contains three half-band
interpolation filters, which each provide a 2× increase in the
output sampling rate and a low-pass function. Table 63 shows
how to select each available interpolation mode, their usable
bandwidths, and their maximum data rates. Note that
fDATA = fDAC/InterpolationFactor
The maximum values of fDATA for interpolator bypass and the
three interpolation factors are listed in Table 2 as adjusted DAC
update rates; fDATA is another name for the adjusted DAC update
rate. Interpolation mode is paged as described in the Dual
Paging section. Register 0x030, Bit 0 is high if an unsupported
interpolation mode is selected.
Table 63. Interpolation Modes and Usable Bandwidth
Interpolation Mode
1× (bypass)
2×
4×
8×
1
INTERPMODE
Reg. 0x112[2:0]
0x00
0x01
0x03
0x04
Usable Bandwidth
0.5 x fDATA
0.4 × fDATA
0.4 × fDATA
0.4 × fDATA
The maximum speed for 1× interpolation is limited by the JESD204B interface.
Filter Performance
Several functions are paged by DAC dual, such as input data
format, downstream protection, interpolation, modulation,
inverse sinc, digital gain, phase offset, dc offset, group delay, IQ
swap, datapath PRBS, LMFC sync, and NCO alignment.
Interpolation modes increase the sampling rate of a digital
signal by a factor of 2, 4, or 8. As part of the process, a digital
low-pass filter is applied. The filter magnitude response for each
interpolation mode is shown in Figure 69.
DATA FORMAT
The usable bandwidth (as shown in Table 63) is defined as the
frequency band over which the filters have a pass-band ripple of
less than ±0.001 dB and an image rejection of greater than 85 dB.
0
2×
4×
8×
–20
MAGNITUDE (dB)
BINARY_FORMAT (Register 0x110, Bit 7), paged as described
in the Dual Paging section) controls the expected input data
format. By default it is 0, which means the input data must be in
twos complement. It can also be set to 1, which means input
data is in offset binary (0x0000 is negative full scale and 0xFFFF
is positive full scale).
–40
–60
–100
0
0.2
0.4
0.6
0.8
FREQUENCY (×fDAC )
Figure 69. All Band Responses of Interpolation Filters
Rev. B | Page 62 of 124
1.0
11389-169
–80
Data Sheet
AD9154
Filter Performance Beyond Specified Bandwidth
where FTW is a 48-bit twos complement number.
–0.1
The frequency tuning word is set as shown in Table 65 and
paged as described in the Dual Paging section.
70
–0.2
60
–0.3
50
–0.4
40
–0.5
30
Table 65. NCO FTW Registers
IMAGE REJECTION
PASS-BAND RIPPLE
20
40
–0.6
41
42
43
44
45
BANDWIDTH (% fDATA )
Figure 70. Interpolation Filter Performance Beyond Specified Bandwidth
Figure 70 shows the performance of the interpolation filters
beyond 0.4 × fDATA. Note that the ripple increases much slower
than the image rejection decreases. This means that if the
application can tolerate degraded image rejection from the
interpolation filters, more bandwidth can be used.
DIGITAL MODULATION
The AD9154 includes modulation blocks that upconvert I/Q
quadrature signal pairs to an IF frequency in the digital domain.
The coarse modulation modes (fDAC/4 and fDAC/8) upconvert an
I/Q pair of digital signals to one of the selected IFs. The NCO
fine modulation mode upconverts an I/Q signal pair to an IF
frequency programmed into the NCO. Modulation mode is
selected as shown in Table 64 and is paged as described in the
Dual Paging section.
Address
0x114
0x115
0x116
0x117
0x118
0x119
Value
FTW[7:0]
FTW[15:8]
FTW[23:16]
FTW[31:24]
FTW[39:32]
FTW[47:40]
Description
8 LSBs of FTW
Next 8 bits of FTW
Next 8 bits of FTW
Next 8 bits of FTW
Next 8 bits of FTW
8 MSBs of FTW
Unlike other registers, the FTW registers are not updated
immediately upon writing. Instead, the FTW registers update on
the rising edge of FTW_UPDATE_REQ (Register 0x113[0]).
After an update request, FTW_UPDATE_ACK (Register 0x113[1])
must be high to acknowledge that the FTW has updated.
SEL_SIDEBAND (Register 0x111, Bit 1; paged as described in
the Dual Paging section) is a convenience bit that can be set to
use the negative modulation result. This is equivalent to flipping
the sign of FTW.
I DATA
INTERPOLATION
COS(ωn + θ)
ω
π NCO
θ
SIN(ωn + θ)
FTW[47:0]
NCO PHASE OFFSET
[15:0]
SINE
Table 64. Modulation Mode Selection
Modulation Mode
None
NCO Fine Modulation
Coarse − fDAC/4
Coarse − fDAC/8
OUT_I
OUT_Q
–
+
–1
MODULATION_TYPE
Register 0x111, Bits[3:2]
0b00
0b01
0b10
0b11
SPECTRAL
INVERSION
Q DATA
0
1
INTERPOLATION
11389-039
80
−fDAC/2 ≤ fCARRIER < +fDAC/2
FTW = (fCARRIER/fDAC) × 248
0
MAXIMUM PASS-BAND RIPPLE (dB)
90
11389-170
MINIMUM INTERPOLATION IMAGE REJECTION (dB)
The usable pass band of the interpolation filter is specified as
0.4 × fDATA. The filters can be used slightly beyond this ratio at
the expense of increased pass-band ripple and decreased
interpolation image rejection.
The frequency of the quadrature carrier is set via an FTW. The
quadrature carrier is mixed with the I and Q data and then
summed into the I and Q datapaths, as shown in Figure 71.
Figure 71. NCO Modulator Block Diagram
NCO Fine Modulation
NCO Phase Offset
This modulation mode uses the NCO, a phase shifter, and a
complex modulator to upconvert an I/Q digital signal pair to an
IF frequency within the first Nyquist zone of the DAC cores.
Figure 71 shows a block diagram of the NCO modulator. This
allows output signals to be placed anywhere in the output
spectrum with very fine frequency resolution. The NCO
produces a quadrature carrier to translate the input signal to a new
center frequency. A quadrature carrier is a pair of sinusoidal
waveforms of the same frequency, offset 90° from each other.
The NCO phase offset feature allows rotation of the I and Q
phases. Unlike phase adjust, this feature moves the phases of
both I and Q channels together. NCO phase offset can be used
only when using NCO fine modulation.
−180° ≤ DegreesOffset < +180°
PhaseOffset = (DegreesOffset/180°) × 215
where PhaseOffset is a 16-bit twos complement number.
The NCO phase offset is set as shown in Table 66 and paged as
described in the Dual Paging section. Because this function is
Rev. B | Page 63 of 124
AD9154
Data Sheet
part of the fine modulation block, phase offset is not updated
immediately upon writing. Instead, it updates on the rising edge of
FTW_ UPDATE_REQ (Register 0x113, Bit 0 ) along with the FTW.
•
Table 66. NCO Phase Offset Registers
Address
0x11A
0x11B
Value
NCO_PHASE_OFFSET[7:0]
NCO_PHASE_OFFSET[15:8]
Digital Gain
INVERSE SINC
DACs have a sin(x)/x amplitude roll-off as a function frequency.
This characteristic is shown in blue in Figure 72. The AD9154
provides a digital inverse sinc function to compensate for this
roll-off over frequency. The filter is enabled by setting the
INVSINC_ENABLE bit (Register 0x111, Bit 7, paged as described
in the Dual Paging section). Inverse sinc is enabled by default.
Figure 72 shows the frequency response of sin(x)/x roll-off, the
inverse sinc filter, and the composite response. The composite
response has less than ±0.05 dB pass-band ripple up to a
frequency of 0.4 × fDACCLK. To provide the necessary peaking at
the upper end of the pass band, the inverse sinc filter shown has
an intrinsic insertion loss of about 3.8 dB; in many cases, this can
be partially compensated as described in the Digital Gain section.
Digital gain is used to independently adjust the digital signal
magnitude being fed into each DAC. The digital gain code can
be left at its default value where it provides 0 dB of digital
backoff (in other words, a gain of 1), or it can be programmed
to provide larger digital backoff. Digital gain can be programmed
to introduce an I/Q pair gain imbalance to help a quadrature
modulator following the AD9154 in a signal chain cancel an
unwanted SSB sideband. Digital gain is enabled by default and
must not be disabled.
The amount of digital gain (GainCode) desired can be programmed in the registers shown in Table 67. The digital gain settings
are described in the following equations:
0 ≤ Gain ≤ 4095/2048
−∞ dB ≤ dBGain ≤ 6.018 dB
Gain = GainCode × (1/2048)
1
dBGain = 20 × log10(Gain)
SIN(X)/X ROLL-OFF
SINC–1 FILTER RESPONSE
COMPOSITE RESPONSE
0
optimize the error vector magnitude (EVM) in zero IF
(ZIF) architectures.
The LO leakage at the output of a quadrature modulator
following the AD9154 in a signal chain can be cancelled by
adjusting the dc current output of each DAC driving
modulator signal inputs.
GainCode = 2048 × Gain = 2048 × 10dBGain/20
MAGNITUDE (dB)
where GainCode is a 12-bit unsigned binary number.
–1
The I/Q digital gain is set as shown in Table 67 and paged as
described in the Dual Paging section.
–2
Table 67. Digital Gain Registers
–3
Addr.
0x111[5]
Value
DIG_GAIN_ENABLE
0x13C
0x13D
0x13E
0x13F
GAINCODEI[7:0]
GAINCODEI[11:8]
GAINCODEQ[7:0]
GAINCODEQ[11:8]
–5
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
FREQUENCY (× fDAC )
0.40
0.45
0.50
11389-041
–4
Figure 72. Responses of sin(x)/x Roll-Off, the Sinc−1 Filter, and the Composite
of the Two Input Signal Power Detection and Protection
DIGITAL GAIN, PHASE ADJUST, DC OFFSET, AND
GROUP DELAY
Digital gain, phase adjust, and dc offset (as described in the
Digital Gain section, Phase Adjust section, and DC Offset
section) allow compensation of imbalances in the I and Q paths
due to analog mismatches between DAC I/Q outputs, quadrature
modulator I/Q baseband inputs, and DAC/modulator interface
I/Q paths. These imbalances can cause the two following issues:
•
An unwanted sideband signal appears at the quadrature
modulator output with significant energy. Cancel this
signal using digital gain and phase adjust. Tuning the
quadrature gain and phase adjust values can optimize
complex image rejection in single sideband radios or can
Description
Set to 1 to enable digital gain
at reset
I DAC LSB gain code
I DAC MSB gain code
Q DAC LSB gain code
Q DAC MSB gain code
Phase Adjust
Ordinarily, the I and Q channels of each DAC pair have an
angle of 90° between them. The phase adjust feature changes the
angle between the I and Q channels, which balances the phase
into a modulator.
−14 ≤ DegreesAdjust < 14
PhaseAdj = (DegreesAdjust/14) × 212
where PhaseAdj is a 13-bit twos complement number.
The phase adjust is set as shown in Table 68 and paged as
described in the Dual Paging section.
Rev. B | Page 64 of 124
Data Sheet
AD9154
Table 68. I/Q Phase Adjustment Registers
Table 70. Group Delay Compensation Registers
Addr.
0x111[4]
Value
PHASE_ADJ_ENABLE
Addr.
0x046
0x11C
0x11D
PHASEADJ[7:0]
PHASEADJ[12:8]
Description
Set to 1 to enable phase
adjust
LSB phase adjust code
MSB phase adjust code
0x044
0x045
DC Offset
The dc offset feature is used to individually offset the data into
the I or Q DACs. This feature is used to cancel LO leakage at the
modulator output.
The offset is programmed individually for I and Q as a 16-bit
twos complement number in LSBs, plus a 5-bit twos complement
number in sixteenths of an LSB, as shown in Table 69. DC offset
is paged as described in the Dual Paging section.
−215 ≤ LSBsOffset < 215
−16 ≤ SixteenthsOffset ≤ 15
Value
DC_OFFSET_ON
LSBSOFFSETI[7:0]
LSBSOFFSETI[15:8]
LSBSOFFSETQ[7:0]
LSBSOFFSETQ[15:8]
SIXTEENTHSOFFSETI
SIXTEENTHSOFFSETQ
Description
Set to 3 to bypass both I and Q
compensation
±85 ps nominal range
±85 ps nominal range
I TO Q SWAP
I_TO_Q (Register 0x111, Bit 0; paged as described in the Dual
Paging section) is a convenience bit that can be set to send the I
datapath to the Q DAC. Note that this swap occurs at the end of
the datapath (after any modulation, digital gain, phase adjust,
and phase offset). If using M = 1 DACs in DualLink mode (as
described in the DAC Power-Down Setup section), set this bit
to direct data to the DAC3 output.
NCO ALIGNMENT
Table 69. DC Offset Registers
Addr.
0x135[0]
0x136
0x137
0x138
0x139
0x13A[4:0]
0x13B[4:0]
Value
GROUP DELAY
COMP BYPASS
GROUP DELAY
COMP I [7:0]
GROUP DELAY
COMP Q [7:0]
Description
Set to 1 to enable dc offset
I DAC LSB dc offset code
I DAC MSB dc offset code
Q DAC LSB dc offset code
Q DAC MSB dc offset code
I DAC sub-LSB dc offset code
Q DAC sub-LSB dc offset code
The NCO alignment block phase aligns the NCO output from
multiple converters. Two NCO alignment modes are supported
by the AD9154. The first is a SYSREF± alignment mode that
phase aligns the NCO outputs to the rising edge of a SYSREF±
pulse. The second alignment mode is a data key alignment;
when this mode is enabled, the AD9154 aligns the NCO
outputs when a user specified data pattern arrives at the DAC
input. Note that the NCO alignment is per dual, and is paged as
described in the Dual Paging section.
Coarse Group Delay
SYSREF± NCO Alignment
Coarse group delay is a global adjustment of the DAC latency,
and it is programmed to identically affect both DACs in an I/Q
signal pair. The coarse group delay range is in +7/−8 steps. Each
step is ½ DAC clock cycle. The default value of 0x8 sets the
delay to zero. This is useful in applications where the user needs
to tune the latency of the DAC path with some accuracy (for
example, in DPD loop delay adjust).
As with the LMFC alignment, in Subclass 1, a SYSREF± pulse
can be used to phase align the NCO outputs of multiple devices
in a system and multiple channels on the same device. Note that
in Subclass 0, this alignment mode can be used to align the
NCO outputs within a device to an internal processing clock
edge. No SYSREF± edge is needed in Subclass 0, but multichip
alignment cannot be achieved. The steps to achieve a SYSREF
NCO alignment are as follows:
Write the value to COARSE_GROUP_DLY (Register 0x014).
This is paged as described in the Dual Paging section.
Group Delay Compensation
Group delay compensation provides separate delay tunability to
either an I or Q channel within each dual digital signal pair. The
user can delay either the I or Q output to align their quadrature.
Table 70 shows the register settings used for group delay
compensation. The group delay compensation bypass register is
located at Register 0x046. The GROUPDELAYCOMP (Bits[7:0])
values are binary, and the default value of 0x00 is a delay
compensation of zero. The difference between this mode and
the phase adjust mode is that group delay compensation can
correct for delay differences between the I and Q channels,
while phase adjust cannot. Group delay compensation is paged
as described in the Dual Paging section.
1.
2.
3.
4.
Rev. B | Page 65 of 124
Set NCOCLRMODE (Register 0x050, Bits[1:0]) = 0b01 for
SYSREF NCO alignment mode.
Set NCOCLRARM to 1 (Register 0x050, Bit 7).
Perform an LMFC alignment to force the NCO phase align
(see the Syncing LMFC Signals section). The phase
alignment occurs on the next SYSREF± edge.
Note that if in one shot sync mode, the LMFC alignment
block must be armed by setting Register 0x03A, Bit 6 = 1. If
in continuous mode or one shot then monitor mode, the
LMFC align block does not need to be armed; the NCO
align automatically trips on the next SYSREF± edge.
Check the alignment status. If NCO phase alignment was
successful, NCOCLRPASS (Register 0x050, Bit 4) = 1. If
phase alignment failed, NCOCLRFAIL (Register 0x050, Bit 3)
= 1.
AD9154
Data Sheet
Data Key NCO Alignment
In addition to supporting the SYSREF± alignment mode, the
AD9154 supports a mode where the NCO phase alignment
occurs when a user-specified pattern is seen at the DAC input.
The steps to achieve a data key NCO alignment are as follows:
1.
2.
3.
4.
5.
Set NCOCLRMODE (Register 0x050, Bits[1:0]) = 0b10.
Write the expected 16-bit data key for the I and Q datapath
into NCOKEYIx (Register 0x051 to Register 0x052) and
NCOKEYQ (Register 0x053 to Register 0x054), respectively.
Set NCOCLRARM (Register 0x050, Bit 7) = 1.
Send the expected 16-bit I and Q data keys to the device to
achieve NCO alignment.
Check the alignment status. If the expected data key was seen
at the DAC input, then NCOCLRMTCH (Register 0x050,
Bit 5) = 1. If NCO phase alignment was successful,
NCOCLRPASS (Register 0x050, Bit 4) = 1. If phase
alignment failed, NCO_ALIGN_FAIL (Register 0x050,
Bit 3) = 1.
Multiple device NCO alignment can be achieved with the data
key alignment mode. To achieve multichip NCO alignment,
program the same expected data key on all devices, arm all
devices, and then send the data key to all devices/channels at
the same time.
NCO Alignment IRQ
An IRQ event showing whether the NCO align was tripped is
available.
Use Register 0x021, Bit 4 to enable DAC Dual A (DAC0 and
DAC1), and then use Register 0x025, Bit 4 to read back its status
and reset the IRQ signal.
Use Register 0x022, Bit 4 to enable DAC Dual B (DAC2 and
DAC3), and then use Register 0x026, Bit 4 to read back its status
and reset the IRQ signal.
See the Interrupt Request Operation section for more
information.
DOWNSTREAM PROTECTION
The AD9154 has several blocks designed to protect the power
amplifier (PA) in its board level signal chain, as well as other
downstream blocks. It consists of a power detection and
protection (PDP) block, a blanking state machine (BSM), and a
transmit enable state machine (Tx ENSM).
The PDP block monitors incoming data. If a moving average of
the data power goes above a threshold, the PDP block provides
a signal (PDP_PROTECT) that can be routed externally on the
PDP OUT0 and PDP OUT1 pins.
The Tx ENSM is a simpler block that controls delay between
TXENx and the Tx_PROTECT signal. The Tx_PROTECT
signal is used as an input to the BSM and its inverse can
optionally be routed externally. Optionally, the Tx ENSM can
also power down its associated DAC dual.
The BSM gently ramps data entering the DAC and flushes the
datapath. The BSM is activated by the Tx_PROTECT signal or
automatically by the LMFC sync logic during a rotation. Digital
gain must be enabled for proper function. Finally, some simple
logic takes the outputs from each of those blocks and uses them
to generate a desired PDP OUTx signal on an external pin. This
signal can be used to enable/disable downstream components,
such as a PA.
Power Detection and Protection
The input signal PDP block detects the average power of the
DAC input signal and to prevent overrange signals from being
passed to the next stage, which may potentially cause destructive
breakdown on power sensitive devices, such as PAs. The protection
function provides a signal (PDP_PROTECT) that can be routed
externally to shut down a PA.
The PDP block uses a separate path with a shorter latency than
the datapath to ensure that PDP_PROTECT gets triggered
before the overrange signal reaches the analog DAC cores. The
sum of the I2 and Q2 are calculated as a representation of the input
signal power (only the top seven MSBs of data samples are
used). The calculated sample power numbers are accumulated
through a moving average filter whose output is the average of
the input signal power in a certain number of samples. When the
output of the averaging filter is larger than the threshold, the
internal signal PDP_PROTECT goes high, which can optionally be
configured to trigger a signal on the PDP OUTx pins. The PDP
block is configured as shown in Table 71 and paged as described
in the Dual Paging section.
The choice of PDP_AVG_TIME (Register 0x062) and
PDP_THRESHOLD[12:0] (Register 0x060 to Register 0x061)
for effective protection are application dependent. Experiment
with real-world vectors to ensure proper configuration. The
PDP_POWER[12:0] readback (Register 0x063 to Register
0x064) can help by storing the maximum power when a set
threshold passes.
Rev. B | Page 66 of 124
Data Sheet
AD9154
FILTER
AND
MODULATION
DATA
PDP
DIGITAL
GAIN
DATA TO DACs
PDP_PROTECT
FROM LMFC
SYNC LOGIC
1
BSM
BSM_PROTECT
0
PDP_PROTECT_OUT
TXENx
Tx ENSM
Tx_PROTECT
1
1
0
0
Tx_PROTECT_OUT
SPI_PROTECT
PROTECT_OUTx
PROTECT_OUT_INVERT
1
SPI_PROTECT_OUT
PROTECT OUTx GENERATION
11389-173
0
Figure 73. Downstream Protection Block Diagram
external pin (PDP_OUTx) to turn downstream components on
or off as desired.
Table 71. PDP Registers
Bit
No.
[7:0]
Value
PDP_THRESHOLD[7:0]
0x061
0x062
[4:0]
7
[3:0]
PDP_THRESHOLD[12:8]
PDP_ENABLE
PDP_AVG_TIME
0x063
[7:0]
PDP_POWER[7:0]
Addr.
0x060
0x064
[4:0]
PDP_POWER[12:8]
Description
Power that triggers
PDP_PROTECT.
8 LSBs.
5 MSBs.
Set to 1 to enable PDP.
Can be set from 0 to
10. Averages across
2(9 + PDP_AVG_TIME), IQ
sample pairs.
If PDP_THRESHOLD is
crossed, this reads
back the maximum
power seen. If not, this
reads back the
instantaneous power.
8 LSBs.
5 MSBs.
Power Detection and Protection IRQ
The TXENx signal can be used to power down their associated
DAC duals. If DACA_MASK (Register 0x012, Bit 6) = 1, a
falling edge of TXENx causes DAC Dual A (DAC0 and DAC1)
to power down. If DACB_MASK (Register 0x012, Bit 7) = 1, a
falling edge of TXENx causes DAC Dual B (DAC2 and DAC3) to
power down. On a rising edge of TXENx, without DACA_MASK
and DACB_MASK enabled, the output is valid after the BSM
settles (see the Blanking State Machine (BSM) section). If the
masks are enabled, an additional delay is imposed; the output is
not valid until the BSM settles and the DACs fully power on
(nominally an additional ~35 µs).
The Tx ENSM is configured as shown in Table 72 and is paged
as described in the Dual Paging section.
Table 72. Tx ENSM Registers
Addr.
0x11F
Bit No.
[7:6]
Value
PA_FALL
[5:4]
PA_RISE
0x121
[7:0]
RISE_COUNT_0
0x122
[7:0]
RISE_COUNT_1
0x123
[7:0]
FALL_COUNT_0
0x124
[7:0]
FALL_COUNT_1
The PDP_PROTECT signal is available as an IRQ event.
Use Register 0x021, Bit 7 to enable PDP_PROTECT for Dual A
(DAC0 and DAC1), and then use Register 0x025, Bit 7 to read
back its status and reset the IRQ signal.
Use Register 0x022, Bit 7 to enable PDP_PROTECT for Dual B
(DAC2 and DAC3), and then use Register 0x026, Bit 7 to read
back its status and reset the IRQ signal.
See the Interrupt Request Operation section for more
information.
Transmit Enable State Machine
The Tx ENSM is a simple block that controls the delay between
the TXENx signal and the TX_PROTECT signal. This signal is
used as an input to the BSM and its inverse can be routed to an
Rev. B | Page 67 of 124
Description
Number of fall counters
to use (1 to 2).
Number of rise counters
to use (0 to 2).
Delay TX_PROTECT rise
from TXENx rising edge
by 32 × RISE_COUNT_0
DAC clock cycles.
Delay TX_PROTECT rise
from TXENx rising edge
by 32 × RISE_COUNT_1
DAC clock cycles.
Delay TX_PROTECT rise
from TXENx rising edge
by 32 × FALL_COUNT_0
DAC clock cycles. Must
be at least 0x12.
Delay TX_PROTECT rise
from TXENx rising edge
by 32 × FALL_COUNT_1
DAC clock cycles.
AD9154
Data Sheet
Blanking State Machine (BSM)
Table 74. PDP OUTx Registers
The BSM gently ramps data entering the DAC and flushes the
datapath.
Addr.
0x013
On a falling edge of TX_PROTECT (the TXENx signal delayed
by the Tx ENSM), the datapath holds the latest data value and
the digital gain gently ramps from its set value to 0. At the same
time, the datapath is flushed with zeroes.
On a rising edge of TX_PROTECT, the TXENx signal is
delayed by the Tx ENSM; data is allowed to flow through the
datapath again and the digital gain gently ramps the data from 0
up to the set digital gain.
Both of the above functions are also triggered automatically by
the LMFC sync logic during a rotation to prevent glitching on
the output.
Ramping
The step size to use when ramping gain to 0 or its assigned value
can be controlled via the GAIN_RAMP_DOWN_STEPx registers
(Register 0x142 and Register 0x143) and the GAIN_RAMP_
UP_STEPx registers (Register 0x140 and Register 0x141). These
registers are paged as described in the Dual Paging section.
The current BSM state can be read back as shown in Table 73.
Table 73. Blanking State Machine Ramping Readbacks
Address
0x147[7:6]
Value
0b00
0b01
0b10
0b11
Description
Data is being held at midscale.
Ramping gain to 0. Data ramping to
midscale.
Ramping gain to assigned value. Data
ramping to normal amplitude.
Data at normal amplitude.
Blanking State Machine IRQ
Blanking completion is available as an IRQ event.
Use Register 0x021, Bit 5 to enable blanking completion for DAC
Dual A (DAC0 and DAC1), and then use Register 0x025, Bit 5
to read back its status and reset the IRQ signal.
Use Register 0x022, Bit 5 to enable blanking completion for
DAC Dual B (DAC2 and DAC3),and then use Register 0x026,
Bit 5 to read back its status and reset the IRQ signal.
See the Interrupt Request Operation section for more
information.
PDP OUTx Generation
Register 0x013 controls which signals are OR’ed into the external
PDP OUTx signal. Register 0x11F, Bit 2 can be used to invert the
PDP OUTx signal, By default, PDP OUTx is high when output is
valid. Both of these registers are paged as described in the Dual
Paging section.
0x11F
Bit No.
6
5
3
2
2
Description
1: PDP block triggers PDP_OUT
1: Tx ENSM triggers PDP_OUT
1: SPI_PROTECT triggers PDP_OUT
Sets SPI_PROTECT
Inverts PDP OUTx
DATAPATH PRBS
The datapath PRBS can be used to verify that the AD9154
datapath is receiving and correctly decoding data. The datapath
PRBS verifies that the JESD204B parameters of the transmitter
and receiver match, the lanes of the receiver are mapped
appropriately, lanes have been appropriately inverted, if
necessary, and in general that the start-up routine has been
implemented correctly.
The datapath PRBS is paged as described in the Dual Paging
section. To run the datapath PRBS test, complete the following
steps:
1.
Set up the device in the desired operating mode. See the
Device Setup Guide section for details on setting up the
device.
2. Send PRBS7 or PRBS15 data.
3. Write Register 0x14B, Bit 2 = 0 for PRBS7 or 1 for PRBS15.
4. Write Register 0x14B, Bit 1 and Bit 0 = 0b11 to enable and
reset the PRBS test.
5. Write Register 0x14B, Bit 1 and Bit 0 = 0b01 to enable the
PRBS test and release reset.
6. Wait 500 ms.
7. Check the status by checking the IRQ for DAC0 to DAC3
PRBS as described in the Datapath PRBS IRQ section.
8. If there are failures, set Register 0x008 = 0x01 to view the
status of Dual A (DAC0/DAC1). Set Register 0x08 = 0x02
to view the status of Dual B (DAC2/DAC3).
9. Read Register 0x14B, Bit 7 and Bit 6. Bit 6 is 0 if the I DAC
of the selected dual has any errors. Bit 7 is 0 if the Q DAC of
the selected dual has any errors. This must match the IRQ.
10. Read Register 0x14C to read the error count for the I DAC
of the selected dual. Read Register 0x14D to read the error
count for the Q DAC of the selected dual.
Note that the PRBS processes 32 bits at a time, and compares
the 32 new bits to the previous set of 32 bits. It detects (and
reports) only 1 error in every group of 32 bits, so the error
count partly depends on when the errors are seen. For example,
•
•
•
Rev. B | Page 68 of 124
Bits: 32 good, 31 good, 1 bad; 32 good (2 errors)
Bits: 32 good, 22 good, 10 bad; 32 good (2 errors)
Bits: 32 good, 31 good, 1 bad; 31 good, 1 bad; 32 good
(3 errors)
Data Sheet
AD9154
Datapath PRBS IRQ
The PRBS fail signals for each DAC are available as IRQ events.
Use Register 0x020, Bits[3:0] to enable the fail signals, and then
use Register 0x024, Bits[3:0] to read back their statuses and
reset the IRQ signals. See the Interrupt Request Operation
section for more information.
DC TEST MODE
DAC input dc level in place of data from the JESD204B transport
layer. DC test mode is enabled by setting Register 0x520, Bit 1
and clearing Register 0x146, Bit 0. Register 0x146, Bit 0 must be
set to 1 for all other modes of operation.
In dc test mode, the digital modulator can generate a sine wave
at a fixed amplitude. Digital gain, dc offset, and phase adjustment
can be applied to the sine wave on its way to each DAC core input.
The AD9154 provides a dc test mode. When dc test mode is
activated, the input to the digital data paths is set to a midscale
Rev. B | Page 69 of 124
AD9154
Data Sheet
INTERRUPT REQUEST OPERATION
0
EVENT_STATUS
1
STATUS_MODE
IRQ
IRQ_EN
EVENT
0
1
IRQ_EN
INTERRUPT_SOURCE
OTHER
INTERRUPT
SOURCES
IRQ_RESET
11389-043
DEVICE_RESET
Figure 74. Simplified Schematic of IRQ Circuitry
The AD9154 provides an interrupt request output signal on
Pin 60 (IRQ) that can be used to notify an external host processor
of significant device events. On assertion of the interrupt, query
the device to determine the precise event that occurred.
The IRQ pin is an open-drain, active low output. Pull the IRQ
pin high external to the device. This pin can be tied to the
interrupt pins of other devices with open-drain outputs to wire;
OR these pins together. Figure 74 shows a simplified block
diagram of how the IRQ blocks works. If IRQ_EN is low, the
INTERRUPT_SOURCE signal is set to 0. If IRQ_EN is high,
any rising edge of EVENT causes the INTERRUPT_SOURCE
signal to be set high. If any INTERRUPT_SOURCE signal is
high, the IRQ pin is pulled low. INTERRUPT_SOURCE can be
reset to 0 by either an IRQ_RESET signal or a DEVICE_RESET.
Depending on STATUS_MODE, the EVENT_STATUS bit reads
back event or INTERRUPT_SOURCE. The AD9154 has several
IRQ register blocks, which can monitor up to 75 events
(depending on device configuration). Certain details vary by
IRQ register block as described in Table 75. Table 76 shows
which registers the IRQ_EN, IRQ_RESET, and STATUS_MODE
signals in Figure 74 are coming from, as well as the address
where EVENT_STATUS is read back.
Table 75. IRQ Register Block Details
Register Block
0x01F to 0x026
EVENT
Reported
Per chip
0x46D to 0x46F; 0x470
to 0x473; 0x47A
0x47B[4]
Per link and
lane
Per link
EVENT_STATUS
INTERRUPT_SOURCE if
IRQ is enabled, if not, it
is EVENT
INTERRUPT_SOURCE if
IRQ is enabled, if not, 0
INTERRUPT_SOURCE if
IRQ is enabled, if not, 0
INTERRUPT SERVICE ROUTINE
Interrupt request management starts by selecting the set of event
flags that require host intervention or monitoring. Enable the
events that require host action so that the host is notified when
they occur. For events requiring host intervention upon IRQ
activation, run the following routine to clear an interrupt request:
1.
2.
3.
4.
5.
6.
7.
Rev. B | Page 70 of 124
Read the status of the event flag bits that are being monitored.
Disable the interrupt by writing 0 to IRQ_EN.
Read the event source. For Register 0x01F to
Register 0x026, EVENT_STATUS has a live readback. For
other events, see their registers.
Perform any actions that may be required to clear the cause
of the event. In many cases, no specific actions may be
required.
Verify that the event source is functioning as expected.
Clear the interrupt by writing 1 to IRQ_RESET.
Enable the interrupt by writing 1 to IRQ_EN.
Data Sheet
AD9154
Table 76. IRQ Register Block Address of IRQ Signal Details
Register Block
0x01F to 0x026
IRQ_EN
0x01F to 0x022; R/W per chip
0x46D to 0x46F
0x47A; W per link
0x470 to 0x473
0x47A; W per link
0x47B[4]
0x47B[3]; R/W per link; 1 by
default
Address of IRQ Signals
IRQ_RESET
STATUS_MODE
0x023 to 0x026; W per chip
STATUS_MODE =
IRQ_EN
0x46D to 0x46F; W per link
Not applicable,
and lane
STATUS_MODE = 1
0x470 to 0x473; W per link
Not applicable,
STATUS_MODE = 1
0x47B[4]; W per link
Not applicable,
STATUS_MODE = 1
Rev. B | Page 71 of 124
EVENT_STATUS
0x023 to 0x26; R per chip
0x47A; R per link
0x47A; R per link
0x47B[4]; R per link
AD9154
Data Sheet
DAC INPUT CLOCK CONFIGURATIONS
The AD9154 DAC sample clock or device clock (DACCLK) can
be sourced directly through CLK± (Pin 2 and Pin 3) or by using
on-chip clock multiplication with the same CLK± differential
input serving as the reference. Clock multiplying employs the
on-chip DAC PLL that accepts a reference clock operating at a
submultiple of the desired DACCLK rate. The PLL then
multiplies the reference clock up to the desired DACCLK
frequency, which is then used to generate all the clocks within
the AD9154.
Charge Pump
The charge pump current is 6-bit programmable variable with a
range of 0.1 mA to 6.4 mA. It is programmed in Register 0x08A,
Bits[5:0] as shown in the DAC PLL Fixed Register Writes section.
The charge pump is automatically calibrated the first time the
DAC PLL is enabled. The charge pump calibration raises Bit 5
of Register 0x084 after it is complete and valid.
DRIVING THE CLK± INPUTS
The CLK± differential input is shown in Figure 75. The on-chip
clock receiver has a differential input impedance of 10 kΩ.
CLK± are not terminated on chip; the inputs are self biased to a
common-mode voltage of 600 mV. The inputs can be driven by
differential PECL or LVDS drivers with ac coupling between the
clock source and the receiver. A typical 100 Ω differential board
level termination resistor is placed between the ac coupling
capacitors and the CLK± pins.
UP
TO LOOP FILTER
CHARGE PUMP CURRENT = 0.1mA TO 6.4mA
11389-046
DOWN
Figure 77. Charge Pump
CLK+
CONDITION SPECIFIC REGISTER WRITES
5kΩ
Clock Multiplication Relationships
600mV
5kΩ
11389-044
CLK–
Figure 75. Clock Receiver Input Simplified Equivalent Circuit
DAC PLL FIXED REGISTER WRITES
To optimize the PLL across all operating conditions, the
following SPI writes are recommended: 0x087 = 0x62, 0x088 =
0xC9, 0x089 = 0x0E, 0x08A = 0x12, 0x08D = 0x7B, 0x1B0 =
0x00, 0x1B5 = 0xC9, 0x1B9 = 0x24, 0x1BC = 0x0D, 0x1BE =
0x02, 0x1BF = 0x8E, 0x1C0 = 0x2A, 0x1C4 = 0x7E, and 0x1C5
= 0x06.
These writes properly set up the DAC PLL, including the loop
filter and the charge pump.
Loop Filter
The RF PLL filter is fully integrated on-chip and is a standard
passive third-order filter with five 4-bit programmable
components (see Figure 76). The C1, C2, C3, R1, and R3 filter
components are programmed in as listed in DAC PLL fixed
register writes in the DAC PLL Fixed Register Writes section to
Register 0x087, Register 0x088, and Register 0x089.
R3
FROM CHARGE PUMP
TO VCO
R1
C3
C2
TO VCO LDO
11389-045
C1
The on-chip PLL clock multiplier circuit can be used to generate
the DAC sample rate clock from a lower frequency reference clock.
The PLL is integrated on chip. The PLL VCO operates over a
frequency range of 6 GHz to 12 GHz. The PLL configuration
parameters must be programmed before the PLL is enabled. Step
by step instructions on how to program the PLL can be found in
the Starting the PLL section. A functional block diagram of the
clock multiplier is shown in Figure 78.
When in use, the clock multiplication circuit generates the DAC
sampling clock from the reference clock (REFCLK) input. The
frequency of the REFCLK (CLK±) input is referred to as fREF.
The REFCLK input is divided by the variable RefDivFactor. Select
the RefDivFactor variable to ensure that the frequency into the
phase frequency detector (PFD) block is between 35 MHz and
80 MHz. The valid values for RefDivFactor are 1, 2, 4, 8, 16, or 32.
Each RefDivFactor maps to the appropriate REFDIVMODE
register control according to Table 77. The REFDIVMODE
register is programmed through Register 0x08C, Bits[2:0].
Table 77. Mapping of RefDivFactor to REFDIVMODE
DAC Reference
Frequency Range (MHz)
35 to 80
80 to 160
160 to 320
320 to 640
640 to 1000
Figure 76. Loop Filter
Rev. B | Page 72 of 124
Divide by
(RefDivFactor)
1
2
4
8
16
REFDIVMODE
Register 0x08C,
Bits[2:0]
0
1
2
3
4
Data Sheet
AD9154
Table 79. Common Frequency Examples
Use the following equation to determine the RefDivFactor:
35 MHz <
f REF
< 80 MHz
(1)
RefDivFactor
where:
RefDivFactor is the reference divider division ratio.
fREF is the reference frequency on the CLK± input pins.
The BCount value is the divide ratio of the loop divider. It is set
to divide the fDACCLK to frequency match the fREF/RefDivFactor.
Select BCount so that the following equation is true:
f DACCLK
f REF
=
2 × BCount RefDivFactor
(2)
where:
BCount is the feedback loop divider ratio.
fDACCLK is the DAC sample clock frequency.
The PFD compares fREF/RefDivRate to fDAC/(2 × BCount) and
pulses the charge pump up or down to control the frequency of
the VCO. The clock multiplication circuit operates such that the
VCO outputs a frequency, fVCO.
(3)
and from Equation 2, the DAC sample clock frequency, fDACCLK,
is equal to
f DACCLK = 2 × BCount ×
f REF
RefDivFact or
fDACCLK
(MHz)
1474.56
1474.56
1228.88
983.04
983.04
1966.08
1966.08
fVCO
(MHz)
11796.48
11796.48
9831.04
7864.35
7864.35
7864.35
7864.35
RefDiv−
Factor
8
4
8
2
1
8
4
LODiv−
Factor
8
8
8
8
8
4
4
BCount
16
16
16
8
8
16
16
Table 79 includes different parameter sets based on fVCO. The
correct value to use is determined by the frequency into the
phase frequency detector block of the PLL.
Temperature Tracking
The BCount value is programmed using Bits[7:0] of
Register 0x085. It is programmable from 6 to 127.
fVCO = fDACCLK × LoDivFactor
Frequency
(MHz)
368.64
184.32
307.2
122.88
61.44
491.52
245.76
(4)
The LODivFactor is chosen to keep fVCO in the operating range
between 6 GHz and 12 GHz. The valid values for LODivFactor
are 4, 8, and 16. Each LODivFactor maps to a LODIVMODE
value. The LODIVMODE (Register 0x08B[1:0]) is programmed
as described in Table 78.
When properly configured, the device automatically selects one of
the 512 VCO bands. The PLL settings selected by the device
ensure that the PLL remains locked over the full −40°C to +85°C
operating temperature range of the device without further
adjustment. The PLL remains locked over the full temperature
range even if the temperature during initialization is at one of
the temperature extremes.
To properly configure temperature tracking, follow the settings
in the DAC PLL Fixed Register Writes section and the fvco
dependent SPI writes shown in Table 80.
Table 80. VCO Control Lookup Table Reference
VCO Frequency
Range (GHz)
fVCO < 6.85
6.85 ≤ fVCO < 8.72
8.72 ≤ fVCO < 10.7
fVCO ≥ 10.7
Register
0x1B4
Setting
0x60
0x60
0x60
0x78
Register
0x1B6
Setting
0x49
0x49
0x4D
0x4D
Register
0x1BB
Setting
0x15
0x13
0x13
0x04
Table 78. DAC VCO Divider Selection
STARTING THE PLL
DAC Frequency
Range (MHz)
>1500
750 to 1500
420 to 750
The programming sequence for the DAC PLL is as follows:
Divide by
(LODivFactor)
4
8
16
LODIVMODE
Register 0x08B, Bits[1:0]
1
2
3
Table 79 lists some common frequency examples for the
RefDivFactor, LODivFactor, and BCount values that are needed
to configure the PLL properly.
1.
2.
3.
4.
5.
6.
7.
Rev. B | Page 73 of 124
Use the equations in the Clock Multiplication
Relationships section to find fVCO, fREF, BCount,
REFDIVMODE, and LODIVMODE .
Program the registers in the DAC PLL Fixed Register
Writes section.
Program LODIVMODE into Register 0x08B, Bits[1:0].
Program the BCount in Register 0x085, Bits[7:0].
Program REFDIVMODE in Register 0x08C, Bits[2:0].
Based on the fVCO found in Step 1, write the temperature
tracking registers as shown in Table 80.
Enable the DAC PLL synthesizer by setting Register 0x083,
Bit 4 to 1.
AD9154
Data Sheet
DAC PLL IRQ
Register 0x084, Bit 5 notifies the user that the DAC PLL calibration
is completed and is valid.
PFD
80MHz
MAX
÷2
÷4
÷8
÷16
RETIMER
C1
R1
UP
C2
C3
LC VCO
6GHz
TO
12GHz
÷2
DOWN
÷2
÷2
÷2
R3
I
ALC CAL
Q
I
Q
I
Q
MUX/SELECTABLE BUFFERS
FO CAL
0.1mA TO 6.4mA
CAL CONTROL BITS
NMUX = 4, 8, 16
÷2
B COUNTER
MAXIMUM FREQUENCY = 1.6GHz
DAC CLOCK
Figure 78. Device Clock PLL Block Diagram
Rev. B | Page 74 of 124
11389-047
fREF
30MHz
TO 1GHz
VCO
LDO
750MHz TO 1.5GHz
N1 =
DIVIDE BY
1, 2, 4, 8, 16, 32
4-BIT
PROGRAMMABLE,
INTEGRATED
LOOP FILTER
1.5GHz TO 3GHz
CHARGE
PUMP
3GHz TO 6GHz
Register 0x084, Bits[7:6] and Register 0x084, Bit 5 notify the
user that the DAC PLL hit the upper or lower edge of its operating
band, respectively. If either of these bits are high, recalibrate the
DAC PLL by setting Register 0x083, Bit 7 to 0 and then 1.
375MHz TO 750MHz
The DAC PLL lock and lost signals are available as IRQ events.
Use Register 0x01F, Bit 5 and Bit 4 to enable these signals, and
then use Register 0x023, Bit 5 and Bit 4 to read back their
statuses and reset the IRQ signals. See the Interrupt Request
Operation section.
Register 0x084, Bit 1 notifies the user that the PLL has locked.
Data Sheet
AD9154
ANALOG OUTPUTS
Figure 79 shows a simplified block diagram of the transmit path
DAC cores. There are four DAC cores: DAC0 and DAC2 are
designated I DACs; DAC1 and DAC3 are designated Q DACs.
The DAC cores consist of a current switch array, digital control
logic, and full-scale output current control. The DAC full-scale
output current (IOUTFS) is defined in Table 1. The output currents
from the OUTx± pins are complementary, meaning that the
sum of the two currents always equals the full-scale current of
the DAC. OUTx± are current sinks. Current flows into the
OUTx± ports. The digital input code to the DAC determines the
differential current output.
OUT1–
11389-048
OUT0+
OUT0–
Figure 79. Simplified Block Diagram of the DAC Core
A 4 kΩ external resistor, RSET, must be connected from the I120 pin
to ground. This resistor, along with the reference control
amplifier, sets up the correct internal bias currents for each
DAC core.
The full-scale current equation, where the DAC gain is set for
each I DAC core pair and each Q DAC core pair in
Registers 0x040 through Register 0x043 is as follows:
I OUTFS =
VREF 
1

× 13.33 + 
× DAC gain  
RSET 
 19.19

11389-050
960
1024
896
832
768
704
640
576
448
512
384
320
256
Transmit DAC Transfer Function
OUT1+
DAC0
192
0
DAC GAIN CODE
DAC1
Q DACS
FULL-SCALE
ADJUST
5
Figure 80. DAC Full-Scale Current (IOUTFS) vs. DAC Gain Code
OUT2–
CURRENT
SCALING
4kΩ
10
0
OUT2+
I20
15
OUT3+
OUT3–
DAC2
20
128
1.2V
25
64
DAC3
I DACS
FULL-SCALE
ADJUST
Figure 80 is a plot of IOUTFS as a function of DAC_GAIN_Ix and
DAC_GAIN_Qx
DAC FULL-SCALE CURRENT (I OUTFS)
TRANSMIT DAC OPERATION
The output currents drawn by the OUTx+ and OUTx− pins are
complementary, meaning that the sum of the two (positive plus
negative) currents always equals the full-scale current of the
DAC, IOUTFS. The digital input code to a DAC determines the
differential current output. The OUTx+ pins provide the
maximum output current when all bits are high. The output
currents vs. DACCODE for the DAC outputs are expressed as
DACCODE 
I OUTP = 
 × I OUTFS
2N

(6)
I OUTN = I OUTFS − I OUTP
(7)
where DACCODE = 0 to 2N − 1 and is the digital signal input to
a DAC core consisting of a stream of 16 bit samples.
(5)
Rev. B | Page 75 of 124
AD9154
Data Sheet
NORMAL AND MIX MODES OF OPERATION
D1
D2
D3
D4
D5
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D6
D7
D8
D9
D10
DACCLK
QUAD-SWITCH
DAC OUTPUT
(NORMAL MODE) D1
t
D6
D2
D3
D4
D7
D8
D9
D10
t
D5
11389-181
TWO-SWITCH
DAC OUTPUT
This ability to change modes provides the user the flexibility to
place a carrier anywhere in the first three Nyquist zones, depending
on the operating mode selected. Switching between baseband
and mix mode reshapes the sinc roll-off inherent at the DAC
output.
FIRST
NYQUIST ZONE
Figure 81. Two-Switch and Quad-Switch DAC Waveforms
Figure 82 depicts a time domain DAC output signal in mix
mode. During each DACCLK cycle, the input sample is
presented at the output on the rising edge and the inverse of the
input sample is presented at the output on the falling edge of
DACCLK.
INPUT
DATA
D1
D2
D3
D4
D5
D7
D6
D8
0
–10
–15
BASEBAND
MODE
–20
–25
–30
0
DACCLK
0.25
0.50
0.75
1.00
1.25
NORMALIZED FREQUENCY RELATIVE TO fDACCLK (Hz)
D3
D2
–D8
D4
D1
D5
–D10
–D6
t
–D5 D6
–D1
–D2
–D4
–D3
D10
D9
D7
D8
1.50
Figure 83. Sinc Roll-Off for Normal Mode and Mix-Mode Operation
–D9
–D7
11389-182
QUAD-SWITCH
DAC OUTPUT
(fS MIX MODE)
MIX MODE
–35
D10
D9
THIRD
NYQUIST ZONE
–5
OUTPUT CURRENT (dBFS)
The DAC cores have a quad-switch architecture. During each
DACCLK cycle, one input sample is presented twice. Figure 81
shows the time domain DAC core output when operating in
normal mode (default). In normal mode, the same output signal
is presented twice during each DAC clock cycle. The DAC
output mode is selected using Bit 0 of Register 0x04A.
SECOND
NYQUIST ZONE
11389-183
INPUT
DATA
Figure 83 is a depiction of the uncompensated DAC SINC rolloff for normal (or baseband) mode and for mix mode. In
normal mode, the first Nyquist zone copy of the output signal
has the highest amplitude. The output sampling images in the
second and third Nyquist zones are attenuated. In MIX mode,
the second and third Nyquist zone sampling images are
emphasized, and the first Nyquist zone signal is attenuated.
Figure 82. Mix Mode Waveform
Rev. B | Page 76 of 124
Data Sheet
AD9154
TEMPERATURE SENSOR
The AD9154 has a band gap temperature sensor for monitoring
junction temperature changes on the AD9154 die. The temperature
must be calibrated against a known temperature to remove the
device-to-device variation in the band gap circuit used to sense
the temperature.
To monitor temperature change, the user must take a reading at
a known ambient temperature for a single-point calibration of
each AD9154 device.
Tx = TREF + 7.3 × (CODE_X − CODE_REF)/1000
where:
CODE_X is the DIE_TEMP readback code from Register 0x132
and Register 0x133 at the unknown temperature, Tx.
CODE_REF is the DIE_TEMP readback from the same addresses
at the calibrated temperature, TREF.
To use the temperature sensor, it must be enabled by setting
Register 0x12F, Bit 0, to 1. The user must write a 1 to
Register 0x134, Bit 0 before reading back the die temperature
from Register 0x132 and Register 0x133.
Rev. B | Page 77 of 124
AD9154
Data Sheet
EXAMPLE START-UP SEQUENCE
Table 81 through Table 90 show the register writes needed to set up
the AD9154 with fDAC = 1474.56 MHz, 2× interpolation, and the
DAC PLL enabled with a 368.64 MHz reference clock. The
JESD204B interface is configured in Mode 4, dual link mode,
Subclass 1, and scrambling is enabled with all eight SERDES
lanes running at 7.3728 Gbps, inputting twos complement formatted data. No remapping of lanes with the crossbar is
performed in this example.
Configure the DAC PLL
Table 83. Configure DAC PLL
Command
W
Address
0x087
Value
0x62
W
0x088
0xC9
W
0x089
0x0E
W
W
0x08A
0x08D
0x12
0x7B
W
0x1B0
0x00
W
0x1B5
0xC9
W
0x1B9
0x24
W
0x1BC
0x0D
W
0x1BE
0x02
W
0x1BF
0x8E
W
0x1C0
0x2A
W
W
0x1C1
0x1C4
0x2A
0x7E
Power-Up and DAC Initialization
W
0x1C5
0x06
Table 81. Power-Up and DAC Initialization
W
0x08B
0x02
W
W
0x08C
0x085
0x03
0x10
W
0x1B6
0x4D
W
0x1BB
0x04
Required Device Configurations
W
0x1B4
0x78
Table 82. Required Device Configuration
W
W
R
0x1C5
0x083
0x084
0x06
0x10
0x01
The sequence of steps to properly start up the AD9154 is as follows:
1.
2.
3.
4.
5.
6.
Set up the SPI interface, power up necessary circuit blocks,
make required writes to the configuration register, and set
up the DAC clocks (see Step 1: Start Up the DAC).
Set the digital features of the AD9154 (see Step 2: Digital
Datapath).
Set up the JESD204B links (see Step 3: Transport Layer).
Set up the physical layer of the SERDES interface (see Step
4: Physical Layer).
Set up the data link layer of the SERDES interface. This
procedure is for quick startup or debug only and does not
guarantee deterministic latency (see Step 5: Data Link
Layer).
Check for errors on Link 0 and Link 1 (see Step 6: Error
Monitoring).
These steps are outlined in detail in the following sections, within
tables that list the required register write and read commands.
STEP 1: START UP THE DAC
Command
W
W
W
Address
0x000
0x000
0x011
Value
0xBD
0x3C
0x00
W
0x080
0x04
W
0x081
0x00
Command
W
W
W
Address
0x12D
0x146
0x333
Value
0x8B
0x01
0x01
Description
Soft reset
Deassert reset, set 4-wire SPI
Enable reference, DAC
channels, and master DAC
Power up all clocks with
duty cycle correction on
Power up SYSREF receiver,
disable hysteresis
Description
Digital datapath configuration
Digital datapath configuration
JESD interface configuration
Description
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL loop filter
settings
Optimal DAC PLL CP settings
Optimal DAC LDO settings for
DAC PLL
Power DAC PLL blocks when
power machine disabled
Optimal DAC PLL VCO
settings
Optimal DAC PLL calibration
options settings
Optimal DAC PLL block
control settings
Optimal DAC PLL VCO power
control settings
Optimal DAC PLL VCO
calibration settings
Optimal DAC PLL lock counter
length setting
Optimal DAC PLL CP setting
Optimal DAC PLL varactor
settings
Optimal DAC PLL VCO
settings
Set the VCO LO divider to 8 so
that 6 GHz ≤ fVCO = fDACCLK ×
2(LODivMode + 1) ≤ 12 GHz
Set the reference clock divider
Set the B counter to 16 to
divide the DAC clock down to
2× the reference clock
Write VCO Varactor settings
from Table 80
Write VCO bias reference and
TC from Table 80
Write VCO calibration offset
from Table 80
Write VCO Varactor reference
Enable DAC PLL
Verify that Bit 1 reads back
high for PLL locked
STEP 2: DIGITAL DATAPATH
Table 84. Digital Datapath
Command
W
W
Rev. B | Page 78 of 124
Address
0x112
0x110
Value
0x01
0x00
Description
Set the interpolation to 2×
Set twos complement data
format
Data Sheet
AD9154
Table 86. Link 1 Transport Layer
STEP 3: TRANSPORT LAYER
Table 85. Link 0 Transport Layer
Command
W
W
W
Address
0x200
0x201
0x300
Value
0x00
0x00
0x08
W
0x450
0x00
W
0x451
0x00
W
0x452
0x00
W
0x453
0x83
W
W
W
W
W
0x454
0x455
0x456
0x457
0x458
0x00
0x1F
0x01
0x0F
0x2F
W
0x459
0x20
W
W
W
W
W
0x45A
0x45D
0x46C
0x476
0x47D
0x80
0x45
0x0F
0x01
0x0F
Description
Power up the interface
Enable all lanes
Bit 3 = 1 for dual link, Bit 2 = 0 to
access Link 0 registers
Set the device ID to match Tx
(0x00 in this example)
Set the bank ID to match Tx (0x00
in this example)
Set the lane ID to match Tx (0x00
in this example)
Set descrambling and L = 4
(in n − 1 notation)
Set F = 1 (in n − 1 notation)
Set K = 32 (in n − 1 notation)
Set M = 2 (in n − 1 notation)
Set N = 16 (in n − 1 notation)
Set Subclass 1 and NP = 16 (in
n − 1 notation)
Set JESD 204B Version and S = 1
(in n − 1 notation)
Set HD = 1
Set checksum for Lane 0
Deskew Lane 0 to Lane3
Set F (not in n − 1 notation)
Enable Lane 0 to Lane 3
Command
W
Address
0x300
Value
0x0C
W
0x450
0x00
W
0x451
0x00
W
0x452
0x04
W
0x453
0x83
W
W
W
W
W
0x454
0x455
0x456
0x457
0x458
0x00
0x1F
0x01
0x0F
0x2F
W
0x459
0x20
W
W
W
0x45A
0x45D
0x46C
0x476
0x47D
0x80
0x45
0x0F
0x01
0x0F
W
Description
Bit 3 = 1 for dual link, Bit 2 = 1 to
access registers for Link 1
Set the device ID to match Tx
(0x00 in this example)
Set the bank ID to match Tx (0x00
in this example)
Set the lane ID to match Tx (0x04
in this example)
Set descrambling and L = 4 (in
n − 1 notation)
Set F = 1 (in n − 1 notation)
Set K = 32 (in n − 1 notation)
Set M = 2 (in n − 1 notation)
Set N = 16 (in n − 1 notation)
Set Subclass 1 and NP = 16 (in
n − 1 notation)
Set JESD 204B and S = 1 (in n − 1
notation)
Set HD
Set checksum for Lane 0
Deskew Lane 4 to Lane 7
Set F (not in n − 1 notation)
Enable Lane 4 to Lane 7
STEP 4: PHYSICAL LAYER
Table 87. Physical Layer
Command
W
W
W
W
W
W
W
Address
0x2A7
0x2AE
0x314
0x230
0x206
0x206
0x289
Value
0x01
0x01
0x01
0x28
0x00
0x01
0x04
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
0x284
0x285
0x286
0x287
0x28A
0x28B
0x290
0x291
0x294
0x296
0x297
0x299
0x29A
0X29C
0x29F
0x2A0
0x280
0x281
0x62
0xC9
0x0E
0x12
0x7B
0x00
0x89
0x4C
0x24
0x1B
0x0D
0x02
0x8E
0x2A
0x7E
0x06
0x01
0x01
W
0x268
0x62
Rev. B | Page 79 of 124
Description
Autotune PHY setting
Autotune PHY setting
SERDES SPI configuration
Configure CDRs in half rate mode
Resets CDR logic
Release CDR logic reset
Configure PLL divider to 1 along
with PLL required configuration
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL loop filter
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO LDO
Optimal SERDES PLL PD
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO
Optimal SERDES PLL VCO
Optimal SERDES PLL PD
Optimal SERDES PLL VCO
Optimal SERDES PLL charge pump
Optimal SERDES PLL VCO
Configure SERDES PLL VCO
Enable SERDES PLL
Verify that Bit 0 reads back high
for SERDES PLL lock
Set equalizer mode to low power
AD9154
Data Sheet
STEP 5: DATA LINK LAYER
Note that this procedure does not guarantee deterministic latency.
Table 88. Data Link Layer (Does Not Guarantee Deterministic Latency)
Command
W
W
W
W
W
W
W
W
SYSREF±
W
Address
0x301
0x304
0x305
0x306
0x307
0x03A
0x03A
0x03A
Value
0x01
0x00
0x00
0x0A
0x0A
0x01
0x81
0xC1
0x300
0x0B
Description
Set subclass = 1
Set the LMFC delay setting to 0
Set the LMFC delay setting to 0
Set the LMFC receive buffer delay to 10
Set the LMFC receive buffer delay to 10
Set sync mode to one-shot sync
Enable the sync machine
Arm the sync machine
Ensure that at least one SYSREF± edge is sent to the device
Bit 1 and Bit 0 = 1 to enable Link 0 and Link 1, Bit 2 = 0 to access Link 0
STEP 6: ERROR MONITORING
Link 0 Checks
Confirm that the registers in Table 89 read back as noted and system tasks are completed as described.
Table 89. Link 0 Checks
Command
R
SYNCOUT0±
SERDINx±
R
R
R
Address
0x470
Value
0x0F
0x471
0x472
0x473
0x0F
0x0F
0x0F
Description
Acknowledge that four consecutive K28.5 characters have been detected on Lane 0 to Lane 3.
Confirm that SYNCOUT0± is high.
Apply ILAS and data to the SERDES input pins.
Check for frame sync on all lanes.
Check for good checksum.
Check for ILAS.
Link 1 Checks
Confirm that the registers in Table 90 read back as noted and system tasks are completed as described.
Table 90. Link 1 Checks
Command
W
R
SYNCOUT1±
SERDINx±
R
R
R
Address
0x300
0x470
Value
0x0F
0x0F
0x471
0x472
0x473
0x0F
0x0F
0x0F
Description
Bit 2 = 1 to access Link 1.
Acknowledge that four consecutive K28.5 characters have been detected on Lane 4 to Lane 7.
Confirm that SYNCOUT1± is high.
Apply ILAS and data to the SERDES input pins.
Check for frame sync on all lanes.
Check for good checksum.
Check for ILAS.
Rev. B | Page 80 of 124
Data Sheet
AD9154
BOARD LEVEL HARDWARE CONSIDERATIONS
POWER SUPPLY RECOMMENDATIONS
AD9154
1.8V
POWER
INPUT
+12V
ADP1741
ADP2119
ADP1741
ADP1753
BUCK
1.2Mhz/600khz
800mA
3.8V
ADM7154-3.3
1.2V
1.2V
SVDD12
DVDD12
CVDD12 + PVDD12
3.3V
AVDD33
3.3V
IOVDD + SIOVDD33
ADP2370
ADM7160-3.3
11389-184
+3.3V
STEP DOWN DC/DC
1.2MHz, 2A
1.2V
Figure 84. Power Supply Connections
Table 91. Power Supplies
Power Supply Domain
DVDD121
PVDD122
SVDD123
CVDD121
IOVDD
VTT4
SIOVDD33
AVDD33
Voltage (V)
1.2
1.2
1.2
1.2
3.3
1.2
3.3
3.3
Circuitry
Digital core
DAC PLL
JESD204B receiver interface
DAC clocking
SPI interface
VTT
Sync LVDS transmit
DAC
1
This supply requires a 1.3 V supply when operating at maximum DAC sample rates. See Table 3 for details.
This supply may be combined with CVDD12 on the same regulator with a separate supply filter network and sufficient bypass capacitors near the pins.
This supply requires a 1.3 V supply when operating at maximum interface rates. See Table 4 for details.
4
This supply is connected to SVDD12 and does not need separate circuitry.
2
3
The power supply domains are described in Table 91. The
power supplies can be grouped into separate PCB domains as
show in Figure 84. All the AD9154 supply domains must
remain as noise free as possible. Optimal DAC output NSD and
DAC output phase noise performance can be achieved using
linear regulators that provide excellent power supply rejection.
AVDD33, PVDD12, and CVDD12 are particularly sensitive to
supply noise.
JESD204B SERIAL INTERFACE INPUTS (SERDIN0±
TO SERDIN7±)
When considering the layout of the JESD204B serial interface
transmission lines, there are many factors to consider to
maintain optimal link performance. Among these factors are
insertion loss, return loss, signal skew, and the topology of the
differential traces.
Insertion Loss
The JESD204B specification limits the amount of insertion loss
allowed in the transmission channel (see Figure 44). The
AD9154 equalization circuitry allows significantly more loss in
the channel than is required by the JESD204B specification. It is
still important that the designer of the PCB minimize the
amount of insertion loss by adhering to the following
guidelines:
•
•
•
Keep the differential traces short by placing the AD9154 as
near to the transmitting logic device as possible and routing
the trace as directly as possible between the devices.
Route the differential pairs on a single plane using a solid
ground plane as a reference.
Use a PCB material with a low dielectric constant (<4) to
minimize loss, if possible.
When choosing between stripline and microstrip techniques,
consider the following: stripline has less loss (see Figure 45) and
emits less EMI, but requires the use of vias that can add complexity
to the task of controlling the impedance, whereas microstrip (see
Figure 46) is easier to implement if the component placement and
density allow routing on the top layer and eases the task of
controlling the impedance.
If using the top layer of the PCB is problematic or the advantages
of stripline are desirable, follow these recommendations:
•
•
Rev. B | Page 81 of 124
Minimize the number of vias.
If possible, use blind vias to eliminate via stub effects and
use micro vias to minimize via inductance.
AD9154
LAYER 1
ADD GROUND VIAS
y
STANDARD VIA
LAYER 5
y
DIFF+
LAYER 6
GND
LAYER 7
LAYER 8
y
DIFF–
LAYER 3
LAYER 4
GND
MINIMIZE STUB EFFECT
11389-023
LAYER 2
Figure 85. Minimizing Stub Effect and Adding Ground Vias for Differential
Stripline Traces
Return Loss
Topology
Structure the differential SERDINx± pairs to achieve 50 Ω to
ground for each half of the pair. Stripline vs. microstrip tradeoffs are described in the Insertion Loss section. In either case, it
is important to keep these transmission lines separated from
potential noise sources such as high speed digital signals and
noisy supplies. If using stripline differential traces, route them
using a coplanar method, with both traces on the same layer.
Although this does not offer more noise immunity than the
broadside routing method (traces routed on adjacent layers), it
is easier to route and manufacture so that the impedance
continuity is maintained. An illustration of broadside vs.
coplanar is shown in Figure 86.
Tx DIFF A
Tx
DIFF A
Tx DIFF B
The JESD204B specification limits the amount of return loss
allowed in a converter device and a logic device, but does not
specify return loss for the channel. However, every effort must
be made to maintain a continuous impedance on the transmission
line between the transmitting logic device and the AD9154. As
mentioned in the Insertion Loss section, minimizing the use of
vias, or eliminating them all together, reduces one of the
primary sources for impedance mismatches on a transmission
line. Maintain a solid reference beneath (for microstrip) or
above and below (for stripline) the differential traces to ensure
continuity in the impedance of the transmission line. If the
stripline technique is used, follow the guidelines listed in the
Insertion Loss section to minimize impedance mismatches and
stub effects.
Another primary source for impedance mismatch is at either
end of the transmission line, where care must be taken to match
the impedance of the termination to that of the transmission
line. The AD9154 handles this internally with a calibrated
termination scheme for the receiving end of the line. See the
Interface Power-Up and Input Termination section for details
on this circuit and the calibration routine.
Signal Skew
There are many sources for signal skew, but the two sources to
consider when laying out a PCB are interconnect skew within a
single JESD204B link and skew between multiple JESD204B
links. In each case, keeping the channel lengths matched to
within 15 mm is adequate for operating the JESD204B link at
speeds of up to 10.6 Gbps. Managing the interconnect skew
within a single link is fairly straightforward. Managing multiple
links across multiple devices is more complex. However, follow
the 15 mm guideline for length matching.
Tx
DIFF B
Tx
ACTIVE
Tx ACTIVE
BROADSIDE DIFFERENTIAL Tx LINES
COPLANAR DIFFERENTIAL Tx LINES
11389-024
•
If using standard vias, use the maximum via length to
minimize the stub size. For example, on an 8-layer board,
use Layer 7 for the stripline pair (see Figure 85).
For each via pair, place a pair of ground vias adjacent to them
to minimize the impedance discontinuity (see Figure 85).
Figure 86. Broadside vs. Coplanar Differential Stripline Routing Techniques
When considering the trace width vs. copper weight and
thickness, the speed of the interface must be considered. At
multigigabit speeds, the skin effect of the conducting material
confines the current flow to the surface. Maximize the surface
area of the conductor by making the trace width made wider to
reduce the losses. Additionally, loosely couple differential traces
to accommodate the wider trace widths. This helps reduce the
crosstalk and minimize the impedance mismatch when the
traces must separate to accommodate components, vias,
connectors, or other routing obstacles. Tightly coupled vs.
loosely coupled differential traces are shown in Figure 87.
Tx
DIFF A
Tx
DIFF B
TIGHTLY COUPLED
DIFFERENTIAL Tx LINES
Tx
DIFF A
Tx
DIFF B
LOOSELEY COUPLED
DIFFERENTIAL Tx LINES
11389-025
•
Data Sheet
Figure 87. Tightly Coupled vs. Loosely Coupled Differential Traces
AC Coupling Capacitors
The AD9154 requires that the JESD204B input signals be
ac-coupled to the source. These capacitors must be 100 nF and
placed as close as possible to the transmitting logic device. To
minimize the impedance mismatch at the pads, select the
package size of the capacitor so that the pad size on the PCB
matches the trace width as closely as possible.
Rev. B | Page 82 of 124
Data Sheet
AD9154
SYNCOUTx±, SYSREF±, and CLK± Signals
Separate the SYNCOUTx± signal from other noisy signals,
because noise on the SYNCOUTx± might be interpreted as a
request for K characters.
The SYNCOUTx± and SYSREF± signals on the AD9154 are
low speed LVDS differential signals. Use controlled impedance
traces routed with 100 Ω differential impedance and 50 Ω to
ground when routing these signals. As with the SERDIN0± to
SERDIN7± data pairs, it is important to keep these signals
separated from potential noise sources such as high speed
digital signals and noisy supplies.
It is important to keep similar trace lengths for the CLK± and
SYSREF± signals from the clock source to each of the devices
on either end of the JESD204B links, see Figure 88. If using a
clock chip that can tightly control the phase of CLK± and
SYSREF±, the trace length matching requirements are greatly
reduced.
LANE 0
LANE 1
Tx
DEVICE
Rx
DEVICE
LANE N – 1
LANE N
SYSREF±
SYSREF±
AD9154
DEVICE CLOCK
DEVICE CLOCK
DEVICE CLOCK TRACE LENGTH
SYSREF TRACE LENGTH
DEVICE CLOCK TRACE LENGTH
Figure 88. SYSREF± Signal and Device Clock Trace Length
Rev. B | Page 83 of 124
11389-026
SYSREF TRACE LENGTH
AD9154
Data Sheet
REGISTER SUMMARY
Table 92. AD9154 Register Summary
Reg.
0x000
0x003
0x004
0x005
0x006
0x008
0x011
0x012
0x013
Name
SPI_INTFCONFA
SPI_CHIPTYPE
SPI_PRODIDL
SPI_PRODIDH
SPI_CHIPGRADE
DUAL_PAGE
PWRCNTRL0
TXENMASK1
PWRCNTRL3
0x014
0x01F
COARSE_
GROUP_DLY
IRQ_ENABLE0
0x020
IRQ_ENABLE1
0x021
IRQ_ENABLE2
0x022
IRQ_ENABLE3
0x023
IRQ_STATUS0
0x024
Bit 7
Bit 6
SOFTRESET_M LSBFIRST_M
PD_BG
DACB_MASK
RESERVED
Bit 0
Reset
SOFTRESET 0x00
0x04
0x54
0x91
PROD_GRADE
DEV_REVISION
0x89
RESERVED
PAGEINDX
0x03
PDDAC0
PDDAC1
PDDAC2
PDDAC3
RESERVED
0xF8
DACA_MASK
RESERVED
0x00
ENA_PA_CTRL ENA_PA_CTRL ENA_PA_CTRL_ ENA_PA_
SPI_PA_
ENA_SPI_ SPI_TXEN 0x20
_FROM_
_FROM_
CTRL_FROM_ CTRL
FROM_BLSM
TXEN
PAPROT_ERR TXENSM
SPI
RESERVED
COARSE_GROUP_DLY
0x88
RESERVED
Bit 4
Bit 3
SDOACTIVE_M SDOACTIVE
CHIPTYPE
PRODIDL
PRODIDH
EN_DAC
PLLLOST
RESERVED
EN_DAC
PLLLOCK
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R
IRQ_
PRBSI0
IRQ_
REFTRIP0
IRQ_
REFTRIP1
ERR_
INTSUPP
0x00
R
0x00
R
0x00
R
0x00
R
0x00
R/W
0x00
R
0x00
R
0x00
R/W
0x00
0x00
R
R
0x00
R
DAC_GAIN_Q0
GROUP DELAY COMP I [7:0]
0x03
0xFF
0x03
0xFF
0x00
R/W
R/W
R/W
R/W
R/W
GROUP DELAY COMP Q [7:0]
0x00
R/W
0x03
R/W
0x00
R/W
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
IRQ_STATUS1
0x025
IRQ_STATUS2
IRQ_PAErr0
RESERVED
0x026
IRQ_STATUS3
IRQ_PAErr1
RESERVED
0x030
JESD_CHECKS
IRQ_
REFNCOCLR0
IRQ_
REFNCOCLR1
ERR_WINLIMIT
0x034
SYNC_
ERRWINDOW
SYNC_
LASTERR_L
SYNC_
LASTERR_H
SYNC_
CONTROL
SYNC_STATUS
SYNC_
CURRERR_L
SYNC_
CURRERR_H
DAC_GAIN0_I
DAC_GAIN1_I
DAC_GAIN0_Q
DAC_GAIN1_Q
GROUPDELAY
COMP_I
GROUPDELAY
COMP_Q
GROUPDELAY
COMP_BYP
0x039
0x03A
0x03B
0x03C
0x03D
0x040
0x041
0x042
0x043
0x044
0x045
0x046
0x04A
MIX_MODE
0x050
0x051
0x052
0x053
NCO_CLRMODE
NCOKEY_ILSB
NCOKEY_IMSB
NCOKEY_QLSB
IRQ_
BLNKDONE0
IRQ_
BLNKDONE1
ERR_DLYOVER
IRQ_REFLOCK0
IRQ_
REFLOCK1
ERR_
JESDBAD
RESERVED
EN_LANEFIFOERR
EN_
PRBSQ0
EN_
EN_
REFROTA0
REFWLIM0
EN_
EN_
REFROTA1
REFWLIM1
IRQ_
IRQ_LANE
SERPLLLOCK FIFOERR
IRQ_PRBSI1 IRQ_
PRBSQ0
IRQ_
IRQ_
REFROTA0
REFWLIM0
IRQ_
IRQ_
REFROTA1
REFWLIM1
ERR_
ERR_
KUNSUPP
SUBCLASS
ERRWINDOW
LASTERROR_L
LASTUNDER
LASTOVER
SYNCENABLE
SYNCARM
REFBUSY
CURRUNDER
RESERVED
SYNCCLRSTKY
SYNCCLRLAST
RESERVED
SYNCMODE
REFLOCK
CURRERROR_L
CURROVER
LAST
ERROR_H
REFROTA
RESERVED
REFWLIM
REFTRIP
CURRERROR_H
DAC_GAIN_I1
RESERVED
DAC_GAIN_I0
RESERVED
DAC_GAIN_Q1
RESERVED
GROUPCOMP_
BYPI
RESERVED
NCOCLRARM
RESERVED
R/W
EN_
PRBSI0
EN_
REFTRIP0
EN_
REFTRIP1
RESERVED
EN_
REFLOCK0
EN_
REFLOCK1
IRQ_
SERPLLLOST
IRQ_PRBSQ1
EN_SERPLLLOCK
EN_PRBSI1
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R/W
R/W
EN_
REFNCOCLR0
EN_
REFNCOCLR1
IRQ_DACPLLLOCK
RESERVED
Bit 1
LSBFIRST
0x00
RESERVED
EN_SERPLLLOST
EN_PRBSQ1
Bit 2
ADDRINC
RESERVED
EN_
BLNKDONE0
EN_PAErr1
RESERVED
EN_
BLNKDONE1
RESERVED
IRQ_DACPLLLOST
RESERVED
0x038
EN_PAERR0
Bit 5
ADDRINC_M
NCOCLRMTCH
NCOCLRPASS
NCOCLRFAIL
NCOKEYILSB
NCOKEYIMSB
NCOKEYQLSB
Rev. B | Page 84 of 124
RESERVED
GROUPCOMP_
BYPQ
MIX_
MODE
NCOCLRMODE
Data Sheet
Reg.
0x054
0x060
0x061
0x062
Name
NCOKEY_QMSB
PA_THRES0
PA_THRES1
PDP_AVG_TIME
0x063
0x064
0x080
PA_POWER0
PA_POWER1
CLKCFG0
0x081
0x082
0x083
SYSREF_ACTRL0
SYSREF_ACTRL1
DACPLLCNTRL
0x084
DACPLLSTATUS
0x085
DACINTEGERWORD0
DACLOOPFILT1
DACLOOPFILT2
DACLOOPFILT3
0x087
0x088
0x089
0x08A
0x08B
0x08C
0x08D
0x110
0x111
0x112
0x113
0x114
0x115
0x116
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
0x11F
0x121
0x122
0x123
0x124
0x12D
0x12F
0x132
0x133
DACCPCNTRL
DACLOGENCNTRL
DACLDOCNTRL1
DACLDOCNTRL2
DATA_FORMAT
DATAPATH_
CTRL
INTERPMODE
NCO_FTW_
UPDATE
FTW0
FTW1
FTW2
FTW3
FTW4
FTW5
NCO_PHASE_
OFFSET0
NCO_PHASE_
OFFSET1
NCO_PHASE_
ADJ0
NCO_PHASE_
ADJ1
TXEN_SM_0
TXEN_SM_2
TXEN_SM_3
TXEN_SM_4
TXEN_SM_5
DEVICE_CONFIG_
REG0
DIE_TEMP_
CTRL0
DIE_TEMP0
DIE_TEMP1
AD9154
Bit 7
Bit 6
PDP_ENABLE
RESERVED
PA_BUS_
SWAP
Bit 5
Bit 4
Bit 3
NCOKEYQMSB
PDP_THRESHOLD[7:0]
Bit 2
Bit 1
Bit 0
PDP_THRESHOLD[12:8]
PDP_AVG_TIME
RESERVED
PDP_POWER[7:0]
PDP_POWER[12:8]
PDCLOCKDIG PD_PCLK
PDCLOCKDUTY_EN
RF_SYNC_ RF_
REC
EN
CLKDIV_EN
RESERVED
PDSYSREF
HYS_ON
SYSREF_RISE
HYS_CNTRL1
HYS_CNTRL0
SYNTH_
RESERVED
ENABLE_
RESERVED
RECAL
SYNTH
CP_OVERRANGE_H
CP_
CP_CAL_VALID VCO_CAL_
RESERVED
RFPLL_
RESERVED
OVERRANGE_L
PROGRESS
LOCK
BCOUNT
RESERVED
PD_CLK01
PD_CLK23
LF_C2_WORD
LF_R1_WORD
LF_BYPASS_
LF_BYPASS_
LF_BYPASS_C2 LF_BYPASS_C1
R3
R1
RESERVED
VT_FORCE
RESERVED
LO_POWER_MODE
LDO_REF_SEL
LDO_BYPASS
DATA_FMT
INVSINC_
ENABLE
LDO_BYPASS_
FILT
LDO_INRUSH
RESERVED
PA_FALL
LF_C1_WORD
LF_C3_WORD
LF_R3_WORD
CP_CURRENT
RESERVED
RESERVED
LODIVMODE
REFDIVMODE
LDO_SEL
RESERVED
PHASE_ADJ_
MODULATION_TYPE
ENABLE
DIG_GAIN_
ENABLE
RESERVED
RESERVED
LDO_VDROP
Reset
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
0x00
0x00
0xFE
R
R
R/W
0x10
0x00
0x00
R/W
R/W
R/W
0x00
R/W
0x06
R/W
0x88
0x88
0x08
R/W
R/W
R/W
0x20
0x00
R/W
R/W
0x00
R/W
0x2B
0x00
0xA0
R/W
R/W
R/W
FTW0
FTW1
FTW2
FTW3
FTW4
FTW5
NCO_PHASE_OFFSET0
SEL_
I_TO_Q
SIDEBAND
INTERPMODE
0x01
FTW_UPFTW_UP0x00
DATE_ACK DATE_REQ
0x00
0x00
0x00
0x00
0x00
0x10
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NCO_PHASE_OFFSET1
0x00
R/W
PHASEADJ[7:0]
0x00
R/W
PHASEADJ[12:8]
0x00
R/W
TXEN_SM_ 0x83
EN
0x0F
0x00
0xFF
0xFF
0x46
R/W
AUXADC_
ENABLE
0x20
R/W
0x00
0x00
R
R
PA_RISE
RESERVED
RISE_COUNT_0
RISE_COUNT_1
FALL_COUNT_0
FALL_COUNT_1
DEVICE_CONFIG_0
RESERVED
DIE_TEMP_LSB
DIE_TEMP_MSB
Rev. B | Page 85 of 124
GP_PA_ON_ GP_PA_
INVERT
CTRL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AD9154
Reg.
0x134
Data Sheet
0x1B1
Name
Bit 7
Bit 6
Bit 5
DIE_TEMP_
UPDATE
DC_OFFSET_
CTRL
IPATH_DC_
OFFSET_1PART0
IPATH_DC_
OFFSET_1PART1
QPATH_DC_
OFFSET_1PART0
QPATH_DC_
OFFSET_1PART1
IPATH_DC_
RESERVED
OFFSET_2PART
QPATH_DC_
RESERVED
OFFSET_2PART
IDAC_DIG_
GAIN0
IDAC_DIG_
RESERVED
GAIN1
QDAC_DIG_
GAIN0
QDAC_DIG_
RESERVED
GAIN1
GAIN_RAMP_
UP_STEP0
GAIN_RAMP_
RESERVED
UP_STEP1
GAIN_RAMP_
DOWN_STEP0
GAIN_RAMP_
RESERVED
DOWN_STEP1
DEVICE_CONFIG
_REG1
BLSM_STAT
BE_ROTATE_REQ
PRBS
PRBS_
PRBS_
GOOD_Q
GOOD_I
PRBS_ERROR_I
PRBS_ERROR_Q
DACPLLT0
VCO_PD_IN
VCO_PD_
VCO_PD_ALC
PTAT
DACPLLT1
RESERVED
0x1B2
DACPLLT2
0x1B3
0x1B4
DACPLLT3
DACPLLT4
0x1B5
0x1B6
DACPLLT5
DACPLLT6
RESERVED
0x1B7
0x1B8
DACPLLT7
DACPLLT8
LD_SYNTH
RESERVED
0x1B9
DACPLLT9
HALF_VCO_
CAL_CLK
0X1BA
0x1BB
0x1BC
DACPLLTA
DACPLLTB
DACPLLTC
0x1BD
DACPLLTD
0x1BE
DACPLLTE
0x1BF
DACPLLTF
0x135
0x136
0x137
0x138
0x139
0x13A
0x13B
0x13C
0x13D
0x13E
0x13F
0x140
0x141
0x142
0x143
0x146
0x147
0x14B
0x14C
0x14D
0x1B0
EXT_ALC_
WORD_EN
BYP_LOAD_
DELAY
VCO_BYP_
BIASR
I_CAL_EN
Bit 4
RESERVED
Bit 3
Bit 2
Bit 1
RESERVED
IPATH_DC_OFFSET_1PART0
Bit 0
Reset
DIE_TEMP 0x00
_UPDATE
DC_OFF0x00
SET_ON
0x00
R/W
R/W
R/W
R/W
IPATH_DC_OFFSET_1PART1
0x00
R/W
QPATH_DC_OFFSET_1PART0
0x00
R/W
QPATH_DC_OFFSET_1PART1
0x00
R/W
IPATH_DC_OFFSET_2PART
0x00
R/W
QPATH_DC_OFFSET_2PART
0x00
R/W
0x00
R/W
0x08
R/W
0x00
R/W
0x08
R/W
0x04
R/W
0x00
R/W
0x09
R/W
0x00
R/W
0x00
R/W
PRBS_EN
0x00
0x10
R/W
R/W
RESERVED
0x00
0x00
0xFA
R
R
R/W
RESERVED
0x04
R/W
0x00
R/W
0x00
0x78
W
R/W
0x83
0x4A
R/W
R/W
0x00
0x00
R/W
R
0x34
R/W
0x00
0x0C
0x00
R/W
R/W
R/W
0x00
R/W
0x00
R/W
0x8D
R/W
IDAC_DIG_GAIN0
IDAC_DIG_GAIN1
GAINCODEQ[7:0]
GAINCODEQ[11:8]
GAIN_RAMP_UP_STEP0
GAIN_RAMP_UP_STEP1
GAIN_RAMP_DOWN_STEP0
GAIN_RAMP_DOWN_STEP1
DEVICE_CONFIG1
RESERVED
RESERVED
PRBS_
MODE
PRBS_COUNT_I
PRBS_COUNT_Q
SYNTH_PD
LDO_PD
RESERVED
PFD_DELAY
PRBS_
RESET
LOGEN_
PD
PFD_
EDGE
EXT_ALC_WORD
EXT_BAND1
VCO_CAL_OFFSET
RESERVED
EXT_
BAND_EN
VCO_VAR
VCO_LVL_OUT
EXT_
BAND2
INIT_ALC_VALUE
PORESETB_
EXT_VCO_BITSEL
VCO
RESERVED
CP_IBLEED
COMP_OUT
CP_CAL_
VCO_CAL_IN_
CP_CALBITS
DONE
PROG
DITHER_
MACHINE_
CP_OFFSET_
FORCE_CP_
CAP_CAL_
CP_TEST
MODE
ENABLE
OFF
CALBITS
EN
MACHINE_STATE
FCP_CALBITS
RESERVED
VCO_BIAS_TCF
VCO_BIAS_REF
RESERVED
VCO_COMP_
PRSC_HIGHR LAST_
PRSC_BIAS_CTRL
BIASR
ALC_EN
RESERVED
VCO_CAL_
VCO_CAL_REF_TCF
REF_MON
RESERVED
VCO_PDO_
VCO_PDO_ VCO_PDO VCO_PDO
VR
VRTCF
_CALTCF _VCOBUF
I_ALC_WAIT_D
I_CAL_COUNT
FDBCK_DELAY
Rev. B | Page 86 of 124
Data Sheet
AD9154
Reg.
0x1C0
Name
DACPLLT10
Bit 7
0x1C1
DACPLLT11
RESERVED
0x1C2
0x1C3
0x1C4
0x1C5
0x200
DACPLLT15
DACPLLT16
DACPLLT17
DACPLLT18
MASTER_PD
SDM_BP
RESERVED
RESERVED
0x201
0x203
PHY_PD
GENERIC_PD
0x206
CDR_RESET
0x230
0x281
CDR_
OPERATING_
MODE_REG_0
EQ_BIAS_REG
SYNTH_ENABLE_
CNTRL
PLL_STATUS
0x284
0x285
0x286
0x287
LOOP_FILTER_1
LOOP_FILTER_2
LOOP_FILTER_3
CP_CURRENT
0x289
REF_CLK_
DIVIDER_LDO
VCO_LDO
PLL_PD_REG
0x268
0x280
0x28A
0x28B
0x290
Bit 6
RESERVED
R/W
R/W
0x15
R/W
0x80
0x00
0x33
0x08
0x01
R/W
R/W
R/W
R/W
R/W
0x00
SPI_
SPI_
0x00
SYNC1_PD SYNC2_PD
SPI_CDR_ 0x01
RESETN
CDR_OVER RESERVED 0x28
-SAMP
R/W
R/W
0x62
0x00
R/W
R/W
0x00
R
0x77
0x87
0x08
0x3F
R/W
R/W
R/W
R/W
0x04
R/W
0x2B
Ox7F
R/W
R/W
0x83
R/W
0x49
0xB0
R/W
R/W
0x0C
0x00
R/W
R/W
0x00
R/W
0xFE
R/W
0x17
R/W
SPI_VCO_VARACTOR_OFFSET
0x33
R/W
SPI_VCO_VARACTOR_REF
0x08
R/W
SPI_I_TUNE 0x00
_R_CAL_
TERMBLK1
SPI_I_TUNE 0x00
_R_CAL_
TERMBLK2
ENLINKS
0x00
R/W
0x01
R/W
SPI_PD_
MASTER
RESERVED
RESERVED
SPI_RECAL_
SYNTH
SPI_CP_OVER_ SPI_CP_OVER_ SPI_CP_CAL_ SPI_VCO_
RANGE_HIGH_ RANGE_LOW_R VALID_RB
CAL_IN_PRO
RB
B
GRESS_RB
LOOP_FILTER_1
LOOP_FILTER_2
LOOP_FILTER_3
SPI_CP_CURRENT
RESERVED
RESERVED
SPI_SERDES_
LOGEN_POWER_MODE
RESERVED
SPI_LDO_REF
_SEL
SPI_SERDES_LDO_CONFIG
SPI_VCO_PD
SPI_VCO_PD_ SPI_VCO_PD_ SPI_SYN_PD
ALC
PTAT
SPI_INIT_ALC_VALUE
RESERVED
0x299
VCO_PD_
OVERRIDES
0x29A
VCO_CAL
0x29C
CP_LEVEL_
DETECT
VCO_VARACTOR RESERVED
_CONTROL_0
VCO_VARACTOR
_CONTROL_1
TERM_BLK1_CTR
LREG0
SPI_HALF_
VCO_CAL_
CLK
RESERVED
SPI_DITHER_
SPI_ENABLE_
MODE
MACHINE
RESERVED
RESERVED
SPI_VCO_BYPASS_BIAS_
DAC_R
RESERVED
SPI_VCO_
CAL_EN
RESERVED
0x2AE
TERM_BLK2_
CTRLREG0
0x300
GENERAL_JRX_C RESERVED
TRL_0
GENERAL_JRX_C
TRL_1
Bit 0
LOCK_MODE
SDM_PROG
SDM_PROG1
VCO_VAR_OFF
VCO_VAR_REF
RESERVED
EQ_POWER_MODE
VCO_BIAS_1
VCO_BIAS_2
0x301
HALFRATE
Bit 1
CP_VL_HIGH
RESERVED
SDM_PROG2
VCO_VAR_REF_TCF
RESERVED
RESERVED
RESERVED
0x296
0x297
0x2A7
Reset
0x2E
RESERVED
0x291
0x294
0x2A0
Bit 3
Bit 2
LOCKDETECT_COUNT
UNUSEDLANES
RESERVED
ALC_
VARACTOR
VCO_OUTPUT
CP_CONFIG
0x29F
CP_LVL_
DET_PD
SDM_PD
SDM_PROG3
Bit 5
Bit 4
USE_NEW_CAL DOUBLE_F0_
CAL_CNT
CP_VL_LOW
SPI_CP_
OFFSET_OFF
SPI_CP_
FORCE_
CALBITS
SPI_VCO_BIAS_TCF
SPI_VCO_
SPI_PRECOMP_BYSCALE_
PASS_BIASR
BYPASS_R
SPI_VCO_PD
_OVERRIDE_
VAR_REF
SPI_VCO_CAL_ALC_WAIT
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Rev. B | Page 87 of 124
DUALLINK
SPI_CURRENTS_
READY_RB
SPI_ENABLE_SYNTH
SPI_PLL_
LOCK_RB
SPI_CDR_OVERSAMP
SPI_SERDES
SPI_SERDES_LOGEN_
_LDO_PD
PD_CORE
SPI_VCO_VARACTOR
SPI_VCO_OUTPUT_LEVEL
SPI_CP_
SPI_CP_TEST
CAL_EN
SPI_VCO_BIAS_REF
SPI_LAST_
SPI_PRESCALE_BIAS
ALC_EN
SPI_VCO_P
D_OVERRIDE_VAR_R
EF_TCF
SPI_VCO_CAL_COUNT
SPI_CP_LEVEL
SPI_CP_LEVEL_THRESHOLD_LOW
_DET_PD
SPI_VCO_VARACTOR_REF_TCF
CHECKSUM_
MODE
SPI_LDO_
BYPASS_FILT
RESERVED
SPI_VCO_ SPI_VCO_
PD_OVER- PD_OVERRIDE_CAL RIDE_VCO
_TCF
BUF
SPI_FB_CLOCK_ADV
SPI_CP_LEVEL_THRESHOLD_HIGH
CURRENTLINK
SUBCLASSV_LOCAL
R/W
R/W
R/W
R/W
AD9154
Reg.
0x302
0x303
0x304
0x305
0x306
0x307
0x308
0x309
0x30A
0x30B
0x30C
0x30D
0x312
0x314
0x315
0x316
0x317
0x318
0x319
0x31A
0x31B
0x31C
0x31D
0x32C
0x32D
0x32E
0x32F
0x333
0x334
0x400
0x401
0x402
0x403
0x404
0x405
0x406
0x407
0x408
Name
DYN_LINK_
LATENCY_0
DYN_LINK_
LATENCY_1
LMFC_DELAY_0
LMFC_DELAY_1
LMFCVAR0
LMFCVAR1
XBAR_LN_0_1
XBAR_LN_2_3
XBAR_LN_4_5
XBAR_LN_6_7
FIFO_STATUS_
REG_0
FIFO_STATUS_
REG_1
SYNCB_GEN_1
SPI_SYNC_CTRL
Data Sheet
Bit 7
Bit 6
RESERVED
Bit 4
Bit 3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Bit 2
Bit 1
DYN_LINK_LATENCY_0
Reset
0x00
R/W
R/W
DYN_LINK_LATENCY_1
0x00
R/W
LMFCDEL0
LMFCDEL1
LMFCVAR0
LMFCVAR1
0x00
0x00
0x06
0x06
0x08
0x1A
0x2C
0x3E
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0x00
R
XBARVAL1
XBARVAL3
XBARVAL5
XBARVAL7
LANE_FIFO_FULL
Bit 0
XBARVAL0
XBARVAL2
XBARVAL4
XBARVAL6
LANE_FIFO_EMPTY
RESERVED
PHY_PRBS_
TEST_EN
PHY_PRBS_
RESERVED
TEST_CTRL
PHY_PRBS_
TEST_THRESHOLD_LOBITS
PHY_PRBS_
TEST_THRESHOLD_MIDBITS
PHY_PRBS_
TEST_THRESHOLD_HIBITS
PHY_PRBS_
TEST_ERRCNT_L
OBITS
PHY_PRBS_
TEST_ERRCNT_
MIDBITS
PHY_PRBS_
TEST_ERRCNT_H
IBITS
PHY_PRBS_
TEST_STATUS
SHORT_TPL_
RESERVED
TEST_0
SHORT_TPL_
TEST_1
SHORT_TPL_
TEST_2
SHORT_TPL_
TEST_3
DEVICE_
CONFIG_REG2
JESD_BIT_
INVERSE_CTRL
DID_REG
BID_REG
LID0_REG
SCR_L_REG
F_REG
K_REG
M_REG
CS_N_REG
NP_REG
Bit 5
SYNCB_ERR_DUR
RESERVED
RESERVED
PHY_TEST_EN
PHY_SRC_ERR_CNT
PHY_PRBS_PAT_SEL
R/W
R/W
R/W
0x00
R/W
PHY_PRBS_THRESHOLD_LOBITS
0x00
R/W
PHY_PRBS_THRESHOLD_MIDBITS
0x00
R/W
PHY_PRBS_THRESHOLD_HIBITS
0x00
R/W
PHY_PRBS_ERR_CNT_LOBITS
0x00
R
PHY_PRBS_ERR_CNT_MIDBITS
0x00
R
PHY_PRBS_ERR_CNT_HIBITS
0x00
R
PHY_PRBS_PASS
0xFF
R
0x00
R/W
SHORT_TPL_REF_SP_LSB
0x00
R/W
SHORT_TPL_REF_SP_MSB
0x00
R/W
0x00
R
RESERVED
0x00
R/W
INVLANES
0x00
R/W
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R
R
R
R
R
R
R
R
R
SHORT_TPL_SP_SEL
SHORT_TPL_M_SEL
PHY_TEST PHY_TEST
_START
_RESET
SHORT_
TPL_TEST
_RESET
RESERVED
ADJCNT_RD
ADJDIR_RD
PHADJ_RD
RESERVED
BID_RD
LID0_RD
L_RD
F_RD
RESERVED
K_RD
M_RD
CS_RD
RESERVED
SUBCLASSV_RD
N_RD
NP_RD
Rev. B | Page 88 of 124
SHORT_
TPL_TEST_
EN
SHORT_
TPL_FAIL
DID_RD
RESERVED
SCR_RD
0x00
SPI_SYNC_ 0x00
CLK_SEL
0x00
Data Sheet
Reg.
0x409
0x40A
0x40B
0x40C
0x40D
0x40E
0x412
0x415
0x416
0x41A
0x41D
0x41E
0x422
0x425
0x426
0x42A
0x42D
0x42E
0x432
0x435
0x436
0x43A
0x43D
0x43E
0x442
0x445
0x446
0x450
0x451
0x452
0x453
0x454
0x455
0x456
0x457
0x458
0x459
0x45A
0x45D
0x46B
0x46C
0x46D
0x46E
0x46F
0x470
0x471
Name
S_REG
HD_CF_REG
RES1_REG
RES2_REG
CHECKSUM_REG
COMPSUM0_REG
LID1_REG
CHECKSUM1_
REG
COMPSUM1_REG
LID2_REG
CHECKSUM2_
REG
COMPSUM2_
REG
LID3_REG
CHECKSUM3_
REG
COMPSUM3_
REG
LID4_REG
CHECKSUM4_
REG
COMPSUM4_
REG
LID5_REG
CHECKSUM5_
REG
COMPSUM5_
REG
LID6_REG
CHECKSUM6_
REG
COMPSUM6_
REG
LID7_REG
CHECKSUM7_
REG
COMPSUM7_
REG
ILS_DID
ILS_BID
ILS_LID0
ILS_SCR_L
ILS_F
ILS_K
ILS_M
ILS_CS_N
ILS_NP
ILS_S
ILS_HD_CF
ILS_CHECKSUM
ERRCNTRMON
LANEDESKEW
BADDISPARITY
NITDISPARITY
UNEXPECTEDKCHAR
CODEGRPSYNCFLG
FRAMESYNCFLG
AD9154
Bit 7
HD_RD
Bit 6
Bit 5
JESDV_RD
RESERVED
Bit 4
Bit 3
Bit 2
S_RD
CF_RD
Bit 1
Reset
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R
R
R
R
R
R
R
R
FCHK2_RD
0x00
0x00
0x00
R
R
R
FCMP2_RD
0x00
R
FCHK3_RD
0x00
0x00
R
R
FCMP3_RD
0x00
R
FCHK4_RD
0x00
0x00
R
R
FCMP4_RD
0x00
R
FCHK5_RD
0x00
0x00
R
R
FCMP5_RD
0x00
R
FCHK6_RD
0x00
0x00
R
R
FCMP6_RD
0x00
R
FCHK7_RD
0x00
0x00
R
R
FCMP7_RD
0x00
R
LANE0CHECKSUM
ERRCNTRMON
LANEDESKEW
BADDISPARITY
NITDISPARITY
UEKC
0x00
0x00
0x00
0x83
0x00
0x1F
0x01
0x1F
0x2F
0x20
0x80
0x45
0x00
0x0F
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CODEGRPSYNC
0x00
R/W
FRAMESYNC
0x00
R/W
RES1_RD
RES2_RD
LANE0CHECKSUM_RD
FCMP0_RD
RESERVED
LID1_RD
FCHK1_RD
FCMP1_RD
RESERVED
LID2_RD
RESERVED
LID3_RD
RESERVED
LID4_RD
RESERVED
LID5_RD
RESERVED
LID6_RD
RESERVED
LID7_RD
DID
RESERVED
SCR
ADJDIR
ADJCNT
PHADJ
RESERVED
BID
LID0
L
F
RESERVED
K
M
CS
HD
RESERVED
SUBCLASSV
JESDVER
RESERVED
N
NP
S
CF
Rev. B | Page 89 of 124
Bit 0
AD9154
Reg.
0x472
Data Sheet
0x476
0x477
Name
GOODCHKSUMFLG
INITLANESYNCFLG
CTRLREG1
CTRLREG2
0x478
0x47A
KVAL
IRQVECTOR
0x47B
0x47C
0x47D
0x47E
SYNCASSERTION- BADDIS_S
MASK
ERRORTHRES
LANEENABLE
RAMP_ENA
0x520
DIG_TEST0
0x521
TEST_DC_
VALUEI0
TEST_DC_
VALUEI1
TEST_DC_
VALUEQ0
TEST_DC_
VALUEQ1
0x473
0x522
0x523
0x524
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
GOODCHECKSUM
Bit 2
Bit 1
Bit 0
Reset
0x00
R/W
R/W
0x00
R/W
0x01
0x00
R/W
R/W
0x01
0x00
R/W
R/W
0x08
R/W
0xFF
0x0F
0x00
R/W
R/W
R/W
0x1C
R/W
TEST_DC_VALUEI0
0x00
R/W
TEST_DC_VALUEI1
0x00
R/W
TEST_DC_VALUEQ0
0x00
R/W
TEST_DC_VALUEQ1
0x00
R/W
INITIALLANESYNC
F_AGAIN
ILAS_MODE
BADDIS_
MASK
RESERVED
THRESHOLD_
MASK_EN
NITD_MASK
UEKC_MASK
KSYNC
RESERVED
NIT_S
UCC_S
CMM
RESERVED
INITIALLANE- BADCHECK- RESERVED CODEGRP
SYNC_
SYNC_MASK SUM_MASK
MASK
CMM_ENABLE
RESERVED
ETH
LANE_ENA
RESERVED
RESERVED
Rev. B | Page 90 of 124
DC_TEST_
MOD
ENA_
RAMP_
CHECK
RESERVED
Data Sheet
AD9154
REGISTER DETAILS
Table 93. AD9154 Register Details
Addr.
0x000
Name
Bits
SPI_INTFCONFA 7
6
5
4
3
2
Bit Name
SOFTRESET_M
LSBFIRST_M
ADDRINC_M
SDOACTIVE_M
SDOACTIVE
ADDRINC
Settings
1
0
1
LSBFIRST
1
0
0
SOFTRESET
1
0
0x003
0x004
0x005
0x006
0x008
SPI_CHIPTYPE
SPI_PRODIDL
SPI_PRODIDH
SPI_CHIPGRADE
DUAL_PAGE
[7:0]
[7:0]
[7:0]
[7:4]
CHIPTYPE
PRODIDL
PRODIDH
PROD_GRADE
[3:0]
[7:2]
[1:0]
DEV_REVISION
RESERVED
PAGEINDX
1
2
3
0x011
PWRCNTRL0
7
PD_BG
0
1
6
PDDAC0
0
1
5
PDDAC1
0
1
4
PDDAC2
0
1
3
PDDAC3
0
1
[2:0]
RESERVED
Description
Soft Reset (Mirror).
LSB First (Mirror).
Address Increment (Mirror).
SDO Active (Mirror).
SDO Active.
Address Increment. When set, causes incrementing
streaming addresses; otherwise, descending
addresses are generated.
Streaming addresses are incremented.
Streaming addresses are decremented.
LSB First. When set, causes input and output data to
be oriented LSB first. If this bit is clear, data is
oriented MSB first.
Shift LSB in first.
Shift MSB in first.
Soft Reset. Setting this bit initiates a reset. This bit is
autoclearing after the soft reset is complete.
Pulse the soft reset line.
Release soft reset.
High Speed DAC.
Product ID Low.
Product ID High.
Product Grade.
Device Revision.
Reserved.
Page or Index Pointer.
Select Link A.
Select Link B.
Select Link A and Link B.
Reference Power-Down.
Reference on.
Reference powered down. Overrides TXENx masked bit.
PD I Channel DAC 0.
Enable DAC0 I channel Dual0.
Power down DAC0 I channel Dual0. Overrides TXENx
masked bit.
PD Q Channel DAC 1.
Enable Q channel DAC of Dual A.
Power Down Q channel DAC of Dual A. Overrides
TXENx masked bit.
PD I Channel DAC 2.
Enable I channel DAC of Dual B.
Power Down I channel DAC of Dual B. Overrides
TXENx masked bit.
PD Q Channel DAC 3.
Enable Q channel DAC of Dual B.
Powers down Q channel DAC of Dual B. Overrides
TXENx masked bit.
Reserved.
Rev. B | Page 91 of 124
Reset
0x0
0x0
0x0
0x0
0x0
0x0
Access
R
R
R
R
R/W
R/W
0x0
R/W
0x0
R/W
0x4
0x54
0x91
0x8
R
R
R
R
0x9
0x0
0x3
R
R
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x0
R
AD9154
Addr.
0x012
Name
TXENMASK1
Data Sheet
Bits
7
Bit Name
DACB_MASK
Settings
0
1
6
DACA_MASK
0
1
0x013
PWRCNTRL3
[5:0]
7
6
2
1
0
RESERVED
RESERVED
ENA_PA_CTRL_
FROM_PAPROT_
ERR
ENA_PA_CTRL_
FROM_TXENSM
ENA_PA_CTRL_
FROM_BLSM
ENA_PA_CTRL_
FROM_SPI
SPI_PA_CTRL
ENA_SPI_TXEN
SPI_TXEN
[7:4]
RESERVED
[3:0]
COARSE_
GROUP_DLY
5
4
3
0x014
0x01F
COARSE_
GROUP_DLY
IRQ_ENABLE0
[7:6]
5
RESERVED
EN_DACPLLLOST
4
EN_DACPLLLOCK
3
EN_SERPLLLOST
2
EN_SERPLLLOCK
Description
Dual 23 DAC Power-Down Mask for TXEN1.
Default power-down to control by power-down bit only.
If TXEN1 is low, DAC 2 and DAC 3 are powered down;
otherwise state of individual power-downs.
Dual 01 DAC power-down mask for TXEN0.
Default power-down to control by power-down bit
only.
If TXEN0 is low, DAC 0 and DAC 1 are powered down;
otherwise state of individual power-downs.
Reserved
Reserved.
Control PA enable from PAProt block.
Reset
0x0
Access
R/W
0x0
R/W
0x0
0x0
0x0
R/W
R
R/W
Control PA enable from TXEN state machine.
0x1
R/W
Control PA enable from blanking state machine.
0x0
R/W
Control PA enable via SPI.
0x0
R/W
0x0
0x0
0x0
R/W
R/W
R/W
0x0
R
0x8
R/W
0x0
0x0
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
PA on/off via SPI.
TXENx from SPI control.
SPI TXENx.
1 TXENx SPI is high.
0 TXENx SPI is low.
Reserved.
Coarse Group Delay. The range of the delay is −4 to
+3 DAC clock periods and the resolution is 1/2 DAC
clock period.
0 minimum delay.
15 maximum delay.
Reserved.
Enable DAC PLL Lost Detection. The DACPLLLOCK,
when enabled, shows that the DAC (clock
generation) PLL has dropped its lock state.
1 Enable DAC PLL lost.
Enable DAC PLL Lock Detection. The DACPLLLOCK,
when enabled, shows that the DAC (clock
generation) PLL has reached a lock state.
1 Enable DAC PLL lock.
Enable SERDES PLL Lost Detection. The SERPLLLOCK,
when enabled, shows that the SERDES (JESD204B
interface) PLL has dropped its lock state.
1 Enable SERDES PLL lost.
Enable SERDES PLL Lock Detection. The SERPLLLOCK,
when enabled, shows that the SERDES (JESD204B
interface) PLL has reached a lock state.
1 Enable SERDES PLL lock.
Rev. B | Page 92 of 124
Data Sheet
Addr.
Name
AD9154
Bits
1
Bit Name
Settings
EN_LANEFIFOERR
0
[7:4]
3
RESERVED
RESERVED
EN_PRBSQ1
2
EN_PRBSI1
1
0x020
IRQ_ENABLE1
1
1
1
EN_PRBSQ0
1
0
EN_PRBSI0
1
0x021
IRQ_ENABLE2
7
EN_PAERR0
6
5
RESERVED
EN_BLNKDONE0
4
EN_REFNCOCLR0
1
1
1
3
EN_REFLOCK0
1
2
EN_REFROTA0
1
EN_REFWLIM0
1
1
0
EN_REFTRIP0
1
0x022
IRQ_ENABLE3
7
EN_PAERR1
1
6
5
RESERVED
EN_BLNKDONE1
4
EN_REFNCOCLR1
1
1
3
EN_REFLOCK1
1
2
EN_REFROTA1
1
1
EN_REFWLIM1
1
0
EN_REFTRIP1
1
0x023
IRQ_STATUS0
[7:6]
5
RESERVED
IRQ_DACPLLLOST
4
IRQ_DACPLLLOCK
1
1
Description
Enable Lane FIFO Error Detection. A lane FIFO error
occurs when there is a full or empty condition on any
of the FIFOs between the deserializer block and the
core digital. An error on this FIFO requires a link
disable and re-enable to remove. The STATUS of the
Lane FIFOs can be found in Register 0x30C (FIFO full)
and Register 0x30D (FIFO empty).
Enable lane FIFO error.
Reserved
Reserved.
Enable PRBS Imaginary DAC Dual B interrupt.
Enable PRBS Q1.
Enable PRBS real DAC Dual B interrupt.
Enable PRBS I1.
Enable PRBS Imaginary DAC Dual A interrupt.
Enable PRBS Q0.
Enable PRBS real DAC Dual A interrupt.
Enable PRBS I0.
Link A PA Error.
Enable PA Error.
Reserved.
Link A Blanking Done.
Enable Link A blanking done.
Link A NCO Clear Tripped.
NCO clear tripped.
Link A Alignment Locked.
Enable ref locked interrupt.
Link A Alignment Rotate.
Enable ref rotate interrupt.
Link A Over/Under Threshold.
Enable over/under limit interrupt.
Link A Alignment Trip.
Enable ref tripped interrupt.
Link B PA Error.
Enable PA error.
Reserved.
Link B Blanking Done.
Enable Link B blanking done.
Link B NCO Clear Tripped.
NCO clear tripped.
Link B Alignment Locked.
Enable ref locked interrupt.
Link B Alignment Rotate.
Enable ref rotate interrupt.
Link B Over/Under Threshold.
Enable over/under limit interrupt.
Link B Alignment Trip.
Enable ref tripped interrupt.
Reserved.
DAC PLL Lost.
DAC PLL lost.
DAC PLL Lock.
DAC PLL lock.
Rev. B | Page 93 of 124
Reset
0x0
Access
R/W
0x0
0x0
0x0
R/W
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R
0x0
R
AD9154
Addr.
Name
Data Sheet
Bits
3
Bit Name
IRQ_SERPLLLOST
2
IRQ_SERPLLLOCK
Settings
1
1
1
IRQ_LANEFIFOERR
1
0x024
IRQ_STATUS1
0
[7:4]
3
RESERVED
RESERVED
IRQ_PRBSQ1
2
IRQ_PRBSI1
1
1
1
IRQ_PRBSQ0
1
0
IRQ_PRBSI0
1
0x025
IRQ_STATUS2
7
IRQ_PAERR0
1
6
5
RESERVED
IRQ_BLNKDONE0
4
IRQ_REFNCOCLR0
1
1
3
IRQ_REFLOCK0
1
2
IRQ_REFROTA0
1
1
IRQ_REFWLIM0
1
0
IRQ_REFTRIP0
1
0x026
IRQ_STATUS3
7
IRQ_PAERR1
1
6
5
4
RESERVED
IRQ_BLNKDONE1
IRQ_REFNCOCLR1
3
IRQ_REFLOCK1
1
1
2
IRQ_REFROTA1
1
1
IRQ_REFWLIM1
1
0
IRQ_REFTRIP1
1
0x030
JESD_CHECKS
[7:6]
5
RESERVED
ERR_DLYOVER
4
ERR_WINLIMIT
1
1
3
ERR_JESDBAD
1
Description
SERDES PLL Lost.
SERDES PLL lost.
SERDES PLL Lock.
SERDES PLL lock.
Lane FIFO Error.
Lane FIFO error.
Reserved
Reserved.
PRBS Data Check Error DAC B Imaginary.
Service PRBS Q1.
PRBS Data Check Error DAC B Real.
Service PRBS I1.
PRBS Data Check Error DAC A Imaginary.
Service PRBS Q0.
PRBS Data Check Error DAC A Real.
Service PRBS I0.
Link A PA Error.
Service Link A PA error.
Reserved.
Link A Blanking Done.
Link A blank done.
Link A Alignment Underrange.
NCO clear tripped.
Link A BIST Done.
Link A alignment locked.
Link A Alignment Trip.
Rotate interrupt occurred.
Link A Alignment Lock.
Service over/under limit interrupt.
Link A Alignment Rotate.
Trip interrupt occurred.
Link B PA Error.
Service Link B PA error.
Reserved.
Reserved
Link B Alignment Underrange.
NCO clear tripped.
Link B BIST Done.
Link B alignment locked.
Link B Alignment Trip.
Rotate interrupt occurred.
Link B Alignment Lock.
Service over/under limit interrupt.
Link B Alignment Rotate.
Ref trip.
Reserved.
LMFC_Delay > JESD_K Parameter.
LMFC_Delay > JESD_K.
Unsupported Window Limit.
Unsupported window limit.
Unsupported M/L/S/F Selection.
This JESD combination is not supported.
Rev. B | Page 94 of 124
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
0x0
0x0
R
R
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
0x0
0x0
R
R
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
Data Sheet
Addr.
0x034
Name
SYNC_
ERRWINDOW
AD9154
Bits
2
Bit Name
ERR_KUNSUPP
1
ERR_SUBCLASS
0
ERR_INTSUPP
[7:3]
RESERVED
[2:0]
ERRWINDOW
Settings
Description
Unsupported K Values.
1 K value unsupported.
Unsupported SUBCLASSV Value.
1 Unsupported subclass value.
Unsupported Interpolation Factor.
1 Error with interpolation value.
Reserved.
0
1
2
3
4
5
6
7
0x038
SYNC_
LASTERR_L
[7:0]
LASTERROR_L
0x039
SYNC_
LASTERR_H
7
LASTUNDER
6
LASTOVER
[5:1]
0
7
RESERVED
LASTERROR_H
SYNCENABLE
1
1
0x03A
SYNC_
CONTROL
6
SYNCARM
5
SYNCCLRSTKY
4
SYNCCLRLAST
Sync Error Window. Synchronization rotates the clock
based on a difference in the sample of the current
phase of the internal clocks and the programmed
target based on the SYSREF± sample time. If SYSREF±
cannot be guaranteed to always exist in the same
period of the device clock associated with the target
phase from SYSREF± to SYSREF± (ERRWINDOW = 0),
then the user may choose to apply an error window
to synchronization. The error window allows the
SYSREF± sample phase to vary within the confines of
the window without triggering a clock adjustment.
Error window tolerance ±1/2.
Error window tolerance ±1.
Error window tolerance ±2.
Error window tolerance ±3.
Error window tolerance ±4.
Error window tolerance ±5.
Error window tolerance ±6.
Error window tolerance ±7.
Sync Last Error[7:0]. The value of SYNC_LASTERR_L
and SYNC_LASTERR_H[0] for the readback
SYNC_LASTERR. SYNC_LASTERR is a measure of the
error between the SYSREF sample phase and the
target value that caused the last clock adjustment.
This value is sticky and does not update until a clock
adjustment occurs. Clear this value using the
SYNCCLRLAST bit. The value is in DAC clocks.
Sync Last Error Under Flag. This bit shows that the
phase error between the SYSREF sample point and
the target is below the error window limit.
Current phase error over window tolerance.
Sync Last Error Over Flag. This bit shows that the
phase error between the SYSREF sample point and
the target is above the error window limit.
Last phase error under window tolerance.
Reserved.
Sync Last Error, Bit 8, and Flags.
Sync Logic Enable.
1 Enable sync logic.
0 Disable sync logic.
Sync Arming Strobe.
1 Sync one-shot arming.
Sync Sticky Bit Clear.
1 Clear sticky status bits REFROTA and REFTRIP.
Sync Clear LAST.
1 Clear the LAST errors.
Rev. B | Page 95 of 124
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
R
0x0
R/W
0x0
R
0x0
R
0x0
R
0x0
0x0
0x0
R
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD9154
Addr.
Name
Data Sheet
Bits
[3:0]
Bit Name
SYNCMODE
Settings
0
1
2
5
6
8
A
9
D
E
0x03B
SYNC_STATUS
7
REFBUSY
1
[6:4]
3
RESERVED
REFLOCK
2
REFROTA
1
1
1
REFWLIM
1
0
REFTRIP
1
0x03C
SYNC_
CURRERR_L
[7:0]
CURRERROR_L
0x03D
SYNC_
CURRERR_H
7
CURRUNDER
6
CURROVER
[5:1]
0
[7:2]
[1:0]
[7:0]
[7:2]
[1:0]
[7:0]
[7:0]
RESERVED
CURRERROR_H
RESERVED
DAC_GAIN_I1
DAC_GAIN_I0
RESERVED
DAC_GAIN_Q1
DAC_GAIN_Q0
GROUP DELAY
COMP I [7:0]
0x040
DAC_GAIN0_I
0x041
0x042
DAC_GAIN1_I
DAC_GAIN0_Q
0x043
0x044
DAC_GAIN1_Q
GROUPDELAY
COMP_I
0x045
GROUPDELAY
COMP_Q
[7:0]
GROUP DELAY
COMP Q [7:0]
0x046
GROUPDELAY
COMP_BYP
[7:2]
RESERVED
Description
Sync Mode.
Reserved.
Sync one-shot mode.
Sync continuous mode.
Reserved.
Reserved.
Sync monitor only mode.
Sync one-shot then monitor.
Sync one-shot then monitor.
Reserved..
Reserved
Sync Machine Busy.
Sync logic SM is busy.
Reserved.
Sync Alignment Locked.
Sync logic aligned within window.
Sync Rotated.
Sync logic rotated with SYSREF± (sticky).
Sync Alignment Limit Range.
Phase error outside of specified window error threshold.
Sync Tripped After Arming.
Sync received SYSREF pulse (sticky).
Sync Alignment Error. This register gives the user real
time access of the SYSREF± to the internal clock
counters. The value of SYNC_CURRERR =
(SYNC_CURRERR_H[0],SYNC_CURRERR_L) is the
difference between the SYSREF± position relative to
the clock divider and the target position relative to
the internal counter. This register monitors the phase
of the internal clocks in monitor modes of operation.
If an adjustment of the clocks is made on any given
SYSREF±, the value of the phase error is placed into
SYNC_LASTERR and SYNC_CURRERR is forced to 0.
Sync Current Error Under Flag.
1 Current phase error under window tolerance.
Sync Current Error Over Flag.
1 Current phase error over window tolerance.
Reserved.
Sync Current Error[8].
Reserved.
I DAC Current Scaling MSBs
I DAC Current Scaling LSBs.
Reserved.
Q DAC Current Scaling MSBs.
Q DAC current scaling LSBs.
Group Delay Compensation Bits for I Channel. These
bits set the group delay compensation for the
I channel DAC.
Group Delay Compensation Bits for Q Channel. These
bits set the group delay compensation for the Q
channel DAC.
Reserved.
Rev. B | Page 96 of 124
Reset
0x0
Access
R/W
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
0x0
0x0
0x3
0xFF
0x0
0x3
0xFF
0x0
R
R
R
R/W
R/W
R
R/W
R/W
R/W
0x0
R/W
0x0
R
Data Sheet
Addr.
Name
AD9154
Bits
1
0x04A
MIX_MODE
[7:1]
0
Bit Name
GROUPCOMP_
BYPI
GROUPCOMP_
BYPQ
RESERVED
MIX_MODE
0x050
NCO_
CLRMODE
7
NCOCLRARM
6
5
RESERVED
NCOCLRMTCH
4
NCOCLRPASS
3
NCOCLRFAIL
2
[1:0]
RESERVED
NCOCLRMODE
[7:0]
[7:0]
[7:0]
[7:0]
NCOKEYILSB
NCOKEYIMSB
NCOKEYQLSB
NCOKEYQMSB
0x060
NCOKEY_ILSB
NCOKEY_IMSB
NCOKEY_QLSB
NCOKEY_
QMSB
PA_THRES0
[7:0]
0x061
PA_THRES1
[7:5]
[4:0]
0x062
PDP_AVG_TIME
7
PDP_THRESHOLD
[7:0]
RESERVED
PA_THRESHOLD_
MSB
PDP_ENABLE
6
PA_BUS_SWAP
[5:4]
[3:0]
[7:0]
RESERVED
PDP_AVG_TIME
PDP_POWER[7:0]
0
0x051
0x052
0x053
0x054
0x063
PA_POWER0
0x064
PA_POWER1
[7:5]
[4:0]
RESERVED
PDP_POWER[12:8]
0x080
CLKCFG0
7
PD_CLK01
6
PD_CLK23
5
PDCLOCKDIG
Settings
Description
Bypass the Q Channel Group Delay Compensation
Circuitry.
Bypass the I Channel Group Delay Compensation
Circuitry.
Reserved.
Mix Mode Enable.
0 Mix mode off.
1 Mix mode on.
Arm NCO Clear. Arms NCO clearing operation.
Reset
0x1
Access
R/W
0x1
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
0x0
R
R
0x0
R
0x0
R
0x0
0x0
R
R/W
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
Average Power Threshold for Comparison.
0x0
R/W
Reserved.
Average Power Threshold for Comparison.
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x0
R
R/W
R
0x0
0x0
R
R
0x1
R/W
0x1
R/W
0x1
R/W
1 Arm NCO clear logic.
Reserved.
NCO Clear Data Match.
1 Key NCO clear data match.
NCO Clear Passed.
1 NCO clear took effect.
NCO Clear Failed.
1 NCO reset during rotate.
Reserved.
NCO Clear Mode.
0 NCO clearing disabled.
2 NCO clear on data key.
1 NCO clear on SYSREF.
NCO DataKey for I Channel LSB.
NCO DataKey for I Channel MSB.
NCO DataKey for Q Channel LSB.
NCO DataKey for Q Channel MSB.
1 Enable Average Power Calculation and Error
Detection
Swap Channel A or Channel B Data Bus for Power
Calculation.
Reserved.
Set Power Average Time.
Average Power Bus = I2 + Q2 (I/Q Use 6 MSBs of Data
Bus).
Reserved.
Average Power Bus = I2 + Q2 (I/Q Use 6 MSBs of Data
Bus).
Power-Down Clock for Dual A.
0 Enable clock divider in Dual A.
1 Disable clock divider in Dual A.
Power-Down Clock for Dual B.
0 Enable clock divider in Dual B.
1 Power-down clock divider in Dual B.
Power-Down Clocks to All DACs.
0 Enable clock for all DACs.
1 Power-down clock for all DACs.
Rev. B | Page 97 of 124
AD9154
Addr.
Name
Data Sheet
Bits
4
Bit Name
PD_PCLK
Settings
0
1
3
PDCLOCKREC
0
1
2
1
0
DUTY_EN
RF_SYNC_EN
RF_CLKDIV_EN
0
1
0x081
SYSREF_
ACTRL0
[7:5]
RESERVED
4
PDSYSREF
3
HYS_ON
0
1
2
SYSREF_RISE
0
1
[1:0]
HYS_CNTRL1
0x082
SYSREF_
ACTRL1
[7:0]
HYS_CNTRL0
0x083
DACPLLCNTRL
7
SYNTH_RECAL
[6:5]
RESERVED
Description
Power-Down Calibration Reference/SERDES PLL Clock.
Enable clock to SERDES PLL/calibration logic.
Disable clock to SERDES PLL/calibration logic.
Power-Down Clock Receiver.
Enable clock receiver analog buffer.
Power-down clock receiver analog buffer.
Enable Duty Cycle Control of Clock Receiver, Always = 1.
Enable SYSREF± timing for RF clock chain.
Enable RF Clock Divider. The RF clock divider divides
the input clock by 2 and provides the result to the
DAC for sampling.
RF clock divider disabled.
RF clock divider enabled.
Reserved.
Reset
0x1
Access
R/W
0x1
R/W
0x1
0x1
0x0
R/W
R/W
R/W
0x0
R
Power Down SYSREF± Buffer. This bit powers down
the SYSREF± receiver. For Subclass 1 operation to
work, this buffer must be enabled.
Hysteresis On. This bit enables the programmable
hysteresis control for the SYSREF± receiver.
Disable hysteresis in SYSREF± receiver.
Enable hysteresis in SYSREF± receiver.
Use SYSREF± Rising Edge.
Use SYSREF± falling edge for alignment.
Use SYSREF± rising edge for alignment.
MSBs of Hysteresis Control. Hysteresis control bits are
control bits for the amount of hysteresis in the
SYSREF± receiver. Each of the ten bits adds 10 mV of
differential hysteresis to the receiver input. Two of
the 10 bits are contained here. The other 8 bits are in
HYS_CNTRL0.
Low Bits of Hysteresis Control. Hysteresis control bits
are control bits for the amount of hysteresis in the
SYSREF± receiver. Each of the ten bits adds 10 mV of
differential hysteresis to the receiver input. Eight of
the 10 bits are contained here. The other 2 bits are in
HYS_CNTRL1.
Recalibrate VCO Band. Set this bit to reinitialize the
calibration of the VCO band in the DAC PLL. This bit
does not power cycle the DAC PLL, nor does it
recalibrate the charge pump. Set this bit after
changing any setting associated with the PLL. Do not
set this bit until after an initial PLL lock is achieved.
Reserved.
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R
Rev. B | Page 98 of 124
Data Sheet
Addr.
Name
AD9154
Bits
4
Bit Name
ENABLE_SYNTH
Settings
0
1
0x084
DACPLLSTATUS
[3:0]
7
RESERVED
CP_
OVERRANGE_H
0
1
6
CP_
OVERRANGE_L
0
1
5
CP_CAL_VALID
0
1
4
VCO_CAL_
PROGRESS
0
1
[3:2]
1
RESERVED
RFPLL_LOCK
1
0
0x085
DACINTEGER
WORD0
0
[7:0]
RESERVED
BCOUNT
Description
Synthesizer Enable. The bit initiates the start-up
sequence of the DAC PLL. The start-up sequence is as
follows:
1. Enable the bias currents.
2. Enable DAC LDO.
3. Wait for LDO to settle.
4. Calibrate DAC PLL charge pump (The DAC charge
pump will only calibrate upon the first setting of
ENABLE_SYNTH).
5. Calibrate the band of the PLL.
6. Settle and lock.
Disable synthesizer including all currents and
calibration codes.
Power up synthesizer and initiate calibration sequence.
Reserved.
Charge Pump High Overrange. This bit indicates that
the charge pump voltage is too high and a
recalibration must be applied.
Control voltage not too high.
Control voltage too high.
Charge Pump Low Overrange. This bit indicates that
the charge pump voltage is too low and a
recalibration must be applied.
Control voltage not too low.
Control VOLTAGE too low.
Charge Pump Calibration Valid. This bit indicates that
the charge pump has been successfully calibrated.
The selection as to whether the charge pump needs
to be calibrated upon startup can be found in
Register 0x1B9.
If CP_CAL_EN low, this stays low.
If CP_CAL_EN high (def ), this happens when charge
pump is calibrated.
VCO Calibration in Progress. This bit is high if the VCO
calibration is currently occurring. If this bit is high for
more than 1 sec there is something wrong with the
VCO calibration.
VCO not calibrating.
VCO calibrating.
Reserved.
PLL Lock bit. This bit is set high by the PLL once the
PLL has achieved lock for the count set by
LOCK_MODE bits in Register 0x1C0.
PLL locked.
PLL unlocked.
Reserved.
Bits[7:0] of the Integer Tuning Word. This bit controls
the integer feedback divider for the DAC PLL. The
frequency of the DAC clock can be determined by
the following equations:
fDAC = fREF/(REFDIVMODE ) × 2 × BCount
fVCO = fREF /(REFDIVMODE ) × 2 × BCount ×
LODivMode
The minimum value is 6.
Rev. B | Page 99 of 124
Reset
0x0
Access
R/W
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
0x6
R
R/W
AD9154
Addr.
0x087
Name
DACLOOPFILT1
0x088
DACLOOPFILT2
0x089
DACLOOPFILT3
Data Sheet
Bits
[7:4]
[3:0]
[7:4]
[3:0]
7
Bit Name
LF_C2_WORD
LF_C1_WORD
LF_R1_WORD
LF_C3_WORD
LF_BYPASS_R3
Settings
0
1
6
LF_BYPASS_R1
0
1
5
LF_BYPASS_C2
0
1
4
LF_BYPASS_C1
0
1
0x08A
DACCPCNTRL
[3:0]
7
6
LF_R3_WORD
RESERVED
VT_FORCE
0
1
0x08B
0x08C
DACLOGEN
CNTRL
DACLDOCNTRL1
[5:0]
[7:6]
CP_CURRENT
RESERVED
[5:4]
LO_POWER_
MODE
[3:2]
[1:0]
RESERVED
LODIVMODE
7
LDO_REF_SEL
6
[5:3]
[2:0]
LDO_BYPASS_
FILT
RESERVED
REFDIVMODE
Description
C2 Control Word.
C1 Control Word.
R1 Control Word.
C3 control Word.
Bypass R3 Resistor.
Enable R3 resistor programming start at 0.
Disable R3 resistor is LF_R3_WORD = 0.
Bypass R1 Resistor.
Enable R1 resistor programming at 0.
Disable R1 if LF_R1_WORD = 0.
Bypass C2 Capacitor.
Enable C2 capacitor programming at 0.
Disable C2 capacitor is LF_C2_WORD = 0.
Bypass C1 Capacitor.
Enable C1 capacitor programming at 0.
Disable C1 capacitor if LF_C1_WORD = 0.
R3 Control Word.
Reserved.
VT Control Out.
Control voltage not brought out for test.
Control voltage brought out for test.
Charge Pump Current Control.
Reserved.
Local Oscillator Generator (Logen) Power Mode.
0 Full power—VCO, 8 GHz to 12 GHz.
1 Half power—VCO, 6 GHz to 8 GHz.
3 Off.
Reserved.
Logen Division.
0 Reserved.
1 Divide by 4—VCO to DAC clock.
2 Divide by 8—VCO to DAC clock.
3 Divide by 16—VCO to DAC clock.
Reference Selection Bit.
0 Generate reference from BG.
1 Generate reference from supply.
Disable LDO Voltage Filter.
0 Enable voltage filter to LDO input.
1 Disable voltage filter to LDO input.
Reserved.
Reference Clock Division Ratio.
0 1×.
1 2×.
2 4×.
3 8×.
4 16×.
5 32×.
6 16×.
7 32×.
Rev. B | Page 100 of 124
Reset
0x8
0x8
0x8
0x8
0x0
Access
R/W
R/W
R/W
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x8
0x0
0x0
R/W
R
R/W
0x20
0x0
R/W
R
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R/W
Data Sheet
Addr.
0x08D
Name
DACLDOCNTRL2
0x110
DATA_FORMAT
0x111
DATAPATH_
CTRL
AD9154
Bits
7
[6:5]
[4:2]
LDO_INRUSH
LDO_SEL
[1:0]
LDO_VDROP
7
BINARY_FMT
[6:0]
7
RESERVED
INVSINC_ENABLE
6
5
RESERVED
DIG_GAIN_
ENABLE
PHASE_ADJ_
ENABLE
MODULATION_
TYPE
4
[3:2]
0x112
INTERPMODE
Bit Name
LDO_BYPASS
1
SEL_SIDEBAND
0
[7:3]
[2:0]
I_TO_Q
RESERVED
INTERPMODE
Settings
Description
Bypass LDO Function.
0 LDO operates normally.
1 LDO output shorted to VDD.
LDO Startup Speed Control.
LDO Voltage and Power Setup.
0 1.08 V low power.
1 1.08 V mid power.
2 1.08 V high power.
3 Not used.
4 1.02 V low power.
5 1.02 V mid power.
6 1.02 V high power.
7 Not used.
LDO Passgate Control.
0 One passgate used.
1 Two passgates used.
2 Three passgates used.
3 Four passgates used.
Binary or Twos Complementary Format on DATA Bus.
0 Input data is twos compliment.
1 Input data is offset binary.
Reserved.
1 Enable Inverse Sinc Filter.
NCO_FTW_
UPDATE
[7:2]
RESERVED
1
FTW_UPDATE_
ACK
FTW_UPDATE_
REQ
FTW0
FTW1
FTW2
0
0x114
0x115
0x116
FTW0
FTW1
FTW2
[7:0]
[7:0]
[7:0]
Access
R/W
0x1
0x2
R/W
R/W
0x3
R/W
0x0
R/W
0x0
0x1
R
R/W
1
Reserved.
Enable Digital Gain.
0x0
0x1
R
R/W
1
Enable Phase Compensation.
0x0
R/W
Selects Type of Modulation Operation.
0x0
R/W
0x0
R/W
0x0
0x0
0x1
R/W
R
R/W
0x0
R
Frequency Tuning Word Update Acknowledge.
0x0
R
Frequency Tuning Word Update Request from SPI.
0x0
R/W
NCO Frequency Tuning Word, FTW[7:0].
NCO Frequency Tuning Word, FTW[15:8].
NCO Frequency Tuning Word, FTW[23:16].
0x0
0x0
0x0
R/W
R/W
R/W
0
1
2
3
1
1
0
1
3
4
0x113
Reset
0x0
No modulation.
Fine modulation (uses FTW).
fS/4 modulation.
fS/8 modulation.
Select Upper or Lower Sideband from Modulation
Result.
Send I Datapath into Q DAC.
Reserved.
Interpolation Mode.
1x (bypass).
2x mode.
4x mode.
8x mode.
Reserved.
Rev. B | Page 101 of 124
AD9154
Addr.
0x117
0x118
0x119
0x11A
0x11B
0x11C
0x11D
0x11F
Name
FTW3
FTW4
FTW5
NCO_PHASE_
OFFSET0
NCO_PHASE_
OFFSET1
NCO_
PHASEADJ[7:0]
NCO_
PHASEADJ
[12:8]
TXEN_SM_0
Data Sheet
Bits
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
FTW3
FTW4
FTW5
NCO_PHASE_
OFFSET0
NCO_PHASE_
OFFSET1
PHASEADJ[7:0]
[7:0]
PHASEADJ[12:8]
Phase Compensation Word, PHASE_ADJ[12:8].
0x0
R/W
[7:6]
[5:4]
3
2
PA_FALL
PA_RISE
RESERVED
GP_PA_ON_
INVERT
GP_PA_CTRL
PA Fall Control.
PA Rises Control.
Reserved.
External Modulator Polarity Invert.
0x2
0x0
0x0
0x0
R/W
R/W
R
R/W
External PA Control. Enabled by default to allow
external mod control instead of sync signal through
this pin.
Enable TXEN State Machine.
0x1
R/W
0x1
0xF
0x0
0xFF
0xFF
0x46
R/W
R/W
R/W
R/W
R/W
R/W
0x10
R/W
[7:0]
1
0x121
0x122
0x123
0x124
0x12D
0x12F
TXEN_SM_2
TXEN_SM_3
TXEN_SM_4
TXEN_SM_5
DEVICE_
CONFIG_REG0
DIE_TEMP_
CTRL0
0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:1]
0
0x132
0x133
0x134
DIE_TEMP0
DIE_TEMP1
DIE_TEMP_
UPDATE
DC_OFFSET_
CTRL
0x136
IPATH_DC_OFFSET_1PART0
IPATH_DC_OFFSET_1PART1
QPATH_DC_
OFFSET_
1PART0
QPATH_DC_
OFFSET_
1PART1
IPATH_DC_
OFFSET_2PART
0x137
0x138
0x139
0x13A
Description
NCO Frequency Tuning Word, FTW[31:24].
NCO Frequency Tuning Word, FTW[39:32].
NCO Frequency Tuning Word, FTW[47:40].
NCO Phase Offset, NCO_PHASE_OFFSET[7:0].
Reset
0x0
0x0
0x10
0x0
Access
R/W
R/W
R/W
R/W
NCO Phase Offset, NCO_PHASE_OFFSET[15:8].
0x0
R/W
Phase Compensation Word, PHASE_ADJ[7:0].
0x0
R/W
Must Be Set to 0x8B for Proper Digital Datapath
Configuration.
Reserved.
AUXADC_
ENABLE
DIE_TEMP_LSB
DIE_TEMP_MSB
RESERVED
1 = Enable AUXADC Block.
0x0
R/W
AUXADC Readback Value Bits[7:0], LSB.
AUXADC Readback Value Bits[15:8], MSB.
Reserved.
0x0
0x0
0x0
R
R
R
DIE_TEMP_
UPDATE
RESERVED
Die Temperature Update. When updated, new
temperature code is received.
Reserved.
0x0
R/W
0x0
R
DC_OFFSET_ON
IPATH_DC_
OFFSET_1PART0
IPATH_DC_
OFFSET_1PART1
QPATH_DC_
OFFSET_1PART0
1 = Enable DC Offset Module.
LSB of First Part of DC Offset Value for I Path.
0x0
0x0
R/W
R/W
MSB of First Part of DC Offset Value for I Path.
0x0
R/W
LSB of First Part of DC Offset Value for Q Path.
0x0
R/W
[7:0]
QPATH_DC_
OFFSET_1PART1
MSB of First Part of DC Offset Value for Q Path.
0x0
R/W
[7:5]
RESERVED
Reserved.
0x0
R
[4:0]
IPATH_DC_
OFFSET_2PART
Second Part Of DC Offset Value For I Path.
0x0
R/W
[7:0]
[7:0]
[7:1]
0
0x135
TXEN_SM_EN
RISE_COUNT_0
RISE_COUNT_1
FALL_COUNT_0
FALL_COUNT_1
DEVICE_
CONFIG_0
RESERVED
Settings
[7:1]
0
[7:0]
[7:0]
[7:0]
Rev. B | Page 102 of 124
Data Sheet
Addr.
0x13B
0x13C
0x13D
Name
QPATH_DC_
OFFSET_2PART
IDAC_DIG_
GAIN0
IDAC_DIG_
GAIN1
AD9154
Bits
[7:5]
Bit Name
RESERVED
[4:0]
[7:0]
[7:4]
[3:0]
0x13E
0x13F
QDAC_DIG_
GAIN0
QDAC_DIG_
GAIN1
[7:0]
[7:4]
[3:0]
0x140
0x141
GAIN_RAMP_
UP_STEP0
GAIN_RAMP_U
P_STEP1
[7:0]
[7:4]
[3:0]
0x142
0x143
0x146
GAIN_RAMP_D [7:0]
OWN_STEP0
GAIN_RAMP_D [7:4]
OWN_STEP1
[3:0]
0x147
DEVICE_CONFI
G_REG1
BLSM_STAT
0x14B
PRBS
[7:0]
[7:6]
[5:0]
7
Settings
Description
Reserved.
Reset
0x0
Access
R
QPATH_DC_
OFFSET_2PART
IDAC_DIG_
GAIN0
RESERVED
Second Part of DC Offset Value for Q Path.
0x0
R/W
LSB of I DAC Digital Gain.
0x0
R/W
Reserved.
0x0
R
IDAC_DIG_
GAIN1
QDAC_DIG_
GAIN0
RESERVED
MSB of I DAC Digital Gain.
0x8
R/W
LSB of Q DAC Digital Gain.
0x0
R/W
Reserved.
0x0
R
QDAC_DIG_
GAIN1
GAIN_RAMP_
UP_STEP0
RESERVED
MSB of Q DAC Digital Gain.
0x8
R/W
LSB of Digital Gain Rises.
0x4
R/W
Reserved.
0x0
R
GAIN_RAMP_
UP_STEP1
GAIN_RAMP_
DOWN_STEP0
RESERVED
MSB of Digital Gain Rises.
0x0
R/W
LSB of Digital Gain Drops.
0x9
R/W
Reserved.
0x0
R
GAIN_RAMP_
DOWN_STEP1
DEVICE_
CONFIG_1
BE_ROTATE_REQ
RESERVED
PRBS_GOOD_Q
MSB of Digital Gain Drops.
0x0
R/W
Must be Set to 0x01 During Startup.
0x0
R/W
BE_ROTATE_REQ Forced Value.
Reserved.
Good Data Indicator Imaginary Channel.
Incorrect sequence detected.
Correct PRBS sequence detected.
Good Data Indicator Real Channel.
Incorrect sequence detected.
Correct PRBS sequence detected.
Reserved.
Reserved.
Polynomial Select.
7-bit: x7 + x6 + 1
15-bit: x15 + x14 + 1
Reset Error Counters.
Normal operation.
Reset counters.
Enable PRBS Checker.
Disable.
Enable.
Error Count Value Real Channel.
Error Count Value Imaginary Channel.
0x0
0x0
0x0
R/W
R/W
R
0x0
R
0x0
0x1
0x0
R
R/W
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R
0
1
6
PRBS_GOOD_I
0
1
5
[4:3]
2
RESERVED
RESERVED
PRBS_MODE
0
1
1
PRBS_RESET
0
1
0
PRBS_EN
0
1
0x14C
0x14D
PRBS_ERROR_I [7:0]
PRBS_ERROR_Q [7:0]
PRBS_COUNT_I
PRBS_COUNT_Q
Rev. B | Page 103 of 124
AD9154
Addr.
0x1B0
Name
DACPLLT0
Data Sheet
Bits
7
Bit Name
VCO_PD_IN
Settings
0
1
6
VCO_PD_PTAT
1
0
5
VCO_PD_ALC
1
0
4
SYNTH_PD
0
1
3
LDO_PD
0
1
2
1
RESERVED
LOGEN_PD
0
1
0x1B1
DACPLLT1
0
[7:4]
[3:2]
RESERVED
RESERVED
PFD_DELAY
0
1
2
3
1
PFD_EDGE
0
1
0x1B2
0x1B3
0x1B4
0x1B5
DACPLLT2
DACPLLT3
DACPLLT4
DACPLLT5
0
7
RESERVED
EXT_ALC_WORD_
EN
[6:0]
[7:0]
7
[6:3]
2
1
EXT_ALC_WORD
EXT_BAND1
BYP_LOAD_DELAY
VCO_CAL_OFFSET
RESERVED
EXT_BAND_EN
0
[7:4]
[3:0]
EXT_BAND2
INIT_ALC_VALUE
VCO_VAR
Description
VCO PD.
If power machine disabled this powers up the VCO.
If power machine disabled this powers down the VCO.
PD ptat current gen VCO.
If power machine disabled this powers down the
VCO ptat gen.
If power machine disabled this powers up the VCO
ptat gen.
PD ALC Circuit in VCO.
If power machine disabled this powers down the
VCO ALC.
If power machine disabled this powers up the VCO
ALC.
PD Total Synthesizer/Reset Machine.
If power machine disabled this powers up the
synthesizer.
If power machine disabled this powers down the
synthesizer.
PD LDO.
If power machine disabled this powers up the LDO.
If power machine disabled this powers down the
LDO.
Reserved.
PD LO Generator.
If power machine disabled this powers up the
Prescaler/DAC clock gen.
If power machine disabled this powers down the
Prescaler/DAC clock gen.
Reserved.
Reserved.
PFD Delay.
Shortest delay.
Longer delay.
Longer delay still.
Longest delay.
PFD Clock Edge.
Reference rising edge.
Reference falling edge.
Reserved.
Force ALC Word Externally.
0 Norm operation auto ALC.
1 Manually set ALC.
External ALC Word.
Bottom bit of VCO tuning band to be forced.
Bypass Load Delay.
Starting Offset for VCO Calibration.
Reserved.
FORCE VCO Tuning Band Externally.
0 Normal autocal mode.
1 Manual for VCO band.
External band MSB.
Initial ALC Sweep Value.
Varactor KVO Setting.
Rev. B | Page 104 of 124
Reset
0x1
Access
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x0
0x1
R
R/W
0x0
0x0
0x1
R
R
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
0x0
0x0
0xF
0x0
0x0
W
W
R/W
R/W
R
R/W
0x0
0x8
0x3
W
R/W
R/W
Data Sheet
Addr.
0x1B6
Name
DACPLLT6
0x1B7
DACPLLT7
0x1B8
0x1B9
DACPLLT8
DACPLLT9
AD9154
Bits
7
6
[5:4]
[3:0]
7
Bit Name
RESERVED
PORESETB_VCO
EXT_VCO_BITSEL
VCO_LVL_OUT
LD_SYNTH
6
[5:0]
7
6
5
4
RESERVED
CP_IBLEED
RESERVED
COMP_OUT
CP_CAL_DONE
VCO_CAL_IN_
PROG
CP_CALBITS
HALF_VCO_CAL_
CLK
DITHER_MODE
MACHINE_
ENABLE
CP_OFFSET_OFF
FORCE_CP_
CALBITS
[3:0]
7
6
5
4
3
0x1BA
DACPLLTA
0x1BB
DACPLLTB
0x1BC
DACPLLTC
0x1BD
DACPLLTD
2
CAP_CAL_EN
[1:0]
[7:4]
[3:0]
CP_TEST
MACHINE_STATE
FCP_CALBITS
[7:5]
[4:3]
[2:0]
7
[6:5]
4
RESERVED
VCO_BIAS_TCF
VCO_BIAS_REF
VCO_BYP_BIASR
RESERVED
VCO_COMP_BYP_
BIASR
PRSC_HIGHR
LAST_ALC_EN
PRSC_BIAS_CTRL
RESERVED
VCO_CAL_REF_
MON
VCO_CAL_REF_
TCF
3
2
[1:0]
[7:4]
3
[2:0]
Settings
Description
Reserved.
Reset for VCO Logic.
External VCO Bitsel.
VCO Amplitude Control.
Manual Recalibration of Synthesizer.
1 Enable circuitry to reduce the voltage of the cal
offset target point.
0 Disable circuitry to reduce the voltage of the cal
offset target point.
Reserved.
Charge Pump Offset.
Reserved.
CP Calibration comparator output.
CP Calibration has completed.
VCO Calibration occurring.
Reset
0x0
0x1
0x0
0xA
0x0
Access
R
R/W
R/W
R/W
R/W
0x0
0x0
0x0
0x0
0x0
0x0
R
R/W
R
R
R
R
Calibrated CP outcome.
Slow down VCO Calibration clock.
0x0
0x0
R
R/W
Dither Mode—Not used.
PLL power mode machine enable.
0x0
0x1
R/W
R/W
Turn off CP offset.
Force external CP cal code.
0x1
0x0
R/W
R/W
0x1
R/W
0x0
0x0
0x0
R/W
R
R/W
0x0
0x1
0x4
0x0
0x0
0x0
R
R/W
R/W
R/W
R/W
R/W
PRSC configuration.
Enable Last ALC.
PRSC bias Control.
Reserved.
Sent control voltage to outside world.
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R
R/W
Temperature Coefficient for Calibration reference.
0x0
R/W
0 CP Calibration auto—if device off.
1 CP Calibration manual—if device off.
Enable CP Calibration.
0 Disable charge pump calibration.
1 Enable charge pump calibration.
CP Test Modes.
Power-Up Machine State.
External CP Calibration Bits to Drive. These are the
externally forced calibration bits for the charge
pump in the PLL when the power-up machine is not
in use. The power-up machine automatically
calibrates the charge pump and stores the value in
the device.
Reserved.
Temperature Coefficient for VCO bias.
VCO Bias control.
Bypass VCO bias Resistor.
Reserved.
Bypass Resistor in VCO Comparator.
Rev. B | Page 105 of 124
AD9154
Addr.
0x1BE
Name
DACPLLTE
Data Sheet
Bits
[7:4]
3
2
1
0
0x1BF
DACPLLTF
0x1C0
DACPLLT10
7
[6:4]
[3:2]
[1:0]
[7:6]
5
4
[3:0]
[7:4]
[3:0]
[7:1]
0
DOUBLE_F0_CAL_
CNT
LOCKDETECT_CO
UNT
LOCK_MODE
RESERVED
CP_LVL_DET_PD
CP_VL_LOW
CP_VL_HIGH
SDM_BP
SDM_PD
RESERVED
SDM_PROG
RESERVED
SDM_PROG3
SDM_PROG2
SDM_PROG1
RESERVED
VCO_VAR_REF_
TCF
VCO_VAR_OFF
RESERVED
VCO_VAR_REF
RESERVED
SPI_PD_MASTER
[3:2]
0x1C1
DACPLLT11
0x1C2
DACPLLT15
0x1C3
DACPLLT16
0x1C4
DACPLLT17
Bit Name
RESERVED
VCO_PDO_VR
VCO_PDO_VRTCF
VCO_PDO_
CALTCF
VCO_PDO_
VCOBUF
I_CAL_EN
I_ALC_WAIT_D
I_CAL_COUNT
FDBCK_DELAY
RESERVED
USE_NEW_CAL
[1:0]
7
6
[5:3]
[2:0]
7
6
[5:4]
[3:0]
7
6
5
[4:0]
7
[6:4]
Settings
Description
Reserved.
Varactor Reference Power-down Override.
Varactor Temperature Coefficient Power-Down
Calibration Temperature Coefficient Power-Down.
Reset
0x0
0x0
0x0
0x0
Access
R
R/W
R/W
R/W
VCO Buffer PD Override.
0x0
R/W
0x1
0x0
0x3
0x1
0x0
0x1
R/W
R/W
R/W
R/W
R
R/W
0x0
R/W
0x3
R/W
Lock Detector Mode.
Reserved.
Level detector power-down.
Low Level detect voltage.
High Level detection point.
Bypass Sigma Delta.
Power-Down SDM.
Reserved.
Program SDM.
Reserved.
SIF Clock.
SIF Preset Bar.
SIF Address.
Reserved.
Varactor Reference Temperature Coefficient.
0x2
0x0
0x0
0x2
0x5
0x1
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x3
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R
R/W
0x3
0x0
0x8
0x0
0x1
R/W
R
R/W
R
R/W
0x0
R/W
0x0
0x0
R
R/W
VCO Band Calibration Enable.
VCO calibration wait for ALC cal from band change.
Calibration Count Length.
Feedback Clock Advance.
Reserved.
Use new calibrator.
0 use old calibrator.
1 use new calibrator.
Increase calibrator count by 2×—Old calibrator
machine.
Counter length for Lock detector.
0x1C5
DACPLLT18
0x200
MASTER_PD
0x201
PHY_PD
[7:0]
UNUSEDLANES
0x203
GENERIC_PD
[7:2]
1
RESERVED
SPI_SYNC1_PD
Varactor Offset.
Reserved.
VCO Varactor Reference.
Reserved.
Power down the entire JESD204B Rx analog (all eight
channels + bias).
SPI override to power down the individual PHYs.
Set Bit x to power down the corresponding SERDINx±
PHY.
Reserved.
Power down LVDS buffer for SYNCOUT0±.
0
SPI_SYNC2_PD
Power down LVDS buffer for SYNCOUT1±.
0x0
R/W
[7:1]
0
RESERVED
SPI_CDR_RESETN
Reserved.
Resets the digital control logic for all PHYs.
0 CDR logic is reset.
1 CDR logic is operational.
0x0
0x1
R
R/W
0x206
CDR_RESET
Rev. B | Page 106 of 124
Data Sheet
Addr.
0x230
Name
CDR_
OPERATING_
MODE_REG_0
0x268
EQ_BIAS_REG
0x280
SYNTH_
ENABLE_
CNTRL
0x281
PLL_STATUS
AD9154
Bits
[7:6]
Bit Name
RESERVED
5
HALFRATE
[4:2]
1
RESERVED
CDR_OVERSAMP
0
[7:6]
RESERVED
EQ_POWER_
MODE
[5:0]
[7:3]
2
RESERVED
RESERVED
SPI_RECAL_
SYNTH
1
0
RESERVED
SPI_ENABLE_
SYNTH
[7:6]
5
RESERVED
SPI_CP_OVER_
RANGE_HIGH_RB
4
SPI_CP_OVER_
RANGE_LOW_RB
3
SPI_CP_CAL_
VALID_RB
2
SPI_VCO_CAL_IN
_PROGRESS_RB
1
SPI_CURRENTS_
READY_RB
0
SPI_PLL_LOCK_
RB
Settings
Description
Reserved.
Enables half rate CDR operation.
0 Disables CDR half rate operation, data rate ≤6 Gbps.
1 Enables CDR half rate operation, data rate > 6 Gbps.
Reserved.
Enables Oversampling of the Input Data. Set to 1
when 1.44 Gbps ≤ lane rate ≤ 2.88 Gbps.
Reserved.
Used to control the equalizer power/insertion loss
capability.
0 Normal Mode.
1 Low Power.
Reserved.
Reserved.
Set this bit high to re-run all of the SERDES PLL
calibration routines.
Set this bit low again to allow for additional recalibrations. Rising edge causes the calibration.
Reserved.
Enable the SERDES PLL.
Setting this bit turns on all currents and proceeds to
calibrate the PLL.
Make sure reference clock and division ratios are
correct before enabling this bit.
Reserved.
Applies if SPI_VCO_OUTPUT_LEVEL = 0. If set, the CP
output is above CP Level Threshold High.
0 Charge pump output is below
CP_LEVEL_THRESHOLD_HIGH.
1 Charge pump output is above
CP_LEVEL_THRESHOLD_HIGH.
Applies if SPI_VCO_OUTPUT_LEVEL = 0. If set, the CP
output is below CP Level Threshold Low.
0 Charge pump output is above
CP_LEVEL_THRESHOLD_LOW.
1 Charge pump output is below
CP_LEVEL_THRESHOLD_LOW.
This bit tells the user if the charge pump cal has
completed.
0 Charge pump calibration is not valid.
1 Charge pump calibration is valid.
This bit set indicates that a VCO calibration is
running.
0 VCO calibration is not running.
1 VCO calibration is running.
0 PLL bias currents are not ready.
1 PLL bias currents are ready.
If set, the synth locked in the number of clock cycles
set by Lock Detect Count.
0 PLL is not locked.
1 PLL is locked.
Rev. B | Page 107 of 124
Reset
0x0
Access
R/W
0x1
R/W
0x0
0x0
R/W
R/W
0x0
0x1
R/W
R/W
0x32
0x0
0x0
R/W
R
R/W
0x0
0x0
R/W
R/W
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
R
AD9154
Addr.
0x284
Name
LOOP_
FILTER_1
0x285
LOOP_
FILTER_2
0x286
LOOP_
FILTER_3
0x287
CP_CURRENT
0x289
REF_CLK_
DIVIDER_LDO
Data Sheet
Bits
[7:4]
[3:0]
[7:4]
[3:0]
[7:4]
[3:0]
7
6
Bit Name
LOOP_FILTER_1
Loop filter configuration setting.
LOOP_FILTER_3
Loop filter configuration setting.
RESERVED
SPI_SERDES_
LOGEN_POWER_
MODE
Reserved.
SPI_CP_CURRENT
RESERVED
3
SPI_LDO_REF_
SEL
2
SPI_LDO_
BYPASS_FILT
[1:0]
SPI_CDR_
OVERSAMP
SPI_SERDES_LDO
_CONFIG
RESERVED
SPI_VCO_PD
VCO_LDO
[7:0]
0x28B
PLL_PD_REG
7
6
5
4
3
2
1
Description
Loop filter configuration setting.
LOOP_FILTER_2
[5:0]
[7:4]
0x28A
Settings
SPI_VCO_PD_
PTAT
SPI_VCO_PD_ALC
SPI_SYN_PD
SPI_SERDES_
LDO_PD
SPI_SERDES_
LOGEN_PD_
OUTBUF
0 Power Mode 0.
1 Power Mode 1.
CP Current Setting.
Reserved.
Selects LDO reference to be from the band gap or a
voltage divider (VDD/2).
0 Select band gap for reference.
1 Select voltage divider (VDD/2) for reference.
Bypasses filter on LDO reference input.
Reset
0x7
0x7
0x8
0x7
0x0
0x8
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
0x3F
0x0
R/W
R
0x0
R/W
0x1
R/W
0 Filter enabled.
1 Filter bypassed.
Enable oversampling of input data.
0x0
The valid options are:
1×, 2×, and 4×.
1× works for Half Rate—6.25 Gbps to 12.5 Gbps.
1× works for Full Rate—3.125 Gbps to 6.25 Gbps.
2× works for Full Rate—1.625 Gbps to 3.125 Gbps (2×
oversampling).
4× works for Full Rate—812.5 Mbps to 1.625 Gbps
(4× oversampling).
Oversampling set in Register 0x230.
0 No oversampling. Data rate > 6 Gbps.
1 Oversample by 2×. 3 Gbps < data rate ≤ 6 Gbps.
2 Oversample by 4×. 1.5 Gbps < data rate ≤ 3 Gbps.
VCO LDO Setting.
0x2B
Reserved.
VCO enable.
0 VCO enabled.
1 VCO disabled.
PD LDO.
0 LDO enabled.
1 LDO disabled.
PD divider buffer.
0 Buffer enabled.
1 Buffer disabled.
Rev. B | Page 108 of 124
R/W
R/W
0x0
0x1
R/W
R/W
0x1
R/W
0x1
0x1
0x1
R/W
R/W
R/W
0x1
R/W
Data Sheet
Addr.
0x290
Name
ALC_
VARACTOR
AD9154
Bits
0
[7:4]
[3:0]
0x291
VCO_OUTPUT
[7:4]
[3:0]
0x294
CP_CONFIG
7
6
5
4
3
0x296
VCO_BIAS_1
2
[1:0]
[7:5]
[4:3]
[2:0]
0x297
VCO_BIAS_2
[7:6]
5
4
3
2
[1:0]
0x299
VCO_PD_
OVERRIDES
[7:4]
3
2
1
0
Bit Name
Settings
SPI_SERDES_
LOGEN_PD_CORE
SPI_INIT_ALC_
VALUE
SPI_VCO_
VARACTOR
RESERVED
SPI_VCO_
OUTPUT_LEVEL
SPI_HALF_VCO_
CAL_CLK
SPI_DITHER_
MODE
SPI_ENABLE_
MACHINE
SPI_CP_OFFSET_
OFF
SPI_CP_FORCE_
CALBITS
SPI_CP_CAL_EN
SPI_CP_TEST
RESERVED
SPI_VCO_BIAS_
TCF
SPI_VCO_BIAS_
REF
RESERVED
SPI_VCO_BYPASS
_BIAS_DAC_R
SPI_VCO_COMP_
BYPASS_BIASR
SPI_PRESCALE_
BYPASS_R
SPI_LAST_ALC_
EN
SPI_PRESCALE_
BIAS
RESERVED
SPI_VCO_PD_
OVERRIDE_VAR_
REF
SPI_VCO_PD_
OVERRIDE_VAR_
REF_TCF
SPI_VCO_PD_
OVERRIDE_CAL_
TCF
SPI_VCO_PD_
OVERRIDE_
VCOBUF
Description
PD Logen Dividers.
Reset
0x1
Access
R/W
0 Dividers enabled.
1 Dividers disabled.
ALC Value Setting.
0x8
R/W
VCO KV Setting.
0x3
R/W
Reserved.
VCO output level setting.
0x4
0x9
R/W
R/W
0x1
R/W
0x0
R/W
0x1
R/W
0x1
R/W
0x0
R/W
0x0
0x0
0x0
0x1
R/W
R/W
R/W
R/W
CP Calibration Control.
0x4
R/W
Reserved.
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Reserved.
Rev. B | Page 109 of 124
AD9154
Addr.
0x29A
Name
VCO_CAL
Data Sheet
Bits
7
[6:4]
[3:2]
[1:0]
0x29C
CP_LEVEL_
DETECT
7
6
[5:3]
[2:0]
0x29F
VCO_
VARACTOR_
CONTROL_0
7
[6:4]
[3:0]
0x2A0
0x2A7
VCO_
VARACTOR_
CONTROL_1
TERM_BLK1_
CTRLREG0
[7:4]
[3:0]
[7:1]
0
0x2AE
TERM_BLK2_
CTRLREG0
[7:1]
0
0x300
GENERAL_
JRX_CTRL_0
7
6
Bit Name
Settings
SPI_VCO_CAL_EN
SPI_VCO_CAL_
ALC_WAIT
SPI_VCO_CAL_
COUNT
SPI_FB_CLOCK_
ADV
RESERVED
SPI_CP_LEVEL_
DET_PD
SPI_CP_LEVEL_
THRESHOLD_LOW
SPI_CP_LEVEL_
THRESHOLD_
HIGH
RESERVED
SPI_VCO_VARACTOR_REF_TCF
SPI_VCO_VARACTOR_OFFSET
RESERVED
SPI_VCO_
VARACTOR_REF
RESERVED
Description
Reset
0x1
0x7
Access
R/W
R/W
0x3
R/W
0x2
R/W
0x0
0x0
R
R/W
0x2
R/W
0x7
R/W
0x0
0x3
R
R/W
0x3
R/W
0x0
0x8
R
R/W
Reserved.
0x0
R
SPI_I_TUNE_R_
CAL_TERMBLK1
RESERVED
Rising edge of this bit starts a termination calibration
routine.
Reserved.
0x0
R/W
0x0
R
SPI_I_TUNE_R_
CAL_TERMBLK2
RESERVED
CHECKSUMMODE
Rising edge of this bit starts a termination calibration
routine.
Reserved.
JESD204B link parameter checksum calculation
method.
checksum is the sum of fields.
checksum is the sum of octets.
Reserved
This register selects either single link or dual link
mode.
Single link mode.
Dual link mode.
To select which QBD register map to work with.
User access to QBD_0 registers.
User access to QBD_1 registers.
Used to bring up JESD204B Rx digital when all link
parameters are programmed and all clocks are ready
Bit 0 applies to Link 0 while Bit 1 applies to Link 1.
Link 1 is only available in dual link mode. Both links
may be brought up separately or together.
Reserved.
0x0
R/W
0x0
0x0
R
R/W
0x0
0x0
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R
0x1
R/W
Reserved.
0
1
[5:4]
3
RESERVED
DUALLINK
0
1
2
CURRENTLINK
0
1
0x301
GENERAL_
JRX_CTRL_1
[1:0]
ENLINKS
[7:3]
RESERVED
[2:0]
SUBCLASSV_
LOCAL
JESD204B Subclass
0 Subclass 0
1 Subclass 1
Rev. B | Page 110 of 124
Data Sheet
AD9154
Addr.
0x302
Name
DYN_LINK_
LATENCY_0
Bits
[7:5]
[4:0]
Bit Name
RESERVED
DYN_LINK_
LATENCY_0
0x303
DYN_LINK_
LATENCY_1
[7:5]
[4:0]
RESERVED
DYN_LINK_
LATENCY_1
0x304
LMFC_
DELAY_0
0x305
LMFC_
DELAY_1
0x306
LMFCVAR0
[7:5]
[4:0]
[7:5]
[4:0]
[7:5]
[4:0]
RESERVED
LMFCDEL0
RESERVED
LMFCDEL1
RESERVED
LMFCVAR0
0x307
LMFCVAR1
[7:5]
[4:0]
RESERVED
LMFCVAR1
0x308
XBAR_LN_0_1
[7:6]
[5:3]
RESERVED
XBARVAL1
[2:0]
XBARVAL0
[7:6]
[5:3]
RESERVED
XBARVAL3
[2:0]
XBARVAL2
[7:6]
[5:3]
RESERVED
XBARVAL5
[2:0]
XBARVAL4
[7:6]
[5:3]
RESERVED
XBARVAL7
[2:0]
XBARVAL6
[7:0]
LANE_FIFO_FULL
0x309
0x30A
0x30B
0x30C
XBAR_LN_2_3
XBAR_LN_4_5
XBAR_LN_6_7
FIFO_
STATUS_
REG_0
Settings
Description
Reserved.
Link 0 Dynamic Link Latency.
Latency between current deframer LMFC and the
global LMFC.
Reserved.
Link 1 Dynamic Link Latency.
Latency between current deframer LMFC and the
global LMFC.
Reserved.
Delay in Frame clock cycles for global LMFC for Link 0.
Reserved.
Delay in Frame clock cycles for global LMFC for Link 1.
Reserved.
Location in Rx LMFC where JESD204B words are read
out from buffer.
This setting should not be more than 10.
Reserved.
Location in Rx LMFC where JESD204B words are read
out from buffer.
This setting should not be more than 10.
Reserved.
Logic Lane 1 Source. Selects a physical lane to be
mapped onto Logical Lane 1.
Data is from SERDINx±.
Logic Lane 0 Source. Selects a physical lane to be
mapped onto Logical Lane 0.
Data is from SERDINx±.
Reserved.
Logic Lane 3 Source. Selects a physical lane to be
mapped onto Logical Lane 3.
Data is from SERDINx±.
Logic Lane 2 Source. Selects a physical lane to be
mapped onto Logical Lane 2.
Data is from SERDINx±.
Reserved.
Logic Lane 5 Source. Selects a physical lane to be
mapped onto Logical Lane 5.
Data is from SERDINx±.
Logic Lane 4 Source. Selects a physical lane to be
mapped onto Logical Lane 4.
Data is from SERDINx±.
Reserved.
Logic Lane 7 Source. Selects a physical lane to be
mapped onto Logical Lane 7.
Data is from SERDINx±.
Logic Lane 6 Source. Selects a physical lane to be
mapped onto Logical Lane 6.
Data is from SERDINx±.
FIFO Full Flags for Each Logical Lane. A full FIFO
indicates an error in the JESD204B configuration or
with a system clock. If the FIFO for Lane x is full, Bit x
in this register will be high.
Rev. B | Page 111 of 124
Reset
0x0
0x0
Access
R
R
0x0
0x0
R
R
0x0
0x0
0x0
0x0
0x0
0x6
R
R/W
R
R/W
R
R/W
0x0
0x6
R
R/W
0x0
0x1
R
R/W
0x0
R/W
0x0
0x3
R
R/W
0x2
R/W
0x0
0x5
R
R/W
0x4
R/W
0x0
0x7
R
R/W
0x6
R/W
0x0
R
AD9154
Data Sheet
Addr.
0x30D
Name
FIFO_STATUS_
REG_1
Bits
[7:0]
Bit Name
LANE_FIFO_
EMPTY
0x312
SYNCB_
GEN_1
[7:6]
[5:4]
RESERVED
SYNCB_ERR_DUR
0x314
SPI_SYNC_
CTRL
[3:0]
[7:1]
RESERVED
RESERVED
0
SPI_SYNC_CLK_
SEL
0x315
0x316
PHY_PRBS_
TEST_EN
PHY_PRBS_
TEST_CTRL
Settings
Description
FIFO Empty Flags for Each Logical Lane. An empty
FIFO indicates an error in the JESD204B configuration
or with a system clock. If the FIFO for Lane x is empty,
Bit x in this register will be high.
Reserved.
Duration of SYNCOUTx± Low for Error. The duration
applies to both SYNCOUT0 and SYNCOUT1. A sync
error is asserted at the end of a multiframe
whenever one or more disparity, not in table or
unexpected control character errors are
encountered.
0 ½ PCLK cycle.
1 1 PCLK cycle.
2 2 PCLK cycles.
Reserved.
Reserved.
SERDES SPI Configuration.
0
1 Setting in PHY Layer setup.
Set Bit x to enable the PHY test for Lane x.
0x0
R/W
0x0
R/W
0x0
R
[6:4]
PHY_SRC_ERR_
CNT
PHY_PRBS_
PAT_SEL
Report Lane Error Count.
0x0
R/W
To select PRBS pattern for PHY BER test.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Bits[15:8] of the 24-bit threshold value to set the
error flag for PHY PRBS test.
0x0
R/W
Bits[23:16] of the 24-bit threshold value to set the
error flag for PHY PRBS test.
0x0
R/W
Bits[7:0] of the 24-bit reported PHY BERT error count
from selected lane.
0x0
R
Bits[15:8] of the 24-bit reported PHY BERT error count 0x0
from selected lane.
R
PHY_TEST_START
PHY_TEST_RESET
0
1
0x31B
R/W
R
Reserved.
0
0x31A
0x0
0x0
RESERVED
0
1
0x319
R/W
R/W
7
1
0x318
0x0
0x0
PHY_TEST_EN
0
1
2
3
PHY_PRBS_
TEST_THRESHOLD_LOBITS
PHY_PRBS_
TEST_THRESH
OLD_MIDBITS
PHY_PRBS_
TEST_THRESHOLD_HIBITS
PHY_PRBS_
TEST_ERRCNT_
LOBITS
PHY_PRBS_
TEST_ERRCNT_
MIDBITS
Access
R
[7:0]
[3:2]
0x317
Reset
0x0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
PHY_PRBS_
THRESHOLD_
LOBITS
PHY_PRBS_
THRESHOLD_
MIDBITS
PHY_PRBS_
THRESHOLD_
HIBITS
PHY_PRBS_ERR_
CNT_LOBITS
PHY_PRBS_ERR_
CNT_MIDBITS
PRBS7.
PRBS15.
PRBS31.
Not used.
To start and stop the PHY PRBS test.
test not started.
test started.
Reset PHY PRBS test state machine, and error
counters.
not reset.
reset.
Bits[7:0] of the 24-bit threshold value to set the error
flag for PHY PRBS test.
Rev. B | Page 112 of 124
Data Sheet
Addr.
0x31C
0x31D
0x32C
AD9154
Name
PHY_PRBS_
TEST_ERRCNT_
HIBITS
PHY_PRBS_
TEST_STATUS
Bits
[7:0]
Bit Name
PHY_PRBS_ERR_
CNT_HIBITS
[7:0]
PHY_PRBS_PASS
SHORT_TPL_
TEST_0
[7:6]
[5:4]
RESERVED
SHORT_TPL_SP_
SEL
Settings
0
1
2
3
[3:2]
SHORT_TPL_M_
SEL
0
1
2
3
1
SHORT_TPL_TEST
_RESET
0
1
0
SHORT_TPL_
TEST_EN
0
1
0x32D
SHORT_TPL_
TEST_1
[7:0]
SHORT_TPL_REF_
SP_LSB
0x32E
SHORT_TPL_
TEST_2
[7:0]
SHORT_TPL_REF_
SP_MSB
0x32F
SHORT_TPL_
TEST_3
[7:1]
RESERVED
0
SHORT_TPL_FAIL
0x333
[7:0]
RESERVED
[7:0]
INVLANES
0x400
DEVICE_CONFIG_REG2
JESD_BIT_
INVERSE_CTRL
DID_REG
[7:0]
DID_RD
0x401
BID_REG
[7:4]
ADJCNT_RD
[3:0]
BID_RD
0x334
Description
Bits[23:16] of the 24-bit reported PHY BERT error
count from selected lane.
Reset
0x0
Access
R
Each bit is for the corresponding lane.
Report PHY BERT pass/fail for each lane.
Reserved.
Short Transport Layer Sample Select. Select which
sample to check from a specific DAC.
Sample 0.
Sample 1.
Sample 2.
Sample 3.
Short Transport Layer Test DAC Select. Select which
DAC to check.
DAC 0.
DAC 1.
DAC 2.
DAC 3.
Short Transport Layer Test Reset. Resets the result of
short transport layer test at SHORT_TPL_DIFF.
Not reset.
Reset.
Short Transport Layer Test Enable. Enable short
transport layer test.
Disable.
Enable.
Short Transport Layer Reference Sample LSB. This is
the lower 8 bits of expected DAC sample. It is used to
compare with the received DAC sample at the output
of JESD204B Rx.
Short Transport Layer Test Reference Sample MSB.
This is the upper 8 bits of expected DAC sample. It is
used to compare with the received sample at JESD Rx
output.
Reserved.
0xFF
R
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R
0x0
R
0x0
R/W
0x0
R/W
0x0
R
0x0
R
0x0
R
Short Transport Layer Test Fail. This bit shows if the
selected DAC sample matches the reference sample.
If they match test pass; otherwise test fail.
0 Test pass.
1 Test fail.
Must be set to 0x1 for correct JESD204B receiver
operation.
Logic Lane Invert. Set Bit x high to invert the
JESD204B deserialized data on Logical Lane x.
DID is the Device ID No.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
ADJCNT is the Adjustment Resolution to DAC LMFC.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
BID is the Bank ID—Extension to DID.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Rev. B | Page 113 of 124
AD9154
Addr.
0x402
0x403
Name
LID0_REG
SCR_L_REG
Data Sheet
Bits
7
6
Bit Name
RESERVED
ADJDIR_RD
5
PHADJ_RD
[4:0]
LID0_RD
7
SCR_RD
Settings
0
1
[6:5]
[4:0]
RESERVED
L_RD
0
1
3
0x404
F_REG
[7:0]
F_RD
0
1
3
0x405
K_REG
[7:5]
[4:0]
RESERVED
K_RD
0x406
M_REG
[7:0]
M_RD
0
1
3
0x407
0x408
CS_N_REG
[7:6]
CS_RD
NP_REG
5
[4:0]
[7:5]
RESERVED
N_RD
SUBCLASSV_RD
Description
Reserved.
ADJDIR is the Direction to Adjust DAC LMFC.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
PHADJ is the Phase Adjustment Request to DAC.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
LID0 is the Lane Identification for Lane 0.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
SCR is the Tx Scrambling Status.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Scrambling is disabled.
Scrambling is enabled.
Reserved.
L is the Number of Lanes per Converter Device.
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
1 lane per converter device.
2 lanes per converter device.
4 lanes per converter device.
F is the Number of Octets Per Frame.
Settings of 1, 2, and 4 are valid.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
1 octet per frame.
2 octets per frame.
4 octets per frame.
Reserved.
K is the Number of Frames per Multiframe.
Settings of 16 or 32 are valid.
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
01111 = 16.
11111 = 32.
M is the Number of Converters/Device.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be 1,2, or 4 to be compatible with AD9154
1 converter per device.
2 converters per device.
4 converters per device.
CS is the Number of Control Bits/Sample.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be 0 to be compatible with AD9154.
Reserved.
N = converter resolution.
SUBCLASSV is the Device SubClass Version.
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
Rev. B | Page 114 of 124
Reset
0x0
0x0
Access
R
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
0x0
0x0
R
R
R
Data Sheet
AD9154
Addr.
Name
Bits
[4:0]
Bit Name
NP_RD
0x409
S_REG
[7:5]
JESDV_RD
Settings
0
1
[4:0]
S_RD
0
1
0x40A
HD_CF_REG
7
HD_RD
0
1
[6:5]
[4:0]
RESERVED
CF_RD
0x40B
RES1_REG
[7:0]
RES1_RD
0x40C
RES2_REG
[7:0]
RES2_RD
0x40D
CHECKSUM_
REG
[7:0]
LANE0CHECKSU
M_RD
0x40E
COMPSUM0_
REG
[7:0]
FCMP0_RD
0x412
LID1_REG
[7:5]
[4:0]
RESERVED
LID1_RD
0x415
CHECKSUM1_
REG
[7:0]
FCHK1_RD
0x416
COMPSUM1_
REG
LID2_REG
[7:0]
FCMP1_RD
[7:5]
[4:0]
RESERVED
LID2_RD
0x41A
Description
Np is the Total Number of Bits/Sample.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
= 16 bits per sample.
JESDV is the JESD204 Version.
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
JESD204A.
JESD204B.
S is the Number of Samples/Converter per Frame
Cycle.
Link information received on lane 0 as specified in
section 8.3 of JESD204B.
One sample per converter per frame.
Two samples per converter per frame.
HD is the High Density Format.
Refer to Section 5.1.3 of JESD204B standard.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Low density mode.
High density mode.
Reserved.
CF is the Number of Control Words per Frame Clock
Period per Link.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be 0 to be compatible to the AD9154.
Reserved Field 1.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Reserved Field 2.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Checksum for Lane 0.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Computed Checksum for Lane 0.
The JESD204B Rx computes the checksum of the link
information received on Lane 0 as specified in
Section 8.3 of JESD204B. The computation method is
set by the CHECKSUMMODE bit (Register 0x300[6])
and should match the likewise calculated checksum
in Register 0x40D.
Reserved.
Lane Identification for Lane 1.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Checksum for Lane 1.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Computed Checksum for Lane 1. See description for
Register 0x40E.
Reserved.
Lane Identification for Lane 2.
Rev. B | Page 115 of 124
Reset
0x0
Access
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R
0x0
R
0x0
R
0x0
0x0
R
R
AD9154
Addr.
0x41D
0x41E
0x422
0x425
0x426
0x42A
0x42D
0x42E
0x432
0x435
0x436
0x43A
0x43D
0x43E
0x442
0x445
Name
CHECKSUM2_
REG
COMPSUM2_
REG
LID3_REG
CHECKSUM3_
REG
COMPSUM3_
REG
LID4_REG
CHECKSUM4_
REG
COMPSUM4_
REG
LID5_REG
CHECKSUM5_
REG
COMPSUM5_
REG
LID6_REG
CHECKSUM6_
REG
COMPSUM6_
REG
LID7_REG
0x450
CHECKSUM7_
REG
COMPSUM7_
REG
ILS_DID
0x451
ILS_BID
0x446
0x452
ILS_LID0
Data Sheet
Bits
[7:0]
Bit Name
FCHK2_RD
[7:0]
FCMP2_RD
[7:5]
[4:0]
[7:0]
RESERVED
LID3_RD
FCHK3_RD
[7:0]
FCMP3_RD
[7:5]
[4:0]
[7:0]
RESERVED
LID4_RD
FCHK4_RD
[7:0]
FCMP4_RD
[7:5]
[4:0]
[7:0]
RESERVED
LID5_RD
FCHK5_RD
[7:0]
FCMP5_RD
[7:5]
[4:0]
[7:0]
RESERVED
LID6_RD
FCHK6_RD
[7:0]
FCMP6_RD
[7:5]
[4:0]
[7:0]
RESERVED
LID7_RD
FCHK7_RD
[7:0]
FCMP7_RD
[7:0]
DID
[7:4]
ADJCNT
[3:0]
BID
7
6
RESERVED
ADJDIR
5
PHADJ
[4:0]
LID0
Settings
Description
Checksum for Lane 2.
Reset
0x0
Access
R
Computed Checksum for Lane 2. See description for
Register 0x40E.
Reserved.
Lane Identification for Lane 3.
Checksum for Lane 3.
0x0
R
0x0
0x0
0x0
R
R
R
0x0
R
0x0
0x0
0x0
R
R
R
0x0
R
0x0
0x0
0x0
R
R
R
0x0
R
0x0
0x0
0x0
R
R
R
0x0
R
0x0
0x0
0x0
R
R
R
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
Computed Checksum for LANE 3 (see description for
Register 0x40E).
Reserved.
Lane Identification for Lane 4.
Checksum for Lane 4
Computed Checksum for Lane 4 (see description for
Register 0x40E).
Reserved.
Lane Identification for Lane 5.
Checksum for Lane 5.
Computed Checksum for Lane 5 (see description for
Register 0x40E).
Reserved.
Lane Identification for Lane 6.
Checksum for Lane 6.
Computed Checksum for Lane 6 (see description for
Register 0x40E).
Reserved.
Lane Identification for Lane 7.
Checksum for Lane 7.
Computed Checksum for Lane 7 (see description for
Register 0x40E).
DID is the Device ID Number.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be set to value read in Register 0x400.
ADJCNT is the Adjustment Resolution to DAC LMFC.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
BID is the Bank ID—Extension to DID.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Must be set to value read in Register 0x401[3:0].
Reserved.
ADJDIR is the Direction to Adjust DAC LMFC.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
PHADJ is the Phase Adjustment Request To DAC.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
LID0 is the Lane identification for Lane 0.
Link information received on Lane 0 as specified in
Section 8.3 of JESD204B.
Rev. B | Page 116 of 124
Data Sheet
Addr.
0x453
Name
ILS_SCR_L
AD9154
Bits
7
Bit Name
SCR
Settings
0
1
[6:5]
[4:0]
RESERVED
L
00000
00001
00011
00111
0x454
ILS_F
[7:0]
F
0x455
ILS_K
[7:5]
[4:0]
RESERVED
K
0x456
ILS_M
[7:0]
M
0
1
3
0x457
0x458
0x459
ILS_CS_N
ILS_NP
ILS_S
[7:6]
CS
5
[4:0]
RESERVED
N
[7:5]
SUBCLASSV
[4:0]
NP
[7:5]
JESDVER
0
1
0x45A
ILS_HD_CF
[4:0]
S
7
HD
0
1
[6:5]
[4:0]
RESERVED
CF
Description
SCR is the Rx Descrambling Enable.
Is disabled.
Is enabled.
Reserved.
L is the Number of Lanes Per Converter Device
Settings of 2, 4, and 8 are valid for single single link
mode. Settings of 1, 2, and 4 are valid for dual link
mode.
1 lane.
2 lanes.
4 lanes.
8 lanes.
This value of F is not used to soft configure the QBD.
The Register CTRLREG1 is used to soft configure the
QBD.
Reserved.
K is the number of frames per multiframe.
Settings of 16 or 32 are valid. Must be set to 32 when
F = 4 (Register 0x476).
01111 = 16.
11111 = 32.
M is the number of converters/device.
Settings of 1, 2, and 4 are valid for single link mode.
Settings of 1 and 2 are valid in dual link mode. Refer
to Table 15 and Table 16.
1 converter per device.
2 converters per device.
4 converters per device.
CS is the number of control bits/sample.
Must be set to 0. Control bits are not supported.
Reserved.
N = converter resolution.
Must be set to 16 (0x0F).
SUBCLASSV = device Subclass version.
Must be set to 1 (3'b001).
Np = total no. of bits/sample.
Must be set to 16 (0x0F). Refer to Table 15 and
Table 16.
JESDV is the JESD204 version.
JESD204A.
JESD204B .
S = no. of samples/converter per frame cycle.
Settings of 1 and 2 are valid. Refer to Table 15 and
Table 16.
S = 00000 -> 1 Sample.
S = 00001 -> 2 Samples.
HD is high density mode.
Refer to section 5.1.3 of JESD204B standard.
density mode.
density mode.
Reserved.
CF is the number of control words per frame clock
period per link.
Must be set to 0. Control bits are not supported.
Rev. B | Page 117 of 124
Reset
0x1
Access
R/W
0x0
0x3
R
R/W
0x0
R/W
0x0
0x1F
R
R/W
0x1
R
0x0
R/W
0x0
0x1F
R
R/W
0x1
R/W
0xF
R/W
0x1
R/W
0x0
R/W
0x1
R/W
0x0
0x0
R
R/W
AD9154
Data Sheet
Addr.
0x45D
Name
ILS_CHECKSUM
Bits
[7:0]
Bit Name
LANE0CHECKSUM
0x46B
ERRCNTRMON
7
[6:4]
RESERVED
LANESEL
Settings
0
1
3
3
4
5
6
7
[3:2]
[7:0]
RESERVED
READERRORCNTR
[1:0]
CNTRSEL
0
1
2
0x46C
LANEDESKEW
[7:0]
LANEDESKEW
Description
Checksum for Lane 0.
The checksum for the values programmed into
Register 0x450 to Register 0x45C must be calculated
according to section 8.3 of the JESD204B spec and
written here [SUM(Register 0x450 – Register 0x45C)
% 256 ].
Reserved.
Lane Select for JESD204B Error Counter.
Writing these bits selects the JESD lane to monitor
the error type designated by the register write to
CNTRSEL (Bits 1:0]) BADDISCNTR, NITCNTR and
UEKCCNTR error counters in each lane are accessed
via indirect addressing. To read a counter value, the
LANESEL and CNTRSEL are first written, then the read
back accesses the desired counter.
Selects Lane 0.
Selects Lane 1.
Selects Lane 2.
Selects Lane 3.
Selects Lane 4.
Selects Lane 5.
Selects Lane 6.
Selects Lane 7.
Reserved.
Read JESD204B Error Counter.
After selecting the lane and error counter by writing
to LANESEL (Bits[6:4]) and CNTRSEL (1:0), the selected
error counter is read back here.
JESD204B Error Counter Select.
Writing these bits allows the readback of the following
JESD204B errors for the lane designated by the register
write to LANESEL (Bits[6:4]). To read a counter value, the
LANESEL and CNTRSEL are first written, then the read
back access the desired counter.
BADDISCNTR: bad running disparity counter.
NITCNTR: not in table error counter.
UCCCNTR: Unexpected control character counter.
Lane Deskew.
Enabled on a per lane basis by writing 1 to the
appropriate bit position: Bits[7:0] map to Lane 7 to
Lane 0. Note that in dual link mode, only Bits[3:0] are
used for each link.
1: Deskew enabled for Lane 0.
1: Deskew enabled for Lane 1.
1: Deskew enabled for Lane 2.
1: Deskew enabled for Lane 3.
1: Deskew enabled for Lane 4.
1: Deskew enabled for Lane 5.
1: Deskew enabled for Lane 6.
1: Deskew enabled for Lane 7.
Rev. B | Page 118 of 124
Reset
0x45
Access
R/W
0x0
0x0
R
W
0x0
0x0
R
R
0x0
W
0xF
R/W
Data Sheet
Addr.
0x46D
0x46E
0x46F
Name
BADDISPARITY
NITDISPARITY
UNEXPECTEDK
CHAR
AD9154
Bits
7
Bit Name
RSTIRQ_DIS
6
5
DISABLE_ERRCNT
_DIS
RSTERRCNTR_DIS
[4:3]
[7:0]
RESERVED
BADDIS
[2:0]
7
LANEADDR_DIS
RSTIRQ_NIT
6
5
DISABLE_
ERRCNT_NIT
RSTERRCNTR_NIT
[4:3]
[7:0]
RESERVED
NITD
[2:0]
7
LANEADDR_NIT
RSTIRQ_K
6
5
DISABLE_ERRCNT
_K
RSTERRCNTR_K
[4:3]
[2:0]
[7:0]
RESERVED
LANEADDR_K
CODEGRPSYNC
0x470
CODEGRPSYNCFLG
0x471
FRAMESYNCFLG
[7:0]
FRAMESYNC
0x472
GOODCHKSUMFLG
[7:0]
GOODCHECKSUM
Settings
Description
Reset BADDIS IRQ counter for lane selected via
Bits[2:0] by writing 1 to this bit.
Disable the BADDIS error counter for lane selected
via Bits[2:0] by writing 1 to this bit.
Reset BADDIS error counter for lane selected via
Bits[2:0] by writing 1 to this bit.
Reserved.
Bad Disparity Character Error (BADDIS).
Each bit corresponds to each lane. The error count
can be accessed via Register 0x46B. Note that in dual
link mode, only Bits[3:0] are used for each link.
1 BadDisparitycharacter error count has reached the
threshold count of Register 0x7C for any lane with its
corresponding bit set when reading this register.
0 Bad Disparity character error count has Not reached
the threshold count.
Lane Address for functions described in Bits[7:5]
Reset IRQ for lane selected via Bits[2:0] by writing 1
to this bit.
Disable the error counter for lane selected via
Bits[2:0] by writing 1 to this bit.
Reset error counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reserved.
Not In Table Disparity Character Error (NITD).
Each bit corresponds to each lane. The error count
can be accessed via Register 0x46B. Note that in dual
link mode, only Bits[3:0] are used for each link.
Lane Address for functions described in Bits[7:5].
Reset IRQ for lane selected via Bits[2:0] by writing 1
to this bit.
Disable the error counter for lane selected via
Bits[2:0] by writing 1 to this bit.
Reset error counter for lane selected via Bits[2:0] by
writing 1 to this bit.
Reserved.
Lane Address for functions described in Bits[7:5].
Code Group Sync Flag (from each instantiated lane)
Writing 1 to Bit 7 resets the IRQ. The associated IRQ
flag is located in Register 0x470[0].
A loss of CODEGRPSYNC triggers Sync Request
assertion. Refer to the SYSREF, SYNCOUT, and the
Deterministic Latency section.
1 on Bit x of this register = synchronization was
achieved on lane L.
0 on Bit x of this register = synchronization was lost
on Lane x.
Frame Sync Flag (from each instantiated lane).
This register indicates the live status for each lane.
Writing 1 to Bit 7 resets the IRQ.
A loss of Frame Sync automatically initiates a
synchronization sequence.
Good Check Sum flag (from each instantiated lane.)
Writing 1 to Bit 7 resets the IRQ. The associated IRQ
flag is located in Register 0x470[2].
Rev. B | Page 119 of 124
Reset
0x0
Access
W
0x0
W
0x0
W
0x0
0x0
R
R
0x0
0x0
W
W
0x0
W
0x0
W
0x0
0x0
R
R
0x0
0x0
W
W
0x0
W
0x0
W
0x0
0x0
0x0
R
W
R/W
0x0
R/W
0x0
R/W
AD9154
Data Sheet
Addr.
0x473
Name
INITLANESYNCFLG
Bits
[7:0]
Bit Name
Settings
INITIALLANESYNC
0x476
CTRLREG1
[7:0]
F_AGAIN
0x477
CTRLREG2
7
ILAS_MODE
[6:4]
3
RESERVED
RESERVED
KSYNC
THRESHOLD_
MASK_EN
Description
Initial Lane Sync Flag (from each instantiated lane).
Writing 1 to Bit 7 resets the IRQ. The associated IRQ
flag is located in Register 0x470[2].
Loss of synchronization is also reported on SYNCOUT.
Refer to the SYSREF, SYNCOUT, and the Deterministic
Latency section.
F is the number of octets per frame.
Settings of 1, 2, and 4 are valid. Refer to Table 15 and
Table 16.
ILAS Test Mode.
Defined in Section 5.3.3.8 of JESD204B specification.
1 JESD204B receiver is constantly receiving ILAS frames.
0 Normal link operation.
Reserved.
Threshold Mask Enable. Set this bit if using
SYNC_ASSERTION_MASK (Register 0x47B[7:5]).
Reserved.
Number of 4 × K multiframes during ILAS.
Sets the number of multiframes to send lane alignment
sequence during the initial lane alignment.
1 = 4 × K multiframes.
Bad Disparity Error Count.
1 Bad disparity character count reached ERRORTHRESH
(Register 0x47C) on at least one lane. Read Register
0x46D to determine which lanes are in error.
Bad Disparity Mask.
1 If the bad disparity count reaches ERRORTHRESH on
any lane, IRQ is pulled low.
Reset
0x0
Access
R/W
0x1
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
0x1
R
R/W
0x0
R
0x0
W
0x478
KVAL
[2:0]
[7:0]
0x47A
IRQVECTOR
7
BADDIS_FLAG
7
BADDIS_MASK
6
NITD_MASK
Not in Table Mask.
1 If the not in table character count reaches
ERRORTHRESH on any lane, IRQ is pulled low.
0x0
W
6
NITD_FLAG
0x0
R
5
UEKC_FLAG
0x0
R
5
UEKC_MASK
Not in Table Error Count.
1 Not in table character count reached ERRORTHRESH
(Register 0x47C) on at least one lane. Read Register
0x46E to determine which lanes are in error.
Unexpected Control Character Error Count.
1 Unexpected control character count reached
ERRORTHRESH (0x47C) on at least one lane. Read
Register 0x46F to determine which lanes are in error.
Unexpected Control Character Mask.
1 If the unexpected control character count reaches
ERRORTHRESH on any lane, IRQ is pulled low.
0x0
W
4
3
RESERVED
INITIALLANESYNC
_FLAG
0x0
0x0
R
R
0x0
W
3
INITIALLANESYNC
_MASK
Reserved.
Unexpected Control Character Error Count.
1 Unexpected control character count reached
ERRORTHRESH (Register 0x47C) on at least one lane.
Read Register 0x46F to determine which lanes are in
error.
Initial Lane Sync Mask.
1
If initial lane sync (Register 0x473) fails on any
lane, IRQ is pulled low.
Rev. B | Page 120 of 124
Data Sheet
Addr.
Name
AD9154
Bits
2
Bit Name
BADCHECKSUM_
MASK
Settings
Description
Bad Checksum Mask.
Reset
0x0
Access
W
0x0
R
0x0
0x0
R
R
0x0
W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
0xFF
R
R/W
0xF
R/W
0x0
R
1 If there is a bad checksum (Register 0x472) on any
lane, IRQ is pulled low.
2
0x47B
SYNCASSERTIONMASK
BADCHECKSUM_
FLAG
1
0
RESERVED
CODEGRPSYNC_
FLAG
0
CODEGRPSYNC_
MASK
7
BADDIS_S
6
NIT_S
5
UCC_S
4
CMM
3
CMM_ENABLE
0x47C
ERRORTHRES
[2:0]
[7:0]
RESERVED
ETH
0x47D
LANEENABLE
[7:0]
LANE_ENA
0x47E
RAMP_ENA
[7:1]
RESERVED
Bad Checksum Flag.
1 Bad checksum on at least one lane. Read Register 0x472
to determine which lanes are in error.
Reserved.
1 Code Group Sync Flag. Code group sync failed on at
least one lane. Read Register 0x470 to determine
which lanes are in error.
Code group sync failed on at least one lane. Read
Register 0x470 to determine which lanes are in error.
1 Code Group Sync Machine Mask. If code group sync
(Register 0x470) fails on any lane, IRQ is pulled low.
Bad Disparity Error on Sync.
1 Asserts a sync request on SYNCOUTx± when the bad
disparity character count reaches the threshold in
Register 0x47C.
Not in table Error on Sync.
1 Asserts a sync request on SYNCOUTx± when the not
in table character count reaches the threshold in
Register 0x47C.
Unexpected Control Character Error on Sync.
1 Asserts a sync request on SYNCOUTx± when the
unexpected control character count reaches the
threshold in Register 0x47C.
Configuration Mismatch IRQ. If CMM_ENABLE is high,
this bit latches on a rising edge and pull IRQ low.
When latched, write a 1 to clear this bit. If
CMM_ENABLE is low, this bit is non-functional.
1 Link Lane 0 configuration registers (Register 0x450 to
Register 0x45D) do not match the JESD204B transmit
settings (Register 0x400 to Register 0x40D).
Configuration Mismatch IRQ. If CMM_ENABLE is high,
this bit latches on a rising edge and pull IRQ low.
When latched, write a 1 to clear this bit. If
CMM_ENABLE is low, this bit is non-functional.
Configuration Mismatch IRQ Enable.
1 Enables IRQ generation if a configuration mismatch
is detected.
0 Configuration mismatch IRQ disabled.
Mismatch IRQ disabled.
Reserved.
Error Threshold. Bad disparity, not in table, and
unexpected control character errors are counted and
compared to the error threshold value. When the
count reaches the threshold, either an IRQ is
generated or the SYNCOUTx± signal is asserted per
the mask register settings, or both. Function is
performed in all lanes.
Lane Enable. Setting Bit x enables Link Lane x.
This register must be programmed before receiving
the code group pattern for proper operation.
Reserved.
Rev. B | Page 121 of 124
AD9154
Addr.
Name
0x520
DIG_TEST0
0x521
TEST_DC_
VALUEI0
TEST_DC_
VALUEI1
TEST_DC_
VALUEQ0
TEST_DC_
VALUEQ1
0x522
0x523
0x524
Data Sheet
Bits
0
[7:2]
1
0
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
ENA_RAMP_
CHECK
RESERVED
DC_TEST_MOD
RESERVED
TEST_DC_
VALUEI0
TEST_DC_
VALUEI1
TEST_DC_
VALUEQ0
TEST_DC_
VALUEQ1
Settings
Description
Enable Ramp Checking at the Beginning of ILAS.
Reset
0x0
Access
R/W
0x0
0x0
0x0
0x0
R
R/W
R/W
R/W
DC value MSB of fS /8 and decoder testing for I DAC.
0x0
R/W
DC value LSB of fS /8 and decoder testing for Q DAC.
0x0
R/W
DC value MSB of fS /8 and decoder testing for Q DAC.
0x0
R/W
0 Disable ramp checking at beginning of ILAS; ILAS
data need not be a ramp.
1 Enable ramp checking; ILAS data needs to be a ramp
starting at 00-01-02; otherwise, the ramp ILAS fails
and the device does not start up.
Reserved.
DC Test Mode Enable.
Reserved.
DC value LSB of fS/8 and decoder testing for I DAC.
Rev. B | Page 122 of 124
Data Sheet
AD9154
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
0.28
0.23
0.18
0.60 MAX
0.60
MAX
88
67
66
PIN 1
INDICATOR
1
PIN 1
INDICATOR
11.85
11.75 SQ
11.65
0.50
BSC
0.50
0.40
0.30
22
23
45
44
TOP VIEW
BOTTOM VIEW
10.50
REF
0.70
0.65
0.60
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.045
0.025
0.005
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
08-10-2012-A
12° MAX
0.90
0.85
0.80
7.55
7.40 SQ
7.25
EXPOSED PAD
COMPLIANT TO JEDEC STANDARDS MO-220-VRRD
Figure 89. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12 mm × 12 mm Body, Very Thin Quad
(CP-88-6)
Dimensions shown in millimeters
12.10
12.00 SQ
11.90
0.30
0.25
0.20
0.60 MAX
0.60
MAX
67
88
66
1
PIN 1
INDICATOR
PIN 1
INDICATOR
0.50
BSC
7.55
7.40 SQ
5.25
EXPOSED
PAD
0.65
0.55
0.45
22
44
TOP VIEW
0.90
0.85
0.80
PKG-004598
SEATING
PLANE
12° MAX
0.190~0.245 REF
0.70
0.65
0.60
0.50
0.40
0.30
45
23
BOTTOM VIEW
10.50
REF
0.045
0.025
0.005
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220
Figure 90. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12 mm × 12 mm Body, Very Thin Quad
(CP-88-9)
Dimensions shown in millimeters
Rev. B | Page 123 of 124
1.00
0.90
0.80
0.80
0.70
0.60
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-04-2014-A
11.85
11.75 SQ
11.65
AD9154
Data Sheet
ORDERING GUIDE
Model1
AD9154BCPZ
AD9154BCPZRL
AD9154BCPAZ
AD9154BCPAZRL
AD9154-EBZ
AD9154-FMC-EBZ
AD9154-M6720-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ
88-Lead LFCSP_VQ (Variable Lead Length)
88-Lead LFCSP_VQ (Variable Lead Length)
DPG3 Evaluation Board
FMC Evaluation Board
DPG3 Evaluation Board with ADRF6720-27 Modulator
Z = RoHs Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11389-0-7/15(B)
Rev. B | Page 124 of 124
Package Option
CP-88-6
CP-88-6
CP-88-9
CP-88-9