TI MSP430F2131IPW Mixed signal microcontroller Datasheet

 SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
D Low Supply Voltage Range 1.8 V to 3.6 V
D Ultralow-Power Consumption
D
D
D
D
D
D
D Serial Onboard Programming,
− Active Mode: 250 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
Ultrafast Wake-Up From Standby Mode in
less than 1 µs
16-Bit RISC Architecture, 62.5 ns
Instruction Cycle Time
Basic Clock Module Configurations:
− Internal Frequencies up to 16MHz with
4 calibrated Frequencies to ±1%
− 32-kHz Crystal
− High-Frequency Crystal up to 16MHz
− Resonator
− External Digital Clock Source
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
Brownout Detector
D
D
D
D
D
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
Bootstrap Loader
On Chip Emulation Module
Family Members Include:
MSP430F2101: 1KB + 256B Flash Memory
128B RAM
MSP430F2111: 2KB + 256B Flash Memory
128B RAM
MSP430F2121: 4KB + 256B Flash Memory
256B RAM
MSP430F2131: 8KB + 256B Flash Memory
256B RAM
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin Plastic
Small-Outline Thin (TSSOP) Package,
20-Pin TVSOP and 24-Pin QFN
For Complete Module Descriptions, Refer
to the MSP430x2xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1µs.
The MSP430x21x1 series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile
analog comparator and sixteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application. The analog comparator provides slope A/D conversion capability.
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
20-PIN SOWB
(DW)
PLASTIC
20-PIN TSSOP
(PW)
PLASTIC
20-PIN TVSOP
(DGV)
PLASTIC
24-PIN QFN
(RGE)
−40°C to 85°C
MSP430F2101IDW
MSP430F2111IDW
MSP430F2121IDW
MSP430F2131IDW
MSP430F2101IPW
MSP430F2111IPW
MSP430F2121IPW
MSP430F2131IPW
MSP430F2101IDGV
MSP430F2111IDGV
MSP430F2121IDGV
MSP430F2131IDGV
MSP430F2101IRGE
MSP430F2111IRGE
MSP430F2121IRGE
MSP430F2131IRGE
−40°C to 105°C
MSP430F2101TDW
MSP430F2111TDW
MSP430F2121TDW
MSP430F2131TDW
MSP430F2101TPW
MSP430F2111TPW
MSP430F2121TPW
MSP430F2131TPW
MSP430F2101TDGV
MSP430F2111TDGV
MSP430F2121TDGV
MSP430F2131TDGV
MSP430F2101TRGE
MSP430F2111TRGE
MSP430F2121TRGE
MSP430F2131TRGE
TA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2004 − 2006 Texas Instruments Incorporated
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device pinout
19
P1.6/TA1/TDI/TCLK
3
18
P1.5/TA0/TMS
VSS
XOUT/P2.7/CA7
4
17
5
16
P1.4/SMCLK/TCK
P1.3/TA2
XIN/P2.6/CA6
6
15
P1.2/TA1
RST/NMI
P2.0/ACLK/CA2
P2.1/INCLK/CA3
7
14
8
13
9
12
P1.1/TA0
P1.0/TACLK
P2.4/TA2/CA1
10
11
P2.3/TA1/CA0
24 23 22 21 20 19
1
VSS 2
XOUT/P2.7/CA7 3
XIN/P2.6/CA6 4
18 P1.5/TA0/TMS
17 P1.4/SMCLK/TCK
16 P1.3/TA2
15 P1.2/TA1
14 P1.1/TA0
13 P1.0/TACLK
5
6
NC
9 10 11 12
P2.4/TA2/CA1
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
7 8
P2.3/TA1/CA0
RST/NMI
P2.0/ACLK/CA2
NC
P2.2/CAOUT/TA0/CA4
NC
NC
2
VCC
P2.5/CA5
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
P1.7/TA2/TDO/TDI
20
P2.5/CA5
1
TEST
VCC
TEST
RGE PACKAGE
(TOP VIEW)
DW, PW, or DGV PACKAGE
(TOP VIEW)
Note: NC pins not internally connected
Power Pad connection to VSS recommended
functional block diagram
VCC
P1.x & JTAG
VSS
8
XOUT
XIN
Basic Clock
System+
ACLK
Flash
8kB
4kB
2kB
1kB
SMCLK
MCLK
16MHz
CPU
incl. 16
Registers
RAM
256B
256B
128B
128B
Comparator
_A+
8 Channel
Input Mux
Port P1
Port P2
8 I/O
Interrupt
capability,
pull−up/down
resistors
8 I/O
Interrupt
capability,
pull−up/down
resistors
MAB
MDB
Emulation
(2BP)
JTAG
Interface
Watchdog
WDT+
Brownout
Protection
15/16−Bit
Timer_A3
3 CC
Registers
RST/NMI
NOTE: See port schematics section for detailed I/O information.
2
P2.x &
XIN/XOUT
8
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Terminal Functions
TERMINAL
DW, PW, or DGV
RGE
NO.
NO.
P1.0/TACLK
13
13
I/O
General-purpose digital I/O pin
Timer_A, clock signal TACLK input
P1.1/TA0
14
14
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output/BSL transmit
P1.2/TA1
15
15
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
16
16
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK/TCK
17
17
I/O
General-purpose digital I/O pin / SMCLK signal output
Test Clock input for device programming and test
P1.5/TA0/TMS
18
18
I/O
General-purpose digital I/O pin / Timer_A, compare: Out0 output
Test Mode Select input for device programming and test
P1.6/TA1/TDI/TCLK
19
20
I/O
General-purpose digital I/O pin / Timer_A, compare: Out1 output
Test Data Input or Test Clock Input for programming and test
P1.7/TA2/TDO/TDI†
20
21
I/O
General-purpose digital I/O pin / Timer_A, compare: Out2 output
Test Data Output or Test Data Input for programming and test
P2.0/ACLK/CA2
8
6
I/O
General-purpose digital I/O pin / ACLK output
Comparator_A+, CA2 input
P2.1/INCLK/CA3
9
7
I/O
General-purpose digital I/O pin / Timer_A, clock signal at INCLK
Comparator_A+, CA3 input
P2.2/CAOUT/
TA0/CA4
10
8
I/O
General-purpose digital I/O pin
Timer_A, capture: CCI0B input/BSL receive
Comparator_A+, output / CA4 input
P2.3/CA0/TA1
11
10
I/O
General-purpose digital I/O pin / Timer_A, compare: Out1 output
Comparator_A+, CA0 input
P2.4/CA1/TA2
12
11
I/O
General-purpose digital I/O pin / Timer_A, compare: Out2 output
Comparator_A+, CA1 input
P2.5/CA5
3
24
I/O
General-purpose digital I/O pin
Comparator_A+, CA5 input
XIN/P2.6/CA6
6
4
I/O
Input terminal of crystal oscillator
General-purpose digital I/O pin
Comparator_A+, CA6 input
XOUT/P2.7/CA7
5
3
I/O
Output terminal of crystal oscillator
general-purpose digital I/O pin
Comparator_A+, CA7 input
RST/NMI
7
5
I
Reset or nonmaskable interrupt input
TEST
1
22
I
Selects test mode for JTAG pins on Port1. The device protection fuse
is connected to TEST.
VCC
VSS
2
23
4
2
NAME
QFN Pad
NA
Package Pad
† TDO or TDI is selected via JTAG instruction.
DESCRIPTION
I/O
Supply voltage
Ground reference
NA
QFN package pad connection to VSS recommended.
NOTE: If XOUT/P2.7/CA7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver
connection to this pad after reset.
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short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
M(EDE) −−> M(TONI)
Absolute
F F
MOV &MEM,&TCDAT
M(MEM) −−> M(TCDAT)
EXAMPLE
OPERATION
R10
−−> R11
M(2+R5)−−> M(6+R6)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) −−> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) −−> R11
R10 + 2−−> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE: S = source
4
SYNTAX
D = destination
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#45
−−> M(TONI)
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operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g. flash is not programmed) the CPU will
go into LPM4 immediately after power−up.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
Flash key violation
PC out-of-range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0FFFEh
31, highest
NMI
Oscillator fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 4)
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
30
0FFFAh
29
0FFF8h
28
Comparator_A+
CAIFG
maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
maskable
0FFF4h
26
Timer_A2
TACCR0 CCIFG (see Note 3)
maskable
0FFF2h
25
Timer_A2
TACCR1 CCIFG,
TAIFG (see Notes 2 & 3)
maskable
0FFF0h
24
0FFEEh
23
0FFECh
22
0FFEAh
21
0FFE8h
20
I/O Port P2
(eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 & 3)
maskable
0FFE6h
19
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 2 & 3)
maskable
0FFE4h
18
0FFE2h
17
0FFE0h
16
(see Note 5)
0FFDEh
15
(see Note 6)
0FFDCh ... 0FFC0h
14 ... 0, lowest
NOTES: 1.
2.
3.
4.
5.
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).
Multiple source flags
Interrupt flags are located in the module
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
This location is used as bootstrap loader security key (BSLSKEY).
A value of 0AA55h at this location disables the BSL completely.
A value of 0h disables the erasure of the flash if an invalid password is supplied.
6. The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
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special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
Address
7
6
0h
5
4
ACCVIE
NMIIE
rw-0
WDTIE:
OFIE:
NMIIE:
ACCVIE:
Address
3
2
1
OFIE
rw-0
0
WDTIE
rw-0
rw-0
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
Oscillator fault enable
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
6
5
4
3
2
1
0
01h
interrupt flag register 1 and 2
Address
7
02h
4
3
2
1
NMIIFG
RSTIFG
PORIFG
OFIFG
rw-0
WDTIFG:
OFIFG:
RSTIFG:
PORIFG:
NMIIFG:
Address
rw-(0)
rw-1
rw-(1)
0
WDTIFG
rw-(0)
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC
power−up
Power−On Reset interrupt flag. Set on VCC power−up.
Set via RST/NMI-pin
7
6
5
4
3
2
1
0
03h
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
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memory organization
MSP430F2101
MSP430F2111
MSP430F2121
MSP430F2131
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
1KB Flash
0FFFFh−0FFE0h
0FFFFh−0FC00h
2KB Flash
0FFFFh−0FFE0h
0FFFFh−0F800h
4KB Flash
0FFFFh−0FFE0h
0FFFFh−0F000h
8KB Flash
0FFFFh−0FFE0h
0FFFFh−0E000h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
128 Byte
027Fh − 0200h
128 Byte
027Fh − 0200h
256 Byte
02FFh − 0200h
256 Byte
02FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader
security key is provided at address 0FFDEh to disable the BSL completely or to disable the erasure of the flash
if an invalid password is supplied. For complete description of the features of the BSL and its implementation,
see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSLKEY
Description
00000h
Erasure of flash disabled if an invalid password is supplied
0AA55h
BSL disabled
any other value
BSL enabled
BSL Function
DW, PW & DGV Package Pins
RGE Package Pins
Data Transmit
14 - P1.1
14 - P1.1
Data Receive
10 - P2.2
8 - P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0−n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming or erasing.
It can be unlocked but care should be taken not to erase this segment if the calibration data is required.
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peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the
following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
D Main clock (MCLK), the system clock used by the CPU.
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency
Calibration Register
Size
1 MHz
CALBC1_1MHZ
byte
010FFh
CALDCO_1MHZ
byte
010FEh
8 MHz
12 MHz
16 MHz
Address
CALBC1_8MHZ
byte
010FDh
CALDCO_8MHZ
byte
010FCh
CALBC1_12MHZ
byte
010FBh
CALDCO_12MHZ
byte
010FAh
CALBC1_16MHZ
byte
010F9h
CALDCO_16MHZ
byte
010F8h
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull−up/pull−down resistor.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
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comparator_A+
The primary function of the Comparator_A+ module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
Device
Input Signal
DW, PW, DGV
RGE
13 - P1.0
13 - P1.0
Module
Block
Module
Output Signal
Output
Pin Number
DW, PW, DGV
RGE
TACLK
ACLK
ACLK
SMCLK
SMCLK
Timer
NA
9 - P2.1
7 - P2.1
INCLK
INCLK
14 - P1.1
14 - P1.1
TA0
CCI0A
14 - P1.1
14 - P1.1
10 - P2.2
8 - P2.2
TA0
CCI0B
18 - P1.5
18 - P1.5
15 - P1.2
16 - P1.3
10
TACLK
Module
Input Name
15 - P1.2
16 - P1.3
GND
CCR0
TA0
VSS
VCC
TA1
VCC
CCI1A
11 - P2.3
10 - P2.3
CAOUT (internal)
CCI1B
15 - P1.2
15 - P1.2
VSS
VCC
GND
19 - P1.6
20 - P1.6
CCR1
TA1
TA2
VCC
CCI2A
12 - P2.4
11 - P2.4
ACLK (internal)
CCI2B
16 - P1.3
16 - P1.3
VSS
VCC
GND
20 - P1.7
21 - P1.7
CCR2
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TA2
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
0176h
0174h
0172h
0170h
0166h
0164h
0162h
0160h
012Eh
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog TImer+
Watchdog/timer control
WDTCTL
0120h
Comparator_A+
Comparator_A+ port disable
Comparator_A+ control 2
Comparator_A+ control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
053h
058h
057h
056h
Port P2
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
02Fh
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
027h
026h
025h
024h
023h
022h
021h
020h
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
003h
002h
001h
000h
PERIPHERALS WITH BYTE ACCESS
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11
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
Storage temperature, Tstg (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TEST pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J−STD−020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
MIN
Supply voltage during program execution, VCC
1.8
Supply voltage during program/erase flash memory, VCC
2.2
Supply voltage, VSS
NOM
MAX
V
3.6
V
0
Operating free-air temperature range, TA
Processor frequency fSYSTEM
(Maximum MCLK frequency)
(see Notes 1, 2 and Figure 1)
UNIT
3.6
V
I Version
−40
85
°C
T Version
°C
−40
105
VCC = 1.8 V, Duty Cycle = 50% ±10%
0
6
VCC = 2.7 V, Duty Cycle = 50% ±10%
(see Note 3)
0
12
VCC = 3.3 V, Duty Cycle = 50% ±10%
(see Note 4)
0
16
MHz
NOTES: 1. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
2. Modules might have a different maximum input clock specification. Refer to the specification of the respective module in this
datasheet.
3. This includes using the provided DCO calibration value for 12 MHz for VCC = 2.7 V to 3.6 V over the operating temperature range.
4. This includes using the provided DCO calibration value for 16 MHz for VCC = 3.3 V to 3.6 V over the operating temperature range.
System Frequency −MHz
16 MHz
12 MHz
6 MHz
1.8 V
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
ÏÏÏÏÏÏÏÏÏ
2.2 V
2.7 V
3.3 V
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
ÏÏ
Legend:
Supply voltage range,
during flash memory
programming
Supply voltage range,
during program execution
3.6 V
Supply Voltage −V
NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Operating Area
12
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM,1MHz
IAM,1MHz
IAM,4kHz
IAM,100kHz
Active mode (AM)
current (1MHz)
Active mode (AM)
current (1MHz)
Active mode (AM)
current (4kHz)
Active mode (AM)
current (100kHz)
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes in flash,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
2.2 V
MIN
TYP
MAX
250
300
UNIT
µA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
fMCLK = fSMCLK =
fACLK = 32,768Hz/8 = 4,096Hz,
fDCO = 0Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
VCC
3V
350
2.2 V
200
410
µA
3V
-40−85°C
2.2 V
105°C
2.2 V
-40−85°C
3V
105°C
3V
300
2
5
6
µA
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100kHz,
fACLK = 0Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
2.2 V
3
9
9
60
85
µA
3V
72
95
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V−T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
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13
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
typical characteristics − active mode supply current (into VCC)
7.0
5.0
fDCO = 12 MHz
4.0
fDCO = 8 MHz
3.0
2.0
Active Mode Current − mA
Active Mode Current − mA
5.0
fDCO = 16 MHz
6.0
4.0
TA = 25 °C
3.0
VCC = 3 V
2.0
TA = 25 °C
VCC = 2.2 V
fDCO = 1 MHz
2.0
2.5
3.0
3.5
4.0
0.0
0.0
VCC − Supply Voltage − V
Figure 2. Active mode current vs VCC, TA = 25°C
14
TA = 85 °C
1.0
1.0
0.0
1.5
TA = 85 °C
POST OFFICE BOX 655303
4.0
8.0
12.0
16.0
fDCO − DCO Frequency − MHz
Figure 3. Active mode current vs DCO frequency
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
ILPM0,1MHz
Low-power mode
0 (LPM0) current,
see Note 3
Low-power mode
ILPM0,100kHz 0 (LPM0) current,
see Note 3
ILPM2
Low-power mode
2 (LPM2) current,
see Note 4
TEST CONDITIONS
TA
fMCLK = 0MHz,
fSMCLK = fDCO = 1MHz,
fACLK = 32,768Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
2.2 V
Low-power mode
4 (LPM4) current,
see Note 5
fDCO = fMCLK = fSMCLK = 0MHz,
fACLK = 0Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
65
80
85
100
2.2 V
37
48
3V
-40−85°C
UNIT
41
52
22
29
2.2 V
105°C
31
-40−85°C
25
32
0.7
1.2
0.7
1.0
1.6
2.3
105°C
3
6
-40°C
0.9
1.2
25°C
0.9
1.2
1.6
2.8
µA
3V
105°C
85°C
85°C
ILPM4
MAX
µA
25°C
fDCO = fMCLK = fSMCLK = 0MHz,
fACLK = 32,768Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
TYP
3V
34
-40°C
Low-power mode
3 (LPM3) current,
ILPM3,LFXT1
see Note 4
MIN
µA
fMCLK = 0MHz,
fSMCLK = fDCO(0, 0) ≈ 100kHz,
fACLK = 0Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1, SCG0 = 0, SCG1 = 0,
OSCOFF = 1
fMCLK = fSMCLK = 0MHz, fDCO = 1MHz,
fACLK = 32,768Hz,
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1, SCG0 = 0, SCG1 = 1,
OSCOFF = 0
VCC
2.2 V
3V
105°C
3
7
-40°C
0.1
0.5
0.1
0.5
0.8
1.9
2
4
25°C
85°C
2.2 V/3 V
105°C
µA
µA
µA
A
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V−T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
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15
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2
PARAMETER
VIT+
VIT−
TEST CONDITIONS
Positive-going input threshold
voltage
Negative-going input threshold
voltage
Vhys
Input voltage hysteresis (VIT+ −
VIT−)
RPull
Pull−up/pull−down resistor
For pull−up: VIN = VSS;
For pull−down: VIN = VCC
CI
Input Capacitance
VIN = VSS or VCC
VCC
MIN
MAX
UNIT
0.45
0.75
VCC
2.2 V
1.00
1.65
3V
1.35
2.25
0.25
0.55
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1.0
3V
0.3
1.0
20
TYP
35
50
5
V
VCC
V
V
kW
pF
inputs − Ports P1 and P2
PARAMETER
t(int)
External interrupt timing
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External
trigger puls width to set interrupt
flag, (see Note 1)
VCC
2.2 V/3 V
MIN
TYP
MAX
20
UNIT
ns
NOTES: 1. An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
leakage current − Ports P1 and P2
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Ilkg(Px.x)
High-impedance leakage current
see Notes 1 and 2
2.2 V/3 V
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull−up/pull−down resistor
is disabled.
16
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 and P2
PARAMETER
VOH
VOL
High-level output
voltage
Low-level output
voltage
VCC
MIN
I(OHmax) = −1.5 mA (see Note 1)
I(OHmax) = −6 mA (see Note 2)
TEST CONDITIONS
2.2 V
VCC−0.25
VCC−0.6
VCC
VCC
I(OHmax) = −1.5 mA (see Note 1)
I(OHmax) = −6 mA (see Note 2)
3V
VCC−0.25
VCC−0.6
VCC
VCC
2.2 V
3V
TYP
MAX
UNIT
I(OLmax) = 1.5 mA (see Note 1)
I(OLmax) = 6 mA (see Note 2)
2.2 V
2.2 V
VSS
VSS
VSS+0.25
VSS+0.6
I(OLmax) = 1.5 mA (see Note 1)
3V
VSS
VSS+0.25
V
V
I(OLmax) = 6 mA (see Note 2)
3V
VSS
VSS+0.6
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum
voltage drop specified.
output frequency − Ports P1 and P2
PARAMETER
fPx.y
fPort_CLK
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
10
MHz
Port output frequency
(with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kOhm
(see Note 1 and 2)
2.2 V
3V
12
MHz
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF
(see Note 2)
2.2 V
12
MHz
3V
16
MHz
NOTES: 1. A resistive divider with 2 times 0.5 kW between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
25.0
TA = 25°C
VCC = 2.2 V
P2.4
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.4
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
VOL − Low-Level Output Voltage − V
1.0
I OH − Typical High-Level Output Current − mA
I OH − Typical High-Level Output Current − mA
3.0
3.5
0.0
VCC = 2.2 V
P2.4
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
1.0
1.5
2.0
2.5
VCC = 3 V
P2.4
−10.0
−20.0
−30.0
−40.0
TA = 85°C
−50.0
0.0
VOH − High-Level Output Voltage − V
TA = 25°C
0.5
1.0
1.5
Figure 7
NOTE: One output loaded at a time.
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH − High-Level Output Voltage − V
Figure 6
18
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
0.5
2.0
Figure 5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−25.0
0.0
1.5
VOL − Low-Level Output Voltage − V
Figure 4
−20.0
TA = 25°C
• DALLAS, TEXAS 75265
3.5
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC(start)
(see Figure 8)
dVCC/dt ≤ 3 V/s
V(B_IT−)
(see Figure 8 through Figure 10)
dVCC/dt ≤ 3 V/s
dVCC/dt ≤ 3 V/s
Vhys(B_IT−)
(see Figure 8)
td(BOR)
(see Figure 8)
t(reset)
Pulse length needed at RST/NMI
pin to accepted reset internally
TA
VCC
MIN
TYP
MAX
0.7 × V(B_IT−)
-40−85°C
70
130
105°C
70
130
2.2 V/3 V
2
UNIT
V
1.71
V
180
mV
210
mV
2000
µs
µs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
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electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − POR/brownout reset (BOR)
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − µs
1 ns
tpw − Pulse Width − µs
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
VCC(drop) − V
2
1.5
t pw
3V
VCC = 3 V
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw − Pulse Width − µs
tpw − Pulse Width − µs
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
20
POST OFFICE BOX 655303
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SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average +
MOD
32 f DCO(RSEL,DCO) f DCO(RSEL,DCO)1)
f DCO(RSEL,DCO))(32*MOD) f DCO(RSEL,DCO)1)
DCO frequency
PARAMETER
Vcc
Supply voltage range
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
RSELx = 15
3.0
3.6
V
fDCO(0,0)
fDCO(0,3)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
fDCO(2,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
fDCO(4,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
fDCO(6,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
fDCO(8,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
fDCO(10,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
fDCO(12,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
fDCO(14,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
fDCO(15,7)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL =
fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
SDCO
Frequency step between
tap DCO and DCO+1
SDCO =
fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
Duty Cycle
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1.55
ratio
%
21
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies − tolerance at calibration
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
25°C
VCC
MIN
TYP
MAX
UNIT
3V
−1
±0.2
+1
25°C
3V
0.990
1
1.010
MHz
%
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12MHz calibration value
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16MHz calibration value
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
25°C
3V
15.84
16
16.16
MHz
VCC
MIN
MAX
UNIT
calibrated DCO frequencies − tolerance over temperature 0°C − +85°C
PARAMETER
1 MHz tolerance over temperature
TA
0−85°C
3.0 V
−2.5
±0.5
+2.5
%
8 MHz tolerance over temperature
0−85°C
3.0 V
−2.5
±1.0
+2.5
%
12 MHz tolerance over temperature
0−85°C
3.0 V
−2.5
±1.0
+2.5
%
16 MHz tolerance over temperature
0−85°C
3.0 V
−3.0
±2.0
+3.0
%
2.2 V
0.970
1
1.030
MHz
3.0 V
0.975
1
1.025
MHz
3.6 V
0.970
1
1.030
MHz
2.2 V
7.760
8
8.400
MHz
3.0 V
7.800
8
8.200
MHz
3.6 V
7.600
8
8.240
MHz
2.2 V
11.70
12
12.30
MHz
3.0 V
11.70
12
12.30
MHz
3.6 V
11.70
12
12.30
MHz
3.0 V
15.52
16
16.48
MHz
3.6 V
15.00
16
16.48
MHz
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
22
1MHz calibration value
8MHz calibration value
12MHz calibration value
16MHz calibration value
TEST CONDITIONS
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
0−85°C
0−85
C
0−85°C
0−85
C
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
0−85°C
0−85
C
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
0−85°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies − tolerance over supply voltage VCC
PARAMETER
TEST CONDITIONS
1 MHz tolerance over VCC
TA
25°C
VCC
MIN
TYP
MAX
UNIT
1.8 V − 3.6 V
−3
±2
+3
%
8 MHz tolerance over VCC
25°C
1.8 V − 3.6 V
−3
±2
+3
%
12 MHz tolerance over VCC
25°C
2.2 V − 3.6 V
−3
±2
+3
%
16 MHz tolerance over VCC
25°C
3.0 V − 3.6 V
−3
±2
+3
%
25°C
1.8 V − 3.6 V
0.970
1
1.030
MHz
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
25°C
1.8 V − 3.6 V
7.760
8
8.240
MHz
fCAL(12MHz)
12MHz calibration value
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
25°C
2.2 V − 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16MHz calibration value
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
25°C
3.0 V − 3.6 V
15.00
16
16.48
MHz
TA
I: -40−85°C
T: -40−105°C
VCC
MIN
MAX
UNIT
calibrated DCO frequencies − overall tolerance
PARAMETER
TEST CONDITIONS
1 MHz tolerance overall
TYP
1.8 V − 3.6 V
−5
±2
+5
%
8 MHz tolerance overall
I: -40−85°C
T: -40−105°C
1.8 V − 3.6 V
−5
±2
+5
%
12 MHz tolerance overall
I: -40−85°C
T: -40−105°C
2.2 V − 3.6 V
−5
±2
+5
%
16 MHz tolerance overall
I: -40−85°C
T: -40−105°C
3.0 V − 3.6 V
−6
±3
+6
%
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
1.8 V − 3.6 V
0.950
1
1.050
MHz
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
1.8 V − 3.6 V
7.600
8
8.400
MHz
fCAL(12MHz)
12MHz calibration value
BCSCTL1= CALBC1_12MHZ
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
I: -40−85°C
T: -40−105°C
2.2 V − 3.6 V
11.40
12
12.60
MHz
fCAL(16MHz)
16MHz calibration value
BCSCTL1= CALBC1_16MHZ
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
I: -40−85°C
T: -40−105°C
3.0 V − 3.6 V
15.00
16
17.00
MHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − calibrated 1MHz DCO frequency
1.03
1.02
VCC = 1.8 V
Frequency − MHz
1.01
1.00
VCC = 2.2 V
VCC = 3.0 V
0.99
0.98
VCC = 3.6 V
0.97
−50.0
−25.0
0.0
25.0
50.0
75.0
100.0
TA − Temperature − °C
Figure 11. Calibrated 1 MHz Frequency vs. Temperature
1.03
Frequency − MHz
1.02
1.01
TA = 105 °C
1.00
TA = 85 °C
TA = 25 °C
0.99
TA = −40 °C
0.98
0.97
1.5
2.0
2.5
3.0
3.5
4.0
VCC − Supply Voltage − V
Figure 12. Calibrated 1 MHz Frequency vs. VCC
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
TEST CONDITIONS
DCO clock wake−up time from
tDCO,LPM3/4 LPM3/4
(see Note 1)
VCC
MIN
TYP
MAX
BCSCTL1= CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ
2.2 V/3 V
2
BCSCTL1= CALBC1_8MHZ;
DCOCTL = CALDCO_8MHZ
2.2 V/3 V
1.5
BCSCTL1= CALBC1_12MHZ;
DCOCTL = CALDCO_12MHZ
2.2 V/3 V
1
BCSCTL1= CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
3V
1
UNIT
µss
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake−up time is measured from the edge of an external wake−up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
tCPU,LPM3/4
CPU wake−up time from LPM3/4
(see Note 2)
typical characteristics − DCO clock wake−up time from LPM3/4
DCO Wake Time − us
10.00
RSELx = 0...11
RSELx = 12...15
1.00
0.10
0.10
1.00
10.00
DCO Frequency − MHz
Figure 13. DCO wake−up time from LPM3 vs DCO frequency
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
LFXT1 oscillator logic level
fLFXT1,LF,logic square wave input frequency,
LF mode
OALF
CL,eff
Oscillation Allowance for LF
crystals
Integrated effective Load
Capacitance, LF mode
(see Note 1)
TEST CONDITIONS
VCC
XTS = 0, LFXT1Sx = 0 or 1
1.8 V − 3.6 V
XTS = 0, LFXT1Sx = 3
1.8 V − 3.6 V
MIN
TYP
MAX
32,768
10,000
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
32,768
UNIT
Hz
50,000
Hz
500
kW
200
kW
XTS = 0, XCAPx = 0
1
pF
XTS = 0, XCAPx = 1
5.5
pF
XTS = 0, XCAPx = 2
8.5
pF
XTS = 0, XCAPx = 3
11
pF
Duty Cycle
LF mode
XTS = 0, Measured at
P1.4/ACLK, fLFXT1,LF = 32,768
Hz
2.2 V/3 V
30
fFault,LF
Oscillator fault frequency, LF
mode (see Note 3)
XTS = 0, LFXT1Sx = 3
(see Notes 2)
2.2 V/3 V
10
50
70
%
10,000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
− Keep as short of a trace as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fLFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 0
XTS = 1, LFXT1Sx = 0
1.8 V − 3.6 V
0.4
1
MHz
fLFXT1,HF1
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, LFXT1Sx = 1
1.8 V − 3.6 V
1
4
MHz
1.8 V − 3.6 V
2
10
MHz
fLFXT1,HF2
LFXT1 oscillator crystal frequency,
HF mode 2
XTS = 1, LFXT1Sx = 2
2.2 V − 3.6 V
2
12
MHz
3.0 V − 3.6 V
2
16
MHz
1.8 V − 3.6 V
0.4
10
MHz
2.2 V − 3.6 V
0.4
12
MHz
3.0 V − 3.6 V
0.4
16
MHz
LFXT1 oscillator logic level square
fLFXT1,HF,logic wave input frequency,
HF mode
XTS = 1, LFXT1Sx = 3
XTS = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz,
CL,eff = 15 pF
OAHF
CL,eff
Duty Cycle
fFault,HF
Oscillation Allowance for HF
crystals
(refer to Figure 14 and Figure 15)
Integrated effective Load
Capacitance, HF mode
(see Note 1)
XTS = 0, LFXT1Sx = 1
fLFXT1,HF = 4 MHz,
CL,eff = 15 pF
XTS = 0, LFXT1Sx = 2
fLFXT1,HF = 16 MHz,
CL,eff = 15 pF
XTS = 1 (see Note 2)
HF mode
Oscillator fault frequency, HF mode
(see Note 4)
2700
W
800
W
300
W
1
pF
XTS = 1, Measured at P1.4/ACLK,
fLFXT1,HF = 10 MHz
2.2 V/3 V
40
50
60
%
XTS = 1, Measured at P1.4/ACLK,
fLFXT1,HF = 16 MHz
2.2 V/3 V
40
50
60
%
XTS = 1, LFXT1Sx = 3
(see Notes 3)
2.2 V/3 V
30
300
kHz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
− Keep as short of a trace as possible between the device and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − LFXT1 oscillator in HF mode (XTS = 1)
Oscillation Allowance − Ohms
100000.00
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 2
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
Crystal Frequency − MHz
Figure 14. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
800.0
XT Oscillator Supply Current − uA
LFXT1Sx = 3
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
LFXT1Sx = 1
0.0
0.0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency − MHz
Figure 15. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
Timer_A clock frequency
tTA,cap
Timer_A, capture timing
Internal: SMCLK, ACLK;
External: TACLK, INCLK;
Duty Cycle = 50% ±10%
TA0, TA1, TA2
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
UNIT
MHz
2.2 V/3 V
20
ns
Comparator_A+ (see Note 1)
PARAMETER
TEST CONDITIONS
I(DD)
CAON=1, CARSEL=0, CAREF=0
I(Refladder/RefDiode)
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
V(IC)
V(Ref025)
V(Ref050)
Common-mode input
voltage
Voltage @ 0.25 V
V
Voltage @ 0.5V
V
CC
CC
CC
node
CC
MIN
3V
45
60
2.2 V
30
50
3V
45
71
CAON=1
2.2 V/3 V
0
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.23
0.24
0.25
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
490
550
400
Offset voltage
2.2 V/3 V
−30
Input hysteresis
CAON=1
2.2 V/3 V
0
2.2 V
3V
V(offset)
Vhys
Response time
(low−high and high−low)
MAX
40
3V
(see Figure 19 and Figure 20)
TYP
25
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, TA = 85°C
See Note 2
V(RefVT)
t(response)
node
VCC
2.2 V
TA = 25°C, Overdrive 10 mV,
Without filter: CAF=0
(see Note 3, Figure 16 and
Figure 17)
VCC−1
UNIT
µA
µA
V
mV
30
mV
0.7
1.4
mV
80
165
300
70
120
240
ns
TA = 25°C, Overdrive 10 mV,
2.2 V
1.4
1.9
2.8
With filter: CAF=1
µs
(see Note 3, Figure 16 and
3V
0.9
1.5
2.2
Figure 17)
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P2.2/CAOUT.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0 V VCC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
+
_
V+
V−
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 16. Block Diagram of Comparator_A+ Module
VCAOUT
Overdrive
V−
400 mV
t(response)
V+
Figure 17. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
−
IOUT = 10µA
Comparator_A+
CASHORT = 1
Figure 18. Comparator_A+ Short Resistance Test Condition
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − Comparator_A+
650
650
VCC = 2.2 V
V(REFVT) − Reference Volts −mV
600
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
−5
15
35
55
75
95
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 20. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 19. V(RefVT) vs Temperature, VCC = 3 V
100.00
Short Resistance − kOhms
V(REFVT) − Reference Volts −mV
VCC = 3 V
VCC = 1.8V
VCC = 2.2V
VCC = 3.0V
10.00
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
1.0
VIN/VCC − Normalized Input Voltage − V/V
Figure 21. Short Resistance vs VIN/VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER
VCC(PGM/
ERASE)
TEST CONDITIONS
VCC
Program and Erase supply voltage
MIN
TYP
2.2
fFTG
IPGM
Flash Timing Generator frequency
Supply current from VCC during program
2.2 V/3.6 V
257
3
IERASE
tCPT
Supply current from VCC during erase
2.2 V/3.6 V
3
Cumulative program time (see Note 1)
2.2 V/3.6 V
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
Program/Erase endurance
tRetention
Data retention duration
TJ = 25°C
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
tBlock, End
Block program time for each additional byte or word
tMass Erase
tSeg Erase
Mass erase time
Block program end-sequence wait time
20
104
MAX
UNIT
3.6
V
476
kHz
5
mA
7
mA
10
ms
ms
105
cycles
100
years
30
25
18
see Note 2
tFTG
6
10593
Segment erase time
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
RAM
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(RAMh)
RAM retention supply voltage (see Note 1)
CPU halted
1.6
V
NOTE 1: This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should
happen during this supply voltage condition.
JTAG Interface
PARAMETER
TEST CONDITIONS
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-down resistance on TEST
VCC
MIN
2.2 V
0
TYP
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/3 V
25
60
90
kΩ
MIN
TYP
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
JTAG Fuse (see Note 1)
PARAMETER
TEST CONDITIONS
VCC(FB)
VFB
Supply voltage during fuse-blow condition
IFB
tFB
Supply current into TEST during fuse blow
Voltage level on TEST for fuse-blow
Time to blow fuse
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
VCC
2.5
6
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the JTAG/Test and emulation feature is possible and is switched to bypass mode.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.3, input/output with Schmitt-trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
DVCC
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
EN
P1IRQ.x
Q
Set
P1IFG.x
Interrupt
Edge
Select
P1SEL.x
P1IES.x
Port P1 (P1.0 to P1.3) pin functions
PIN NAME (P1.X)
P1.0/TACLK
CONTROL BITS / SIGNALS
X
0
FUNCTION
P1.0† (I/O)
TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
1
2
3
DVSS
P1.1† (I/O)
P1DIR.x
P1SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
P1.2† (I/O)
P1.3† (I/O)
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P1 pin schematic: P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
Pad Logic
P1REN.1
P1DIR.1
0
P1OUT.1
0
1
0
1
1
Direction
0: Input
1: Output
1
Module X OUT
DVSS
DVCC
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI
P1.7/TA2/TDO/TDI
Bus
Keeper
P1SEL.1
EN
P1IN.1
EN
Module X IN
D
P1IE.1
P1IRQ.1
EN
Q
P1IFG.1
P1SEL.1
P1IES.1
Set
Interrupt
Edge
Select
To JTAG
From JTAG
TDO From JTAG
P1.7/TA2/TDO/TDI only
TEST pad
TEST
JTAG
Fuse
DVSS
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P1 (P1.4 to P1.7) pin functions
PIN NAME (P1.X)
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
P1.7/TA2/TDO/TDI
CONTROL BITS / SIGNALS
X
4
5
6
7
FUNCTION
P1.4† (I/O)
P1DIR.x
P1SEL.x
TEST
I: 0; O: 1
0
0
SMCLK
1
1
0
TCK
X
X
1
I: 0; O: 1
0
0
P1.5† (I/O)
Timer_A3.TA0
1
1
0
TMS
X
X
1
I: 0; O: 1
0
0
P1.6† (I/O)
Timer_A3.TA1
1
1
0
TDI/TCLK (see Note 3)
X
X
1
I: 0; O: 1
0
0
P1.7† (I/O)
Timer_A3.TA2
1
1
0
TDO/TDI (see Note 3)
X
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Function controlled by JTAG.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 pin schematic: P2.0 to P2.5, input/output with Schmitt-trigger
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
DVCC
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/TA1/CA0
P2.4/TA2/CA1
P2.5/CA5
Bus
Keeper
P2SEL.x
EN
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
Set
P2IFG.x
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Control signal “From Comparator_A+”
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
FUNCTION
P2CA4
P2CA0
P2CA3
P2CA2
P2CA1
P2.0/ACLK/CA2
CA2
1
1
0
1
0
P2.1/INCLK/CA3
CA3
N/A
N/A
0
1
1
P2.2/CAOUT/TA0/CA4
CA4
N/A
N/A
1
0
0
P2.3/TA1/CA0
CA0
0
1
N/A
N/A
N/A
P2.4/TA2/CA1
CA1
1
0
0
0
1
P2.5/CA5
CA5
N/A
N/A
1
0
1
OR
NOTES: 1. N/A: Not available or not applicable.
36
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 (P2.0 to P2.5) pin functions
PIN NAME (P2.X)
P2.0/ACLK/CA2
P2.1/INCLK/CA3
P2.2/CAOUT/TA0/CA4
CONTROL BITS / SIGNALS
X
0
1
2
FUNCTION
P2.0† (I/O)
3
P2.5/CA5
5
0
1
1
0
X
X
1
I: 0; O: 1
0
0
Timer_A3.INCLK
0
1
0
DVSS
CA3 (see Note 3)
1
1
0
X
X
1
P2.1† (I/O)
P2.2† (I/O)
I: 0; O: 1
0
0
Timer_A3.CCI0B
0
1
0
CAOUT
1
1
0
P2.3† (I/O)
CA0 (see Note 3)
4
CAPD.x
0
CA2 (see Note 3)
Timer_A3.TA1
P2.4/TA2/CA1
P2SEL.x
I: 0; O: 1
ACLK
CA4 (see Note 3)
P2.3/TA1/CA0
P2DIR.x
P2.4† (I/O)
X
X
1
I: 0; O: 1
0
0
1
1
0
X
X
1
I: 0; O: 1
0
0
Timer_A3.TA2
1
1
0
CA1 (see Note 3)
X
X
1
I: 0; O: 1
0
0
P2.5† (I/O)
CA5 (see Note 3)
X
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 pin schematic: P2.6, input/output with Schmitt-trigger and crystal oscillator input
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT/CA7
LFXT1 off
0
LFXT1CLK
1
P2SEL.7
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/CA6
Bus
Keeper
P2SEL.6
EN
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
Set
P2IFG.6
P2SEL.6
P2IES.6
Interrupt
Edge
Select
Control signal “From Comparator_A+”
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
P2.6/XIN/CA6
38
FUNCTION
CA6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2CA3
P2CA2
P2CA1
1
1
0
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 pin schematic: P2.7, input/output with Schmitt-trigger and crystal oscillator output
Pad Logic
To Comparator_A+
From Comparator_A+
CAPD.x
LFXT1 Oscillator
BCSCTL3.LFXT1Sx = 11
LFXT1 off
0
LFXT1CLK
1
From
P2.6/XIN
P2.6/XIN/CA6
Pad Logic
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
DVCC
P2.7/XOUT/CA7
Bus
Keeper
P2SEL.7
EN
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
Set
P2IFG.7
P2SEL.7
P2IES.7
Interrupt
Edge
Select
Control signal “From Comparator_A+”
SIGNAL “FROM COMPARATOR_A+” = 1
PIN NAME
P2.7/XOUT/CA7
FUNCTION
CA7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2CA3
P2CA2
P2CA1
1
1
1
39
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Port P2 (P2.6) pin functions
PIN NAME (P2.X)
P2.6/XIN/CA6
CONTROL BITS / SIGNALS
X
6
FUNCTION
P2.6 (I/O)
P2DIR.x
P2SEL.x
CAPD.x
I: 0; O: 1
0
0
0
XIN†
X
1
CA6 (see Note 3)
X
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPDx bit.
Port P2 (P2.7) pin functions
PIN NAME (P2.X)
P2.7/XOUT/CA7
CONTROL BITS / SIGNALS
X
6
FUNCTION
P2.7 (I/O)
XOUT† (see Note 4)
P2DIR.x
P2SEL.x
CAPD.x
I: 0; O: 1
0
0
X
1
0
CA7 (see Note 3)
X
X
1
† Default after reset (PUC/POR)
NOTES: 1. N/A: Not available or not applicable.
2. X: Don’t care.
3. Setting the CAPD.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. Selecting the CAx input pin to the comparator multiplexer with the P2CAx bits automatically disables the input buffer
for that pin, regardless of the state of the associated CAPD.x bit.
4. If the pin XOUT/P2.7/CA7 is used as an input a current can flow until P2SEL.7 is cleared due to the oscillator output driver connection
to this pin after reset.
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, ITF , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is again taken low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 22). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITEST
ITF
Figure 22. Fuse Check Mode Current, MSP430F21x1
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also, see the bootstrap loader section for more information.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
SLAS439C − SEPTEMBER 2004 − REVISED JULY 2006
Data Sheet Revision History
Literature
Number
SLAS439
Summary
Preliminary PRODUCT PREVIEW datasheet release.
SLAS439A
MSP430x21x1 production datasheet release.
SLAS439B
Corrected instruction cycle time to 62.5ns, pg 1
Updated Figure 1. Operating Area, pg 12
Updated Figures 2 & 3, pg 13
RPull unit corrected from ”W” to ”kW”, pg 15
Max load current specification and Note 3 removed from ”outputs” table, pg 16
MIN and MAX percentages for ”calibrated DCO frequencies − tolerance over supply voltage VCC” corrected from 2.5% to
3% to match the specified frequency ranges., pg 22
SLAS439C
MSP430x21x1T production datasheet release.
105°C characterization results added.
NOTE: The referring page and figure numbers are referred to the respective document revision.
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2101IDGV
ACTIVE
TVSOP
DGV
20
MSP430F2101IDGVR
ACTIVE
TVSOP
DGV
20
MSP430F2101IDW
ACTIVE
SOIC
DW
20
MSP430F2101IDWR
ACTIVE
SOIC
DW
20
MSP430F2101IPW
ACTIVE
TSSOP
PW
20
MSP430F2101IPWR
ACTIVE
TSSOP
PW
MSP430F2101IRGER
ACTIVE
QFN
MSP430F2101IRGET
ACTIVE
MSP430F2101TDGV
90
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
QFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
TVSOP
DGV
20
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2101TDGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2101TDW
ACTIVE
SOIC
DW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2101TDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2101TPW
ACTIVE
TSSOP
PW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2101TPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2101TRGER
ACTIVE
QFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2101TRGET
ACTIVE
QFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2111IDGV
ACTIVE
TVSOP
DGV
20
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2111IDGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2111IDW
ACTIVE
SOIC
DW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2111IDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2111IPW
ACTIVE
TSSOP
PW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2111IPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2111IRGER
ACTIVE
QFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2111IRGET
ACTIVE
QFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2111TDGV
ACTIVE
TVSOP
DGV
20
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
25
70
25
70
25
70
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2111TDGVR
ACTIVE
TVSOP
DGV
20
MSP430F2111TDW
ACTIVE
SOIC
DW
20
MSP430F2111TDWR
ACTIVE
SOIC
DW
20
MSP430F2111TPW
ACTIVE
TSSOP
PW
20
MSP430F2111TPWR
ACTIVE
TSSOP
PW
MSP430F2111TRGER
ACTIVE
QFN
MSP430F2111TRGET
ACTIVE
MSP430F2121IDGV
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-2-260C-1 YEAR
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
QFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
TVSOP
DGV
20
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2121IDGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2121IDW
ACTIVE
SOIC
DW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121IDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121IPW
ACTIVE
TSSOP
PW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121IPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121IRGER
ACTIVE
QFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2121IRGET
ACTIVE
QFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2121TDGV
ACTIVE
TVSOP
DGV
20
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2121TDGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2121TDW
ACTIVE
SOIC
DW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121TDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121TPW
ACTIVE
TSSOP
PW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121TPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2121TRGER
ACTIVE
QFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2121TRGET
ACTIVE
QFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2131IDGV
ACTIVE
TVSOP
DGV
20
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2131IDGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2131IDW
ACTIVE
SOIC
DW
20
CU NIPDAU
Level-1-260C-UNLIM
25
70
25
70
25
70
25
Addendum-Page 2
Green (RoHS &
no Sb/Br)
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2131IDWR
ACTIVE
SOIC
DW
20
MSP430F2131IPW
ACTIVE
TSSOP
PW
20
MSP430F2131IPWR
ACTIVE
TSSOP
PW
MSP430F2131IRGER
ACTIVE
QFN
MSP430F2131IRGET
ACTIVE
MSP430F2131TDGV
2000 Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
QFN
RGE
24
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
ACTIVE
TVSOP
DGV
20
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2131TDGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2131TDW
ACTIVE
SOIC
DW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2131TDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2131TPW
ACTIVE
TSSOP
PW
20
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2131TPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
MSP430F2131TRGER
ACTIVE
QFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
MSP430F2131TRGET
ACTIVE
QFN
RGE
24
250
CU NIPDAU
Level-2-260C-1 YEAR
70
25
70
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 4
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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