Samsung K4E660812E 8m x 8bit cmos dynamic ram with extended data out Datasheet

K4E660812E,K4E640812E
CMOS DRAM
8M x 8bit CMOS Dynamic RAM with Extended Data Out
DESCRIPTION
This is a family of 8,388,608 x 8 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption( Normal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 8Mx8 EDO Mode DRAM family is fabricate d using
Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.
FEATURES
• Extended Data Out Mode operation
• Part Identification
- K4E660812E-JC/L(3.3V, 8K Ref.)
- K4E640812E-JC/L(3.3V, 4K Ref.)
- K4E660812E-TC/L(3.3V, 8K Ref.)
- K4E640812E-TC/L(3.3V, 4K Ref.)
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Active Power Dissipation
• Early Write or output enable controlled write
Unit : mW
• JEDEC Standard pinout
Speed
8K
4K
• Available in Plastic SOJ and TSOP(II) packages
-45
324
432
• +3.3V ±0.3V power supply
-50
288
396
-60
252
360
• Refresh Cycles
Refresh
cycle
K4E660812E*
8K
K4E640812E
FUNCTIONAL BLOCK DIAGRAM
Refresh time
Normal
L-ver
64ms
128ms
4K
RAS
CAS
W
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS -before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
¡Ü
Control
Clocks
Refresh Timer
Refresh Counter
Speed
t RAC
t CAC
t RC
t HPC
-45
45ns
12ns
74ns
17ns
-50
50ns
13ns
84ns
20ns
-60
60ns
15ns
104ns
25ns
Row Decoder
Refresh Control
Performance Range:
A0~A12
(A0~A11)*1
Row Address Buffer
A0~A9
(A0~A10)*1
Col. Address Buffer
Vcc
Vss
VBB Generator
Memory Array
8,388,608 x 8
Cells
Column Decoder
Note) *1 : 4K Refresh
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
Sens e Amps & I/O
Part
NO.
Data in
Buffer
DQ0
to
DQ7
Data out
Buffer
OE
K4E660812E,K4E640812E
CMOS DRAM
PIN CONFIGURATION (Top Views)
• K4E660812E-T
• K4E640812E-T
• K4E660812E-J
• K4E640812E-J
V CC
DQ0
DQ1
DQ2
DQ3
N.C
V CC
W
RAS
A0
A1
A2
A3
A4
A5
V CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
V CC
DQ0
DQ1
DQ2
DQ3
N.C
V CC
W
RAS
A0
A1
A2
A3
A4
A5
V CC
(J : 400mil SOJ)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(T : 400mil TSOP(II))
* (N.C) : N.C for 4K Refresh product
Pin Name
Pin Function
A0 - A12
Address Inputs(8K Product)
A0 - A11
Address Inputs(4K Product)
DQ0 - 7
Data In/Out
VSS
Ground
RAS
Row Address Strobe
CAS
Column Address Strobe
W
Read/Write Input
OE
Data Output Enable
VCC
Power(+3.3V)
N.C
No Connection
VSS
DQ7
DQ6
DQ5
DQ4
VSS
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
K4E660812E,K4E640812E
CMOS DRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Units
VIN, VO U T
-0.5 to +4.6
V
Voltage on VC C supply relative to VSS
V CC
-0.5 to +4.6
V
Storage Temperature
Tstg
-55 to +150
°C
PD
1
W
IOS Address
50
mA
Voltage on any pin relative to VSS
Power Dissipation
Short Circuit Output Current
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
(Voltage referenced to Vss, T A= 0 to 70 °C)
Symbol
Min
Typ
Max
Units
Supply Voltage
VC C
3.0
3.3
3.6
V
Ground
VSS
0
0
0
V
*1
Input High Voltage
VI H
2.0
-
Vcc+0.3
V
Input Low Voltage
V IL
-0.3 *2
-
0.8
V
*1 : Vcc+1.3V at pulse width ≤15ns which is measured at VC C
*2 : -1.3 at pulse width≤15ns which is measured at V SS
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter
Symbol
Min
Max
Units
Input Leakage Current (Any input 0≤V I N≤V CC+0.3V,
all other pins not under test=0 Volt)
II(L)
-5
5
uA
Output Leakage Current
(Data out is disabled, 0V≤V OUT ≤VCC )
IO(L)
-5
5
uA
Output High Voltage Level(IO H=-2mA)
VO H
2.4
-
V
Output Low Voltage Level(I OL =2mA)
VOL
-
0.4
V
K4E660812E,K4E640812E
CMOS DRAM
DC AND OPERATING CHARACTERISTICS
Symbol
Power
(Continued)
Max
Speed
Units
K4E660812E
K4E640812E
IC C 1
Don′t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
IC C 2
Normal
L
Don′t care
1
1
1
1
mA
mA
IC C 3
Don′t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
IC C 4
Don′t care
-45
-50
-60
100
90
80
100
90
80
mA
mA
mA
IC C 5
Normal
L
Don′t care
0.5
200
0.5
200
mA
uA
IC C 6
Don′t care
-45
-50
-60
120
110
100
120
110
100
mA
mA
mA
IC C 7
L
Don′t care
350
350
uA
ICCS
L
Don′t care
350
350
uA
IC C 1* : Operating Current (RAS and CAS, Address cycling @ t RC=min.)
IC C 2 : Standby Current (RAS=CAS=W=V I H)
IC C 3* : RAS-only Refresh Current (CAS =VI H, RAS cycling @ t RC=min.)
IC C 4* : Extended Data Out Mode Current (RAS=V IL , CAS , Address cycling @t HPC =min.)
IC C 5 : Standby Current (RAS=CAS=W=V CC -0.2V)
IC C 6* : CAS-Before- RAS Refresh Current (RAS and CAS cycling @ tRC =min)
IC C 7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH )=VC C-0.2V, Input low voltage(VIL )=0.2V, CAS=CAS-before-RAS cycling or 0.2V
W, OE=V IH , Address=Don′t care, DQ=Open, TRC=31.25us
IC C S : Self Refresh Current
RAS=CAS=0.2V, W=OE =A0 ~ A12(A11)=VCC -0.2V or 0.2V, DQ0 ~ DQ7=V CC-0.2V, 0.2V or Open
*Note :
ICC1 , I CC3 , ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In IC C 1, I CC3 and ICC6, address can be changed maximum once while RAS=V IL . In IC C 4,
address can be changed maximum once within one EDO mode cycle time, t HPC .
K4E660812E,K4E640812E
CAPACITANCE
CMOS DRAM
(TA=25°C, VCC=3.3V, f=1MHz)
Parameter
Symbol
Min
Max
Units
Input capacitance [A0 ~ A12]
CI N 1
-
5
pF
Input capacitance [RAS, CAS , W, OE]
CI N 2
-
7
pF
Output capacitance [DQ0 - DQ7]
C DQ
-
7
pF
AC CHARACTERISTICS
(0°C≤T A≤70° C, See note 2)
Test condition : V CC =3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter
-45
Symbol
Min
-50
Max
Min
-60
Max
Min
Units
Note
Max
Random read or write cycle time
tR C
74
84
104
ns
Read-modify-write cycle time
tRWC
101
113
138
ns
Access time from RAS
tRAC
45
50
60
ns
3,4,10
Access time from CAS
tCAC
12
13
15
ns
3,4,5
Access time from column address
tAA
23
25
30
ns
3,10
CAS to output in Low-Z
tCLZ
3
ns
3
Output buffer turn-off delay from CAS
ns
6,13
ns
3
ns
2
3
13
3
3
tC E Z
3
OE to output in Low-Z
tOLZ
3
13
Transition time (rise and fall)
tT
1
RAS precharge time
tR P
25
RAS pulse width
tR A S
45
RAS hold time
tRSH
8
8
10
ns
CAS hold time
tCSH
35
38
40
ns
CAS pulse width
tC A S
7
5K
8
10K
10
10K
ns
14
RAS to CAS delay time
tRCD
11
33
11
37
14
45
ns
4
RAS to column address delay time
tRAD
9
22
9
25
12
30
ns
10
CAS to RAS precharge time
3
50
1
50
13
3
50
30
10K
3
1
50
40
10K
60
ns
10K
ns
tCRP
5
5
5
ns
Row address set-up time
tASR
0
0
0
ns
Row address hold time
tRAH
7
7
10
ns
Column address set-up time
tASC
0
0
0
ns
Column address hold time
tCAH
7
7
10
ns
Column address to RAS lead time
tR A L
23
25
30
ns
Read command set-up time
tRCS
0
0
0
ns
Read command hold time referenced to CAS
tRCH
0
0
0
ns
8
Read command hold time referenced to RAS
tRRH
0
0
0
ns
8
Write command hold time
tWCH
7
7
10
ns
Write command pulse width
tW P
6
7
10
ns
Write command to RAS lead time
tRWL
8
8
10
ns
Write command to CAS lead time
tCWL
7
7
10
ns
Data set-up time
tD S
0
0
0
ns
9
K4E660812E,K4E640812E
AC CHARACTERISTICS
CMOS DRAM
(Continued)
Parameter
-45
Symbol
Min
Data hold time
tD H
Refresh period (Normal)
tR E F
Refresh period (L-ver)
tR E F
Write command set-up time
-50
Max
7
Min
-60
Max
7
64
Min
10
64
128
128
Units
Note
ns
9
Max
64
ms
128
ms
t WCS
0
0
0
ns
7
CAS to W delay time
t CWD
24
27
32
ns
7
RAS to W delay time
t RWD
57
64
77
ns
7
Column address to W delay time
tA W D
35
39
47
ns
7
CAS set-up time (CAS -before-RAS refresh)
t CSR
5
5
5
ns
CAS hold time (CAS -before-RAS refresh)
t CHR
10
10
10
ns
RAS to CAS precharge time
t RPC
5
5
5
ns
Access time from CAS precharge
tCPA
Hyper Page cycle time
t HPC
17
20
Hyper Page read-modify-write cycle time
t HPRWC
47
CAS precharge time (Hyper page cycle)
tC P
6.5
RAS pulse width (Hyper page cycle)
24
28
35
ns
3
25
ns
14
47
56
ns
14
7
10
ns
t RASP
45
RAS hold time from CAS precharge
t RHCP
24
OE access time
t OEA
OE to data delay
t OED
8
10
13
ns
CAS precharge to W delay time
t CPWD
36
41
52
ns
Output buffer turn off delay time from OE
tOEZ
3
OE command hold time
t OEH
5
5
5
ns
Write command set-up time (Test mode in)
t WTS
10
10
10
ns
11
Write command hold time (Test mode in)
t WTH
10
10
10
ns
11
W to RAS precharge time (C-B-R refresh)
t WRP
10
10
10
ns
W to RAS hold time (C-B-R refresh)
t WRH
10
10
10
ns
Output data hold time
tD O H
4
5
5
ns
Output buffer turn off delay from RAS
tR E Z
3
13
Output buffer turn off delay from W
13
200K
50
200K
30
12
11
60
13
3
200K
35
13
3
13
3
13
ns
15
3
ns
13
ns
ns
3
6
3
13
ns
6,13
3
13
ns
6
tW E Z
3
W to data delay
t WED
8
15
15
ns
OE to CAS hold time
tO C H
5
5
5
ns
CAS hold time to OE
t CHO
5
5
5
ns
OE precharge time
t OEP
5
5
5
ns
W pulse width (Hyper Page Cycle)
tW P E
5
5
5
ns
RAS pulse width (C-B-R self refresh)
t RASS
100
100
100
us
15,16,17
RAS precharge time (C-B-R self refresh)
tRPS
74
90
110
ns
15,16,17
CAS hold time (C-B-R self refresh)
t CHS
-50
-50
-50
ns
15,16,17
K4E660812E,K4E640812E
CMOS DRAM
TEST MODE CYCLE
Parameter
( Note 11 )
-45
Symbol
Min
-50
Max
Min
-60
Max
Min
Units
Note
Max
Random read or write cycle time
tR C
79
89
109
ns
Read-modify-write cycle time
t RWC
110
121
145
ns
Access time from RAS
t RAC
50
55
65
ns
3,4,10,12
Access time from CAS
t CAC
17
18
20
ns
3,4,5,12
Access time from column address
t AA
28
30
35
ns
3,10,12
RAS pulse width
tRAS
50
10K
55
10K
65
10K
ns
CAS pulse width
tCAS
12
10K
13
10K
15
10K
ns
RAS hold time
t RSH
18
18
20
ns
CAS hold time
t CSH
39
43
50
ns
Column Address to RAS lead time
tRAL
28
30
35
ns
CAS to W delay time
t CWD
29
35
39
ns
7
RAS to W delay time
t RWD
62
72
84
ns
7
Column Address to W delay time
t AWD
40
47
54
ns
7
Hyper Page cycle time
t HPC
22
25
30
ns
14
Hyper Page read-modify-write cycle time
t HPRWC
52
53
61
ns
14
RAS pulse width (Hyper page cycle)
t RASP
50
Access time from CAS precharge
tCPA
29
OE access time
t OEA
17
OE to data delay
t OED
13
18
20
ns
OE command hold time
t OEH
13
18
20
ns
200K
55
200K
65
200K
ns
33
40
ns
3
18
20
ns
3
K4E660812E,K4E640812E
CMOS DRAM
NOTES
1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
2. Input voltage levels are Vih/Vil. V IH(min) and VIL (max) are reference levels for measuring timing of input signals. Transition
times are measured between V IH(min) and V IL (max) and are assumed to be 2ns for all inputs.
3. Measured with a load equivalent to 1 TTL load and 100pF.
4. Operation within the t RCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only.
If t RCD is greater than the specified t RCD (max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that t R C D≥t R C D(max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or V ol .
7. t W C S, tRWD , tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric characteristics only. If t W C S≥ tWCS (min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD ≥ tCWD (min), t RWD ≥t RWD (min) and tAWD ≥t AWD (min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
8. Either tRCH or t RRH must be satisfied for a read cycle.
9. This parameters are referenced to the CAS falling edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
10. Operation within the t RAD (max) limit insures that t RAC (max) can be met. t RAD (max) is specified as a reference point only. If
t RAD is greater than the specified t RAD (max) limit, then access time is controlled by t AA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC , t AA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
14. t ASC ≥6ns, Assume tT = 2.0ns, if t ASC ≤6ns, then tHPC (min) and tCAS (min) must be increased by the value of "6ns-tASC ".
15. If t R A S S≥100us, then RAS precharge time must use t RPS instead of t R P.
16. For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed
within 64ms before and after self refresh, in order to meet refresh specification.
17. For distributed CAS -before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before
and after self refresh in order to meet refresh specification.
K4E660812E,K4E640812E
CMOS DRAM
READ CYCLE
tR C
t RAS
RAS
VIL -
t CSH
tC R P
CAS
tR P
VIH -
tR C D
tCRP
t RSH
VIH -
t CAS
VIL -
t RAD
t ASR
A
V IH V IL -
t RAH
tR A L
t ASC
t CAH
ROW
ADDRESS
COLUMN
ADDRESS
tR C H
tR C S
W
tRRH
V IH V IL -
t WEZ
tC E Z
tAA
OE
VIH -
tO E Z
tOEA
VIL -
tOLZ
tCAC
DQ0 ~ DQ3(7)
VO H V OL -
tRAC
OPEN
tCLZ
t REZ
DATA-OUT
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRC
tR A S
RAS
tR P
VIH VIL -
tCSH
t CRP
CAS
t RSH
V IH -
VIH VIL -
tC R P
tCAS
V IL -
tRAD
tASR
A
tRCD
tRAH
t ASC
ROW
ADDRESS
t RAL
t CAH
COLUMN
ADDRESS
tC W L
t RWL
tWCS
W
OE
VIH -
t WCH
tW P
VIL -
V IH V IL -
DQ0 ~ DQ3(7)
VIH VIL -
t DS
tD H
DATA-IN
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
tR C
t RAS
RAS
V IL -
tCSH
tCRP
CAS
tRP
V IH -
tRCD
tRSH
tCAS
V IH -
tCRP
V IL -
tRAD
tR A L
t ASR
A
V IH V IL -
t RAH
tASC
tCAH
ROW
ADDRESS
COLUMN
ADDRESS
tCWL
t RWL
W
OE
t WP
V IH V IL -
VIH VIL -
DQ0 ~ DQ3(7)
V IH -
t OED
tDS
t OEH
tDH
DATA-IN
V IL -
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
READ - MODIFY - WRITE CYCLE
tRAS
RAS
tRP
V IH V IL -
t CRP
CAS
tR W C
tRCD
tRSH
V IH -
tC A S
V IL -
t RAD
t ASR
tRAH
t ASC
tCAH
tCSH
A
V IH V IL -
ROW
ADDR
COLUMN
ADDRESS
tAWD
t RWL
tCWD
W
tC W L
VIH -
tW P
VIL -
tRWD
OE
t OEA
V IH V IL -
DQ0 ~ DQ3(7)
V I/OH V I/OL -
tOLZ
tCLZ
tCAC
tAA
tOED
tOEZ
t RAC
VALID
DATA-OUT
tD S
tDH
VALID
DATA-IN
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
HYPER PAGE READ CYCLE
t RP
t RASP
RAS
VIH VIL -
¡ó
t RHCP
tCSH
tHPC
tC R P
CAS
VIL -
VIH VIL -
tC P
tCAS
VIH -
tC P
tCAS
t HPC
tC P
tCAS
tCAS
t RAD
t ASR
A
tR C D
t HPC
t RAH tASC
ROW
ADDR
t CAH
COLUMN
ADDRESS
tASC
tCAH
t ASC
COLUMN
ADDRESS
tCAH
COLUMN
ADDR
tASC
tCAH
t REZ
COLUMN
ADDRESS
tRAL
t RCS
W
V IH V IL -
tCAC
tAA
VIH -
t AA
t CPA
tOCH
tOEA
tCPA
tCAC
t CAC
t AA
tCPA
OE
tRRH
t RCH
tAA
t CHO
t OEP
tOEA
VIL -
t OEP
tCAC
DQ0 ~ DQ3(7)
VOH VOL -
tD O H
tRAC
VALID
DATA-OUT
tOLZ
tCLZ
tOEZ
t OEA
tOEZ
VALID
DATA-OUT
tO E Z
VALID
DATA-OUT
VALID
DATA-OUT
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
HYPER PAGE WRITE CYCLE ( EARLY WRITE )
NOTE : DOUT = OPEN
tRP
t RASP
RAS
V IH -
t RHCP
V IL -
¡ó
tHPC
tCRP
CAS
tR C D
tHPC
tC P
VIH -
tCAS
VIL -
t RSH
t CP
tCAS
t CAS
t RAD
¡ó
tCSH
tASR
A
V IH V IL -
tRAH
ROW
ADDR.
t ASC
t CAH
tASC
COLUMN
ADDRESS
t CAH
COLUMN
ADDRESS
tASC
t CAH
¡ó
¡ó
COLUMN
ADDRESS
t RAL
tWCS
W
V IH -
tW C H
tW C S
t WP
t WP
¡ó
tWCH
tW P
V IL -
tC W L
OE
tWCS
tWCH
t CWL
t CWL
t RWL
VIH -
¡ó
VIL -
¡ó
DQ0 ~ DQ3(7)
V IH V IL -
tDS
t DH
tD S
tD H
tDS
tD H
¡ó
VALID
DATA-IN
VALID
DATA-IN
VALID
DATA-IN
¡ó
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
HYPER PAGE READ-MODIFY-WRITE CYCLE
tRP
tRASP
RAS
VIH -
t CSH
VIL -
tC R P
CAS
tHPRWC
tRCD
t CP
V IH V IL -
VIH VIL -
tCAS
t RAD
t RAH
ROW
ADDR
t RAL
tCAH
tASC
tCAH
t ASC
COL.
ADDR
COL.
ADDR
tRCS
W
tCRP
t CAS
t ASR
A
t RSH
tRWL
tCWL
tC W L
VIH -
tWP
VIL -
tW P
t CWD
tCWD
tAWD
t RWD
OE
V IH -
t AWD
tC P W D
t OEA
tOEA
V IL -
tOED
tOED
t CAC
t AA
DQ0 ~ DQ3(7)
V I/OH V I/OL -
tD H
tO E Z
t CAC
tAA
tD S
t DH
tOEZ
tDS
t RAC
t CLZ
tCLZ
t OLZ
VALID
DATA-OUT
VALID
DATA-IN
t OLZ
VALID
DATA-OUT
VALID
DATA-IN
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
HYPER PAGE READ AND WRITE MIXED CYCLE
tR P
t RASP
RAS
VIH -
READ( tCAC )
R E A D (t CPA)
t HPC
VIH -
t CP
VIL -
t ASR
A
VIH VIL -
t CAS
tRAD
t RAH
tASC
ROW
ADDR
t CAH
COLUMN
ADDRESS
tC P
tCAS
tCAS
tCAS
t CAH
tASC
tR H C P
tHPC
tHPC
t CP
CAS
R E A D (tAA )
WRITE
VIL -
tCAH
tASC
COLUMN
ADDRESS
t ASC
COL.
ADDR
t CAH
COL.
ADDR
tRAL
tR C S
W
tR C H
t RCS
tRCH
tW C H
t RCH
tWCS
V IH V IL -
t WPE
tCLZ
tWED
tC P A
OE
VIH VIL -
DQ0 ~ DQ3(7)
V I/OH V I/OL -
tOEA
tCAC
t AA
t WEZ
t DH
tW E Z
t REZ
t AA
tD S
t CLZ
tRAC
VALID
DATA-OUT
VALID
DATA-OUT
VALID
DATA-IN
VALID
DATA-OUT
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
RAS - ONLY REFRESH CYCLE*
NOTE : W, OE, D IN = Don′t care
DOUT = OPEN
t RC
V IH -
RAS
tR P
t RAS
V IL -
tRPC
tCRP
tCRP
V IH -
CAS
V IL -
tASR
V IH -
A
V IL -
tRAH
ROW
ADDR
CAS - BEFORE - RAS REFRESH CYCLE
NOTE : OE , A = Don′t care
tR C
tRP
RAS
VIH VIL -
tRPC
tCP
CAS
t RAS
VIH -
tRPC
t CSR
t CHR
VIL -
tW R P
W
t RP
tWRH
VIH V IL -
DQ0 ~ DQ3(7)
VO H V OL -
tC E Z
OPEN
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
HIDDEN REFRESH CYCLE ( READ )
tRC
RAS
tRAS
V IH -
t RP
t RAS
V IL -
tC R P
CAS
t RC
tRP
tRCD
t RSH
t CHR
V IH V IL -
tRAD
tASR
A
V IH V IL -
t RAH
t RAL
t ASC
tCAH
COLUMN
ADDRESS
ROW
ADDRESS
tW R H
tR C S
W
V IH V IL -
tAA
OE
V IH -
t OEA
V IL -
tOLZ
t CAC
t CLZ
tRAC
DQ0 ~ DQ3(7)
VO H VOL -
OPEN
t CEZ
tREZ
tWEZ
tOEZ
DATA-OUT
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
HIDDEN REFRESH CYCLE ( WRITE )
NOTE : DOUT = OPEN
tRC
RAS
t RAS
VIH -
tRCD
tRSH
tC H R
V IH V IL -
t RAD
t ASR
A
tR P
tR A S
VIL -
t CRP
CAS
t RC
tR P
VIH VIL -
t RAH
tASC
ROW
ADDRESS
t RAL
tCAH
COLUMN
ADDRESS
tWRH
tWRP
tWCS
W
OE
V IH -
tWCH
tWP
V IL -
VIH VIL -
tDS
DQ0 ~ DQ3(7)
VIH -
t DH
DATA-IN
VIL -
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
CAS - BEFORE - RAS SELF REFRESH CYCLE
NOTE : OE, A = Don ′t care
tRP
RAS
VIL -
t RPC
tC H S
t CSR
V IH VIL -
DQ0 ~ DQ3(7)
VOH -
tCEZ
OPEN
VOL -
W
tRPS
t RPC
tCP
CAS
t RASS
V IH -
V IH VIL -
tW R P
t WRH
TEST MODE IN CYCLE
NOTE : OE , A = Don ′t care
tR C
t RP
RAS
tR P
tR A S
V IH VIL -
tRPC
tRPC
tCP
CAS
t CSR
V IH -
tWTS
W
tCHR
VIL -
t WTH
V IH VIL -
DQ0 ~ DQ3(7)
VOH VOL -
t OFF
OPEN
Don′t care
Undefined
K4E660812E,K4E640812E
CMOS DRAM
PACKAGE DIMENSION
32 SOJ 400mil
Units : Inches (millimeters)
0.360 (9.15)
0.380 (9.65)
0.400 (10.16)
0.445 (11.30)
0.435 (11.06)
#32
0.006 (0.15)
0.012 (0.30)
#1
0.148 (3.76)
MAX
0.027 (0.69)
MIN
0.841 (21.36)
MAX
0.820 (20.84)
0.830 (21.08)
0.0375 (0.95)
0.050 (1.27)
0.026 (0.66)
0.032 (0.81)
0.015 (0.38)
0.021 (0.53)
32 TSOP(II) 400mil
0.400 (10.16)
0.471 (11.96)
0.455 (11.56)
Units : Inches (millimeters)
0.004 (0.10)
0.010 (0.25)
0.841 (21.35)
MAX
0.821 (20.85)
0.829 (21.05)
0.037 (0.95)
0.050 (1.27)
0.047 (1.20)
MAX
0.010 (0.25)
TYP
0.002 (0.05)
MIN
0.012 (0.30)
0.020 (0.50)
0.018 (0.45)
0.030 (0.75)
0~8
O
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