Drivers for Large LCD Panels 6bit RSDSTM Source Driver BU95306 No.10043EAT03 ●Description ROHMLCD drivers for large panels are display drivers optimized for large LCDs in a variety of applications, including desktop PCs, laptops, and TVs. The broad lineup is offered in low amplitude differential transmission interface type TM (RSDS ) featuring low EMI, 6bit gradation precision, and different output configurations (642 and up) for wide compatibility. ●Features 1) 600/618/630/642 output channels TM 2) 6bit 9pair RSDS inputs 3) Dot & n-line inversion available 4) Built-in 2ch repair amplifiers 5) γ correction is possible 6) Built-in input data reversing function (INV) 7) Output voltage range : AVSS+0.1V~AVDD-0.1V 8) High speed data transfer: fCLK (MAX) =85MHz 9) Logic power supply voltage (DVDD) : 2.3~3.6V 10) Driver power supply voltage (AVDD) : 8.0~13.5V 11) Package: COF48 ●Applications TFT LCD Panels ●Line up matrix Number of outputs BU95101 BU95303 BU95306 BU95408 384 384 / 414 / 420 / 432 600 / 618 / 630 / 642 684 / 690 / 702 / 720 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 1/14 2010.10 - Rev.A Technical Note BU95306 ●Absolute maximum ratings Parameter Symbol Ratings Unit Logic power supply voltage DVDD -0.3 ~ +4.5 V Driver power supply voltage AVDD -0.3 ~ +14.0 V Logic input voltage VI1 -0.3 ~ DVDD+0.3 V Logic output voltage VO1 -0.3 ~ DVDD+0.3 V Driver input voltage VI2 -0.3 ~ AVDD+0.3 V Driver output voltage VO2 -0.3 ~ AVDD+0.3 V Storage temperature range Tstg -55~+125 ℃ Symbol Ratings Unit Logic power supply voltage DVDD +2.3 ~ +3.6 V Driver power supply voltage AVDD +8.0 ~ +13.5 V V0~V15 0.1 ~ AVDD-0.1 V Driver output voltage VO 0.1 ~ AVDD-0.1 V Output load capacitance CL 150 pF fCLK(MAX) 85 MHz Topr -30 ~ +85 ℃ ●Recommended Operating Range Parameter γ-correction reference voltage Maximum clock frequency Operating temperature range * AVSS=DVSS=0V www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 2/14 2010.10 - Rev.A Technical Note BU95306 ●Electrical characteristics (DC) (Unless otherwise noted, Ta=-30~+85℃, DVDD=2.3~3.6V, AVDD=8.0~13.5V, DVSS=AVSS=0V) Limits Parameter Symbol Unit Conditions Min. Typ. Max. Logic Part DVDD=3.3V, Data=00h-3Fh(dot), fclk=65MHz, fstb=50kHz, 1Line-inverison Logic supply current IDDL - 4 8 mA Input “H” voltage V1H 0.7DVDD - DVDD V Input “L” voltage V1L 0 - 0.3DVDD V Input “H” current I1H1 - - +1 μA VIN=DVDD Input “L” current I1L1 -1 - - μA VIN=DVSS Input “H” current 2 I1H2 - 20 40 μA VIN=DVDD DVDD=3.3V Input “L” current 2 I1L2 -3 - +3 μA VIN=DVSS Output “H” voltage VOH DVDD-0.5 - - V IOH=-1.0mA Output “L” voltage VOL - - 0.5 V IOL=1.0mA IDDA - 9 12 mA RγUP 10.9 15.5 20.2 kΩ RγLOW 10.8 15.4 20.0 kΩ - ±25 - mV - ±10 ±25 mV - ±25 - mV - ±3 ±10 mV V8~V15 AVDD=12V Yout=0.1V~1.5V,Yout=10.5V~11.9V AVDD=12V, Yout=1.5V~10.5V AVDD=12V Yout=0.1V~1.5V,Yout=10.5V~11.9V AVDD=12V, Vout=1.5V~10.5V AVDD=12V, Data=32-gray R/L,SFTR,INV,SFTL, POL,STB,SEL0,SEL1, LPC0, LPC1 ,TEST0 Dxx, SFTR, POL, INV, SFTL,CLK,STB,R/L SEL0,SEL1, LPC0,LPC1,TEST0 Built-in Pull down R SFTR,SFTL Driver part Driver supply current γ correction resistance Output voltage deviation VOD1*1 AVDD=12V, Data=00h-3Fh(dot), fclk=65MHz, fstb=50kHz,1Line-inverison, noLoad, LPC:normal V0~V7 Output swing voltage Deviation VRMS Output voltage deviation 2 (between chips) VOD2*3 - - ±7.5 mV Repair input voltage V1NB 0.1 - AVDD-0.1 V Repair input “H” current I1BH -1 - +1 μA VIN=AVDD=13.5V Repair input “L” current I1BL -1 - +1 μA VIN=AVSS Driver output “H” current Driver output“L” current *2 IREP1,2 IVOHY - - -0.4 mA Y1~Y642, AVDD=12V, Vx=6 V,Yout=11V IVOHR - - -0.8 mA OREP1,2 ,AVDD=12V, Vx=6 V, Yout=11V IVOLY 0.4 - - mA Y1~Y642, AVDD=12V, Vx=6 V,Yout=1V IVOLR 0.8 - - mA OREP1,2 ,AVDD=12V, Vx=6 V, Yout=1V VIHRSDS 100 200 - mV VILRSDS - -200 -100 mV VCMRSDS 0.4 - DVDD-1.2 V RSDSTM input part RSDSTM input “H” voltage RSDS TM input “L” voltage RSDSTM common input voltage *1 *2 *3 *4 *5 VCMRSDS=+1.2V*4 CLKP/N,DXXP/N (X=0,1,2) VDIFF=200mV*5 VOD1=measured output voltage - averaged output voltage of all outputs VRMS=measured output swing voltage - averaged output swing voltage of all outputs VOD2=averaged output voltage - target value VCM RSDS = (VCLKP+VCLKN)/2 or (VDXXP+VDXXN)/2 VDIFF = VCLKP- VCLKN or VDXXP-VDXXN www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 3/14 2010.10 - Rev.A Technical Note BU95306 ●Electrical characteristics (AC) (Unless otherwise noted, Ta=-30~+85℃, DVDD=2.3~3.6V, AVDD=8.0~13.5V, DVSS=AVSS=0V) Limits Parameter Symbol Unit Min. Typ. Max. Conditions Clock pulse width tw 1/85MHz - - ns Clock pulse "H" period th 5 - - ns Clock pulse "L" period tl 5 - - ns Data setup time tsu1 2 - - ns Data hold time thd1 0 - - ns Start pulse setup time tsu2 1 - - ns Start pulse hold time thd2 2 - - ns Start pulse width tWSFT 1 - 2 CLK period tdc - - 11 ns STB pulse width tWSTB 1 - - CLK period Final data timing tLDT 1 - - CLK period Time between STB↑and start pulse↑ tSTB-SFT 6 - - CLK period Time between STB↑and CLK↓ tSTB-CLK 4 - - ns tsp 14 - - ns - - 3 μs LPC:normal *1*3 - - 5 μs LPC:normal *2*3 - - 5 μs LPC:low power *1*3 - - 7 μs LPC:low power *2*3 Carry output delay time POL/STB setup time Output delay time *1 *2 *3 tdout CL=15pF The value is specified when the drive voltage value reaches the target output voltage level of 90%. The value is specified when the drive voltage value reaches the target output voltage level of 6-bit accuracy. Output load condition: R1=R2=R3=10kΩ, C1=C2=C3=20pF Output R1 R2 R3 (Test Probe) C1 C2 C3 Vcom=AVSS www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 4/14 2010.10 - Rev.A Technical Note BU95306 AVDD AVSS LPC0,LPC1 ・・・・・・・・・・・・・・・・・ Output Buffer 2 OREP2 IREP2 ・・・・・・・・・・・・・・・・・ OREP1 IREP1 V0 ～V13 POL Y640 Y641 Y642 Y1 Y2 Y3 ●Block diagram D/A Converter 14 6 6 6 6 6 6 ・・・・・・・・・・・・・・・・・ Level Shifter 6 6 6 Data Latch STB 6 6 6 INV Latch D20P/N～D22P/N 6 6 6 ・・・・・・・・・・・・・・・・・ Data Register RSDS Rx D00P/N～D02P/N D10P/N～D12P/N 6 6 6 ・・・・・・・・・・・・・・・・・ 214 bit Bi-directional Shift Register 2 CLKP/N SFTR SEL1, SEL0 R/L DVDD DVSS SFTL Fig.1 Block diagram www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 5/14 2010.10 - Rev.A Technical Note BU95306 ●Pin configuration IREP2 OREP2 AVSS AVDD DVSS DVDD SFTL D22P D22N D21P D21N D20P D20N D12P D12N D11P D11N D10P D10N DVDD LPC0 R/L V15 V14 V13 V12 V11 V10 V9 V8 AVDD AVSS V7 V6 V5 V4 V3 V2 V1 V0 DVSS TEST0 CLKP CLKN STB POL INV D02P D02N D01P D01N D00P D00N SEL1 SEL0 SFTR DVDD LPC1 DVSS AVSS AVDD OREP1 IREP1 Y642 Y641 Y640 ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ BU95306 ・ ・ ・ Top View ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ Y3 Y2 Y1 ↓ BUMP BUMP IC Fig.2 Pin configuration (Top View) www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 6/14 2010.10 - Rev.A Technical Note BU95306 ●Pin Descriptions Pin Name In/Out Active Descriptions TM D00P/N~D02P/N D10P/N~D12P/N D20P/N~D22P/N In RSDS input terminals of display data Differential The 3-bit differential input pairs generate the internal 6-bit data through the comparison between DXXP and DXXN. CLKP/N In Differential Out - R/L In - SEL0 SEL1 In - LPC0 LPC1 In H SFTR In/Out H SFTL In/Out H STB In INV In H V0~V15 In - POL In - IREP1,2 In - Repair amplifier input OREP1,2 Out - Repair amplifier output AVDD In - Power supply for driver block AVSS In - Ground for AVDD DVDD In - Power supply for digital block DVSS In - Ground for DVDD Y1~Y642 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. The RSDSTM clock input pair generate the internal shift clock through the comparison between CLKP and CLKN. Driver outputs for D/A converted 64 gray scale analog voltage. The shift direction of internal shift register is controlled by this pin as shown below. R/L=H : Right shift SFTR→Y1→Y642→SFTL R/L=L : Left shift SFTL→Y642→Y1→SFTR The output channel number is controlled by this pin as shown below. Number of effective SEL1 SEL0 Invalid output terminal output terminal H H 600 Y301~Y342 become Hi-Z H L 618 Y310~Y333 become Hi-Z L H 630 Y316~Y327 become Hi-Z L L 642 (default) This pin is pulled down to the DVSS inside the IC. Low power control pin LPC1 LPC0 power condition H H Strong power H L Normal power L H Ultra-low power L L Low power(default). This pin is pulled down to the DVSS inside the IC. SFTR=H:Right shift start pulse input terminal in cascade connection. SFTR=L:Carry output terminal in cascade connection. SFTL=H:Carry output terminal in cascade connection. SFTL=L:Left shift start pulse input terminal in cascade connection. The data in the data register are transferred to the data latch at the rising edge of STB, then the gray scale voltages are output from the buffer at the falling edge of STB. Terminal to specify inverting or non-inverting of display data INV:H : Input data are inverted in the IC. INV:L : Input data are not inverted. Input for the γ-correction reference voltage The following external reference voltages are input. At the rising edge of STB, the state of POL are transferred to the driver. POL=H : The reference voltage for odd number outputs are V0 to V7 and those for even number outputs are V8 to V15. POL=L : The reference voltage for odd number outputs are V8 to V15 and those for even number outputs are V0 to V7 7/14 2010.10 - Rev.A Technical Note BU95306 ●Relationship between Input Data and Output Terminals R/L=H (Right Shift) First Data Last → D00P~D02N D10P~D12N D20P~D22N … D00P~D02N D10P~D12N D20P~D22N Y1 Y2 Y3 … Y640 Y641 Y642 Output R/L=L (Left Shift) First Data Output Last → D00P~D02N D10P~D12N D20P~D22N … D00P~D02N D10P~D12N D20P~D22N Y640 Y641 Y642 … Y1 Y2 Y3 ●Relationship between R/L , SFTR , SFTL and Output Direction R/L pin controls the shift direction of the internal shift resistor as shown below. Terminal Right Shift Mode Left Shift Mode R/L “H” “L” SFTR Input Output SFTL Output Input Output direction Y1,Y2,Y3→Y640,Y641,Y642 Y642,Y641,Y640→Y3,Y2,Y1 ●Relationship between POL and Output Polarity POL Y1 *1 “H” + *1 “L” -*1 Y2 - + Y3 + - Y4 - + Y5 + - Y6 - + ・ ・ ・ ・ ・ ・ Y637 + - Y638 - + Y639 + - Y640 - + Y641 + - Y642 - + +: The reference voltage are V0~V7 -: The reference voltage are V8~V15 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 8/14 2010.10 - Rev.A Technical Note BU95306 ●Relationship between Input Data and Output Voltage The LCD driver output voltages are determined by the input data and 16γ-corrected power supply. 0.1V≦V15≦V14≦V13≦V12≦V11≦V10≦V9≦V8≦0.5AVDD 0.5 AVDD≦V7≦V6≦V5≦V4≦V3≦V2≦V1≦V0≦AVDD -0.1V V1(upper side:00) V2(upper side:16) V3(upper side:20) V4(upper side:24) V5(upper side:32) V6(upper side:56) V7(upper side:63) V8(lower side:63) V9(lower side:56) V10(lower side:32) V11(lower side:24) V12(lower side:20) V13(lower side:16) 00 16 20 24 Fig.3 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 32 56 V14(lower side:00) 63 Input data - γ correction curve 9/14 2010.10 - Rev.A Technical Note BU95306 ●γ correction Power Supply Circuit 16 external γ-corrected power supply is connected to ladder resistors inside IC. IC Internal Circuit V0 RS0 = 476Ω V1 RS1 = 7,523Ω V2 RS2 = 705Ω V3 RS3 = 573Ω V4 RS4 = 981Ω V5 RS5 = 2,433Ω V6 External γ-corrected power supply RS6 = 2,819Ω V7 V8 RS7 = 3,290Ω V9 RS8 = 2,916Ω V10 RS9 = 933Ω V11 RS10 = 543Ω V12 RS11 = 669Ω V13 RS12 = 6,678Ω V14 RS13 = 392Ω V15 Fig.4 www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. γ correction power supply circuit 10/14 2010.10 - Rev.A Technical Note BU95306 ●RSDSTM data timing thd2 thd1 thd1 tsu2 tsu1 tsu1 CLKP/N SFTR D00P/N Y1 (0) Y1 (1) Y4 (0) Y4 (1) Y7 (0) Y7 (1) D01P/N Y1 (2) Y1 (3) Y4 (2) Y4 (3) Y7 (2) Y7 (3) D02P/N Y1 (4) Y1 (5) Y4 Y4 Y7 (4) (5) (4) Y7 (5) D10P/N Y2 (0) Y2 (1) Y5 (0) Y5 (1) Y8 (0) Y8 (1) D11P/N Y2 Y2 (3) Y5 (2) Y5 (3) Y8 (2) (2) Y8 (3) D12P/N (4) Y2 (5) Y5 (4) Y5 (5) Y2 Y8 (4) Y8 (5) D20P/N Y3 Y3 (1) Y6 (0) (0) Y6 (1) D21P/N Y3 (2) Y3 (3) Y6 (2) Y6 (3) Y9 (2) Y9 (3) D22P/N Y3 (4) Y3 (5) Y6 (4) Y6 (5) Y9 (4) Y9 (5) Y9 (0) Y9 (1) Fig.5 RSDSTM data timing www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 11/14 2010.10 - Rev.A © 2010 ROHM Co., Ltd. All rights reserved. www.rohm.com 12/14 Yout POL STB 1 2 th 0V(DVSS) INVALID tWSFT tsu2 thd2 SFTL output (SFTR output) (SFTL input) SFTR input -DXXN DXXP -CLKN CLKP tw VDIFE tl VCM EVEN ODD tsu1 thd1 tsu1 thd1 3 214 tdc EVEN ODD tdc EVEN 215 ODD tsp tLDT Last Data Hi-Z*1 tSTB-CLK 2 tdout 3 Share*2 *1: Hi-Z period = tSTB-CLK + tWSTB + 2CLK period *2: share period = tWSTB 1CLK period tWSTB tSTB-SFT INVALID tSTB-CLK 1 BU95306 Technical Note ●Timing chart Fig.6 Timing chart 2010.10 - Rev.A Technical Note BU95306 ●Start pulse timing 2CLK period over CLKP SFTR input (SFTL) 1st 2nd Invalid DATA 1(E) 1(O) 2(E) 2(O) When the start pulse (SFTR, SFTL) is input two times, the data is sampled based on the second start pulse. ●Power Supply Sequence Maintain the following power supply order to prevent the device from being destroyed. Turn on power order : DVDD → Input signal → AVDD, V0~V15 Turn off power order : AVDD, V0~V15 → Input signal → DVDD Voltage AVDD V0～V15 DVDD Input signal DVSS, AVSS t ●Notes for use 1. When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow instantaneously. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of connections. 2. For ICs with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of wiring. www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. 13/14 2010.10 - Rev.A Technical Note BU95306 ●Ordering part number B U Part No. 9 5 3 0 6 - Part No. S R Reel packing specification SR: A pattern side is an inner arrow. The output side is the right side. SL: A pattern side is an inner arrow. The output side is the left side. BR: A pattern side is an outside arrow. The output side is the right side. BL: A pattern side is an outside arrow. The output side is the left side. COF48 <Tape dimensions> www.rohm.com © 2010 ROHM Co., Ltd. All rights reserved. <Packing specifications> 14/14 2010.10 - Rev.A Notice Notes No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). 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