FMS6501 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Features Description ■ 12 x 9 Crosspoint Matrix The FMS6501 switch matrix provides flexible options for today’s video applications. The 12 inputs that can be routed to any of nine outputs. Each input can be routed to one or more outputs, but only one input may be routed to any one output. The input to output routing is controlled via an I2C™-compatible digital interface. ■ Supports SD, PS, and HD 1080i/1080p Video ■ Input Clamp / Bias Circuitry ■ AC or DC-Coupled Inputs ■ AC or DC-Coupled Outputs ■ Dual-Load (75Ω) Output Drivers with High-Impedance ■ ■ ■ ■ ■ Disable One-to-One or One-to-Many Input to Output Switching Programmable Gain: +6, +7, +8, or +9dB I2CTM Compatible Digital Interface, Standard Mode 3.3V or 5V Single-Supply Operation Lead-Free SSOP-28 Package Each input supports an integrated clamp option to set the output sync tip level of video with sync to ~300mV. Alternatively, the input may be internally biased to center signals without sync (Chroma, Pb, Pr) at ~1.25V. These DC output levels are for the 6dB gain setting. Higher gain settings increase the DC output levels accordingly. The input clamp / bias mode is selected via I2C. Unused outputs may be powered down to reduce power dissipation. Applications ■ Cable and Satellite Set-Top Boxes ■ TV and HDTV Sets ■ A/V Switchers ■ Personal Video Recorders (PVR) ■ Security / Surveillance ■ Video Distribution ■ Automotive (In-Cabin Entertainment) Ordering Information Part Number Pb-Free Temperature Range Package Container Quantity FMS6501MSA28 Yes -40°C to 85°C SSOP-28 Rail 47 FMS6501MSA28X Yes -40°C to 85°C SSOP-28 Reel 2000 © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers April 2007 IN1 C/B IN2 C/B IN12 C/B SDA SCL ADDR Programmable Gain 6, 7, 8, or 9dB VCC (2) GND (2) OUT1 OUT2 OUT9 Programmable Enable/Disable Figure 1. FMS6501 Block Diagram © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 2 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Block Diagram IN1 1 28 OUT1 IN2 2 27 OUT2 IN3 3 26 OUT3 IN4 4 25 OUT4 FAIRCHILD Pin# Name Type Description 1 IN1 Input Input, channel 1 2 IN2 Input Input, channel 2 3 IN3 Input Input, channel 3 4 IN4 Input Input, channel 4 5 IN5 Input Input, channel 5 6 IN6 Input Input, channel 6 24 OUT5 23 OUT6 7 VCC Input Positive power supply 7 22 VCCO 8 GND Input Must be tied to ground GND 8 21 GNDO 9 IN7 Input Input, channel 7 IN7 9 20 OUT7 10 IN8 Input Input, channel 8 11 IN9 Input Input, channel 9 IN8 10 19 OUT8 12 IN10 Input Input, channel 10 IN9 11 18 OUT9 13 IN11 Input Input, channel 11 IN10 12 17 SDA 14 IN12 Input Input, channel 12 IN11 13 16 SCL 15 ADDR Input Selects I2C address. “0” = 0x06 (0000 0110), ‘1” = 0x86 (1000 0110) IN12 14 15 ADDR 16 SCL Input Serial clock for I2C port 17 SDA Input Serial data for I2C port 18 OUT9 Output Output, channel 9 19 OUT8 Output Output, channel 8 20 OUT7 Output Output, channel 7 21 GNDO Input Must be tied to ground 22 VCCO Input Positive power supply for output drivers 23 OUT6 Output Output, channel 6 24 OUT5 Output Output, channel 5 25 OUT4 Output Output, channel 4 26 OUT3 Output Output, channel 3 27 OUT2 Output Output, channel 2 28 OUT1 Output Output, channel 1 IN5 5 IN6 6 VCC FMS6501 28L SSOP Figure 2. Pin Configuration © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 3 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Pin Assignments Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter Min. Max. Unit DC Supply Voltage -0.3 6.0 V Analog and Digital I/O -0.3 Vcc + 0.3 V 40 mA Output Current Any One Channel, Do Not Exceed Reliability Information Symbol TJ TSTG TL ΘJA Parameter Min. Typ. Junction Temperature Storage Temperature Range -65 Lead Temperature (Soldering, 10 seconds) Thermal Resistance, JEDEC Standard Multilayer Test Board, Still Air Max. Unit 150 °C 150 °C 300 °C 50 °C/W Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol TA VCC Parameter Min. Operating Temperature Range Typ. Max. Unit 85 °C 5.000 5.250 V -40 Supply Voltage Range 3.135 Electrostatic Discharge Protection Symbol Parameter Value Unit HBM Human Body Model 5 kV CDM Charged Device Model 2 kV © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 4 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Absolute Maximum Ratings The I2C-compatible interface is used to program output enables, input to output routing, input clamp / bias, and output gain. The I2C address of the FMS6501 is 0x06 (0000 0110) with the ability to offset it to 0x86 (1000 0110) by tying the ADDR pin high. same input channel for one-to-many routing. When the outputs are disabled, they are placed in a high-impedance state. This allows multiple FMS6501 devices to be paralleled to create a larger switch matrix. Typical output power-up time is less than 500ns. Both data and address data, of eight bits each, are written to the I2C address to access all the control functions. The clamp / bias control bits are written to their own internal address, since they should always remain the same regardless of signal routing. They are set based on the input signal connected to the FMS6501. There are separate internal addresses for each output. Each output’s address includes bits to select an input channel, adjust the output gain, and enable or disable the output amplifier. More than one output can select the All undefined addresses may be written without effect. Output Control Register Contents and Defaults Control Name Width Type Default Bit(s) Enable 1 bit Write 0 7 Description Channel Enable: 1=Enable, 0=Power Down(1) Gain 2 bits Write 0 6:5 Channel Gain: 00=6dB, 01=7dB, 10=8dB, 11=9dB Inx 5 bits Write 0 4:0 Input selected to drive this output: 00000=OFF(2), 00001=IN1, 00010=IN2... 01100=IN12 Notes: 1. Power down places the output in a high-impedance state so multiple FMS6501 devices may be paralleled. Power down also de-selects any input routed to the specified output. 2. When all inputs are OFF, the amplifier input is tied to approximately 150mV and the output goes to approximately 300mV with the 6dB gain setting. Output Control Register MAP Register Register Name Address Bit 7 Bit 6 Bit5 Bit4(1) Bit3 Bit2 Bit1 Bit0 OUT1 0x01 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT2 0x02 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT3 0x03 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT4 0x04 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT5 0x05 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT6 0x06 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT7 0x07 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT8 0x08 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 OUT9 0x09 Enable Gain1 Gain0 IN4 IN3 IN2 IN1 IN0 Notes: 1. IN4 is provided for forward compatibility and should always be written as ‘0’ in the FMS6501. Clamp Control Register Contents and Defaults Control Name Width Type Default Bit(s) Description Clmp 1 bit Write 0 7:0 Clamp / Bias selection: 1 = Clamp, 0 = Bias Clamp Control Register Map Register Name Register Address Bit 7 Bit 6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CLAMP1 0x1D Clmp8 Clmp7 Clmp6 Clmp5 Clmp4 Clmp3 Clmp2 Clmp1 CLAMP2 0x1E Resv’d Resv’d Resv’d Resv’d Clmp12 Clmp11 Clmp10 Clmp9 © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 5 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Digital Interface TA = 25°C, Vcc = 5V, VIN = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with 0.1µF, unused inputs AC-terminated through 75Ω to GND, all outputs AC coupled with 220µF into 150Ω loads, referenced to 400kHz, unless otherwise noted. Symbol ICC Parameter Conditions Supply Current1 Min. No load, all outputs enabled VOUT Video Output Range ROFF Off Channel Output Impedance Output disabled 1 Typ. Max Units 80 100 mA 2.8 Vpp 3.0 kΩ Vclamp DC Output Level Clamp mode 0.2 0.3 0.4 V Vbias DC Output Level1 Bias mode 1.15 1.25 1.35 V Power Supply Rejection Ratio All channels, DC PSRR 50 dB Notes: 1. 100% tested at 25°C. AC Electrical Characteristics TA = 25°C, VCC = 5V, VIN = 1Vpp, input bias mode, one-to-one routing, 6dB gain, all inputs AC coupled with 0.1µF, unused inputs AC-terminated through 75Ω to GND, all outputs AC coupled with 220µF into 150Ω loads, referenced to 400kHz, unless otherwise noted. Symbol AVSD AVSTEP Parameter Channel Gain Gain(1) Error Step(1) Conditions Min. Typ. Max Units All Channels, All Gain Settings, DC -0.2 0 +0.2 dB All Channels, DC 0.9 1.0 1.1 dB f+1dB 1dB Peaking Bandwidth VOUT = 1.4Vpp 65 MHz f-1dB -1dB Bandwidth VOUT = 1.4Vpp 90 MHz fC -3dB Bandwidth VOUT = 1.4Vpp 115 MHz dG Differential Gain 3.58MHz 0.1 % dP Differential Phase 3.58MHz 0.2 deg THDSD SD Output Distortion VOUT = 1.4Vpp, 5MHz 0.05 % THDHD HD Output Distortion VOUT = 1.4Vpp, 22MHz 0.6 % XTALK1 Input Crosstalk -72 dB XTALK2 Input Crosstalk -50 dB XTALK3 Output Crosstalk -68 dB XTALK4 Output Crosstalk 1MHz, VOUT = 2Vpp(2) 15MHz, VOUT = 2Vpp(2) 1MHz, VOUT = 2Vpp(3) 15MHz, VOUT = 2Vpp(3) -61 dB -45 dB NTC-7 Weighting, 4.2MHz LP, 100kHz HP 73 dB 400kHz to 100MHz, Input Referred 20 nV/rtHz 300 ns XTALK5 Multi-Channel Crosstalk SNRSD Signal-to-Noise Ratio(5) VNOISE Channel Noise AMPON Amplifier Recovery Time Standard Video, VOUT = 2Vpp Post I 2C Programming (4) Notes: 1. 100% tested at 25°C. 2. Adjacent input pair to adjacent output pair. Interfering input is through an open switch. 3. Adjacent input pair to adjacent output pair. Interfering input is through a closed switch. 4. Crosstalk of eight synchronous switching outputs onto single, asynchronous switching output. 5. Signal-to-Noise Ration (SNR) = 20 * log (714mV / rms noise). © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 6 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers DC Electrical Characteristics TA = 25°C and VCC = 5V unless otherwise noted. Symbol Vil Vih Conditions Min. (1) Parameter SDA, SCL, ADDR (1) SDA, SCL, ADDR Digital Input Low Digital Input High Typ. Max Units 0 1.5 V 3.0 Vcc V fscl Clock Frequency SCK 100 kHz tr Input Rise Time 1.5V to 3V 1000 ns tf Input Fall Time 1.5V to 3V 300 ns 4.7 µs tlow Clock Low Period thigh Clock High Period 4.0 µs tSU,DAT Data Set-up Time 300 ns tHD,DAT Data Hold Time 0 ns tSU,STO Set-up Time from Clock High to Stop 4 µs 4.7 µs 4 µs 4.7 µs tBUF Start Set-up Time Following a Stop tHD,STA Start Hold Time tSU,STA Start Set-up Time Following Clock Low to High Notes: 1. 100% tested at 25°C. SDA tBUF tf tLOW SCL tHD,STA tr t HD,DAT tSU,DAT t HIGH SDA tSU,STA tSU,STO Figure 3. I2C Bus Timing © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 7 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers I2C BUS Characteristics Operation Bit Transfer The I2C-compatible interface conforms to the I2C specification for Standard Mode. Individual addresses may be written. There is no read capability. The interface consists of two lines. These is a serial data line (SDA) and a serial clock line (SCL), both of which must be connected to a positive supply through an external resistor. Data transfer may be initiated only when the bus is not busy. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Changes in the line during this time are interpreted as a control signal. SCL SDA Data line stable; data valid Change of data allowed Figure 4. Bit Transfer Start and Stop Conditions The data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as START condition SCL (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as STOP condition (P). S P SDA STOP condition START condition Figure 5. Definition of START and STOP conditions © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 8 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers I2C Interface The data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a high-level signal put on the bus by the transmitter, during which the master generates an extra acknowledge-related clock pulse. A slave receiver must generate an acknowledge after the reception of each byte. A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. START condition clock pulse for acknowledgement SCL FROM MASTER 1 2 8 9 DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER Figure 6. Acknowledgement on the I2C Bus I2C Bus Protocol Before any data is transmitted on the I2C bus, the device that should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C bus configuration for a data write to the FMS6501 is shown in Figure 5. 1 9 1 9 SCL SDA A6 A5 START BY MASTER A4 A3 A2 A1 A0 FRAME1 R/W D7 D6 ACK. BY FMS6501 D5 D4 D3 D2 D1 D0 ACK. BY FMS6501 FRAME 2 ADDRESS POINTER REGISTER BYTE SERIAL BUS ADDRESS BYTE 1 9 SCL (CONTINUED) SDA (CONTINUED) D7 D6 D5 D4 D3 D2 FRAME 3 DATA BYTE D1 D0 ACK. BY FMS6501 STOP BY MASTER Figure 7. Write a Register Address to the Pointer Register, Then Write Data to the Selected Register © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 9 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Acknowledge Input Clamp / Bias Circuitry Figure 9 shows the bias mode input circuit and internally controlled voltage at the input pin for AC-coupled inputs. The FMS6501 accommodates AC- or DC-coupled inputs. Lowest voltage set to 625mV Internal clamping and bias circuitry are provided to support AC-coupled inputs. These are selectable through the CLMP bits via the I2C compatible interface. Video source must be AC-coupled For DC-coupled inputs, the device should be programmed to use the 'bias' input configuration. In this configuration, the input is internally biased to 625mV through a 100kΩ resistor. Distortion is optimized with the output levels set between 250mV above ground and 500mV below the power supply. These constraints, along with the desired channel gain, need to be considered when configuring the input signal levels for input DC coupling. Figure 9. Bias Mode Input Circuit Output Configuration The FMS6501 outputs may be either AC or DC coupled. Resistive output loads can be as low as 75Ω, representing a dual, doubly terminated video load. High impedance, capacitive loads up to 20pF can also be driven without loss of signal integrity. For standard 75Ω video loads, a 75Ω matching resistor should be placed in series to allow for a doubly terminated load. DC-coupled outputs should be connected as shown in Figure 10. If symmetric AC-coupled input signals are used (chroma,Pb,Pr,Cb,Cr), the bias circuit described above can be used to center them within the input common range. The average DC value at the output is approximately 1.27V with a 6dB gain setting. This value changes depending upon the selected gain setting. Clamp Voltage Bias Voltage 6dB 300mV 1.27V 7dB 330mV 1.43V 8dB 370mV 1.60V 9dB 420mV 1.80V 75 FMS6501 Output Amplifier If multiple low-impedance loads are DC coupled, increased power and thermal issues need to be addressed. In this case, the use of a multilayer board with a large ground plane to help dissipate heat is recommended. If a two-layer board is used under these conditions, an extended ground plane directly under the device is recommended. This plane should extend at least 0.5 inches beyond the device. PC board layout issues are covered in the Layout Considerations section. Lowest voltage set to 125mV 0.1µF 75 Figure 10. DC-Coupled Load Connection Figure 8 shows the clamp mode input circuit and the internally controlled voltage at the input pin for AC-coupled inputs. Video source must be AC-coupled 0.1µF 75 With AC-coupled inputs, the FMS6501 uses a simple clamp rather than a full DC-restore circuit. For video signals with and without sync (Y,CV,R,G,B), the lowest voltage at the output pins is clamped to approximately 300mV above ground when the 6dB gain setting is selected. Gain Setting FMS6501 Input Bias FMS6501 Input Clamp 75 AC-coupled loads should be configured as in Figure 11: FMS6501 Output Amplifier Figure 8. Clamp Mode Input Circuit 75 220µF 75 Figure 11. AC-Coupled Load Connection © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 10 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Applications Information For input crosstalk, the switch is open. All inputs are in bias mode. Channel 1 input is driven with a 1Vpp signal, while all other inputs are AC terminated with 75Ω. All outputs are enabled and crosstalk is measured from IN1 to any output. Each of the outputs can be independently powered down and placed in a high-impedance state with the ENABLE bit. This function can be used to mute video signals, to parallel multiple FMS6501 outputs, or to save power. When the output amplifier is disabled, the high-impedance output presents a 3kΩ load to ground. The output amplifier typically enters and recovers from the powerdown state in less than 300ns after being programmed. For output crosstalk, the switch is closed. Crosstalk from OUT1 to any output is measured. Crosstalk from multiple sources into a given channel was measured with the setup shown in Figure 6. Input IN1 is driven with a 1Vpp pulse source and is connected to outputs Out1 to Out8. Input In9 is driven with a secondary, asynchronous, gray-field video signal, and is connected to Out9. All other inputs are AC terminated with 75Ω. Crosstalk effects on the gray field are measured and calculated with respect to a standard 1Vpp output measured at the load. When an output channel is not connected to an input, the input to that channel’s amplifier is forced to approximately 150mV. The output amplifier is still active unless specifically disabled by the I2C interface. Voltage output levels depend on the programmed gain for that channel. Crosstalk If not all inputs and outputs are needed, avoid using adjacent channels, where possible, to reduce crosstalk. Disable all unused channels to further reduce crosstalk and power dissipation. Crosstalk is an important consideration when using the FMS6501. Input and output crosstalk are defined to represent the two major coupling modes in a typical application. Input crosstalk is crosstalk in the input pins and switches when the interfering signal drives an open switch. It is dominated by inductive coupling in the package lead frame between adjacent leads. It decreases rapidly as the interfering signal moves farther away from the pin adjacent to the input signal selected. Output crosstalk is coupling from one driven output to another active output. It decreases with increasing load impedance, as it is caused mainly by ground and power coupling between output amplifiers. If a signal is driving an open switch, its crosstalk is mainly input crosstalk. If it is driving a load through an active output, its crosstalk is mainly output crosstalk. TERMINATION Bias IN1 IN1 driven with SD videio 1Vpp IN9 driven with asynchronous SD video 1Vpp IN2-8 + IN10-12 driven with AC term to GND with 75 IN9 Input and output crosstalk measurements are performed with the test configuration shown in Figure 12. IN12 Bias Bias TERMINATION Bias Gain = 6dB OUT1 = 2.0Vpp IN1 IN2 - IN12 are AC-Term to ground with 75 IN1 = 1Vpp Measure crosstalk from Channels 1-8 into Channel 9 OUT1 OUT9 Figure 13. Test Configuration for Multi-Channel Crosstalk Open switch for input crosstalk Close switch for output crosstalk IN12 Bias Gain = 6dB OUT1 = 2.0Vpp Input crosstalk from IN1 to OUTx OUT1 Output crosstalk from OUT1 to OUTx OUT9 Figure 12. Test Configuration for Crosstalk © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 11 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Thermal issues are significantly reduced with AC-coupled outputs, alleviating special PC layout requirements. FMS6501 Video Switch Matrix Applications General layout and supply bypassing play major roles in high-frequency performance and thermal characteristics. Fairchild offers a demonstration board, FMS6501DEMO, to use as a guide for layout and to aid in device testing and characterization. The FMS6501DEMO is a 4-layer board with a full power and ground plane. For optimum results, follow the steps below as a basis for high frequency layout. The increased demand for consumer multimedia systems has created a challenge for system designers to provide cost-effective solutions to capitalize on the growth potential in graphics display technologies. These applications requires cost-effective video switching and filtering solutions to deploy high-quality display technologies rapidly and effectively to the target audience. Areas of specific interest include HDTV, media centers, and automotive “infotainment” (includes navigation, in-cabin entertainment, and back-up camera). In all cases, the advantages an integrated video switch matrix provides are high quality video switching specific to the application, as well as video input clamps and on-chip, lowimpedance output cable drivers with switchable gain. ■ Include 10µF and 0.1µF bypass capacitors. ■ Place the 10µF capacitor within 0.75 inches of the power pin. ■ Place the 0.1µF capacitor within 0.1 inches of the power pin. ■ Connect all external ground pins as tightly as possible, preferably with a large ground plane under the package. ■ Layout channel connections to reduce mutual trace inductance. ■ Minimize all trace lengths to reduce series inductances. If routing across a board, place device such that longer traces are at the inputs rather than the outputs. If using multiple, low-impedance, DC-coupled outputs, special layout techniques may be employed to help dissipate heat. Generally the largest application for a video switch is for the front end of an HDTV, where it takes multiple inputs and routes them to appropriate signal paths (main picture and picture in picture - PiP). These are normally routed into ADCs followed by decoders. There are many different technologies for HDTV; including LCD, Plasma, and CRT, with similar analog switching circuitry. An example of a HDTV application is shown in Figure 14. This system combines a video switch matrix and two three-channel switchable anti-aliasing filters. There are two three-channel signal paths in the system; one for the main picture, the other for “Picture in Picture” (PiP). If a multilayer board is used, a large ground plane directly under the device helps reduce package case temperature. VIPDEMOTM Control Software The FMS6501 is configured via an I2C-compatible digital interface. To facilitate demonstration, Fairchild Semiconductor had developed the VIPDEMOTM GUI-based control software to write to the FMS6501 register map. This software is included in the FMS6501DEMO kit. Also included is a parallel port I2C adapter and an interface cable to connect to the demo board. Besides using the full FMS6501 interface, the VIPDEMOTM can also be used to control single-register read and writes for I2C. For dual-layer boards, an extended plane can be used. Worst-case, additional die power due to DC loading can be estimated at (Vcc2/4Rload) per output channel. This assumes a constant DC output voltage of Vcc/2. For 5V Vcc with a dual-DC video load, add 25/(4*75) = 83mW, per channel. Figure 14. HDTV Application using the FMS6501 Video Switch Matrix © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 12 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Layout Considerations FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers Physical Dimensions Dimensions are in millimeters unless otherwise noted. SSOP-28 Figure 15. FMS6501 28-Lead Small Scale Outline Package (SSOP) © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4 www.fairchildsemi.com 13 FMS6501 — 12 Input / 9 Output Video Switch Matrix with Input Clamp, Input Bias Circuitry, and Output Drivers 14 www.fairchildsemi.com © 2004 Fairchild Semiconductor Corporation FMS6501 Rev. 1.0.4