LINER LTNS 24-bit no latency adc with differential input and reference in msop Datasheet

LTC2411/LTC2411-1
24-Bit No Latency ∆ΣTM ADC
with Differential Input and
Reference in MSOP
DESCRIPTIO
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FEATURES
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24-Bit ADC in an MS10 Package
Low Supply Current (200µA in Conversion Mode
and 4µA in Autosleep Mode)
Differential Input and Differential Reference
with GND to VCC Common Mode Range
2ppm INL, No Missing Codes
4ppm Full-Scale Error and 1ppm Offset
0.29ppm Noise
No Latency: Digital Filter Settles in a Single Cycle.
Each Conversion Is Accurate, Even After an
Input Step
Single Supply 2.7V to 5.5V Operation
Internal Oscillator—No External Components
Required
110dB Min, Pin Selectable 50Hz/60Hz Notch Filter
(LTC2411)
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
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APPLICATIO S
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain Gauge Transducers
Instrumentation
Data Acquisition
Industrial Process Control
6-Digit DVMs
The LTC®2411/LTC2411-1 are 2.7V to 5.5V micropower
24-bit differential ∆Σ analog-to-digital converters with an
integrated oscillator, 2ppm INL and 0.29ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the LTC2411 can be configured for better than
110dB differential mode rejection at 50Hz or 60Hz ±2%,
and the LTC2411-1 can provide better than 87dB input
differential mode rejection over the range of 49Hz to
61.2Hz, or they can be driven by an external oscillator for
a user-defined rejection frequency. The LTC2411 and
LTC2411-1 are identical when driven by an external
oscillator. The internal oscillator requires no external
frequency setting components.
The converters accept any external differential reference
voltage from 0.1V to VCC for flexible ratiometric and
remote sensing measurement configurations. The fullscale differential input range is from – 0.5VREF to 0.5VREF.
The reference common mode voltage, VREFCM, and the
input common mode voltage, VINCM, may be independently set anywhere within the GND to VCC range of the
LTC2411/LTC2411-1. The DC common mode input rejection is better than 140dB.
The LTC2411/LTC2411-1 communicate through a flexible
3-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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TYPICAL APPLICATIO
VCC
2.7V TO 5.5V
1µF
VCC
1µF
1
VCC
FO
10
LTC2411/
LTC2411-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
IN –
CS
5
6
SCK
= INTERNAL OSC/50Hz REJECTION (LTC2411)
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
BRIDGE
IMPEDANCE
100Ω TO 10kΩ
9
8
7
GND
2
3-WIRE
SPI INTERFACE
4
5
IN
1
REF + VCC
+
IN –
3
9 SCK
8 SDO
LTC2411/
LTC2411-1
7 CS
REF – GND
6
3-WIRE
SPI
INTERFACE
FO
10
2411 TA02
2411 TA01
1
LTC2411/LTC2411-1
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Pins Voltage
to GND .................................... – 0.3V to (VCC + 0.3V)
Reference Input Pins Voltage
to GND .................................... – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2411C ............................................... 0°C to 70°C
LTC2411I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART NUMBER
LTC2411CMS
LTC2411IMS
LTC2411-1CMS
LTC2411-1IMS
TOP VIEW
VCC
REF +
REF –
IN +
IN –
1
2
3
4
5
10
9
8
7
6
FO
SCK
SDO
CS
GND
MS10 PART MARKING
MS10 PACKAGE
10-LEAD PLASTIC MSOP
LTNS
LTNT
LTWV
LTNN
TJMAX = 125°C, θJA = 120°C/W
Consult LTC Marketing for parts specified with wider operating temperature
ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
0.1V ≤ VREF ≤ VCC, – 0.5 • VREF ≤ VIN ≤ 0.5 • VREF (Note 5)
Integral Nonlinearity
4.5V ≤ VCC ≤ 5.5V, REF + = 2.5V, REF– = GND, VINCM = 1.25V (Note 6)
5V ≤ VCC ≤ 5.5V, REF + = 5V, REF – = GND, VINCM = 2.5V (Note 6)
REF + = 2.5V, REF – = GND, VINCM = 1.25V (Note 6)
Offset Error
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN + = IN – ≤ VCC (Note 14)
Offset Error Drift
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN + = IN – ≤ VCC
Positive Full-Scale Error
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.75REF +, IN – = 0.25 • REF +
Positive Full-Scale Error Drift
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.75REF +, IN – = 0.25 • REF +
Negative Full-Scale Error
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.25 • REF +, IN – = 0.75 • REF +
Negative Full-Scale Error Drift
2.5V ≤ REF + ≤ VCC, REF – = GND,
IN + = 0.25 • REF+, IN – = 0.75 • REF +
Total Unadjusted Error
4.5V ≤ VCC ≤ 5.5V, REF + = 2.5V, REF – = GND, VINCM = 1.25V
5V ≤ VCC ≤ 5.5V, REF + = 5V, REF– = GND, VINCM = 2.5V
REF + = 2.5V, REF – = GND, VINCM = 1.25V
Output Noise
5V ≤ VCC ≤ 5.5V, REF + = 5V, VREF – = GND,
GND ≤ IN – = IN + ≤ 5V, (Note 13)
2
MIN
●
TYP
MAX
24
UNITS
Bits
●
1
2
6
14
ppm of VREF
ppm of VREF
ppm of VREF
●
5
20
µV
20
●
4
nV/°C
12
0.04
●
4
0.04
3
3
6
1.45
ppm of VREF
ppm of VREF/°C
12
ppm of VREF
ppm of VREF/°C
ppm of VREF
ppm of VREF
ppm of VREF
µVRMS
LTC2411/LTC2411-1
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CO VERTER CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ REF + ≤ V
–
CC, REF = GND,
–
+
IN = IN ≤ 5V
MIN
TYP
●
130
140
Input Common Mode Rejection
60Hz ±2% (LTC2411)
2.5V ≤ REF+ ≤ VCC, REF – = GND,
GND ≤ IN – = IN + ≤ 5V, (Note 7)
●
140
dB
Input Common Mode Rejection
50Hz ±2% (LTC2411)
2.5V ≤ REF + ≤ VCC, REF – = GND,
GND ≤ IN – = IN + ≤ 5V, (Note 8)
●
140
dB
Input Common Mode Rejection
49Hz to 61.2Hz (LTC2411-1)
2.5V < REF + < VCC, REF – = GND,
GND < IN– = IN+ < VCC (Note 15)
●
140
dB
Input Normal Mode Rejection
60Hz ±2% (LTC2411)
(Note 7)
●
110
140
dB
Input Normal Mode Rejection
50Hz ±2% (LTC2411)
(Note 8)
●
110
140
dB
Input Normal Mode Rejection
49Hz to 61.2Hz (LTC2411-1)
(Note 15)
●
87
Reference Common Mode
Rejection DC
2.5V ≤ REF+ ≤ VCC, GND ≤ REF – ≤ 2.5V,
VREF = 2.5V, IN – = IN + = GND
●
130
Power Supply Rejection, DC
Power Supply Rejection, 60Hz ±2%
(LTC2411)
GND ≤
MAX
UNITS
dB
dB
140
dB
REF + = 2.5V, REF – = GND, IN – = IN + = GND
110
dB
REF + = 2.5V, REF –
= IN + = GND, (Note 7)
120
dB
Power Supply Rejection, 50Hz ±2% REF + = 2.5V, REF – = GND, IN – = IN + = GND, (Note 8)
(LTC2411)
120
dB
120
dB
REF + = 2.5V, REF – = GND, IN – = IN + = GND, (Note 15)
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Power Supply Rejection,
49Hz to 61.2Hz (LTC2411-1)
= GND, IN –
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN +
Absolute/Common Mode IN +
CONDITIONS
MIN
Voltage
●
GND – 0.3V
VCC + 0.3V
IN –
Absolute/Common Mode IN –
Voltage
●
GND – 0.3V
VCC + 0.3V
V
VIN
Input Differential Voltage Range
(IN + – IN –)
●
– VREF/2
VREF/2
V
REF +
Absolute/Common Mode REF + Voltage
●
0.1
VCC
V
REF –
Absolute/Common Mode REF – Voltage
●
GND
VCC – 0.1V
V
VREF
Reference Differential Voltage Range
(REF + – REF –)
●
0.1
VCC
V
CS (IN +)
IN + Sampling Capacitance
6
pF
CS
(IN –)
IN – Sampling Capacitance
6
pF
CS
(REF +)
REF + Sampling Capacitance
6
pF
CS (REF –)
REF – Sampling Capacitance
6
pF
IDC_LEAK
(IN +)
IN +
IDC_LEAK
(IN –)
IN –
IDC_LEAK
(REF +)
REF + DC Leakage Current
IDC_LEAK (REF –)
REF – DC Leakage Current
CS = VCC = 5.5V, REF – = GND
DC Leakage Current
DC Leakage Current
TYP
MAX
UNITS
V
CS = VCC
= 5.5V, IN + = GND
●
–10
1
10
nA
CS = VCC
= 5.5V, IN – = GND
●
–10
1
10
nA
CS = VCC
= 5.5V, REF +
●
–10
1
10
nA
●
–10
1
10
nA
= 5V
3
LTC2411/LTC2411-1
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
MIN
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = – 800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
Hi-Z Output Leakage
SDO
●
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5V
V
0.4
V
VCC – 0.5V
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
Sleep Mode
4
CONDITIONS
MIN
●
CS = 0V (Note 12)
CS = VCC (Note 12)
CS = VCC, 2.7V ≤ VCC ≤ 3.3V (Note 12)
●
●
TYP
2.7
200
4
2
MAX
UNITS
5.5
V
300
10
µA
µA
µA
LTC2411/LTC2411-1
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
fEOSC
External Oscillator Frequency Range
●
tHEO
External Oscillator High Period
●
tLEO
External Oscillator Low Period
●
tCONV
Conversion Time
FO = 0V (LTC2411)
FO = VCC (LTC2411)
FO = 0V (LTC2411-1)
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (LTC2411) (Note 10)
Internal Oscillator (LTC2411-1) (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
●
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
tHESCK
External SCK High Period
(Note 9)
●
250
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (LTC2411) (Notes 10, 12)
Internal Oscillator (LTC2411-1) (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
●
1.64
1.80
tDOUT_ESCK
External SCK 32-Bit Data Output Time (Note 9)
●
t1
CS ↓ to SDO Low Z
●
0
200
ns
t2
CS ↑ to SDO High Z
●
0
200
ns
t3
CS ↓ to SCK ↓
(Note 10)
●
0
200
ns
t4
CS ↓ to SCK ↑
(Note 9)
●
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
●
15
ns
t5
SCK Set-Up Before CS ↓
●
50
ns
t6
SCK Hold After CS ↓
●
●
●
●
●
MAX
UNITS
2.56
2000
kHz
0.25
390
µs
0.25
390
µs
130.86
133.53
136.20
157.03
160.23
163.44
143.78
146.71
149.64
20510/fEOSC (in kHz)
19.2
17.5
fEOSC/8
45
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified.
VREF = REF + – REF –, VREFCM = (REF + + REF –)/2;
VIN = IN + – IN –, VINCM = (IN + + IN –)/2.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
ms
ms
ms
ms
kHz
kHz
kHz
55
%
2000
kHz
250
ns
ns
1.67
1.70
1.83
1.86
256/fEOSC (in kHz)
ms
ms
ms
32/fESCK (in kHz)
ms
ns
220
●
(Note 5)
TYP
50
ns
ns
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: FO = 0V (internal oscillator) or fEOSC = 139800Hz ±2%
(external oscillator).
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LTC2411/LTC2411-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
3
1.5
2
1.0
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
10
1
TA = 25°C
0
–2
TA = –45°C
TA = –45°C
0
–0.5
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = GND
VCC = 5V
REF + = 2.5V
REF – = GND
VINCM = 2.5V
FO = GND
–1.0
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
1
1.5
2
2.5
–1.5
–1.25
–0.75
TA = 90°C
–0.25
0.25
VIN (V)
0.75
INL (ppm OF VREF)
INL (ppm OF VREF)
TA = 25°C
TA = 90°C
0.5
TA = –45°C
0
VCC = 5V
REF + = 2.5V
REF – = GND
VINCM = 2.5V
FO = GND
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5
VIN (V)
–1.5
–1.25
1
1.5
2
2.5
–0.75
TA = 90°C
1.25
4
2
–2
–4
–8
–0.25
0.25
VIN (V)
0.75
VCC = 2.7V
REF + = 2.5V
REF – = GND
VINCM = 1.25V
FO = GND
–10
–1.25
1.25
– 0.75
TA = –45°C
TA = 25°C
0.25
– 0.25
VIN (V)
0.75
RMS Noise
vs Input Differential Voltage
Long Term ADC Readings
1.0
ADC READING (ppm OF VREF)
GAUSSIAN
DISTRIBUTION
m = –0.647ppm
σ = 0.287ppm
0.5
0
–0.5
6
–1.0
4
–1.5
2
–2.0
1
2411 G07
0.5
VCC = 5V, VREF = 5V, VIN = 0V, VINCM = 2.5V,
FO = GND, TA = 25°C, RMS NOISE = 0.29ppm
RMS NOISE (ppm OF VREF)
16
0
1.25
2411 G06
2411 G01
Noise Histogram
0
0.5
–0.5
OUTPUT CODE (ppm OF VREF)
TA = 90°C
0
–6
2411 G04
NUMBER OF READINGS (%)
0.75
6
–1.0
6
0.25
– 0.25
VIN (V)
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
TA = 25°C
–2
–1.0
TA = 25°C
10
–0.5
–1.5
– 0.75
TA = –45°C
8
–1
0
–2.0
VCC = 2.7V
REF + = 2.5V
REF – = GND
VINCM = 1.25V
FO = GND
2411 G03
1.0
TA = –45°C
10,000 CONSECUTIVE
READINGS
14
VCC = 5V
= 5V
V
12 REF
VIN = 0V
= 2.5V
V
10 INCM
FO = GND
TA = 25°C
8
–4
–10
–1.25
1.25
1.5
0
–2
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
3
1
TA = 90°C
0
2411 G02
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
2
2
–8
2411 G01
VCC = 5V
REF + = 5V
REF – = GND
VINCM = 2.5V
FO = GND
4
–6
INL (ppm OF VREF)
–1
TA = 25°C
0.5
TUE (ppm OF VREF)
6
TA = 90°C
TUE (ppm OF VREF)
TUE (ppm OF VREF)
8
5 10 15 20 25 30 35 40 45 50 55 60
TIME (HOURS)
2411 G08
0.4
0.3
0.2
0.1
TA = 25°C
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = GND
0
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
2.5
2411 G09
LTC2411/LTC2411-1
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TYPICAL PERFOR A CE CHARACTERISTICS
RMS Noise vs Temperature
1.60
VCC = 5V
VIN = 0V
REF + = 5V FO = GND
–
REF = GND TA = 25°C
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
FO = GND
1.55
1.50
RMS NOISE (µV)
RMS NOISE (µV)
1.55
1.45
1.40
1.50
1.55
1.45
1.40
1.35
1.35
1.30
–1
0
1
3
2
VINCM (V)
5
4
1.30
–45 –30 –15
6
0 15 30 45 60
TEMPERATURE (°C)
75
1.35
1.30
VCC = 5V
REF + = 5V
REF – = GND
VIN = 0V
FO = GND
TA = 25°C
–0.2
–0.3
–0.4
–0.1
–0.5
–0.6
–0.7
–0.8
3
VREF (V)
–1
0
1
2
3
VINCM (V)
5
4
2411 G13
0.6
0.4
0.2
6
0
–0.4
–0.6
–0.8
–1.0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–1.0
3.5
–0.6
–0.7
–0.8
–1.0
–45 –30 –15
3.9 4.3
VCC (V)
4.7
5.1
5.5
2411 G16
0 15 30 45 60
TEMPERATURE (°C)
0
1
3
2
VREF (V)
90
75
2411 G15
+ Full-Scale Error vs Temperature
–0.8
3.1
–0.5
3
VCC = 5V
REF– = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
0.8
–0.2
5.5
–0.4
Offset Error vs VREF
REF + = 2.5V
REF – = GND
VIN = 0V
VINCM = GND
FO = GND
TA = 25°C
2.7
–0.3
0
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.8
5.1
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
FO = GND
2411 G14
Offset Error vs VCC
0
4.7
–0.9
–1.0
5
4
–0.2
FULL-SCALE ERROR (ppm OF VREF)
2
3.9 4.3
VCC (V)
Offset Error vs Temperature
–0.9
1
3.5
2411 G12
OFFSET ERROR (ppm OF VREF)
1.40
3.1
0
–0.1
1.45
0
1.30
2.7
90
Offset Error vs VINCM
OFFSET ERROR (ppm OF VREF)
1.50
1.40
0
VCC = 5V
REF – = GND
VIN = 0V
FO = GND
TA = 25°C
1.55
1.45
2411 G11
RMS Noise vs VREF
1.60
1.50
REF + = 2.5V
REF – = GND
VIN = 0V
FO = GND
TA = 25°C
1.35
2411 G10
RMS NOISE (µV)
RMS Noise vs VCC
1.60
RMS NOISE (µV)
RMS Noise vs VINCM
1.60
4
5
2411 G17
2
1
VCC = 5V
REF + = 5V
REF – = GND
IN+ = 2.5V
IN – = GND
FO = GND
0
–1
–2
–3
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2411 G18
7
LTC2411/LTC2411-1
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TYPICAL PERFOR A CE CHARACTERISTICS
+ Full-Scale Error vs Temperature
–Full-Scale Error vs Temperature
2
1
0
–1
–2
–3
–4
–5
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2
1
0
VCC = 5V
REF + = 5V
REF – = GND
+
–2 IN – = GND
IN = 2.5V
FO = GND
–3
–45 –30 –15 0 15 30 45 60
TEMPERATURE (°C)
–1
2411 G19
–40
–80
1
0
–1
–2
–3
–4
0
–60
–20
–40
–80
–60
–120
–120
–120
–140
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
0
1M
30
0
0
REJECTION (dB)
REJECTION (dB)
VCC = 4.1V DC ±1.4V
REF + = 2.5V
–20
REF – = GND
IN + = GND
–40 IN – = GND
FO = GND
–60 TA = 25°C
–80
VCC = 4.1V DC ±0.7V
REF + = 2.5V
–20 REF – = GND
IN + = GND
–40 IN – = GND
FO = GND
–60 TA = 25°C
–80
–100
–100
–100
–120
–120
–120
–140
–140
1
10
10k 100k
1k
100
FREQUECY AT VCC (Hz)
1M
2411 G31
8
7800
PSRR vs Frequency at VCC
(LTC2411-1)
0
–80
7700
7750
FREQUENCY AT VCC (Hz)
2411 G24
PSRR vs Frequency at VCC
(LTC2411-1)
VCC = 4.1V DC
REF + = 2.5V
–20
REF – = GND
IN + = GND
–40 IN – = GND
FO = GND
–60 TA = 25°C
7650
2411 G23
PSRR vs Frequency at VCC
(LTC2411-1)
90
VCC = 4.1V DC ±0.7VP-P
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–140
7600
60 90 120 150 180 210 240
FREQUENCY AT VCC (Hz)
2411 G22
75
–80
–100
10
0 15 30 45 60
TEMPERATURE (°C)
PSRR vs Frequency at VCC
(LTC2411)
–100
1
VCC = 2.7V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = 1.25V
FO = GND
2411 G21
–100
–140
REJECTION (dB)
2
–5
–45 –30 –15
90
VCC = 4.1V DC ±1.4V
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–20
REJECTION (dB)
REJECTION (dB)
0
VCC = 4.1V DC
REF + = 2.5V
REF – = GND
IN + = GND
IN – = GND
FO = GND
TA = 25°C
–60
3
PSRR vs Frequency at VCC
(LTC2411)
0
–40
4
2411 G20
PSRR vs Frequency at VCC
(LTC2411)
–20
75
REJECTION (dB)
3
–FULL-SCALE ERROR (ppm OF VREF)
VCC = 2.7V
REF + = 2.5V
REF – = GND
IN + = 1.25V
IN – = GND
FO = GND
4
–Full-Scale Error vs Temperature
5
3
–FULL-SCALE ERROR (ppm OF VREF)
FULL-SCALE ERROR (ppm OF VREF)
5
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2411 G32
–140
6880
6930
6980
7030
FREQUENCY AT VCC (Hz)
7080
2411 G33
LTC2411/LTC2411-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Conversion Current
vs Temperature
650
VCC = 5.5V
SUPPLY CURRENT (µA)
210
VCC = 5V
200
190
VCC = 3V
180
REF + = VCC
600 REF – = GND
IN + = GND
550 IN – = GND
500 TA = 25°C
SCK = NC
450 SDO = NC
CS = GND
400
FO = EXT OSC
350
300
75
150
90
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
VCC = 3V
–20
VREF = 5V
–40
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 25°C
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
0 15 30 45 60
TEMPERATURE (°C)
90
Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate
20
VREF = 2.5V
20
VCC = 5V
REF – = GND
VINCM = 2.5V
19 VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/NOISERMS)
TA = 25°C
18
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2411 G28
75
22
21
RESOLUTION (BITS)
OFFSET ERROR (ppm OF VREF)
VREF = 2.5V
0
1
2411 G27
VREF = 5V
0
–120
VCC = 5V
0
–45 –30 –15
22
–100
2
Resolution (NOISERMS ≤ 1LSB)
vs Output Data Rate
40
–80
VCC = 5.5V
3
2411 G26
Offset Error vs Output Data Rate
–60
4
VCC = 2.7V
2411 G25
20
FO = GND
CS = VCC
SCK = NC
SDO = NC
200
VCC = 2.7V
0 15 30 45 60
TEMPERATURE (°C)
VCC = 5V
VCC = 3V
250
170
5
2411 G29
RESOLUTION (BITS)
CONVERSION CURRENT (µA)
FO = GND
230 CS = GND
SCK = NC
220 SDO = NC
SLEEP MODE CURRENT (µA)
240
160
–45 –30 –15
Sleep Mode Current
vs Temperature
Conversion Current
vs Output Data Rate
18
VREF = 5V
16
VCC = 5V
VREF = 2.5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/INLMAX)
TA = 25°C
14
12
10
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2411 G30
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PI FU CTIO S
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 6) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
REF + (Pin 2), REF – (Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and VCC as long as the reference positive input, REF +, is
more positive than the reference negative input, REF –, by
at least 0.1V.
IN + (Pin 4), IN– (Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and VCC + 0.3V. Within these limits, the
converter bipolar input range (VIN = IN+ – IN–) extends
from – 0.5 • (VREF ) to 0.5 • (VREF ). Outside this input
range, the converter produces unique overrange and
underrange output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
9
LTC2411/LTC2411-1
U
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PI FU CTIO S
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. For the LTC2411, when the FO pin is connected to VCC
(FO = VCC), the converter uses its internal oscillator and the
digital filter first null is located at 50Hz. When the FO pin is
connected to GND (FO = OV), the converter uses its internal
oscillator and the digital filter first null is located at 60Hz.
For the LTC2411-1, the converter provides simultaneous
50Hz/60Hz rejection with the FO pin connected to GND.
When FO is driven by an external clock signal with a
frequency fEOSC, the converters use this signal as their
system clock and the digital filter first null is located at a
frequency fEOSC/2560.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
W
FU CTIO AL BLOCK DIAGRA
U
INTERNAL
OSCILLATOR
U
VCC
GND
IN +
IN –
AUTOCALIBRATION
AND CONTROL
+
–∫
∫
FO
(INT/EXT)
∫
SDO
∑
SERIAL
INTERFACE
ADC
SCK
CS
+
REF
REF –
DECIMATING FIR
– +
DAC
2411 FD
Figure 1
VCC
TEST CIRCUITS
1.69k
SDO
SDO
1.69k
CLOAD = 20pF
2411 TA03
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
10
CLOAD = 20pF
2411 TA04
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
LTC2411/LTC2411-1
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APPLICATIO S I FOR ATIO
CONVERTER OPERATION
Converter Operation Cycle
The LTC2411/LTC2411-1 are low power, delta-sigma analog-to-digital converters with an easy-to-use 3-wire serial
interface (see Figure 1). Their operation is made up of three
states. The converter operating cycle begins with the conversion, followed by the low power sleep state and ends with
the data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2411/LTC2411-1 perform a conversion.
Once the conversion is complete, the devices enter the
sleep state. While in this sleep state, power consumption
is reduced by an order of magnitude. The parts remain in
the sleep state as long as CS is HIGH. The conversion
result is held indefinitely in a static shift register while the
converter is in the sleep state.
Once CS is pulled LOW, the devices begin outputting the
conversion result. There is no latency in the conversion
result. The data output corresponds to the conversion just
performed. This result is shifted out on the serial data out
pin (SDO) under the control of the serial clock (SCK). Data
is updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 32 bits are read
out of the ADC or when CS is brought HIGH. The devices
automatically initiate a new conversion and the cycle
repeats.
Through timing control of the CS and SCK pins, the
LTC2411/LTC2411-1 offer several flexible modes of operation (internal or external SCK and free-running conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50 or 60Hz
plus their harmonics. The filter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2411/LTC2411-1 incorporate a highly accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the LTC2411
achieves a minimum of 110dB rejection at the line frequency (50Hz or 60Hz ±2%) and the LTC2411-1 achieves
a minimum of 87dB rejection over 49Hz to 61.2Hz.
Ease of Use
The LTC2411/LTC2411-1 data output has no latency,
filter settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog voltages is easy.
CONVERT
SLEEP
FALSE
CS = LOW
AND
SCK
TRUE
The LTC2411/LTC2411-1 perform offset and full-scale
calibrations in every conversion cycle. This calibration is
transparent to the user and has no effect on the cyclic
operation described above. The advantage of continuous
calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift.
Power-Up Sequence
DATA OUTPUT
2411 F02
Figure 2. LTC2411/LTC2411-1 State Transition Diagram
The LTC2411/LTC2411-1 automatically enter an internal
reset state when the power supply voltage VCC drops
below approximately 1.9V. This feature guarantees the
11
LTC2411/LTC2411-1
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APPLICATIO S I FOR ATIO
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 1ms. The POR
signal clears all internal registers. Following the POR
signal, the LTC2411/LTC2411-1 start a normal conversion
cycle and follow the succession of states described above.
The first conversion result following POR is accurate
within the specifications of the device if the power supply
voltage is restored within the operating range (2.7V to
5.5V) before the end of the POR time interval.
Reference Voltage Range
The LTC2411/LTC2411-1 accept a truly differential external reference voltage. The absolute/common mode voltage specification for the REF + and REF – pins covers the
entire range from GND to VCC. For correct converter
operation, the REF + pin must always be more positive than
the REF – pin.
The LTC2411/LTC2411-1 can accept a differential reference voltage from 0.1V to VCC. The converter output noise
is determined by the thermal noise of the front-end circuits, and, as such, its value in nanovolts is nearly constant
with reference voltage. A decrease in reference voltage will
not significantly improve the converter’s effective resolution. On the other hand, a reduced reference voltage will
improve the converter’s overall INL performance. A reduced
reference voltage will also improve the converter performance when operated with an external conversion clock
(external FO signal) at substantially higher output data rates.
Input Voltage Range
The analog input is truly differential with an absolute/
common mode range for the IN+ and IN– input pins
extending from GND – 0.3V to VCC + 0.3V. Outside
these limits, the ESD protection devices begin to turn on
and the errors due to input leakage current increase
rapidly. Within these limits, the LTC2411/LTC2411-1 convert the bipolar differential input signal, VIN = IN + – IN –,
from – FS = – 0.5 • VREF to +FS = 0.5 • VREF where VREF =
REF+ – REF –. Outside this range the converter indicates
12
the overrange or the underrange condition using distinct
output codes.
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance of the device. In the physical layout, it is important
to maintain the parasitic capacitance of the connection
between these series resistors and the corresponding pins
as low as possible; therefore, the resistors should be
located as close as practical to the pins. In addition, series
resistors will introduce a temperature dependent offset
error due to the input leakage current. A 1nA input leakage
current will develop a 1ppm offset error on a 5k resistor if
VREF = 5V. This error has a very strong temperature
dependency.
Output Data Format
The LTC2411/LTC2411-1 serial output data stream is 32
bits long. The first 3 bits represent status information indicating the sign and conversion state. The next 24 bits are
the conversion result, MSB first. The remaining 5 bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. The third
and fourth bits together are also used to indicate an
underrange condition (the differential input voltage is below – FS) or an overrange condition (the differential input
voltage is above + FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 29 also
provides the underrange or overrange indication. If both
Bit 29 and Bit 28 are HIGH, the differential input voltage is
LTC2411/LTC2411-1
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above +FS. If both Bit 29 and Bit 28 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2411/LTC2411-1 Status Bits
Bit 31 Bit 30 Bit 29 Bit 28
EOC
DMY SIG MSB
Input Range
VIN ≥ 0.5 • VREF
0
0
1
1
0V ≤ VIN < 0.5 • VREF
0
0
1
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < – 0.5 • VREF
0
0
0
0
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
EOC
“0”
SIG
MSB
BIT 27
BIT 5
BIT 0
LSB24
Hi-Z
SCK
1
2
3
4
SLEEP
5
26
27
32
DATA OUTPUT
CONVERSION
2411 F03
Figure 3. Output Data Timing
Table 2. LTC2411/LTC2411-1 Output Data Format
Differential Input Voltage
VIN *
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
…
Bit 0
VIN* ≥ 0.5 • VREF**
0
0
1
1
0
0
0
…
0
0.5 • VREF** – 1LSB
0
0
1
0
1
1
1
…
1
0.25 • VREF**
0
0
1
0
1
0
0
…
0
0.25 • VREF** – 1LSB
0
0
1
0
0
1
1
…
1
0
0
0
1
0
0
0
0
…
0
–1LSB
0
0
0
1
1
1
1
…
1
– 0.25 • VREF**
0
0
0
1
1
0
0
…
0
– 0.25 • VREF** – 1LSB
0
0
0
1
0
1
1
…
1
– 0.5 • VREF**
0
0
0
1
0
0
0
…
0
VIN* < –0.5 • VREF**
0
0
0
0
1
1
1
…
1
*The differential input voltage VIN = IN+ – IN–.
**The differential reference voltage VREF = REF+ – REF–.
13
LTC2411/LTC2411-1
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Frequency Rejection Selection (FO) (LTC2411 Only)
The LTC2411 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics for 50Hz ±2% or 60Hz ±2%. For 60Hz rejection, FO should be connected to GND while for 50Hz
rejection the FO pin should be connected to VCC.
The selection of 50Hz or 60Hz rejection can also be made
by driving FO to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2411 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the FO pin and turns off the internal oscillator. The
frequency fEOSC of the external signal must be at least
2560Hz (1Hz notch frequency) to be detected. The external clock signal duty cycle is not significant as long as the
minimum and maximum specifications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2411 provides better than 110dB
normal mode rejection in a frequency range fEOSC/2560
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/2560
is shown in Figure 4.
Whenever an external clock is not present at the FO pin, the
converter automatically activates its internal oscillator and
14
–80
–85
NORMAL MODE REJECTION (dB)
As long as the voltage on the IN+ and IN– pins is maintained
within the – 0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF to
+FS = 0.5 • VREF. For differential input voltages greater than
+FS, the conversion result is clamped to the value corresponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/2560(%)
2411 F04
Figure 4. LTC2411 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
enters the Internal Conversion Clock mode. The LTC2411
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external
serial clock. If the change occurs during the conversion
state, the result of the conversion in progress may be
outside specifications but the following conversions will
not be affected. If the change occurs during the data output
state and the converter is in the Internal SCK mode, the
serial clock duty cycle may be affected but the serial data
stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of FO.
Simultaneous Frequency Rejection (LTC2411-1 Only)
The LTC2411-1 internal oscillator provides better than
87dB normal mode rejection over the range of 49Hz to
61.2Hz. For this simultaneous 50/60Hz rejection, FO should
be connected to GND. The performance of the LTC2411-1
is the same as the LTC2411 when driven by an external
conversion clock at FO pin.
SERIAL INTERFACE PINS
The LTC2411/LTC2411-1 transmit the conversion results
and receive the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
LTC2411/LTC2411-1
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Table 3. LTC2411/LTC2411-1 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
Duration
FO = LOW (LTC2411)
(60Hz Rejection)
133ms, Output Data Rate ≤ 7.5 Readings/s
FO = HIGH (LTC2411)
(50Hz Rejection)
160ms, Output Data Rate ≤ 6.2 Readings/s
FO = LOW (LTC2411-1)
(Simultaneous 50Hz/60Hz Rejection)
147ms, Output Data Rate ≤ 6.8 Readings/s
External Oscillator
FO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/2560 Rejection)
20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s
Internal Serial Clock
FO = LOW/HIGH (LTC2411)
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
FO = LOW (LTC2411-1)
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 1.83ms
(32 SCK cycles)
FO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 256/fEOSCms
(32 SCK cycles)
SLEEP
DATA OUTPUT
As Long As CS = HIGH Until CS = LOW and SCK
External Serial Clock with
Frequency fSCK kHz
As Long As CS = LOW But Not Longer Than 32/fSCKms
(32 SCK cycles)
converter status and during the data output state it is used
to read the conversion result.
used as an end of conversion indicator during the conversion and sleep states.
Serial Clock Input/Output (SCK)
When CS (Pin 7) is HIGH, the SDO driver is switched to a
high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
The serial clock signal present on SCK (Pin 9) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2411/LTC2411-1 create their own serial clock by dividing the internal conversion clock by 8. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected on
power-up and then reselected every time a HIGH-to-LOW
transition is detected at the CS pin. If SCK is HIGH or floating at power-up or during this transition, the converter
enters the internal SCK mode. If SCK is LOW at power-up
or during this transition, the converter enters the external
SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 8), provides the result
of the last conversion as a serial bit stream (MSB first)
during the data output state. In addition, the SDO pin is
Chip Select Input (CS)
The active LOW chip select, CS (Pin 7), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2411/LTC2411-1 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output state
(i.e., after the first rising edge of SCK occurs with
CS␣ =␣ LOW).
15
LTC2411/LTC2411-1
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Table 4. LTC2411/LTC2411-1 Interface Timing Modes
SCK
Source
Conversion
Cycle
Control
Data
Output
Control
Connection
and
Waveforms
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 5, 6
External SCK, 2-Wire I/O
External
SCK
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS ↓
CS ↓
Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
Configuration
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
10
LTC2411/
LTC2411-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
3-WIRE
SPI INTERFACE
8
7
GND
CS
TEST EOC
TEST EOC
SDO
BIT 31
EOC
Hi-Z
BIT 30
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 5
BIT 0
LSB
SUB LSB
TEST EOC
Hi-Z
Hi-Z
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2411 F05
Figure 5. External Serial Clock, Single Cycle Operation
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
SERIAL INTERFACE TIMING MODES
The LTC2411/LTC2411-1’s 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/external serial clock, 2- or 3-wire I/O, single cycle conversion.
The following sections describe each of these serial interface timing modes in detail. In all these cases, the
converter can use the internal oscillator (FO = LOW or FO
= HIGH) or an external oscillator connected to the FO pin.
Refer to Table␣ 4 for a summary.
16
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC␣ =␣ 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. Independent of CS, the
LTC2411/LTC2411-1
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APPLICATIO S I FOR ATIO
device automatically enters the low power sleep state once
the conversion is complete.
requiring all 32 bits of output data, aborting an invalid
conversion cycle or synchronizing the start of a conversion.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift register. The device remains in the sleep state until the first
rising edge of SCK is seen while CS is LOW. Data is shifted
out the SDO pin on each falling edge of SCK. This enables
external circuitry to latch the output on the rising edge of
SCK. EOC can be latched on the first rising edge of SCK
and the last bit of the conversion result can be latched on
the 32nd rising edge of SCK. On the 32nd falling edge of
SCK, the device begins a new conversion. SDO goes HIGH
(EOC = 1) indicating a conversion is in progress.
External Serial Clock, 2-Wire I/O
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 32nd
falling edge of SCK, see Figure 6. On the rising edge of CS,
the device aborts the data output state and immediately
initiates a new conversion. This is useful for systems not
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 1.9V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven LOW prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and
EOC␣ =␣ 0 once the conversion enters the low power sleep
state. On the falling edge of EOC, the conversion result is
loaded into an internal static shift register. The device
remains in the sleep state until the first rising edge of SCK.
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
10
LTC2411/
LTC2411-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
3-WIRE
SPI INTERFACE
8
7
GND
CS
BIT 0
SDO
TEST EOC
TEST EOC
BIT 31
EOC
EOC
Hi-Z
Hi-Z
BIT 30
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 9
Hi-Z
TEST EOC
BIT 8
Hi-Z
SCK
(EXTERNAL)
SLEEP
CONVERSION
SLEEP
DATA OUTPUT
DATA OUTPUT
CONVERSION
2411 F06
Figure 6. External Serial Clock, Reduced Data Output Length
17
LTC2411/LTC2411-1
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Internal Serial Clock, Single Cycle Operation
Data is shifted out the SDO pin on each falling edge of SCK
enabling external circuitry to latch data on the rising edge
of SCK. EOC can be latched on the first rising edge of SCK.
On the 32nd falling edge of SCK, SDO goes HIGH (EOC␣ =␣ 1)
indicating a new conversion has begun.
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
10
LTC2411/
LTC2411-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
9
2-WIRE I/O
8
7
GND
CS
BIT 31
SDO
BIT 30
EOC
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 5
BIT 0
LSB24
SCK
(EXTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2411 F07
Figure 7. External Serial Clock, CS = 0 Operation
VCC
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
10
LTC2411/
LTC2411-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
SCK
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
10k
9
3-WIRE
SPI INTERFACE
8
7
GND
<tEOCtest
CS
TEST EOC
SDO
BIT 31
EOC
Hi-Z
BIT 30
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 5
BIT 0
TEST EOC
LSB24
Hi-Z
Hi-Z
Hi-Z
SCK
(INTERNAL)
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
2411 F08
Figure 8. Internal Serial Clock, Single Cycle Operation
18
LTC2411/LTC2411-1
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if the device is using its internal oscillator for the LTC2411
(FO = logic LOW or HIGH) and 26µs for the LTC2411-1
(FO = logic LOW). If FO is driven by an external oscillator
of frequency fEOSC, then tEOCtest is 3.6/fEOSC. If CS is pulled
HIGH before time tEOCtest, the device remains in the sleep
state. The conversion result is held in the internal static
shift register.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.
If CS remains LOW longer than tEOCtest, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 32nd
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 32nd rising edge of SCK. After the
32nd rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to prevent the device
from exiting the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time tEOCtest after the falling edge of CS
(if EOC = 0) or tEOCtest after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of tEOCtest is 23µs
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 32nd rising edge
of SCK, see Figure 9. On the rising edge of CS, the device
VCC
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
10
LTC2411/
LTC2411-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
REF –
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
> tEOCtest
SCK
10k
9
3-WIRE
SPI INTERFACE
8
7
GND
<tEOCtest
CS
TEST EOC
BIT 0
SDO
TEST EOC
EOC
Hi-Z
BIT 31
EOC
Hi-Z
Hi-Z
BIT 30
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
Hi-Z
BIT 8
TEST EOC
Hi-Z
SCK
(INTERNAL)
SLEEP
CONVERSION
SLEEP
DATA OUTPUT
DATA OUTPUT
CONVERSION
2411 F09
Figure 9. Internal Serial Clock, Reduced Data Output Length
19
LTC2411/LTC2411-1
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APPLICATIO S I FOR ATIO
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 32 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2411/LTC2411-1’s internal pull-up at pin SCK is disabled. Normally, SCK is not
externally driven if the device is in the internal SCK timing
mode. However, certain applications may require an external driver on SCK. If this driver goes Hi-Z after outputting a LOW signal, the LTC2411/LTC2411-1’s internal
pull-up remains disabled. Hence, SCK remains LOW. On
the next falling edge of CS, the device is switched to the
external SCK timing mode. By adding an external 10k pullup resistor to SCK, this pin goes HIGH once the external
driver goes Hi-Z. On the next CS falling edge, the device
will remain in the internal SCK timing mode.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simplifying the user interface or isolation barrier.
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
10
LTC2411/
LTC2411-1
REFERENCE
VOLTAGE
0.1V TO VCC
2
REF +
3
–
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
4
IN +
SDO
5
IN –
CS
6
REF
SCK
= 50Hz REJECTION (LTC2411)
= EXTERNAL OSCILLATOR
= 60Hz REJECTION (LTC2411)
= SIMULTANEOUS 50Hz/60Hz REJECTION (LTC2411-1)
9
2-WIRE I/O
8
7
GND
CS
BIT 31
SDO
BIT 30
EOC
BIT 29
BIT 28
SIG
MSB
BIT 27
BIT 26
BIT 5
BIT 0
LSB24
SCK
(INTERNAL)
CONVERSION
DATA OUTPUT
SLEEP
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
20
CONVERSION
2411 F10
LTC2411/LTC2411-1
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The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 1.9V. An internal
weak pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
low power sleep state. The part remains in the sleep state
a minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting data. The data output
cycle begins on the first rising edge of SCK and ends after
the 32nd rising edge. Data is shifted out the SDO pin on
each falling edge of SCK. The internally generated serial
clock is output to the SCK pin. This signal may be used
to shift the conversion result into external circuitry. EOC
can be latched on the first rising edge of SCK and the last
bit of the conversion result can be latched on the 32nd
rising edge of SCK. After the 32nd rising edge, SDO goes
HIGH (EOC = 1) indicating a new conversion is in progress.
SCK remains HIGH during the conversion.
PRESERVING THE CONVERTER ACCURACY
The LTC2411/LTC2411-1 are designed to reduce as much
as possible the conversion result sensitivity to device
decoupling, PCB layout, antialiasing circuits, line frequency perturbations and so on. Nevertheless, in order to
preserve the extreme accuracy capability of this part,
some simple precautions are desirable.
Digital Signal Levels
The LTC2411/LTC2411-1’s digital interface is easy to use.
Its digital inputs (FO, CS and SCK in External SCK mode of
operation) accept standard TTL/CMOS logic levels and the
internal hysteresis receivers can tolerate edge rates as slow
as 100µs. However, some considerations are required to
take advantage of the exceptional accuracy and low supply
current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC␣ –␣ 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (FO, CS and SCK
in External SCK mode of operation) is within this range,
the LTC2411/LTC2411-1 power supply current may increase even if the signal in question is at a valid logic level.
For micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [VIL < 0.4V and
VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the LTC2411/
LTC2411-1 pins may severely disturb the analog to digital
conversion process. Undershoot and overshoot can occur because of the impedance mismatch at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver to
LTC2411/LTC2411-1. For reference, on a regular FR-4
board, signal propagation velocity is approximately
183ps/inch for internal traces and 170ps/inch for surface
traces. Thus, a driver generating a control signal with a
minimum transition time of 1ns must be connected to the
converter pin through a trace shorter than 2.5 inches. This
problem becomes particularly difficult when shared control lines are used and multiple reflections may occur. The
solution is to carefully terminate all transmission lines
close to their characteristic impedance.
Parallel termination near the LTC2411/LTC2411-1 pin will
eliminate this problem but will increase the driver power
dissipation. A series resistor between 27Ω and 56Ω
placed near the driver or near the LTC2411/LTC2411-1 pin
will also eliminate this problem without additional power
dissipation. The actual resistor value depends upon the
trace impedance and connection topology.
An alternate solution is to reduce the edge rate of the
control signals. It should be noted that using very slow
edges will increase the converter power supply current
during the transition time. The differential input and reference architecture reduce substantially the converter’s
sensitivity to ground currents.
21
LTC2411/LTC2411-1
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Particular attention must be given to the connection of the
FO signal when the LTC2411/LTC2411-1 are used with an
external conversion clock. This clock is active during the
conversion time and the normal mode rejection provided
by the internal digital filter is not very high at this frequency. A normal mode signal of this frequency at the
converter reference terminals may result into DC gain and
INL errors. A normal mode signal of this frequency at the
converter input terminals may result into a DC offset error.
Such perturbations may occur due to asymmetric capacitive coupling between the FO signal trace and the converter
input and/or reference connection traces. An immediate
solution is to maintain maximum possible separation
between the FO signal trace and the input/reference signals. When the FO signal is parallel terminated near the
converter, substantial AC current is flowing in the loop
formed by the FO connection trace, the termination and the
ground return path. Thus, perturbation signals may be
inductively coupled into the converter input and/or reference. In this situation, the user must reduce to a minimum
the loop area for the FO signal as well as the loop area for
the differential input and reference connections.
IREF+
VCC
ILEAK
VCC
ILEAK
RSW (TYP)
20k
VIN+
CEQ
6pF
(TYP)
ILEAK
IIN –
VCC
V2
I REF +
(
+ VREFCM
IN
−
)AVG = 1.5 • VREF0−.5V•INCM
REQ
VREF • REQ
(
+ VREFCM
IN
+
)AVG = −1.5 • VREF0.−5 •VINCM
REQ
VREF • REQ
I REF −
V2
where:
 REF + + REF − 
VREFCM = 

2


VIN –
ILEAK
IREF –
When using the internal oscillator (FO = LOW or HIGH), the
LTC2411 (LTC2411-1)’s front-end switched-capacitor network is clocked at 76800Hz (69900Hz) corresponding to
VREF = REF + − REF −
RSW (TYP)
20k
ILEAK
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, REF+ or REF–) can be
considered to form, together with RSW and CEQ (see
Figure␣ 11), a first order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worstcase circumstances, the errors may add.
− VREFCM
( )AVG = VIN + V0INCM
.5 • REQ
−V + V
−V
= IN INCM REFCM
I(IN− )
AVG
0.5 • REQ
VREF+
IIN+
The input and reference pins of the LTC2411/LTC2411-1
converter are directly connected to a network of sampling
capacitors. Depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four
pins transfering small amounts of charge in the process.
A simplified equivalent circuit is shown in Figure 11.
I IN+
RSW (TYP)
20k
ILEAK
Driving the Input and Reference
VIN = IN+ − IN−
VCC
ILEAK
 IN+ − IN− 
VINCM = 

2


RSW (TYP)
20k
2411 F11
VREF –
REQ = 10.8MΩ INTERNAL OSCILLATOR 60Hz Notch (FO = LOW)(LTC 2411)
REQ = 13.0MΩ INTERNAL OSCILLATOR 50Hz Notch (FO = HIGH)(LTC 2411)
ILEAK
REQ = 11.9MΩ INTERNAL OSCILLATOR (FO = LOW)(LTC 2411 − 1)
SWITCHING FREQUENCY
fSW = 76800Hz INTERNAL OSCILLATOR (FO = LOW OR HIGH)
fSW = 0.5 • fEOSC EXTERNAL OSCILLATOR
(
)
REQ = 1.67 • 1012 / fEOSC EXTERNAL OSCILLATOR
Figure 11. LTC2411/LTC2411-1 Equivalent Analog Input Circuit
22
LTC2411/LTC2411-1
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a 13µs (14.2µs) sampling period. Thus, for settling errors
of less than 1ppm, the driving source impedance should
be chosen such that τ ≤ 13µs/14 = 920ns (1.02µs). When
an external oscillator of frequency fEOSC is used, the
sampling period is 2/fEOSC and, for a settling error of less
than 1ppm, τ ≤ 0.14/fEOSC.
they include the effect of the actual second order input
network together with the nonlinear settling process of
the input amplifiers. For small CIN values, the settling on
IN+ and IN – occurs almost independently and there is little
benefit in trying to match the source impedance for the
two pins.
RSOURCE
Input Current
For relatively small values of input capacitance (C IN <
0.01µF), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
for CIN will deteriorate the converter offset and gain
performance without significant benefits of signal filtering and the user is advised to avoid them. Nevertheless,
when small values of CIN are unavoidably present as
parasitics of input multiplexers, wires, connectors or
sensors, the LTC2411/LTC2411-1 can maintain their exceptional accuracy while operating with relative large
values of source resistance as shown in Figures 13 and
14. These measured results may be slightly different from
the first order approximation suggested earlier because
CPAR
≅ 20pF
CIN
RSOURCE
VINCM – 0.5VIN
LTC2411/
LTC2411-1
IN –
CPAR
≅ 20pF
CIN
2411 F12
Figure 12. An RC Network at IN + and IN –
50
+FS ERROR (ppm OF VREF)
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The CPAR capacitor
includes the LTC2411/LTC2411-1 pin capacitance (5pF
typical) plus the capacitance of the test fixture used to
obtain the results shown in Figures 13 and 14. A careful
implementation can bring the total input capacitance (CIN
+ CPAR) closer to 5pF thus achieving better performance
than the one predicted by Figures 13 and 14. The effect of
the input dynamic current is almost the same for the
LTC2411 and the LTC2411-1 and measurements of the
LTC2411 with FO = GND are plotted out as a typical case.
For simplicity, two distinct situations can be considered.
VINCM + 0.5VIN
VCC = 5V
REF + = 5V
REF – = GND
IN + = 5V
IN – = 2.5V CIN = 0.01µF
FO = GND
TA = 25°C
40
30
CIN = 0.001µF
20
CIN = 100pF
CIN = 0pF
10
0
1
10
100
1k
RSOURCE (Ω)
10k
100k
2411 F13
Figure 13. +FS Error vs RSOURCE
0
–FS ERROR (ppm OF VREF)
If complete settling occurs on the input, conversion results will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN + and IN – pins as a result of the
sampling charge transfers when integrated over a substantial time period (longer than 64 internal clock cycles).
IN +
at IN +
or IN – (Small CIN)
VCC = 5V
REF + = 5V
REF – = GND
IN + = GND
IN – = 2.5V CIN = 0pF
FO = GND
TA = 25°C
CIN = 100pF
–10
–20
CIN = 0.001µF
–30
CIN = 0.01µF
–40
–50
1
10
100
1k
RSOURCE (Ω)
10k
100k
2411 F14
Figure 14. –FS Error vs RSOURCE
at IN +
or IN – (Small CIN)
23
LTC2411/LTC2411-1
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Larger values of input capacitors (CIN > 0.01µF) may be
required in certain configurations for antialiasing or general input signal filtering. Such capacitors will average the
input sampling charge and the external source resistance
will see a quasi constant input differential impedance. For
the LTC2411, when FO = LOW (internal oscillator and 60Hz
notch), the typical differential input resistance is 5.4MΩ
which will generate a gain error of approximately 0.093ppm
for each ohm of source resistance driving IN+ or IN –.
When FO = HIGH (internal oscillator and 50Hz notch), the
typical differential input resistance is 6.5MΩ which will
generate a gain error of approximately 0.077ppm for each
ohm of source resistance driving IN+ or IN –. For the
LTC2411-1, the typical differential input resistance is
6MΩ which will generate a gain error of approximately
0.084ppm for each ohm of source resistance driving IN+
or IN– (FO = LOW). When FO is driven by an external
oscillator with a frequency fEOSC (external conversion
clock operation), the typical differential input resistance is
0.83 • 1012/fEOSCΩ and each ohm of source resistance
driving IN+ or IN – will result in 0.59 • 10–6 • fEOSCppm gain
error. The effect of the source resistance on the two input
pins is additive with respect to this gain error. The typical
+FS and –FS errors as a function of the sum of the source
resistance seen by IN+ and IN– for large values of CIN are
shown in Figure 15.
reference common mode voltages. While the input drive
circuit nonzero source impedance combined with the
converter average input current will not degrade the INL
performance, indirect distortion may result from the modulation of the offset error by the common mode component
of the input signal. Thus, when using large CIN capacitor
values, it is advisable to carefully match the source impedance seen by the IN+ and IN– pins. For the LTC2411, when
FO = LOW (internal oscillator and 60Hz notch), every 1Ω
mismatch in source impedance transforms a full-scale
common mode input signal into a differential mode input
signal of 0.093ppm. When FO = HIGH (internal oscillator
and 50Hz notch), every 1Ω mismatch in source impedance transforms a full-scale common mode input signal
into a differential mode input signal of 0.077ppm. For the
LTC2411-1, when internal oscillator is used (FO = LOW),
every 1Ω mismatch in source impedance transforms a
full-scale common mode input signal into a differential
mode input signal of 0.084ppm. When FO is driven by an
external oscillator with a frequency fEOSC, every 1Ω mismatch in source impedance transforms a full-scale common mode input signal into a differential mode input
signal of 0.59 • 10–6 • fEOSCppm. Figure 16 shows the
typical offset error due to input common mode voltage for
various values of source resistance imbalance between
the IN+ and IN– pins when large CIN values are used.
In addition to this gain error, an offset error term may also
appear. The offset error is proportional with the mismatch
between the source impedance driving the two input pins
IN+ and IN– and with the difference between the input and
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
+FS ERROR (ppm OF VREF)
100
80
0
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CIN = 0.01µF
–20
CIN = 10µF
CIN = 1µF
60
40
20
CIN = 0.1µF
CIN = 0.01µF
–40
CIN = 0.1µF
–60
–80
–100
–120
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2411 F15a
Figure 15a. + FS Error vs RSOURCE at IN + or IN – (Large CIN)
24
–FS ERROR (ppm OF VREF)
120
VCC = 5V
REF + = 5V
REF – = GND
IN + = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CIN = 10µF
CIN = 1µF
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2411 F15b
Figure 15b. – FS Error vs RSOURCE at IN + or IN – (Large CIN)
LTC2411/LTC2411-1
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50
OFFSET ERROR (ppm OF VREF)
30
B
20
does not change the converter offset, but it may degrade
the gain and INL performance. The effect of this current
can be analyzed in the same two distinct situations.
VCC = 5V
REF + = 5V
REF – = GND
IN + = IN – = VINCM
A
40
C
10
D
0
E
–10
F
–20
–30
FO = GND
TA = 25°C
RSOURCEIN – = 500Ω
CIN = 10µF
G
–40
–50
0
0.5
1
1.5
2 2.5 3
VINCM (V)
A: ∆RIN = +400Ω
B: ∆RIN = +200Ω
C: ∆RIN = +100Ω
D: ∆RIN = 0Ω
3.5
4
4.5
5
E: ∆RIN = –100Ω
F: ∆RIN = –200Ω
G: ∆RIN = –400Ω
2411 F16
Figure 16. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(∆RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1µF)
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 1%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respective values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 100Ω source resistance will create
a 0.1µV typical and 1µV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2411/LTC2411-1 sample the
differential reference pins REF+ and REF– transfering small
amount of charge to and from the external driving circuits
thus producing a dynamic reference current. This current
For relatively small values of the external reference capacitors (CREF < 0.01µF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01µF)
may be required as reference filters in certain configurations. Such capacitors will average the reference sampling charge and the external source resistance will see a
quasi constant reference differential impedance. For the
LTC2411, when FO = LOW (internal oscillator and 60Hz
notch), the typical differential reference resistance is
3.9MΩ which will generate a gain error of approximately
0.13ppm for each ohm of source resistance driving REF+
or REF–. When FO = HIGH (internal oscillator and 50Hz
notch), the typical differential reference resistance is
4.68MΩ which will generate a gain error of approximately
0.11ppm for each ohm of source resistance driving REF+
or REF –. For the LTC2411-1, when internal oscillator is
used (FO = LOW), the typical differential reference resistance is 4.29MΩ which will generate a gain error of
approximately 0.12ppm for each ohm of source resistance driving REF + or REF –. When FO is driven by an
external oscillator with a frequency fEOSC (external conversion clock operation), the typical differential reference
resistance is 0.60 • 1012/fEOSCΩ and each ohm of source
resistance drving REF+ or REF– will result in 0.823 •
10–6 • fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical FS errors for various
combinations of source resistance seen by the REF+ and
REF– pins and external capacitance CREF connected to
these pins are shown in Figures 17 and 18. Typical – FS
errors are similar to + FS errors with opposite polarity.
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
For LTC2411, when FO = LOW (internal oscillator and 60Hz
notch), every 100Ω of source resistance driving REF+ or
25
LTC2411/LTC2411-1
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50
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
–10
–20
–FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
0
CREF = 0pF
–30
CREF = 100pF
CREF = 0.001µF
–40
VCC = 5V
REF + = 5V
REF – = GND
40 IN + = 1.25V
IN – = 3.75V
FO = GND
30 TA = 25°C
CREF = 0pF
20
CREF = 100pF
CREF = 0.001µF
10
CREF = 0.01µF
CREF = 0.01µF
–50
0
1
10
100
1k
RSOURCE (Ω)
10k
100k
1
10
100
1k
RSOURCE (Ω)
10k
100k
2411 F17a
Figure 17a. +FS Error vs RSOURCE at REF+ or REF– (Small CIN)
2411 F17b
Figure 17b. – FS Error vs RSOURCE at REF+ or REF– (Small CIN)
160
0
CREF = 0.01µF
CREF = 0.1µF
– FS ERROR (ppm OF VREF)
+FS ERROR (ppm OF VREF)
–20
–40
–60
CREF = 10µF
CREF = 1µF
–80
–100
–120
–140
–160
VCC = 5V
REF + = 5V
REF – = GND
IN + = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
VCC = 5V
+
140 REF – = 5V
REF = GND
+
120 IN – = 1.25V
IN = 3.75V
100 FO = GND
TA = 25°C
CREF = 10µF
CREF = 1µF
80
CREF = 0.1µF
60
40
CREF = 0.01µF
20
0
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
0 100 200 300 400 500 600 700 800 900 1000
RSOURCE (Ω)
2411 F18b
2411 F18a
Figure 18a. +FS Error vs RSOURCE at REF+ or REF– (Large CIN)
Figure 18b. – FS Error vs RSOURCE at REF+ or REF– (Large CIN)
10
REF– translates into about 0.45ppm additional INL error.
26
6
INL (ppm OF VREF)
When FO = HIGH (internal oscillator and 50Hz notch),
every 100Ω of source resistance driving REF+ or REF–
translates into about 0.37ppm additional INL error. For the
LTC2411-1, when FO = LOW, every 100Ω of source
resistance driving REF+ or REF– translates into about
0.41ppm additional INL error. When FO is driven by an
external oscillator with a frequency fEOSC, every 100Ω of
source resistance driving REF+ or REF– translates into
about 2.91 • 10–6 • fEOSCppm additional INL error. Figure␣ 19 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF+
and REF– pins does not help the gain or the INL error. The
9
RSOURCE = 2k
RSOURCE = 1k
4
2
0
–2
RSOURCE = 500Ω
–4
–6
–8
–10
–0.5–0.4– 0.3– 0.2– 0.1 0 0.1 0.2 0.3 0.4 0.5
VINDIF/VREFDIF
VCC = 5V
FO = GND
REF + = 5V
CREF = 10µF
REF – = GND
TA = 25°C
2411 F19
VINCM = 0.5 • (IN + + IN –) = 2.5V
Figure 19. INL vs Differential Input Voltage (VIN = IN+ = IN–)
and Reference Source Resistance (RSOURCE at REF + and REF –)
for Large CREF Values (CREF ≥ 1µF)
LTC2411/LTC2411-1
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user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
1%. Such a specification can also be easily achieved by an
external clock. When relatively stable resistors (50ppm/°C)
are used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications, a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05µV typical and 0.5µV maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2411 can produce up to 7.5 readings per second with a notch frequency
of 60Hz (FO = LOW) and 6.25 readings per second with a
notch frequency of 50Hz (FO = HIGH) and the LTC2411-1
can produce up to 6.8 readings per second with FO = LOW.
The actual output data rate will depend upon the length of
the sleep and data output phases which are controlled by
the user and which can be made insignificantly short.
When operated with an external conversion clock (FO
connected to an external oscillator), the LTC2411/LTC24111 output data rate can be increased as desired. The
duration of the conversion phase is 20510/fEOSC. If fEOSC
= 153600Hz, the converter behaves as if the internal
oscillator is used and the notch is set at 60Hz. There is no
significant difference in the LTC2411/LTC2411-1 performance between these two operation modes.
An increase in fEOSC over the nominal 153600Hz will
translate into a proportional increase in the maximum
output data rate. This substantial advantage is nevertheless
accompanied by three potential effects, which must be
carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent performance degradation can be substantially reduced by relying upon the LTC2411/LTC2411-1’s exceptional common
mode rejection and by carefully eliminating common
mode to differential mode conversion sources in the input
circuit. The user should avoid single-ended input filters
and should maintain a very high degree of matching and
symmetry in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the
effect of the source resistance upon the converter performance for any value of fEOSC. If small external input and/
or reference capacitors (CIN, CREF) are used, the effect of
the external source resistance upon the LTC2411/
LTC2411-1 typical performance can be inferred from
Figures 13, 14 and 17 in which the horizontal axis is scaled
by 153600/fEOSC.
Third, an increase in the frequency of the external oscillator above 460800Hz (a more than 3× increase in the output
data rate) will start to decrease the effectiveness of the
internal autocalibration circuits. This will result in a progressive degradation in the converter accuracy and linearity.
Typical measured performance curves for output data rates
up to 100 readings per second are shown in Figures␣ 20 to
27. In order to obtain the highest possible level of accuracy
from this converter at output data rates above 20 readings
per second, the user is advised to maximize the power
supply voltage used and to limit the maximum ambient
operating temperature. In certain circumstances, a reduction of the differential reference voltage may be beneficial.
Input Bandwidth
The combined effect of the internal sinc4 digital filter and
of the analog and digital autocalibration circuits determines the LTC2411/LTC2411-1 input bandwidth. When
27
LTC2411/LTC2411-1
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250
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
80
40
VCC = 5V
VREF = 5V
IN + = 3.75V
IN – = 1.25V
FO = EXT OSC
200
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
120
TA = 85°C
0
–40
TA = 25°C
150
100
TA = 85°C
50
TA = 25°C
0
–80
–50
–120
0
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2411 F21
2411 F20
Figure 20. Offset Error vs Output Data Rate and Temperature
Figure 21. + FS Error vs Output Data Rate and Temperature
22
100
TA = 25°C
21
50
0
TA = 85°C
–50
VCC = 5V
VREF = 5V
–100 IN + = 1.25V
IN – = 3.75V
FO = EXT OSC
–150
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
–FS ERROR (ppm OF VREF)
TA = 25°C
TA = 85°C
20
19
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/NOISERMS)
18
17
16
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2411 F22
2411 F23
Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 22. – FS Error vs Output Data Rate and Temperature
40
22
RESOLUTION (BITS)
18
TA = 85°C
TA = 25°C
16
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/INLMAX)
14
12
10
0
VREF = 2.5V
0
–20
VREF = 5V
–40
–60
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
TA = 25°C
–80
–100
–120
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2411 F24
Figure 24. Resolution (INLRMS ≤ 1LSB)
vs Output Data Rate and Temperature
28
OFFSET ERROR (ppm OF VREF)
20
20
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2411 F25
Figure 25. Offset Error vs Output
Data Rate and Reference Voltage
LTC2411/LTC2411-1
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22
22
VREF = 5V
20
VREF = 2.5V
20
VCC = 5V
REF – = GND
VINCM = 2.5V
19 VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/NOISERMS)
TA = 25°C
18
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
RESOLUTION (BITS)
RESOLUTION (BITS)
21
18
VREF = 2.5V
VCC = 5V
REF – = GND
VINCM = 2.5V
VIN = 0V
FO = EXT OSC
RES = LOG2(VREF/INLMAX)
TA = 25°C
14
12
10
0
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2411 F27
2411 F26
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
0.0
–0.5
INPUT SIGNAL ATTENUATION (dB)
the internal oscillator is used, the 3dB input bandwidth of
the LTC2411 is 3.63Hz for 60Hz notch frequency (FO =
LOW) and 3.02Hz for 50Hz notch frequency (FO = HIGH).
The 3dB input bandwidth for the LTC2411-1 is 3.30Hz
(FO = LOW). If an external conversion clock generator of
frequency fEOSC is connected to the FO pin, the 3dB input
bandwidth is 0.236 • 10–6 • fEOSC.
VREF = 5V
16
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
FO = HIGH
(LTC2411)
FO = LOW
(LTC2411)
FO = LOW
(LTC2411-1)
–4.5
Due to the complex filtering and calibration algorithms
utilized, the converter input bandwidth is not modeled very
accurately by a first order filter with the pole located at the
3dB frequency. When the internal oscillator is used, the
shape of the LTC2411/LTC2411-1 input bandwidth is
shown in Figure␣ 28. When an external oscillator of frequency fEOSC is used, the shape of the LTC2411/LTC2411-1
input bandwidth can be derived from Figure␣ 28, FO = LOW
curve of the LTC2411 in which the horizontal axis is scaled
by fEOSC/153600.
solution is a high gain, low bandwidth amplifier stage
followed by a high bandwidth unity-gain buffer.
The conversion noise (1.45µVRMS typical for VREF = 5V)
can be modeled as a white noise source connected to a
noise free converter. The noise spectral density is 70nV/√Hz
for an infinite bandwidth source and 126nV/√Hz for a
single 0.5MHz pole source. From these numbers, it is clear
that particular attention must be given to the design of
external amplification circuits. Such circuits face the
simultaneous requirements of very low bandwidth (just a
few Hz) in order to reduce the output referred noise and
relatively high bandwidth (at least 500kHz) necessary to
drive the input switched-capacitor network. A possible
When external amplifiers are driving the LTC2411/
LTC2411-1, the ADC input referred system noise calculation can be simplified by Figure 29. The noise of an
amplifier driving the LTC2411/LTC2411-1 input pin can be
modeled as a band-limited white noise source. Its bandwidth can be approximated by the bandwidth of a single
pole lowpass filter with a corner frequency fi. The amplifier
noise spectral density is ni. From Figure␣ 29, using fi as the
x-axis selector, we can find on the y-axis the noise equivalent bandwidth freqi of the input driving amplifier. This
bandwidth includes the band limiting effects of the ADC
–5.0
–5.5
–6.0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2411 F28
Figure 28. Input Signal Bandwidth
Using the Internal Oscillator
29
LTC2411/LTC2411-1
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internal calibration and filtering. The noise of the driving
amplifier referred to the converter input and including all
these effects can be calculated as N␣ = ni • √freqi. The total
system noise (referred to the LTC2411/LTC2411-1 input)
can now be obtained by summing as square root of sum
of squares the three ADC input referred noise sources: the
LTC2411/LTC2411-1 internal noise (1.45µV), the noise of
the IN + driving amplifier and the noise of the IN – driving
amplifier.
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 29 can still be used for noise calculation if the
x-axis is scaled by fEOSC/153600. For large values of the
ratio fEOSC/153600, the Figure 29 plot accuracy begins to
decrease, but in the same time the LTC2411/LTC2411-1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
1000
100
FO = LOW
10
FO = HIGH
1
0.1
0.1
1
10
100 1k
10k 100k
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1M
2411 G29
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
–30
–40
–50
–60
–70
–80
–90
–100
–110
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2411 F30
Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch (LTC2411)
30
One of the advantages delta-sigma ADCs offer over conventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2411/LTC2411-1 significantly simplifies antialiasing filter requirements.
The sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2411/LTC2411-1’s autocalibration circuits further simplify the antialiasing requirements by additional normal
mode signal filtering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUTMAX where fN is the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode, for the LTC2411, FS = 12800Hz with a 50Hz notch
setting and fS = 15360Hz with a 60Hz notch setting. For the
LTC2411-1, fS = 13980Hz (FO = LOW). In the external
oscillator mode, fS = fEOSC/10.
The combined normal mode rejection performance is
shown in Figure␣ 30 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure␣ 31 for the internal
oscillator with FO = LOW and for the external oscillator
mode. The regions of low rejection occurring at integer
multiples of fS have a very narrow bandwidth. Magnified
details of the normal mode rejection curves are shown in
0
FO = HIGH
–20
–120
Normal Mode Rejection and Antialiasing
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
0
–10
noise floor rises and the noise contribution of the driving
amplifiers lose significance.
FO = LOW OR
FO = EXTERNAL OSCILLATOR,
fEOSC = 10 • fS
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2411 F31
Figure 31. Input Normal Mode Rejection, Internal
Oscillator and FO = LOW or External Oscillator
LTC2411/LTC2411-1
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0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
APPLICATIO S I FOR ATIO
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2411 F33
2411 F32
Figure 32. Input Normal Mode Rejection
As a result of these remarkable normal mode specifications, minimal (if any) antialias filtering is required in front
of the LTC2411/LTC2411-1. If passive RC components
are placed in front of the LTC2411/LTC2411-1, the input
dynamic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of dynamic input current.
Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from
potential instabilities at large input signal levels. The proprietary architecture used for the LTC2411/LTC2411-1
third order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of
NORMAL MODE REJECTION (dB)
The user can expect to achieve in practice this level of
performance using the internal oscillator as it is demonstrated by Figures 34 to 36. Typical measured values of the
normal mode rejection of the LTC2411 operating with an
internal oscillator and a 60Hz notch setting are shown in
Figure 34 superimposed over the theoretical calculated
curve. Similarly, typical measured values of the normal
mode rejection of the LTC2411 operating with an internal
oscillator and a 50Hz notch setting are shown in Figure 35
superimposed over the theoretical calculated curve.
0
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
– 60
–80
–100
–120
0
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2411 F34
Figure 34. Input Normal Mode Rejection
vs Input Frequency (LTC2411)
0
NORMAL MODE REJECTION (dB)
Figure␣ 32 (rejection near DC) and Figure␣ 33 (rejection at
fS = 256fN) where fN represents the notch frequency.
These curves have been derived for the external oscillator
mode but they can be used in all operating modes by
appropriately selecting the fN value.
Figure 33. Input Normal Mode Rejection
MEASURED DATA
CALCULATED DATA
VCC = 5V
VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
FO = 5V
TA = 25°C
–20
–40
– 60
–80
–100
–120
0
25
50
75
100
125
INPUT FREQUENCY (Hz)
150
175
200
2411 F35
Figure 35. Input Normal Mode Rejection
vs Input Frequency (LTC2411)
31
LTC2411/LTC2411-1
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NORMAL MODE REJECTION (dB)
MEASURED DATA
CALCULATED DATA
–20
–40
– 60
VCC = 5V
VREF = 5V
REF – = GND
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25°C
–80
–100
–120
NORMAL MODE REJECTION (dB)
0
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = GND
TA = 25°C
– 60
–80
–100
–120
0
20
40
60
80 100 120 140 160
INPUT FREQUENCY (Hz)
180
200
0
220
15 30 45 60 75 90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2411 F37
2411 F36
Figure 36. Input Normal Mode Rejection
vs Input Frequency (LTC2411-1)
BRIDGE APPLICATIONS
Typical strain gauge based bridges deliver only 2mV/Volt
of excitation. As the maximum reference voltage of the
LTC2411/LTC2411-1 is 5V, remote sensing of applied
excitation without additional circuitry requires that excitation be limited to 5V. This gives only 10mV full scale, which
can be resolved to 1 part in 5000 without averaging. For
many solid state sensors, this is comparable to the sensor.
32
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
VCC = 5V
VREF = 5V
VINCM = 2.5V
FO = 5V
TA = 25°C
– 60
–80
–100
–120
0
25
50
75
100
125
INPUT FREQUENCY (Hz)
150
175
200
2411 F38
Figure 38. Measured Input Normal Mode Rejection
vs Input Frequency (LTC2411)
0
NORMAL MODE REJECTION (dB)
up to 150% of full scale. In many industrial applications,
it is not uncommon to have to measure microvolt level
signals superimposed over volt level perturbations and
LTC2411/LTC2411-1 are eminently suited for such tasks.
When the perturbation is differential, the specification of
interest is the normal mode rejection for large input signal
levels. With a reference voltage VREF␣ =␣ 5V, the LTC2411/
LTC2411-1 have a full-scale differential input range of 5V
peak-to-peak. Figures 37 and 38 show measurement results for the LTC2411 normal mode rejection ratio with a
7.5V peak-to-peak (150% of full scale) input signal superimposed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full scale)
input signal and Figure 39 shows the corresponding measurement result for the LTC2411-1. It is clear that the
LTC2411/LTC2411-1 rejection performance is maintained
with no compromises in this extreme situation. When operating with large input signal levels, the user must observe that such signals do not violate the device absolute
maximum ratings.
Figure 37. Measured Input Normal Mode Rejection
vs Input Frequency (LTC2411)
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
VCC = 5V
VREF = 5V
REF – = GND
VINCM = 2.5V
FO = GND
TA = 25°C
– 60
–80
–100
–120
0
20
40
60
80 100 120 140 160
INPUT FREQUENCY (Hz)
180
200
220
2411 F39
Figure 39. Measured Input Normal Mode Rejection
vs Input Frequency (LTC2411-1)
LTC2411/LTC2411-1
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Another option is the use of a reference within the 5V input
range of the LTC2411/LTC2411-1 and developing excitation via fixed gain, or LTC1043 based voltage multiplication, along with remote feedback in the excitation
amplifiers, as shown in Figures 45 and 46.
Averaging 64 samples however reduces the noise level by
a factor of eight, bringing the resolving power to 1 part in
40000, comparable to better weighing systems. Hysteresis and creep effects in the load cells are typically much
greater than this. Most applications that require strain
measurements to this level of accuracy are measuring
slowly changing phenomena, hence the time required to
average a large number of readings is usually not an issue.
For those systems that require accurate measurement of
a small incremental change on a significant tare weight,
the lack of history effects in the LTC2400 family is of great
benefit.
Figure 40 shows an example of a simple bridge connection. Note that it is suitable for any bridge application
where measurement speed is not of the utmost importance. For many applications where large vessels are
weighed, the average weight over an extended period of
time is of concern and short term weight is not readily
determined due to movement of contents, or mechanical
resonance. Often, large weighing applications involve load
cells located at each load bearing point, the output of
which can be summed passively prior to the signal processing circuitry, actively with amplification prior to the
ADC, or can be digitized via multiple ADC channels and
summed mathematically. The mathematical summation
of the output of multiple LTC2411/LTC2411-1’s provide
the benefit of a root square reduction in noise. The low
power consumption of the LTC2411/LTC2411-1 make it
attractive for multidrop communication schemes where
the ADC is located within the load-cell housing.
For those applications that cannot be fulfilled by the
LTC2411/LTC2411-1 alone, compensating for error in
external amplification can be done effectively due to the
“no latency” feature of the LTC2411/LTC2411-1. No
latency operation allows samples of the amplifier offset
and gain to be interleaved with weighing measurements.
The use of correlated double sampling allows suppression of 1/f noise, offset and thermocouple effects within
the bridge. Correlated double sampling involves alternating the polarity of excitation and dealing with the reversal
of input polarity mathematically. Alternatively, bridge
excitation can be increased to as much as ±10V, if one of
several precision attenuation techniques is used to produce a precision divide operation on the reference signal.
A direct connection to a load cell is perhaps best incorporated into the load-cell body, as minimizing the distance to
+
R1
350Ω
BRIDGE
LT1019
1
2
REF +
3
REF –
4
IN +
VCC
SDO
SCK
CS
8
9
7
LTC2411/
LTC2411-1
5
IN –
GND
R2
FO
10
6
2411 F40
R1 AND R2 CAN BE USED TO INCREASE TOLERABLE AC COMPONENT ON REF SIGNALS
Figure 40. Simple Bridge Connection
33
LTC2411/LTC2411-1
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the sensor largely eliminates the need for protection
devices, RFI suppression and wiring. The LTC2411/
LTC2411-1 exhibit extremely low temperature dependent
drift. As a result, exposure to external ambient temperature ranges does not compromise performance. The incorporation of any amplification considerably complicates
thermal stability, as input offset voltages and currents,
temperature coefficient of gain settling resistors all become factors.
input stage from the transient load steps produced during
conversion.
The gain stability and accuracy of this approach is very
good, due to a statistical improvement in resistor matching due to individual error contribution being reduced. A
gain of 34 may seem low, when compared to common
practice in earlier generations of load-cell interfaces, however the accuracy of the LTC2411/LTC2411-1 changes the
rationale. Achieving high gain accuracy and linearity at
higher gains may prove difficult, while providing little
benefit in terms of noise reduction.
The circuit in Figure 41 shows an example of a simple
amplification scheme. This example produces a differential output with a common mode voltage of 2.5V, as
determined by the bridge. The use of a true three amplifier
instrumentation amplifier is not necessary, as the LTC2411/
LTC2411-1 have common mode rejection far beyond that
of most amplifiers. The LTC1051 is a dual autozero amplifier that can be used to produce a gain of 30 before its input
referred noise dominates the LTC2411/LTC2411-1 noise.
This example shows a gain of 34, that is determined by a
feedback network built using a resistor array containing
eight individual resistors. The resistors are organized to
optimize temperature tracking in the presence of thermal
gradients. The second LTC1051 buffers the low noise
At a gain of 100, the gain error that could result from
typical open-loop gain of 160dB is –1ppm, however,
worst-case is at the minimum gain of 116dB, giving a gain
error of –158ppm. Worst-case gain error at a gain of 34,
is –54ppm. The use of the LTC1051A reduces the worstcase gain error to –33ppm. The advantage of gain higher
than 34, then becomes dubious, as the input referred
noise sees little improvement1 and gain accuracy is potentially compromised.
1Input referred noise for A
V = 34 is approximately 0.05µVRMS, whereas at a gain of 50, it would be
0.048µVRMS.
5VREF
0.1µF
5V
3
8
+
2
5V
–
2
4
350Ω
BRIDGE
–
14
4
5
12
3
1
RN1
16
6
11
7
2
6
8
3
–
2
REF +
3
REF –
4
IN +
4
13
U2B
5
7
5
+
RN1 = 5k × 8 RESISTOR ARRAY
U1A, U1B, U2A, U2B = 1/2 LTC1051
Figure 41. Using Autozero Amplifiers to Reduce Input Referred Noise
34
VCC
SDO
SCK
CS
8
9
7
LTC2411/
LTC2411-1
–
7
+
1
9
6
U1B
5
10
+
1
8
U2A
15
0.1µF
0.1µF
1
U1A
IN –
GND
FO
10
6
2411 F41
LTC2411/LTC2411-1
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Note that this 4-amplifier topology has advantages over
the typical integrated 3-amplifier instrumentation amplifier in that it does not have the high noise level common in
the output stage that usually dominates when an instrumentation amplifier is used at low gain. If this amplifier is
used at a gain of 10, the gain error is only 10ppm and input
referred noise is reduced to 0.15µVRMS. The buffer stages
can also be configured to provide gain of up to 50 with high
gain stability and linearity.
Common mode gain is half the differential gain. The
maximum differential signal that can be used is 1/4 VREF,
as opposed to 1/2 VREF in the 2-amplifier topology above.
Remote Half Bridge Interface
As opposed to full bridge applications, typical half bridge
applications must contend with nonlinearity in the bridge
output, as signal swing is often much greater. Applications
include RTD’s, thermistors and other resistive elements
that undergo significant changes over their span. For
single variable element bridges, the nonlinearity of the half
Figure 42 shows an example of a single amplifier used to
produce single-ended gain. This topology is best used in
applications where the gain setting resistor can be made
to match the temperature coefficient of the strain gauges.
If the bridge is composed of precision resistors, with only
one or two variable elements, the reference arm of the
bridge can be made to act in conjunction with the feedback
resistor to determine the gain. If the feedback resistor is
incorporated into the design of the load cell, using resistors which match the temperature coefficient of the loadcell elements, good results can be achieved without the
need for resistors with a high degree of absolute accuracy.
The common mode voltage in this case, is again a function
of the bridge output. Differential gain as used with a 350Ω
bridge is:
VS
2.7V TO 5.5V
1
2
R1
25.5k
0.1%
REF +
VCC
3
REF –
LTC2411/
LTC2411-1
4
+
IN
2 4
PLATINUM
100Ω
RTD 1
3
5
IN –
GND
6
R1 + R2
A V = 9.95 =
R1 + 175Ω
2411 F43
Figure 43. Remote Half Bridge Interface
5V
+
10µF
0.1µF
5V
350Ω
BRIDGE
3
+
LTC1050S8
2
+
–
1
0.1µV
7
6
175Ω
REF +
3
REF –
4
IN +
+
1µF
4
2
20k
1µF
R1
4.99k
R2
46.4k
VCC
LTC2411/
LTC2411-1
20k
5
IN –
GND
6
AV = 9.95 =
R1 + R2
R1 + 175Ω
2411 F42
Figure 42. Bridge Amplification Using a Single Amplifier
35
LTC2411/LTC2411-1
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bridge output can be eliminated completely; if the reference arm of the bridge is used as the reference to the ADC,
as shown in Figure 43. The LTC2411/LTC2411-1 can
accept inputs up to 1/2 VREF. Hence, the reference resistor
R1 must be at least 2× the highest value of the variable
resistor.
result as the two resistor version, but has a few benefits.
If, for example, a 25k reference resistor is used to set the
excitation current with a 100Ω RTD, the negative
reference input is sampling the same external node as the
positive input, but may result in errors if used with a long
cable. For short cable applications, the errors may be
acceptably low. If instead the single 25k resistor is
replaced with a 10k 5% and a 10k 0.1% reference
resistor, the noise level introduced at the reference, at
least at higher frequencies, will be reduced. A filter can be
introduced into the network, in the form of one or more
capacitors, or ferrite beads, as long as the sampling
pulses are not translated into an error. The reference
voltage is also reduced, but this is not undesirable, as it
will decrease the value of the LSB, although, not the input
referred noise level.
In the case of 100Ω platinum RTD’s, this would suggest a
value of 800Ω for R1. Such a low value for R1 is not
advisable due to self-heating effects. A value of 25.5k is
shown for R1, reducing self-heating effects to acceptable
levels for most sensors.
The basic circuit shown in Figure 43 shows connections
for a full 4-wire connection to the sensor, which may be
located remotely. The differential input connections will
reject induced or coupled 60Hz interference, however, the
reference inputs do not have the same rejection. If 60Hz or
other noise is present on the RTD, a low pass filter is
recommended as shown in Figure 44. Note that you
cannot place a large capacitor directly at the junction of R1
and R2, as it will store charge from the sampling process.
A better approach is to produce a low pass filter decoupled
from the input lines with a high value resistor (R3).
The circuit shown in Figure 44 shows a more rigorous
example of Figure 43, with increased noise suppression
and more protection for remote applications.
Figure 45 shows an example of gain in the excitation circuit
and remote feedback from the bridge. The LTC1043s
provide voltage multiplication, providing ±10V from a 5V
reference with only 1ppm error. The amplifiers are used at
unity-gain and, hence, introduce a very little error due to
The use of a third resistor in the half bridge, between the
variable and fixed elements gives essentially the same
5V
R2
10k
0.1%
R1
10k, 5%
2 4
PLATINUM
100Ω
RTD 1
3
5V
R3
10k
5%
+
1µF
1
560Ω
LTC1050
2
REF +
3
REF –
–
VCC
LTC2411/
LTC2411-1
10k
4
IN +
10k
5
IN –
GND
6
2411 F44
Figure 44. Remote Half Bridge Sensing with Noise Suppression on Reference
36
LTC2411/LTC2411-1
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15V
7
20Ω
Q1
2N3904
15V
U1
4
LTC1043
15V
6
+
4
200Ω
2
LT1236-5
+
47µF
11
10V
+
0.1µF
12
14
13
+
10µF
0.1µF
1k
5V
7
1µF
–15V
33Ω
8
*
LTC1150
–
10V
3
17
350Ω 10V
BRIDGE
5V
0.1µF
1
VCC
LTC2411/
LTC2411-1
2
REF +
3
REF –
–10V
33Ω
Q2
2N3906
6
+
3
4
–15V
–
6
6
*
2
2
3
–15V
1k
IN –
GND
5
LTC1150
20Ω
IN +
5
U2
LTC1043
15V
7
4
15
18
0.1µF
*FLYING CAPACITORS ARE
1µF FILM (MKP OR EQUIVALENT)
5V
U2
4
LTC1043
8
7
SEE LTC1043 DATA SHEET FOR
DETAILS ON UNUSED HALF OF U1
*
11
1µF
FILM
12
200Ω
14
13
2411 F45
–10V
17
–10V
Figure 45. LTC1043 Provides Precise 4 × Reference for Excitation Voltages
37
LTC2411/LTC2411-1
U
W
U U
APPLICATIO S I FOR ATIO
gain error or due to offset voltages. A 1µV/°C offset voltage
drift translates into 0.05ppm/°C gain error. Simpler alternatives, with the amplifiers providing gain using resistor
arrays for feedback, can produce results that are similar to
bridge sensing schemes via attenuators. Note that the
amplifiers must have high open-loop gain or gain error will
be a source of error. The fact that input offset voltage has
relatively little effect on overall error may lead one to use
low performance amplifiers for this application. Note that
the gain of a device such as an LF156, (25V/mV over
temperature) will produce a worst-case error of –180ppm
at a noise gain of 3, such as would be encountered in an
inverting gain of 2, to produce –10V from a 5V reference.
the LTC2411/LTC2411-1 of 2.5V, maximizing the AC input
range for applications where induced 60Hz could reach
amplitudes up to 2VRMS.
The circuits in Figures 45 and 47 could be used where
multiple bridge circuits are involved and bridge output can
be multiplexed onto a single LTC2411/LTC2411-1, via an
inexpensive multiplexer such as the 74HC4052.
Figure 46 shows the use of an LTC2411/LTC2411-1 with
a differential multiplexer. This is an inexpensive multiplexer that will contribute some error due to leakage if
used directly with the output from the bridge, or if resistors
are inserted as a protection mechanism from overvoltage.
Although the bridge output may be within the input range
of the A/D and multiplexer in normal operation, some
thought should be given to fault conditions that could
result in full excitation voltage at the inputs to the multiplexer or ADC. The use of amplification prior to the
multiplexer will largely eliminate errors associated with
channel leakage developing error voltages in the source
impedance.
The error associated with the 10V excitation would be
–80ppm. Hence, overall reference error could be as high
as 130ppm, the average of the two.
Figure 47 shows a similar scheme to provide excitation
using resistor arrays to produce precise gain. The circuit
is configured to provide 10V and –5V excitation to the
bridge, producing a common mode voltage at the input to
5V
5V
+
16
47µF
12
14
15
11
REF +
3
REF –
LTC2411/
LTC2411-1
74HC4052
1
5
TO OTHER
DEVICES
2
1
VCC
13
4
IN +
3
5
IN –
2
6
4
GND
6
8
9
10
A0
A1
2411 F46
Figure 46. Use a Differential Multiplexer to Expand Channel Capability
38
LTC2411/LTC2411-1
U
PACKAGE DESCRIPTIO
MS10 Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.118 ± 0.004*
(3.00 ± 0.102)
10 9 8 7 6
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1 2 3 4 5
0.034
(0.86)
REF
0.043
(1.10)
MAX
0.007
(0.18)
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE 0.007 – 0.011
(0.17 – 0.27)
0.0197
(0.50)
BSC
0.005 ± 0.002
(0.13 ± 0.05)
MSOP (MS10) 1100
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
39
LTC2411/LTC2411-1
U
TYPICAL APPLICATIO
15V
+
20Ω
Q1
2N3904
1/2
LT1112
1
–
C1
0.1µF
22Ω
5V
3
LT1236-5
+
C3
47µF
2
C1
0.1µF
RN1
10k
10V
1
5V
2
RN1
10k
350Ω BRIDGE
TWO ELEMENTS
VARYING
3
1
VCC
LTC2411/
LTC2411-1
2
REF +
3
REF –
4
–5V
8
RN1
10k
5
7
IN +
5
IN –
GND
6
6
C2
0.1µF
33Ω
×2
Q2, Q3
2N3906
×2
RN1
10k
4
20Ω
7
15V
RN1 IS CADDOCK T914 10K-010-02
8
4
–15V
–
1/2
LT1112
–15V
+
6
5
2411 F47
Figure 47. Use Resistor Arrays to Provide Precise Matching in Excitation Amplifier
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max Initial Accuracy
LT1025
Micropower Thermocouple Cold Junction Compensator
80µA Supply Current, 0.5°C Initial Accuracy
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ∆Σ ADC in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410
24-Bit, Fully Differential, No Latency ∆Σ ADC
0.16ppm Noise, 2ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2413
24-Bit, Fully Differential, No Latency ∆Σ ADC
Simultaneous 50Hz and 60Hz Rejection, 800nVRMS Noise
LTC2415
24-Bit, No Latency ∆Σ ADC with 15Hz Output Rate
Pin Compatible with the LTC2410
LTC2420
20-Bit, No Latency ∆Σ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin Compatible with LTC2400
LTC2424/LTC2428
4-/8-Channel, 20-Bit, No Latency ∆Σ ADC
1.2ppm Noise, Pin Compatible with LTC2404/LTC2408
40
Linear Technology Corporation
24111f LT/TP 0601 2K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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●
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