Cypress CY7C1009D 1-mbit (128k x 8) static ram Datasheet

CY7C109D
CY7C1009D
1-Mbit (128K x 8) Static RAM
Functional Description [1]
Features
• Pin- and function-compatible with CY7C109B/CY7C1009B
• High speed
— tAA = 10 ns
• Low active power
— ICC = 80 mA @ 10 ns
• Low CMOS standby power
The CY7C109D/CY7C1009D is a high-performance CMOS
static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW
Output Enable (OE), and tri-state drivers.The eight input and
output pins (IO0 through IO7) are placed in a high-impedance
state when:
• Deselected (CE1 HIGH or CE2 LOW),
— ISB2 = 3 mA
• Outputs are disabled (OE HIGH),
• 2.0V Data Retention
• When the write operation is active (CE1 LOW, CE2 HIGH,
and WE LOW)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2 and OE options
• CY7C109D available in Pb-free 32-pin 400-Mil wide Molded
SOJ and 32-pin TSOP I packages. CY7C1009D available
in Pb-free 32-pin 300-Mil wide Molded SOJ package
Write to the device by taking Chip Enable One (CE1) and Write
Enable (WE) inputs LOW and Chip Enable Two (CE2) input
HIGH. Data on the eight IO pins (IO0 through IO7) is then
written into the location specified on the address pins (A0
through A16).
Read from the device by taking Chip Enable One (CE1) and
Output Enable (OE) LOW while forcing Write Enable (WE) and
Chip Enable Two (CE2) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
appears on the IO pins.
Logic Block Diagram
IO0
INPUT BUFFER
IO1
128K x 8
ARRAY
IO2
SENSE AMPS
ROW DECODER
A0
A1
A2
A3
A4
A5
A6
A7
A8
IO3
IO4
IO5
IO6
CE1
CE2
COLUMN DECODER
A9
A10
A11
A12
A13
A14
A15
A16
WE
IO7
POWER
DOWN
OE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05468 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 22, 2007
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CY7C109D
CY7C1009D
Pin Configurations [2]
SOJ
Top View
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
IO7
IO6
IO5
IO4
IO3
GND
IO2
IO1
IO0
A0
A1
A2
A3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
IO 0
IO 1
IO 2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
IO 7
IO 6
IO 5
IO 4
IO 3
Selection Guide
CY7C109D-10
CY7C1009D-10
Unit
Maximum Access Time
10
ns
Maximum Operating Current
80
mA
Maximum CMOS Standby Current
3
mA
Note
2. NC pins are not connected on the die.
Document #: 38-05468 Rev. *E
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CY7C109D
CY7C1009D
DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND [3] ... –0.5V to +6.0V
DC Voltage Applied to Outputs
in High-Z State [3] ...................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current .................................................... > 200 mA
Operating Range
Range
Ambient
Temperature
VCC
Speed
Industrial
–40°C to +85°C
5V ± 0.5V
10 ns
Electrical Characteristics (Over the Operating Range)
Parameter
Description
7C109D-10
7C1009D-10
Test Conditions
Min
VOH
Output HIGH Voltage
IOH = –4.0 mA
VOL
Output LOW Voltage
IOL = 8.0 mA
VIH
Input HIGH Voltage
Unit
Max
2.4
[3]
V
0.4
V
2.2
VCC + 0.5
V
–0.5
0.8
V
VIL
Input LOW Voltage
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating Supply Current VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
80
mA
83 MHz
72
mA
66 MHz
58
mA
40 MHz
37
mA
ISB1
Automatic CE Power-Down
Current—TTL Inputs
Max VCC,
CE1 > VIH or CE2 < VIL,
VIN > VIH or VIN < VIL, f = fmax
10
mA
ISB2
Automatic CE Power-Down
Current—CMOS Inputs
Max VCC,
CE1 > VCC – 0.3V, or CE2 < 0.3V,
VIN > VCC – 0.3V, or VIN < 0.3V, f = 0
3
mA
Note
3. VIL (min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
Document #: 38-05468 Rev. *E
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CY7C109D
CY7C1009D
Capacitance [4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max
Unit
8
pF
8
pF
TA = 25°C, f = 1 MHz, VCC = 5.0V
Thermal Resistance [4]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
300-Mil
Wide SOJ
400-Mil
Wide SOJ
TSOP I
Unit
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
57.61
56.29
50.72
°C/W
40.53
38.14
16.21
°C/W
AC Test Loads and Waveforms [5]
ALL INPUT PULSES
3.0V
Z = 50Ω
90%
OUTPUT
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30 pF*
90%
10%
10%
GND
1.5V
Rise Time: ≤ 3 ns
(a)
(b)
Fall Time: ≤ 3 ns
High-Z characteristics:
R1 480Ω
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
R2
255Ω
5 pF
(c)
Notes
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05468 Rev. *E
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CY7C109D
CY7C1009D
Switching Characteristics (Over the Operating Range) [6]
Parameter
7C109D-10
7C1009D-10
Description
Min
Unit
Max
Read Cycle
tpower [7]
VCC(typical) to the first access
100
µs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE1 LOW to Data Valid, CE2 HIGH to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
tLZCE
tHZCE
tPU
[10]
tPD
[10]
Write Cycle
OE HIGH to High Z
10
3
ns
10
ns
5
ns
0
[8, 9]
CE1 LOW to Low Z, CE2 HIGH to Low Z
ns
5
[9]
CE1 HIGH to High Z, CE2 LOW to High Z
3
[8, 9]
CE1 LOW to Power-Up, CE2 HIGH to Power-Up
ns
ns
5
0
CE1 HIGH to Power-Down, CE2 LOW to Power-Down
ns
ns
ns
10
ns
[11, 12]
tWC
Write Cycle Time
10
ns
tSCE
CE1 LOW to Write End, CE2 HIGH to Write End
7
ns
tAW
Address Set-Up to Write End
7
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-Up to Write End
6
ns
tHD
Data Hold from Write End
0
ns
[9]
tLZWE
WE HIGH to Low Z
tHZWE
WE LOW to High Z [8, 9]
3
ns
5
ns
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed
8. tHZOE, tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured when the outputs enter
a high impedance state.
9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. CE1 and WE must be LOW and CE2 HIGH to initiate a write, and
the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05468 Rev. *E
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CY7C109D
CY7C1009D
Data Retention Characteristics (Over the Operating Range)
Parameter
Description
Conditions
VCC = VDR = 2.0V,
CE1 > VCC – 0.3V or CE2 < 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR [4]
Chip Deselect to Data Retention Time
tR
[13]
Min
Max
2.0
V
3
Operation Recovery Time
Unit
mA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
4.5V
VCC
4.5V
VDR > 2V
tCDR
tR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [14, 15]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [15, 16]
ADDRESS
tRC
CE1
CE2
tACE
OE
tHZOE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
50%
50%
ICC
ISB
Notes
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.
14. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
15. WE is HIGH for read cycle.
16. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
Document #: 38-05468 Rev. *E
Page 6 of 11
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CY7C109D
CY7C1009D
Switching Waveforms (continued)
Write Cycle No. 1 (CE1 or CE2 Controlled) [17, 18]
tWC
ADDRESS
tSCE
CE1
tSA
CE2
tSCE
tAW
tHA
tPWE
WE
tSD
tHD
DATA VALID
DATA IO
Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [17, 18]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tSA
tHA
tPWE
WE
OE
tSD
DATA IO
t HD
DATAIN VALID
NOTE 19
tHZOE
Notes
17. Data IO is high impedance if OE = VIH.
18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state.
19. During this period the IOs are in the output state and input signals should not be applied.
Document #: 38-05468 Rev. *E
Page 7 of 11
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CY7C109D
CY7C1009D
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW) [12, 18]
tWC
ADDRESS
tSCE
CE1
CE2
tSCE
tAW
tHA
tSA
tPWE
WE
tSD
DATA IO
NOTE 19
tHD
DATA VALID
tLZWE
tHZWE
Truth Table
CE1
CE2
OE
WE
IO0–IO7
Mode
Power
H
X
X
X
High Z
Power-down
Standby (ISB)
X
L
X
X
High Z
Power-down
Standby (ISB)
L
H
L
H
Data Out
Read
Active (ICC)
L
H
X
L
Data In
Write
Active (ICC)
L
H
H
H
High Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
Ordering Code
Package
Diagram
Package Type
CY7C109D-10VXI
51-85033
32-pin (400-Mil) Molded SOJ (Pb-free)
CY7C109D-10ZXI
51-85056
32-pin TSOP Type I (Pb-free)
CY7C1009D-10VXI
51-85041
32-pin (300-Mil) Molded SOJ (Pb-free)
Operating
Range
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Document #: 38-05468 Rev. *E
Page 8 of 11
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CY7C109D
CY7C1009D
Package Diagrams
Figure 1. 32-pin (300-Mil) Molded SOJ, 51-85041
51-85041-*A
Figure 2. 32-pin (400-Mil) Molded SOJ, 51-85033
51-85033-*B
Document #: 38-05468 Rev. *E
Page 9 of 11
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CY7C109D
CY7C1009D
Package Diagrams (continued)
Figure 3. 32-pin Thin Small Outline Package Type I (8x20 mm), 51-85056
51-85056-*D
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05468 Rev. *E
Page 10 of 11
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C109D
CY7C1009D
Document History Page
Document Title: CY7C109D/CY7C1009D, 1-Mbit (128K x 8) Static RAM
Document Number: 38-05468
REV.
ECN NO.
Issue Date
Orig. of
Change
**
201560
See ECN
SWI
Advance Information data sheet for C9 IPP
*A
233722
See ECN
RKF
DC parameters are modified as per EROS (Spec # 01-2165)
Pb-free offering in Ordering Information
*B
262950
See ECN
RKF
Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics Table
Shaded Ordering Information
*C
See ECN
See ECN
RKF
Reduced Speed bins to -10 and -12 ns
*D
560995
See ECN
VKN
Converted from Preliminary to Final
Removed Commercial Operating range
Removed 12 ns speed bin
Added ICC values for the frequencies 83MHz, 66MHz and 40MHz
Updated Thermal Resistance table
Updated Ordering Information Table
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3
*E
802877
See ECN
VKN
Changed ICC spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for
83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz
Document #: 38-05468 Rev. *E
Description of Change
Page 11 of 11
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