Microchip MCP4024T-202E/OT Low-cost nv digital pot with wiperlockâ ¢ technology Datasheet

MCP4021/2/3/4
Low-Cost NV Digital POT with WiperLock™ Technology
Package Types
• Non-volatile Digital Potentiometer in SOT-23,
SOIC, MSOP and DFN packages
• 64 Taps: 63 Resistors with Taps to terminal A and
terminal B
• Simple Up/Down (U/D) Protocol
• Power-on Recall of Saved Wiper Setting
• Resistance Values: 2.1 kΩ, 5 kΩ, 10 kΩ or 50 kΩ
• Low Tempco:
- Absolute (Rheostat): 50 ppm (0°C to 70°C typ.)
- Ratiometric (Potentiometer): 10 ppm (typ.)
• Low Wiper Resistance: 75Ω (typ.)
• WiperLock™ Technology to Secure the wiper
setting in non-volatile memory (EEPROM)
• High-Voltage Tolerant Digital Inputs: Up to 12.5V
• Low-Power Operation: 1 µA Max Static Current
• Wide Operating Voltage: 2.7V to 5.5V
• Extended Temperature Range: -40°C to +125°C
• Wide Bandwidth (-3 dB) Operation:
- 4 MHz (typ.) for 2.1 kΩ device
MCP4021
MCP4022
SOIC, MSOP, DFN
Potentiometer
SOT-23-6
Rheostat
VDD 1
VSS 2
A 3
A
B
W
W 4
8 U/D
VDD 1
7 NC
VSS 2
6 B
U/D 3
A
6 A
W
5 W
4 CS
B
5 CS
MCP4023
MCP4024
SOT-23-6
Potentiometer
SOT-23-5
Rheostat
VDD 1
VSS 2
U/D 3
A
W
B
6 A
VDD 1
5 W
VSS 2
4 CS
U/D 3
5 W
W
B
A
4 CS
Block Diagram
A
VDD
Description
VSS
The MCP4021/2/3/4 devices are non-volatile, 6-bit
digital potentiometers that can be configured as either a
potentiometer or rheostat. The wiper setting is
controlled through a simple Up/Down (U/D) serial
interface.
Power-Up
and
Brown-Out
Control
2-Wire
Interface
and
Control
Logic
CS
U/D
These device’s implement Microchip’s WiperLock technology, which allows application-specific calibration
settings to be secured in the EEPROM without
requiring the use of an additional write-protect pin.
Wiper Register
(Resistor Array)
Features
W
EEPROM and
WiperLock™
Technology
B
Device Features
Device
Wiper
Configuration
Memory
Type
Resistance (typical)
Options (kΩ)
VDD
# of
Control WiperLock™
Operating
Steps
Interface
Technology
Wiper (Ω)
Range
MCP4021 Potentiometer (1)
EE
2.1, 5.0, 10.0, 50.0
75
64
2.7V - 5.5V
U/D
Yes
MCP4022
Rheostat
EE
2.1, 5.0, 10.0, 50.0
75
64
2.7V- 5.5V
U/D
Yes
MCP4023
Potentiometer
EE
2.1, 5.0, 10.0, 50.0
75
64
2.7V - 5.5V
U/D
Yes
MCP4024
Rheostat
EE
2.1, 5.0, 10.0, 50.0
75
64
2.7V - 5.5V
U/D
Yes
Note 1:
Floating either terminal (A or B) allows the device to be used in Rheostat mode.
.
© 2006 Microchip Technology Inc.
DS21945E-page 1
MCP4021/2/3/4
1.0
ELECTRICAL
CHARACTERISTICS
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
Absolute Maximum Ratings †
VDD ............................................................................................................. 6.5V
CS and U/D inputs w.r.t VSS.................................... -0.3V to 12.5V
A, B and W terminals w.r.t VSS.................... -0.3V to VDD + 0.3V
Current at Input Pins ..................................................±10 mA
Current at Supply Pins ...............................................±10 mA
Current at Potentiometer Pins ...................................±2.5 mA
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-55°C to +125°C
ESD protection on all pins ........... ≥ 4 kV (HBM), ≥ 400V (MM)
Maximum Junction Temperature (TJ) . .........................+150°C
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Operating Voltage Range
CS Input Voltage
Supply Current
IDD
Resistance
(± 20%)
Min
Typ
VDD
2.7
—
5.5
V
VCS
VSS
—
12.5
V
RAB
Resolution
N
Step Resistance
RS
Note 1:
2:
3:
4:
5:
6:
7:
8:
Max
Units
Conditions
The CS pin will be at one of three
input levels (VIL, VIH or VIHH).
(Note 6)
—
45
—
µA
5.5V, CS = VSS, fU/D = 1 MHz
—
15
—
µA
2.7V, CS = VSS, fU/D = 1 MHz
—
0.3
1
µA
Serial Interface Inactive
(CS = VIH, U/D = VIH)
—
0.6
3
mA
EE Write cycle, TA = +25°C
1.68
2.1
2.52
kΩ
-202 devices (Note 1)
4.0
5
6.0
kΩ
-502 devices (Note 1)
8.0
10
12.0
kΩ
-103 devices (Note 1)
40.0
50
60.0
kΩ
-503 devices (Note 1)
—
RAB / 63
64
Taps
—
Ω
No Missing Codes
Note 6
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
MCP4022/24 only, test conditions are:
Current at Voltage
Device
Resistance
5.5V
2.1 kΩ
2.25 mA
1.1 mA
5 kΩ
1.4 mA
450 µA
10 kΩ
450 µA
210 µA
50 kΩ
90 µA
40 µA
Comments
2.7V
MCP4022 includes VWZSE
MCP4024 includes VWFSE
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
DS21945E-page 2
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
RW
—
70
125
Ω
—
70
325
Ω
—
50
—
ppm/°C
TA = -20°C to +70°C
—
100
—
ppm/°C
TA = -40°C to +85°C
—
150
—
ppm/°C
TA = -40°C to +125°C
ΔVWA/ΔT
—
10
—
ppm/°C
MCP4021 and MCP4023 only,
code = 1Fh
Full-Scale Error
VWFSE
-0.5
-0.1
+0.5
LSb
Code 3Fh (MCP4021/23 only)
Zero-Scale Error
VWZSE
-0.5
+0.1
+0.5
LSb
Code 00h (MCP4021/23 only)
Wiper Resistance (Note 3, Note 4)
ΔR/ΔT
Nominal Resistance Tempco
Ratiometeric Tempco
Monotonicity
N
Yes
Conditions
5.5V
2.7V
Bits
Potentiometer Integral Non-linearity
INL
-0.5
±0.25
+0.5
LSb
MCP4021/23 only (Note 2)
Potentiometer Differential
Non-linearity
DNL
-0.5
±0.25
+0.5
LSb
MCP4021/23 only (Note 2)
VA,VW,VB
Vss
—
VDD
V
Maximum current through A, W or B
IW
—
—
2.5
mA
Note 6
Leakage current into A, W or B
IWL
—
100
—
nA
MCP4021 A = W = B = VSS
—
100
—
nA
MCP4022/23 A = W = VSS
—
100
—
nA
MCP4024 W = VSS
CAW
—
75
—
pF
f =1 MHz, code = 1Fh
Capacitance (Pw)
CW
—
120
—
pF
f =1 MHz, code = 1Fh
Capacitance (PB)
CBW
—
75
—
pF
f =1 MHz, code = 1Fh
Bandwidth -3 dB
BW
—
4
—
MHz
-202
devices
—
2
—
MHz
-502
devices
—
1
—
MHz
-103
devices
—
200
—
kHz
-503
devices
Resistor Terminal Input Voltage
Range (Terminals A, B and W)
Capacitance (PA)
Note 1:
2:
3:
4:
5:
6:
7:
8:
Note 5, Note 6
Code = 1F,
output load = 30 pF
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
MCP4022/24 only, test conditions are:
Current at Voltage
Device
Resistance
5.5V
2.1 kΩ
2.25 mA
1.1 mA
5 kΩ
1.4 mA
450 µA
10 kΩ
450 µA
210 µA
50 kΩ
90 µA
40 µA
Comments
2.7V
MCP4022 includes VWZSE
MCP4024 includes VWFSE
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
© 2006 Microchip Technology Inc.
DS21945E-page 3
MCP4021/2/3/4
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Rheostat Integral Non-linearity
MCP4021 (Note 4, Note 8)
MCP4022 and MCP4024 (Note 4)
Rheostat Differential Non-linearity
MCP4021 (Note 4, Note 8)
MCP4022 and MCP4024 (Note 4)
Note 1:
2:
3:
4:
5:
6:
7:
8:
R-INL
R-DNL
Min
Typ
Max
Units
-0.5
±0.25
+0.5
LSb
-8.5
+4.5
+8.5
LSb
-0.5
±0.25
+0.5
LSb
-5.5
+2.5
+5.5
LSb
-0.5
±0.25
+0.5
LSb
-3
+1
+3
LSb
-0.5
±0.25
+0.5
LSb
-1
+0.25
+1
LSb
-0.5
±0.25
+0.5
LSb
-1
+0.5
+2
LSb
-0.5
±0.25
+0.5
LSb
-1
+0.25
+1.25
LSb
-0.5
±0.25
+0.5
LSb
-1
0
+1
LSb
-0.5
±0.25
+0.5
LSb
-0.5
0
+0.5
LSb
Conditions
-202
devices
(2.1 kΩ)
5.5V
-502
devices
(5 kΩ)
5.5V
-103
devices
(10 kΩ)
5.5V
2.7V (Note 7)
-503
devices
(50 kΩ)
2.7V (Note 7)
2.7V (Note 7)
2.7V (Note 7)
5.5V
-202
devices
(2.1 kΩ)
5.5V
-502
devices
(5 kΩ)
5.5V
2.7V (Note 7)
2.7V (Note 7)
-103
devices
(10 kΩ)
5.5V
-503
devices
(50 kΩ)
5.5V
2.7V (Note 7)
2.7V (Note 7)
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
MCP4022/24 only, test conditions are:
Current at Voltage
Device
Resistance
5.5V
2.1 kΩ
2.25 mA
1.1 mA
5 kΩ
1.4 mA
450 µA
10 kΩ
450 µA
210 µA
50 kΩ
90 µA
40 µA
Comments
2.7V
MCP4022 includes VWZSE
MCP4024 includes VWFSE
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
DS21945E-page 4
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.
TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V,
TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
VIH
0.7 VDD
—
—
V
Conditions
Digital Inputs/Outputs (CS, U/D)
Input High Voltage
VIL
—
—
0.3 VDD
V
High-Voltage Input Entry Voltage
VIHH
8.5
—
12.5(6)
V
High-Voltage Input Exit Voltage
VIHH
—
—
VDD+0.8(6)
V
CS Pull-up/Pull-down Resistance
RCS
—
16
—
kΩ
VDD = 5.5V, VCS = 3V
CS Weak Pull-up/Pull-down Current
IPU
—
170
—
µA
VDD = 5.5V, VCS = 3V
Input Leakage Current
IIL
-1
—
1
µA
VIN = VDD
CIN, COUT
—
10
—
pF
fC = 1 MHz
N
0h
—
3Fh
hex
Input Low Voltage
CS and U/D Pin Capacitance
Threshold for WiperLock™
Technology
RAM (Wiper) Value
Value Range
EEPROM
Endurance
—
1M
—
Cycles
EEPROM Range
N
0h
—
3Fh
hex
Initial Factory Setting
N
Endurance
1Fh
hex
WiperLock Technology = Off
Power Requirements
Power Supply Sensitivity
(MCP4021 and MCP4023 only)
Note 1:
2:
3:
4:
5:
6:
7:
8:
PSS
—
0.0015
0.0035
%/%
VDD = 4.5V to 5.5V, VA = 4.5V,
Code = 1Fh
—
0.0015
0.0035
%/%
VDD = 2.7V to 4.5V, VA = 2.7V,
Code = 1Fh
Resistance is defined as the resistance between terminal A to terminal B.
INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V).
MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h.
MCP4022/24 only, test conditions are:
Current at Voltage
Device
Resistance
5.5V
2.1 kΩ
2.25 mA
1.1 mA
5 kΩ
1.4 mA
450 µA
10 kΩ
450 µA
210 µA
50 kΩ
90 µA
40 µA
Comments
2.7V
MCP4022 includes VWZSE
MCP4024 includes VWFSE
Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
This specification by design
Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See
Section 6.0 “Resistor” for additional information.
The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.
© 2006 Microchip Technology Inc.
DS21945E-page 5
MCP4021/2/3/4
tCSHI
tCSLO
CS
tLUC
1/fUD
tLO
tLCUF
tLUC
tLCUF
U/D
tHI
tLCUR
tS
tS
W
FIGURE 1-1:
Increment Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C.
Parameters
Sym
Min
Typ
Max
Units
CS Low Time
tCSLO
5
—
—
µs
CS High Time
tCSHI
500
—
—
ns
U/D to CS Hold Time
tLUC
500
—
—
ns
CS to U/D Low Setup Time
tLCUF
500
—
—
ns
CS to U/D High Setup Time
tLCUR
3
—
—
µs
U/D High Time
tHI
500
—
—
ns
U/D Low Time
tLO
500
—
—
ns
Up/Down Toggle Frequency
fUD
—
—
1
MHz
tS
0.5
—
—
µs
2.1 kΩ, CL = 100 pF
1
—
—
µs
5 kΩ, CL = 100 pF
2
—
—
µs
10 kΩ, CL = 100 pF
10
5
—
µs
50 kΩ, CL = 100 pF
Wiper Settling Time
Conditions
Wiper Response on Power-up
tPU
—
200
—
ns
Internal EEPROM Write Time
twc
—
—
5
ms
@25°C
—
—
10
ms
-40°C to +125°C
DS21945E-page 6
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
tCSHI
tCSLO
CS
1/fUD
tLUC
tLUC
tHI
tLCUF
U/D
tLO
tLCUR
tS
tS
W
FIGURE 1-2:
Decrement Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C.
Parameters
Sym
Min
Typ
Max
Units
CS Low Time
tCSLO
5
—
—
µs
CS High Time
tCSHI
500
—
—
ns
U/D to CS Hold Time
tLUC
500
—
—
ns
CS to U/D Low Setup Time
tLCUF
500
—
—
ns
CS to U/D High Setup Time
tLCUR
3
—
—
µs
U/D High Time
tHI
500
—
—
ns
U/D Low Time
tLO
500
—
—
ns
Up/Down Toggle Frequency
fUD
—
—
1
MHz
tS
0.5
—
—
µs
2.1 kΩ, CL = 100 pF
1
—
—
µs
5 kΩ, CL = 100 pF
2
—
—
µs
10 kΩ, CL = 100 pF
10
5
—
µs
50 kΩ, CL = 100 pF
Wiper Settling Time
Conditions
Wiper Response on Power-up
tPU
—
200
—
ns
Internal EEPROM Write Time
twc
—
—
5
ms
@25°C
—
—
10
ms
-40°C to +125°C
© 2006 Microchip Technology Inc.
DS21945E-page 7
MCP4021/2/3/4
tCSHI
tCSLO
12V
CS
5V
tHUC
1/fUD
tLO
tHCUF
tHUC
tHCUF
U/D
tHI
tHCUR
tS
tS
W
FIGURE 1-3:
High-Voltage Increment Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C.
Parameters
Sym
Min
Typ
Max
Units
CS Low Time
tCSLO
5
—
—
µs
CS High Time
tCSHI
500
—
—
ns
U/D High Time
tHI
500
—
—
ns
U/D Low Time
tLO
500
—
—
ns
Up/Down Toggle Frequency
fUD
—
—
1
MHz
HV U/D to CS Hold Time
tHUC
1.5
—
—
µs
HV CS to U/D Low Setup Time
tHCUF
8
—
—
µs
HV CS to U/D High Setup Time
tHCUR
4.5
—
—
µs
tS
0.5
—
—
µs
2.1 kΩ, CL = 100 pF
1
—
—
µs
5 kΩ, CL = 100 pF
2
—
—
µs
10 kΩ, CL = 100 pF
10
5
—
µs
50 kΩ, CL = 100 pF
Wiper Settling Time
Conditions
Wiper Response on Power-up
tPU
—
200
—
ns
Internal EEPROM Write Time
twc
—
—
5
ms
@25°C
—
—
10
ms
-40°C to +125°C
DS21945E-page 8
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
tCSHI
tCSLO
CS
12V
5V
1/fUD
tHUC
tHUC
tHI
tHCUF
U/D
tLO
tHCUR
tS
tS
W
FIGURE 1-4:
High-Voltage Decrement Timing Waveform.
SERIAL TIMING CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.
Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C.
Parameters
Sym
Min
Typ
Max
Units
CS Low Time
tCSLO
5
—
—
µs
CS High Time
tCSHI
500
—
—
ns
U/D High Time
tHI
500
—
—
ns
U/D Low Time
tLO
500
—
—
ns
Up/Down Toggle Frequency
fUD
—
—
1
MHz
HV U/D to CS Hold Time
tHUC
1.5
—
—
µs
HV CS to U/D Low Setup Time
tHCUF
8
—
—
µs
HV CS to U/D High Setup Time
tHCUR
4.5
—
—
µs
tS
0.5
—
—
µs
2.1 kΩ, CL = 100 pF
1
—
—
µs
5 kΩ, CL = 100 pF
2
—
—
µs
10 kΩ, CL = 100 pF
10
5
—
µs
50 kΩ, CL = 100 pF
Wiper Settling Time
Conditions
Wiper Response on Power-up
tPU
—
200
—
ns
Internal EEPROM Write Time
twc
—
—
5
ms
@25°C
—
—
10
ms
-40°C to +125°C
© 2006 Microchip Technology Inc.
DS21945E-page 9
MCP4021/2/3/4
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5L-SOT-23
θJA
—
255
—
°C/W
Thermal Resistance, 6L-SOT-23
θJA
—
230
—
°C/W
Thermal Resistance, 8L-DFN (2x3)
θJA
—
85
—
°C/W
Thermal Resistance, 8L-MSOP
θJA
—
206
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
117
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
DS21945E-page 10
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
250
2.7V -40°C
2.7V 25°C
2.7V 85°C
2.7V 125°C
5.5V -40°C
5.5V 25°C
5.5V 85°C
5.5V 125°C
70
60
50
40
30
150
ICS
100
20
50
10
RCS
0
0.20
0
0.40
0.60
fU/D (MHz)
0.80
1.00
FIGURE 2-1:
Device Current (IDD) vs. U/D
Frequency (fU/D) and Ambient Temperature
(VDD = 2.7V and 5.5V).
9
600.0
12
500.0
10
VDD = 5.5V
400.0
300.0
200.0
VDD = 2.7V
100.0
0.0
8
7
6
5
4
VCS (V)
3
2
1
FIGURE 2-4:
CS Pull-up/Pull-down
Resistance (RCS) and Current (ICS) vs. CS Input
Voltage (VCS) (VDD = 5.5V).
CS VPP Threshold (V)
Device Current (IDD) (µA)
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
200
RCS (kOhms)
Device Current (IDD) (µA)
80
Ics (µA)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
1.8V Entry
2.7V Entry
5.5V Entry
1.8V Exit
2.7V Exit
5.5V Exit
8
6
4
2
0
-40
25
85
125
Ambient Temperature (°C)
FIGURE 2-2:
Write Current (IWRITE) vs.
Ambient Temperature and VDD.
-40
-20
0
20
40
60
80 100
Ambient Temperature (°C)
120
FIGURE 2-5:
CS High Input Entry/Exit
Threshold vs. Ambient Temperature and VDD.
Device Current (IDD) (µA)
0.8
0.7
VDD = 5.5V
0.6
0.5
0.4
0.3
VDD = 2.7V
0.2
0.1
0.0
-40
25
85
125
Ambient Temperature (°C)
FIGURE 2-3:
Device Current (ISHDN) vs.
Ambient Temperature and VDD. (CS = VDD).
© 2006 Microchip Technology Inc.
DS21945E-page 11
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
INL
100
0.075
120
0.05
100
0.025
80
0
DNL
60
-0.025
40
-0.05
RW
20
-0.1
0
8
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
300
0
DNL
RW
100
-0.05
0
-0.1
0
60
8
16 24 32 40 48
Wiper Setting (decimal)
56
FIGURE 2-7:
2.1 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
DS21945E-page 12
0.2
40
0
DNL
RW
-0.2
-0.4
8
16 24 32 40 48
Wiper Setting (decimal)
56
FIGURE 2-8:
2.1 kΩ Rheo Mode – RW
(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
400
INL
0.6
0.4
500
0.1
0.8
INL
0
0.05
200
125C Rw
125C INL
125C DNL
0
Error (LSb)
Wiper Resistance
(Rw)(ohms)
-40C Rw
-40C INL
-40C DNL
85C Rw
85C INL
85C DNL
80
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-6:
2.1 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
400
25C Rw
25C INL
25C DNL
20
-0.075
0
-40C Rw
-40C INL
-40C DNL
Error (LSb)
125C Rw
125C INL
125C DNL
INL
10
8
6
300
4
200
2
100
Error (LSb)
85C Rw
85C INL
85C DNL
Wiper Resistance
(Rw)(ohms)
Wiper Resistance
(Rw)(ohms)
25C Rw
25C INL
25C DNL
Wiper Resistance
(Rw)(ohms)
-40C Rw
-40C INL
-40C DNL
120
Error (LSb)
140
0
RW
DNL
0
-2
0
8
16 24 32 40 48
Wiper Setting (decimal)
56
FIGURE 2-9:
2.1 kΩ Rheo Mode – RW
(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2500
-40°C
25°C
85°C
125°C
2000
2060
RWB (Ohms)
Nominal Resistance (RAB)
(Ohms)
2080
VDD = 5.5V
2040
1500
1000
2020
500
VDD = 2.7V
2000
0
-40
0
40
80
Ambient Temperature (°C)
120
FIGURE 2-10:
2.1 kΩ – Nominal
Resistance (Ω) vs. Ambient Temperature and
VDD.
© 2006 Microchip Technology Inc.
0
8
16
24
32
40
48
Wiper Setting (decimal)
56
64
FIGURE 2-11:
2.1 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
DS21945E-page 13
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
WIPER
WIPER
U/D
U/D
FIGURE 2-12:
2.1 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
FIGURE 2-15:
2.1 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
WIPER
WIPER
U/D
U/D
FIGURE 2-13:
2.1 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
FIGURE 2-16:
2.1 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
WIPER
VDD
FIGURE 2-14:
Response Time.
DS21945E-page 14
2.1 kΩ – Power-Up Wiper
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
125C Rw
125C INL
125C DNL
0.075
120
0.05
100
0.025
INL
80
0
DNL
60
-0.025
40
-0.05
RW
20
8
16
24
32
40
48
60
0
DNL
40
-0.2
RW
-0.4
-0.6
8
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
600
0.075
300
0.025
250
0
DNL
-0.025
RW
150
24
100
-0.05
50
-40C Rw
-40C INL
-40C DNL
500
-0.075
400
25C Rw
25C INL
25C DNL
0
-0.125
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-18:
5 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
© 2006 Microchip Technology Inc.
40
48
56
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
5
4
3
INL
300
2
200
1
100
0
-0.1
0
32
FIGURE 2-19:
5 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V)
0.1
0.05
INL
200
16
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
Wiper Resistance
(Rw)(ohms)
350
25C Rw
25C INL
25C DNL
0.4
0.2
0
Error (LSb)
-40C Rw
-40C INL
-40C DNL
0.6
INL
56
FIGURE 2-17:
5 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
400
125C Rw
125C INL
125C DNL
80
Wiper Setting (decimal)
450
85C Rw
85C INL
85C DNL
0
-0.1
0
25C Rw
25C INL
25C DNL
20
-0.075
0
-40C Rw
-40C INL
-40C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
Error (LSb)
Wiper Resistance
(Rw)(ohms)
100
25C Rw
25C INL
25C DNL
Wiper Resistance
(Rw)(ohms)
-40C Rw
-40C INL
-40C DNL
120
Error (LSb)
140
RW
DNL
0
0
8
16
24
32
40
48
-1
56
Wiper Setting (decimal)
FIGURE 2-20:
5 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
DS21945E-page 15
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
6000
2.7V Vdd
5.5V Vdd
4925
4900
4875
VDD = 5.5V
4850
-40°C
25°C
85°C
125°C
5000
RWB (Ohms)
Nominal Resistance (RAB)
(Ohms)
4950
4000
3000
2000
1000
4825
VDD = 2.7V
0
4800
-40
-20
0
20 40 60 80 100 120
Ambient Temperature (°C)
FIGURE 2-21:
5 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
DS21945E-page 16
0
8
16
24
32
40
48
Wiper Setting (decimal)
56
64
FIGURE 2-22:
5 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
WIPER
WIPER
U/D
U/D
FIGURE 2-23:
5 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
FIGURE 2-25:
5 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
WIPER
WIPER
U/D
FIGURE 2-24:
5 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
© 2006 Microchip Technology Inc.
U/D
FIGURE 2-26:
5 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
DS21945E-page 17
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
125C Rw
125C INL
125C DNL
0.05
120
0.025
100
DNL
80
0
INL
60
-0.025
40
-0.05
RW
20
-0.075
0
-40C Rw
-40C INL
-40C DNL
80
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
350
125C Rw
125C INL
125C DNL
INL
250
-0.025
200
-0.05
150
RW
100
0.05
60
0
40
-0.05
RW
-0.1
-0.15
500
0.025
0
300
-0.075
8
16 24 32 40 48
Wiper Setting (decimal)
56
-40C Rw
-40C INL
-40C DNL
400
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0
-0.125
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-28:
10 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
DS21945E-page 18
2.5
1.5
INL
300
0.5
200
-0.5
DNL
RW
100
-1.5
-0.1
50
0.1
FIGURE 2-29:
10 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.05
DNL
0.15
DNL
0
Error (LSb)
Wiper Resistance
(Rw)(ohms)
400
125C Rw
125C INL
125C DNL
0
FIGURE 2-27:
10 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
450
85C Rw
85C INL
85C DNL
INL
16 24 32 40 48 56
Wiper Setting (decimal)
Wiper Resistance
(Rw)(ohms)
8
25C Rw
25C INL
25C DNL
20
-0.1
0
-40C Rw
-40C INL
-40C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
Error (LSb)
Wiper Resistance
(Rw)(ohms)
100
25C Rw
25C INL
25C DNL
Error (LSb)
-40C Rw
-40C INL
-40C DNL
Wiper Resistance
(Rw)(ohms)
120
0
-2.5
0
8
16 24 32 40 48 56
Wiper Setting (decimal)
FIGURE 2-30:
10 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
12000
10250
10230
10210
10190
10170
10150
10130
10110
10090
10070
10050
-40°C
25°C
85°C
125°C
10000
VDD = 5.5V
RWB (Ohms)
Nominal Resistance (RAB)
(Ohms)
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
8000
6000
4000
2000
VDD = 2.7V
0
-40
-20
0
20 40 60 80 100 120
Ambient Temperature (°C)
FIGURE 2-31:
10 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
© 2006 Microchip Technology Inc.
0
8
16
24
32
40
48
Wiper Setting (decimal)
56
64
FIGURE 2-32:
10 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
DS21945E-page 19
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
WIPER
WIPER
U/D
FIGURE 2-33:
10 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
WIPER
U/D
FIGURE 2-34:
10 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
DS21945E-page 20
U/D
FIGURE 2-35:
10 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
WIPER
U/D
FIGURE 2-36:
10 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
0.1
125C Rw
125C INL
125C DNL
200
0.05
DNL
120
0
INL
80
-0.05
RW
40
8
16
24
32
40
48
50
-0.1
0
8
125C Rw
125C INL
125C DNL
400
300
600
0.025
500
-0.025
INL
200
-0.05
-0.075
RW
0
-0.1
8
16
24
32
40
48
56
Wiper Setting (decimal)
FIGURE 2-38:
50 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
© 2006 Microchip Technology Inc.
24
32
40
48
56
FIGURE 2-39:
50 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
0.05
0
0
16
Wiper Setting (decimal)
DNL
100
-0.05
0
-40C Rw
-40C INL
-40C DNL
Wiper Resistance
(Rw)(ohms)
85C Rw
85C INL
85C DNL
0.1
0
RW
56
Error (LSb)
Wiper Resistance
(Rw)(ohms)
500
25C Rw
25C INL
25C DNL
0.15
0.05
DNL
FIGURE 2-37:
50 kΩ Pot Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
-40C Rw
-40C INL
-40C DNL
125C Rw
125C INL
125C DNL
INL
Wiper Setting (decimal)
600
85C Rw
85C INL
85C DNL
100
-0.15
0
25C Rw
25C INL
25C DNL
150
-0.1
0
-40C Rw
-40C INL
-40C DNL
Error (LSb)
85C Rw
85C INL
85C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
1.5
1
RW
400
0.5
INL
300
0
DNL
200
-0.5
100
-1
0
Error (LSb)
Wiper Resistance
(Rw)(ohms)
160
25C Rw
25C INL
25C DNL
Wiper Resistance
(Rw)(ohms)
-40C Rw
-40C INL
-40C DNL
Error (LSb)
200
-1.5
0
8
16
24
32
40
48
56
Wiper Setting (decimal)
FIGURE 2-40:
50 kΩ Rheo Mode – RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 2.7V).
DS21945E-page 21
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
60000
49600
-40C
25C
85C
125C
50000
49400
VDD = 5.5V
49200
49000
48800
VDD = 2.7V
48600
48400
RWB (Ohms)
Nominal Resistance (RAB)
(Ohms)
49800
40000
30000
20000
10000
48200
48000
0
-40
-20
0
20 40 60 80 100 120
Ambient Temperature (°C)
FIGURE 2-41:
50 kΩ – Nominal Resistance
(Ω) vs. Ambient Temperature and VDD.
DS21945E-page 22
0
8
16
24
32
40
48
Wiper Setting (decimal)
56
64
FIGURE 2-42:
50 kΩ – RWB (Ω) vs. Wiper
Setting and Ambient Temperature.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
U/D
U/D
WIPER
WIPER
FIGURE 2-43:
50 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V).
FIGURE 2-46:
50 kΩ – Low-Voltage
Increment Wiper Settling Time (VDD = 2.7V).
U/D
U/D
WIPER
WIPER
FIGURE 2-44:
50 kΩ – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V).
FIGURE 2-47:
50 kΩ - Low-Voltage
Increment Wiper Settling Time (VDD = 5.5V).
WIPER
VDD
FIGURE 2-45:
Response Time.
50 kΩ – Power-Up Wiper
© 2006 Microchip Technology Inc.
DS21945E-page 23
MCP4021/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
-3dB Frequency (MHz)
4.5
4
A
2.1 k:
+5V
3.5
3
VIN
2.5
5 k:
2
1.5
10 k:
1
0.5
W
~
OFFSET
GND
DUT
B
+
VOUT
-
50 k:
2.5V DC
0
-40
25
125
Temperature (°C)
FIGURE 2-48:
Temperature.
DS21945E-page 24
-3 dB Bandwidth vs.
FIGURE 2-49:
Circuit.
-3 dB Bandwidth Test
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin Number
MCP4021
(SOIC-8)
MCP4022
MCP4024 Symbol
MCP4023
(SOT-23-5)
(SOT-23-6)
Buffer
Type
1
1
1
VDD
P
—
Positive Power Supply Input
2
2
VSS
P
—
Ground
3
6
—
A
I/O
A
Potentiometer Terminal A
4
5
5
W
I/O
A
Potentiometer Wiper Terminal
5
4
4
CS
I
TTL
6
—
—
B
I/O
A
Potentiometer Terminal B
7
—
—
NC
—
—
No Connection
8
3
3
U/D
I
TTL
Chip Select Input
Increment/Decrement Input
A = Analog input
O = Output
Positive Power Supply Input (VDD)
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS and can range
from 2.7V to 5.5V. A decoupling capacitor on VDD (to
VSS) is recommended to achieve maximum
performance.
3.2
Function
2
Legend: TTL = TTL compatible input
I = Input
P = Power
3.1
Pin
Type
Ground (VSS)
3.4
Potentiometer Wiper (W) Terminal
The terminal W pin is connected to the internal potentiometer’s terminal W (the wiper). The wiper terminal is
the adjustable terminal of the digital potentiometer. The
terminal W pin does not have a polarity relative to
terminals A or B pins. The terminal W pin can support
both positive and negative current. The voltage on
teminal W must be between VSS and VDD.
The VSS pin is the device ground reference.
3.5
3.3
The terminal B pin is connected to the internal potentiometer’s terminal B (available on some devices). The
potentiometer’s terminal B is the fixed connection to the
0x00 terminal of the digital potentiometer.
Potentiometer Terminal A
The terminal A pin is connected to the internal potentiometer’s terminal A (available on some devices). The
potentiometer’s terminal A is the fixed connection to the
0x3F terminal of the digital potentiometer.
The terminal A pin is available on the MCP4021,
MCP4022 and MCP4023 devices. The terminal A pin
does not have a polarity relative to the terminal W or B
pins. The terminal A pin can support both positive and
negative current. The voltage on teminal A must be
between VSS and VDD.
The terminal A pin is not available on the MCP4024.
The potentiometer’s terminal A is internally floating.
Potentiometer Terminal B
The terminal B pin is available on the MCP4021 device.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on teminal B must be between VSS and VDD.
The terminal B pin is not available on the MCP4022,
MCP4023 and MCP4024 devices.
For the MCP4023 and MCP4024, the internal potentiometer’s terminal B is internally connected to VSS.
Terminal B does not have a polarity relative to terminals
W or A. Terminal B can support both positive and
negative current.
For the MCP4022, terminal B is internally floating.
© 2006 Microchip Technology Inc.
DS21945E-page 25
MCP4021/2/3/4
3.6
Chip Select (CS)
The CS pin is the chip select input. Forcing the CS pin
to VIL enables the serial commands. These commands
can increment and decrement the wiper. Depending on
the command, the wiper may (or may not) be saved to
non-volatile memeory (EEPROM). Forcing the CS pin
to VIHH enables the high-voltage serial commands.
These commands can increment and decrement the
wiper and enable or disable the WiperLock technology.
The wiper is saved to non-volatile memory (EEPROM).
3.7
Increment/Decrement (U/D)
The U/D pin input is used to increment or decrement
the wiper on the digital potentiometer. An increment
moves the wiper one step toward terminal A, while a
decrement moves the wiper one step toward
terminal B.
The CS pin has an internal pull-up resistor. The resistor
will become “disabled” when the voltage on the CS pin
is below the VIH level. This means that when the CS pin
is “floating”, the CS pin will be pulled to the VIH level
(serial communication (the U/D pin) is ignored). And
when the CS pin is driven low (VIL), the resistance
becomes very large to reduce the device current
consumption when serial commands are occurring.
See Figure 2-4 for additional information.
DS21945E-page 26
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
4.0
GENERAL OVERVIEW
EQUATION 4-1:
The MCP402X devices are general purpose digital
potentiometers intended to be used in applications
where a programmable resistance with moderate
bandwidth is desired.
Applications generally suited for the MCP402X devices
include:
•
•
•
•
Set point or offset trimming
Sensor calibration
Selectable gain and offset amplifier designs
Cost-sensitive mechanical trim pot replacement
There are 63 resistors in a string between terminal A
and terminal B. The wiper can be set to tap onto any of
these 63 resistors thus providing 64 possible settings
(including terminal A and terminal B).
Figure 4-1 shows a block diagram for the resistive
network of the device. Equation 4-1 shows the
calculation for the step resistance, while Equation 4-2
illustrates the calculation used to determine the
resistance between the wiper and terminal B.
A
N = 62
RS
3Eh
RW
(1)
RW
(1)
N = 61
RS
3Dh
W
N=1
RS
01h
RW
(1)
RW
(1)
N=0
B
00h
Analog
Mux
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation
effects the smaller resistance devices
(2.1 kΩ) more.
FIGURE 4-1:
EQUATION 4-2:
RWB CALCULATION
R AB N
- + RW
R WB = ------------63
1 LSb is the ideal resistance difference between two
successive codes. If we use N = 1 and RW = 0 in
Equation 4-2, we can calculate the step size for each
increment or decrement command.
The MCP4021 device offers a voltage divider
(potentiometer) with all terminals available on pins.
The MCP4022 is a true rheostat, with terminal A and
the wiper (W) of the variable resistor available on pins.
The MCP4023 device offers a voltage divider (potentiometer) with terminal B connected to ground.
The MCP4024 device is a rheostat device with terminal
A of the resistor floating, terminal B connected to
ground, and the wiper (W) available on pin.
The MCP4021 can be externally configured to
implement any of the MCP4022, MCP4023 or
MCP4024 configurations.
4.1
3Fh
RW (1)
RS
R AB
R S = --------63
N = 0 to 63 (decimal)
The digital potentiometer is available in four nominal
resistances (RAB), where the nominal resistance is
defined as the resistance between terminal A and
terminal B. The four nominal resistances are 2.1 kΩ,
5 kΩ, 10 kΩ and 50 kΩ.
N = 63
RS CALCULATION
Serial Interface
A 2-wire synchronous serial protocol is used to
increment or decrement the digital potentiometer’s
wiper terminal. The Increment/Decrement (U/D)
protocol utilizes the CS and U/D input pins. Both inputs
are tolerant of signals up to 12.5V without damaging
the device. The CS pin can differenciate between two
high-voltage levels, VIH and VIHH. This enables
additional commands without requiring additional input
pins. The high-voltage commands (VIHH on the CS pin)
are similar to the standard commands, except that they
control (enable, disable, ...) the state of the non-volatile
WiperLock technolgy feature.
The simple U/D protocol uses the state of the U/D pin
at the falling edge of the CS pin to determine if
Increment or Decrement mode is desired. Subsequent
rising edges of the U/D pin move the wiper.
The wiper value will not underflow or overflow. The new
wiper setting can be saved to EEPROM, if desired, by
selecting the state of the U/D pin during the rising edge
of the CS pin.
The non-volatile wiper enables the MCP4021/2/3/4 to
operate stand alone (without microcontroller control).
Resistor Block Diagram.
© 2006 Microchip Technology Inc.
DS21945E-page 27
MCP4021/2/3/4
serial
• Incrementing or decrementing the wiper setting
• Writing the wiper setting to the non-volatile
memory
Enabling and disabling the WiperLock technology
feature requires high-voltage serial commands
(CS = VIHH). Incrementing and decrementing the wiper
requires high-voltage commands when the feature is
enabled. The high-voltage threshold (VIHH) is intended
to prevent the wiper setting from being altered by noise
or intentional transitions on the U/D and CS pins, while
still providing flexibility for production or calibration
environments.
Both the CS and U/D input pins are tolerant of signals
up to 12V. This allows the flexibility to multiplex the
digital pot’s control signals onto application signals for
manufacturing/calibration.
4.3
Power-up
When the device powers up, the last saved wiper
setting is restored.
While VDD < Vmin (2.7V), the electrical performance
may not meet the data sheet specifications (see
Figure 4-2). The wiper may be unknown or initialized to
the value stored in the EEPROM. Also the device may
be capable of incrementing, decrementing and writing
to its EEPROM, if a valid command is detected on the
CS and U/D pins.
VDD
Outside
Specified AC/DC
Range
Typical
RAB Value
the
DEFAULT FACTORY
SETTINGS SELECTION
WiperLock™
Technology
Setting
The WiperLock technology prevents
commands from doing the following:
TABLE 4-1:
Wiper
Code
The MCP4021/2/3/4 device’s WiperLock technology
allows application-specific calibration settings to be
secured in the EEPROM without requiring the use of an
additional write-protect pin.
The default settings of the MCP4021/2/3/4 device’s
from the factory are shown in Table 4-1.
Default
POR
Wiper
Setting
The WiperLock™ Technology
Package
Code
4.2
-202
Mid-scale
1Fh
Disabled
2.1 kΩ
-502
Mid-scale
1Fh
Disabled
5.0 kΩ
-103
Mid-scale
1Fh
Disabled
10.0 kΩ
-503
Mid-scale
1Fh
Disabled
50.0 kΩ
It is good practice in your manufacturing flow to
configure the device to your desired settings.
4.4
Brown Out
If the device VDD is below the specified minimum
voltage, care must be taken to ensure that the CS and
U/D pins do not “create” any of the serial commands.
When the device VDD drops below Vmin (2.7V), the
electrical performance may not meet the data sheet
specifications (see Figure 4-2). The wiper may be
unknown or initialized to the value stored in the
EEPROM. Also the device may be capable of
incrementing, decrementing and writing to its EEPROM
if a valid command is detected on the CS and U/D pins.
4.5
Serial Interface Inactive
The serial interface is inactive any time the CS pin is at
VIH and all write cycles are completed.
EEPROM
Write
Protect
2.7V
VWP
VSS
FIGURE 4-2:
DS21945E-page 28
Power-up and Brown-out.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
5.0
SERIAL INTERFACE
5.2
5.1
Overview
The MCP402X devices support 10 serial commands.
The commands can be grouped into the following
types:
The MCP4021/2/3/4 utilizes a simple 2-wire interface to
increment or decrement the digital potentiometer’s
wiper terminal (W), store the wiper setting in non-volatile memory and turn the WiperLock technology feature
on or off. This interface uses the Chip Select (CS) pin,
while the U/D pin is the Up/Down input.
The Increment/Decrement protocol enables the device
to move one step at a time through the range of
possible resistance values. The wiper value is
initialized with the value stored in the internal EEPROM
upon power-up. A wiper value of 00h connects the
wiper to terminal B. A wiper value of 3Fh connects the
wiper to terminal A. Increment commands move the
wiper toward terminal A, but will not increment to a
value greater than 3Fh. Decrement commands move
the wiper toward terminal B, but will not decrement
below 00h.
Refer to Section 1.0 “Electrical Characteristics”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.
Communication is unidirectional. Therefore, the value
of the current wiper setting cannot be read out of the
MCP402X device.
TABLE 5-1:
Serial Commands
• Serial Commands
• High-voltage Serial Commands
All the commands are shown in Table 5-1.
The command type is determined by the voltage level
on the CS pin. The initial state that the CS pin must be
driven is VIH. From VIH, the two levels that the CS pin
can be driven are:
• VIL
• VIHH
If the CS pin is driven from VIH to VIL, a serial
command is selected. If the CS pin is driven from VIH to
VIHH, a high-voltage serial command is selected.
High-voltage serial commands control the state of the
WiperLock technology. This is a unique feature, where
the user can determine whether or not to “lock” or
“unlock” the wiper state.
High-voltage serial commands increment/decrement
the wiper regardless of the status of the WiperLock
technology.
COMMANDS
Command Name
Increment without Writing Wiper Setting to EEPROM
Increment with Writing Wiper Setting to EEPROM
Decrement without Writing Wiper Setting to EEPROM
Saves
Wiper
Value in
EEPROM
High
Voltage
on CS
pin?
After
Command
Wiper is
“locked”/
”unlocked”
Works
when
Wiper is
“locked”?
—
—
unlocked
Note 1
Yes
—
unlocked
Note 1
—
—
unlocked
Note 1
Decrement with Writing Wiper Setting to EEPROM
Yes
—
unlocked
Note 1
Write Wiper Setting to EEPROM
Yes
—
unlocked
Note 1
High-Voltage Increment and Disable WiperLock Technology
Yes
Yes
unlocked
Yes
High-Voltage Increment and Enable WiperLock Technology
Yes
Yes
locked
Yes
High-Voltage Decrement and Disable WiperLock Technology
Yes
Yes
unlocked
Yes
High-Voltage Decrement and Enable WiperLock Technology
Yes
Yes
locked
Yes
Write Wiper Setting to EEPROM and Disable WiperLock
Technology
Yes
Yes
unlocked
Yes
Write Wiper Setting to EEPROM and Enable WiperLock
Technology
Yes
Yes
locked
Yes
Note 1:
This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled).
© 2006 Microchip Technology Inc.
DS21945E-page 29
MCP4021/2/3/4
5.2.1
INCREMENT WITHOUT WRITING
WIPER SETTING TO EEPROM
The EEPROM value has not been updated to this new
wiper value, so if the device voltage is lowered below
the RAM retention voltage of the device, once the
device returns to the operating range, the wiper will be
loaded with the wiper setting in the EEPROM.
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
increment the wiper setting toward terminal A. This is
shown in Figure 5-1.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered. This is
since an EEPROM write cycle (twc) is not active.
After the wiper is incremented to the desired position,
the CS pin should be forced to VIH to ensure that
“unexpected” transitions (on the U/D pin do not cause
the wiper setting to increment. Driving the CS pin to VIH
should occur as soon as possible (within device
specifications) after the last desired increment occurs.
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
VIH
VIL
CS
1
U/D
2
3
5
4
6
VIH
VIL
X
EEPROM
X
Wiper
X
X
X
X
X+1
X+2
X+3
X+4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
Note: If WiperLock technology enabled, wiper will not move.
FIGURE 5-1:
DS21945E-page 30
Increment without Writing Wiper Setting to EEPROM.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
5.2.2
INCREMENT WITH WRITING WIPER
SETTING TO EEPROM
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to increment, the U/D pin
should be driven low and the CS pin forced to VIH as
soon as possible (within device specifications) after the
last desired increment occurs.
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
increment the wiper setting toward terminal A. This is
shown in Figure 5-2.
After the CS pin is driven to VIH (from VIL), all other
serial commands are ignored until the EEPROM write
cycle (twc) completes.
After the wiper is incremented to the desired position,
the U/D pin should be driven low (VIL). Then when the
CS pin is forced to VIH, the wiper value is written to the
EEPROM. Therefore, if the device voltage is lowered
below the RAM retention voltage of the device, once
the device returns to the operating range, the wiper will
be loaded with this wiper setting (stored in the
EEPROM).
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
VIH
VIH
VIL
CS
tWC
VIH
1
2
3
4
5
EEPROM
Wiper
6
VIL
U/D
X
X
X
X
X
X
X+1
X+2
X+3
X+4
X+4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
Note: If WiperLock technology enabled, wiper will not move.
FIGURE 5-2:
Increment with Writing Wiper Setting to EEPROM.
© 2006 Microchip Technology Inc.
DS21945E-page 31
MCP4021/2/3/4
5.2.3
DECREMENT WITHOUT WRITING
WIPER SETTING TO EEPROM
The EEPROM value has not been updated to this new
wiper value, so, if the device voltage is lowered below
the RAM retention voltage of the device, once the
device returns to the operating range, the wiper will be
loaded with the wiper setting in the EEPROM.
This mode is achieved by initializing the U/D pin to a low
state (VIL) prior to achieving a low state (VIL) on the CS
pin. Subsequent rising edges of the U/D pin will
decrement the wiper setting toward terminal B. This is
shown in Figure 5-3.
After the CS pin is driven to VIH (from VIL), any other
serial command may immediately be entered, since an
EEPROM write cycle (tWC) is not started.
After the wiper is decremented to the desired position,
the U/D pin should be forced low (VIL) and the CS pin
should be forced to VIH. This will ensure that
“unexpected” transitions on the U/D pin do not cause
the wiper setting to decrement. Driving the CS pin to
VIH should occur as soon as possible (within device
specifications) after the last desired increment occurs.
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
VIH
VIL
CS
1
U/D
EEPROM
Wiper
2
3
4
5
VIH
6
VIL
VIL
X
X
X
X
X
X
X-1
X-2
X-3
X-4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
Note: If WiperLock technology enabled, wiper will not change.
FIGURE 5-3:
DS21945E-page 32
Decrement without Writing Wiper Setting to EEPROM.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
5.2.4
DECREMENT WITH WRITING
WIPER SETTING TO EEPROM
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to decrement, the U/D
pin should be driven low (VIL) and the CS pin forced to
VIH as soon as possible (within device specifications)
after the last desired increment occurs.
This mode is achieved by initializing the U/D pin to a
low state (VIL) prior to achieving a low state (VIL) on the
CS pin. Subsequent rising edges of the U/D pin
decrement the wiper setting (toward terminal B). This is
shown in Figure 5-4.
After the CS pin is driven to VIH (from VIL), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
After the wiper is decremented to the desired position,
the U/D pin should remain high (VIH). Then when the
CS pin is raised to VIH, the wiper value is written to the
EEPROM. Therefore, if the device voltage is lowered
below the RAM retention voltage of the device, once
the device returns to the operating range, the wiper will
be loaded with this wiper setting (stored in the
EEPROM).
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
VIH
VIL
CS
tWC
1
U/D
EEPROM
Wiper
2
3
4
5
6
VIH
VIL
X
X
X
X
X
X
X-1
X-2
X-3
X-4
X-4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
Note: If WiperLock technology enabled, wiper will not change.
FIGURE 5-4:
Decrement with Writing Wiper Setting to EEPROM.
© 2006 Microchip Technology Inc.
DS21945E-page 33
MCP4021/2/3/4
5.2.5
WRITE WIPER SETTING TO
EEPROM
To write the current wiper setting to EEPROM, force
both the CS pin and U/D pin to VIH. Then force the CS
pin to VIL. Before there is a rising edge on the U/D pin,
force the CS pin to VIH. This causes the wiper setting
value to be written to EEPROM.
Note:
After the U/D pin is forced to VIL, each
rising edge on the U/D pin will cause the
wiper to increment.
This is the same command as the “Increment with Writing Wiper Setting to
EEPROM“ command, but the U/D pin is
held at VIL, so the wiper is not incremented.
When the CS pin is forced to VIH, the wiper value is
written to the EEPROM. Therefore, if the device
voltage is lowered below the RAM retention voltage of
the device, once the device returns to the operating
range, the wiper will be loaded with this wiper setting
(stored in the EEPROM).
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to increment, force the
CS pin to VIH as soon as possible (within device
specifications) after the U/D pin is forced to VIL.
After the CS pin is driven to VIH (from VIL), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
VIH
VIH
VIL
CS
VIH
tWC
5
EEPROM
Wiper
6
VIL
U/D
X
X+4
X+4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
FIGURE 5-5:
DS21945E-page 34
Write Wiper Setting to EEPROM.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
5.2.6
HIGH-VOLTAGE INCREMENT AND
DISABLE WiperLock TECHNOLOGY
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to the CS pin being driven to VIHH.
Subsequent rising edges of the U/D pin increment the
wiper setting toward terminal A. Set the U/D pin to the
high state (VIH) prior to forcing the CS pin to VIH. This
begins a write cycle and disables the WiperLock
Technology feature (See Figure 5-6).
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
VIHH
VIH
VIH
CS
VIH
1
U/D
VIL
EEPROM
X
Wiper
X
2
3
tWC
4
X
X
X
X
X+1
X+2
X+3
X+4
5
6
VIH
X+4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
FIGURE 5-6:
High-Voltage Increment and Disable WiperLock™ Technology.
© 2006 Microchip Technology Inc.
DS21945E-page 35
MCP4021/2/3/4
5.2.7
HIGH-VOLTAGE INCREMENT AND
ENABLE WiperLock TECHNOLOGY
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
This mode is achieved by initializing the U/D pin to a
high state (VIH) prior to the CS pin being driven to VIHH.
Subsequent rising edges of the U/D pin increment the
wiper setting toward terminal A. Set the U/D pin to the
low state (VIL) prior to forcing the CS pin to VIH. This
begins a write cycle and enables the WiperLock
Technology feature (See Figure 5-7).
Note:
The wiper value will not overflow. That is,
once the wiper value equals 0x3F,
subsequent increment commands are
ignored.
VIHH
VIH
VIH
CS
VIH
1
U/D
VIL
EEPROM
X
Wiper
2
3
tWC
4
5
6
VIL
X
X
X
X
X
X+1
X+2
X+3
X+4
X+4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
FIGURE 5-7:
DS21945E-page 36
High-Voltage Increment and Enable WiperLock™ Technology.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
5.2.8
HIGH-VOLTAGE DECREMENT AND
DISABLE WiperLock TECHNOLOGY
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
This mode is achieved by initializing the U/D pin to a
low state (VIL) prior to the CS pin being driven to VIHH.
Subsequent rising edges of the U/D pin decrement the
wiper setting toward terminal B. Set the U/D pin to the
low state (VIL) prior to forcing the CS pin to VIH. This
begins a write cycle and disables the WiperLock
Technology feature (See Figure 5-8).
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
VIHH
VIH
VIH
CS
1
U/D
EEPROM
Wiper
2
3
tWC
4
5
6 VIH
VIL
VIL
X
X
X
X
X
X
X-1
X-2
X-3
X-4
X-4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
FIGURE 5-8:
High-Voltage Decrement and Disable WiperLock™ Technology.
© 2006 Microchip Technology Inc.
DS21945E-page 37
MCP4021/2/3/4
5.2.9
HIGH-VOLTAGE DECREMENT AND
ENABLE WiperLock TECHNOLOGY
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
This mode is achieved by initializing the U/D pin to the
low state (VIL) prior to driving the CS pin to VIHH.
Subsequent rising edges of the U/D pin decrement the
wiper setting toward terminal B. Set the U/D pin to a
high state (VIH) prior to forcing the CS pin to VIH. This
begins a write cycle and enables the WiperLock
Technology feature (See Figure 5-9).
Note:
The wiper value will not underflow. That is,
once the wiper value equals 0x00,
subsequent decrement commands are
ignored.
VIHH
VIH
VIH
CS
1
U/D
EEPROM
Wiper
2
3
tWC
4
VDD 5
6
VIH
VIL
X
X
X
X
X
X
X-1
X-2
X-3
X-4
X-4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
FIGURE 5-9:
DS21945E-page 38
High-Voltage Decrement and Enable WiperLock™ Technology.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
5.2.10
WRITE WIPER SETTING TO
EEPROM AND DISABLE WiperLock
TECHNOLOGY
This mode is achieved by keeping the U/D pin static
(either at VIL or at VIH), while the CS pin is driven from
VIH to VIHH and then returned to VIH. When the falling
edge of the CS pin occurs (from VIHH to VIH), the wiper
value is written to EEPROM and the WiperLock
Technology is disabled (See Figure 5-10).
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to change, force the CS
pin to VIH as soon as possible (within device
specifications) after the CS pin is forced to VIHH.
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
VIHH
VIH
VIH
CS
tWC
U/D
EEPROM
Wiper
VIH
VIL
X
X+4
X+4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
FIGURE 5-10:
Write Wiper Setting to EEPROM and Disable WiperLock™ Technology.
© 2006 Microchip Technology Inc.
DS21945E-page 39
MCP4021/2/3/4
5.2.11
WRITE WIPER SETTING TO
EEPROM AND ENABLE WiperLock
TECHNOLOGY
This mode is achieved by initializing the U/D and CS
pins to a high state (VIH) prior to the CS pin being driven
to VIHH (from VIH). Set the U/D pin to a low state (VIL)
prior to forcing the CS pin to VIH (from VIHH). This
begins a write cycle and enables the WiperLock
Technology feature (See Figure 5-11).
To ensure that “unexpected” transitions on the U/D pin
do not cause the wiper setting to increment, force the
CS pin to VIH as soon as possible (within device
specifications) after the U/D pin is forced to VIL.
After the CS pin is driven to VIH (from VIHH), all other
serial commands are ignored until the EEPROM write
cycle (tWC) completes.
VIHH
VIH
VIH
CS
VIH
U/D
EEPROM
Wiper
tWC
VIL
X
X+4
X+4
WiperLock Technology Enable
WiperLock™ Technology
WiperLock Technology Disable
FIGURE 5-11:
DS21945E-page 40
Write Wiper Setting to EEPROM and Enable WiperLock™ Technology.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
5.3
CS High Voltage
Depending on the requirements of the system, the use
of high voltage (VIHH) on the CS pin, may or may not be
required during system operation. Table 5-2 shows
possible system applications, and whether a high
voltage (VIHH) is required on the system.
The MCP402X supports six high-voltage commands
(the CS input voltage must meet the VIHH
specification).
TABLE 5-2:
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
HIGH-VOLTAGE
APPLICATIONS
High
Voltage
System Operation
Production calibration only - system
should not update wiper setting
The circuit in Figure 5-13 shows the method used on
the MCP402X Non-volatile Digital Potentiometer
Evaluation Board. This method requires that the
system voltage be approximately 5V. This ensures that
when the PIC10F206 enters a brown-out condition,
there is an insufficent voltage level on the CS pin to
change the stored value of the wiper. The MCP402X
Non-volatile Digital Potentiometer Evaluation Board
User’s Guide (DS51546) contains a complete
schematic.
From
Calibration
Unit
WiperLock™ Technogy disabled during
system operation
Not
Required
Wiper setting can be updated and
“locked” during system operation
Required
For the serial commands, configure the GP2 pin as an
input (high impedence). The output state of the GP0 pin
will determine the voltage on the CS pin (VIL or VIH).
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH) and configure the
GP2 pin to output the internal clock. This will form a
charge pump and increase the voltage on the CS pin
(when the system voltage is approximately 5V).
PIC10F206
5.3.1
TECHNIQUES TO FORCE THE CS
PIN TO VIHH
The circuit in Figure 5-12 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is high, the TC1240A is off, and the level on the CS pin
is controlled by the PIC® microcontrollers (MCUs) IO2
pin.
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the CS
pin to go higher than the voltage such that the PIC
MCU’s IO2 pin “clamps” at approximately VDD.
®
PIC MCU
TC1240A
C+
VIN
CSHDN
MCP402X
GP2
CS
C1
C2
FIGURE 5-13:
MCP402X Non-volatile
Digital Potentiometer Evaluation Board
(MCP402XEV) implementation to generate the
VIHH voltage.
C1
VOUT
IO1
IO2
R1
GP0
MCP402X
R1
CS
C2
FIGURE 5-12:
Using the TC1240A to
generate the VIHH voltage.
© 2006 Microchip Technology Inc.
DS21945E-page 41
MCP4021/2/3/4
6.0
RESISTOR
Digital potentiometer applications can be divided into
two categories:
• Rheostat configuration
• Potentiometer (or voltage divider) configuration
Figure 6-1 shows a block diagram for the MCP402X
resistors.
A
RW
RS
(1)
N = 62
3Eh
RW (1)
RS
TABLE 6-1:
TYPICAL STEP RESISTANCES
Typical Resistance (Ω)
Total (RAB)
Step (RS)
MCP402X-203E
2100
33.33
MCP402X-503E
5000
79.37
MCP402X-104E
10000
158.73
MCP402X-504E
50000
793.65
3Dh
N = 61
RW (1)
RS
The total resistance of the device has minimal variation
due to operating voltage (see Figure 2-6, Figure 2-17,
Figure 2-27 or Figure 2-37).
Part Number
3Fh
N = 63
Step resistance (RS) is the resistance from one tap
setting to the next. This value will be dependent on the
RAB value that has been selected. Table 6-1 shows the
typical step resistances for each device.
Terminal A and B, as well as the wiper W, do not have
a polarity. These terminals can support both positive
and negative current.
W
01h
N=1
RS
RW
(1)
RW
(1)
N=0
B
00h
Analog
Mux
Note 1: The wiper resistance is tap dependent.
That is, each tap selection resistance
has a small variation. This variation
effects the smaller resistance devices
(2.1 kΩ) more.
FIGURE 6-1:
DS21945E-page 42
Resistor Block Diagram.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
6.1
Resistor Configurations
6.1.1
6.1.2
RHEOSTAT CONFIGURATION
When used as a rheostat, two of the three digital
potentiometer’s terminals are used as a resistive
element in the circuit. With terminal W (wiper) and
either terminal A or terminal B, a variable resistor is
created. The resistance will depend on the tap setting
of the wiper and the wiper’s resistance. The resistance
is controlled by changing the wiper setting.
The unused terminal (B or A) should be left floating.
Figure 6-2 shows the two possible resistors that can be
used. Reversing the polarity of the A and B terminals
will not affect operation.
POTENTIOMETER
CONFIGURATION
When used as a potentiometer, all three terminals are
tied to different nodes in the circuit. This allows the
potentiometer to output a voltage proportional to the
input voltage. This configuration is sometimes called
voltage divider mode. The potentiometer is used to
provide a variable voltage by adjusting the wiper
position between the two endpoints as shown in
Figure 6-3. Reversing the polarity of the A and B
terminals will not affect operation.
V1
A
W
A
B
RAW or
W
RBW
B
V2
FIGURE 6-3:
Resistor
FIGURE 6-2:
Rheostat Configuration.
This allows the control of the total resistance between
the two nodes. The total resistance depends on the
“starting” terminal to the wiper terminal. At the code
00h, the RBW resistance is minimal (RW), but the RAW
resistance in maximized (RAB + RW). Conversely, at the
code 3Fh, the RAW resistance is minimal (RW), but the
RBW resistance in maximized (RAB + RW).
The resistance step size (RS) equates to one LSb of the
resistor.
Note:
V3
To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
Potentiometer Configuration.
The temperature coefficient of the RAB resistors is
minimal by design. In this configuration, the resistors all
change uniformally, so minimal variation should be
seen.
The wiper resistor temperature coefficient is different
from the RAB temperature coefficient. The voltage at
node V3 (Figure 6-3) is not dependent on this wiper
resistance, just the ratio of the RAB resistors, so this
temperature coefficient in most cases can be
ignored.
Note:
To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
The change in wiper-to-end terminal resistance over
temperature is shown in Figure 2-6, Figure 2-17,
Figure 2-27 and Figure 2-37. The most variation over
temperature will occur in the first few codes due to the
wiper resistance coefficient affecting the total
resistance. The remaining codes are dominated by the
total resistance tempco RAB.
© 2006 Microchip Technology Inc.
DS21945E-page 43
MCP4021/2/3/4
6.2
Wiper Resistance
Wiper resistance is the series resistance of the wiper.
This resistance is typically measured when the wiper is
positioned at either zero-scale (00h) or full-scale (3Fh).
The slope of the resistance has a linear area (at the
higher voltages) and a non-linear area (at the lower
voltages), where resistance increases faster than the
voltage drop (at low voltages).
The wiper resistance in potentiometer-generated
voltage divider applications is not a significant source
of error.
The wiper resistance in rheostat applications can
create significant non-linearity as the wiper is moved
toward zero-scale (00h). The lower the nominal
resistance, the greater the possible error.
Wiper resistance is significant depending on the
devices operating voltage. As the device voltage
decreases, the wiper resistance increases (see
Figure 6-4 and Table 6-2).
In a rheostat configuration, this change in voltage
needs to be taken into account, particularly for the
lower resistance devices. For the 2.1 kΩ device, the
maximum wiper resistance at 5.5V is approximately 6%
of the total resistance, while at 2.7V, it is approximately
15.5% of the total resistance.
In a potentiometer configuration, the wiper resistance
variation does not effect the output voltage seen on the
terminal W pin.
TABLE 6-2:
RW
VDD
Note:
The slope of the resistance has a linear
area (at the higher voltages) and a nonlinear area (at the lower voltages).
FIGURE 6-4:
Relationship of Wiper
Resistance (RW) to Voltage
Since there is minimal variation of the total device
resistance over voltage, at a constant temperature (see
Figure 2-6, Figure 2-17, Figure 2-27 or Figure 2-37),
the change in wiper resistance over voltage can have a
significant impact on the INL and DNL error.
TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE
RW / RS (%) (1)
Resistance (Ω)
Typical
Wiper (RW)
RW =
Typical
RW = Max RW = Max
@ 5.5V
@ 2.7V
RW =
Typical
RW = Max RW = Max
@ 5.5V
@ 2.7V
Total
(RAB)
Step
(RS)
Typical
2100
33.33
75
125
325
225.0%
375.0%
975.0%
3.57%
5.95%
15.48%
5000
79.37
75
125
325
94.5%
157.5%
409.5%
1.5%
2.50%
6.50%
10000
158.73
75
125
325
47.25%
78.75%
204.75%
0.75%
1.25%
3.25%
50000
793.65
75
125
325
9.45%
15.75%
40.95%
0.15%
0.25%
0.65%
Note 1:
2:
Max @ Max @
5.5V
2.7V
RW / RAB (%) (2)
RS is the typical value. The variation of this resistance is minimal over voltage.
RAB is the typical value. The variation of this resistance is minimal over voltage.
DS21945E-page 44
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
6.3
Operational Characteristics
Understanding the operational characteristics of the
device’s resistor components is important to the system
design.
6.3.1
6.3.1.1
6.3.1.2
Differential Non-Linearity (DNL)
DNL error is the measure of variations in code widths
from the ideal code width. A DNL error of zero would
imply that every code is exactly 1 LSb wide.
ACCURACY
Integral Non-Linearity (INL)
INL error for these devices is the maximum deviation
between an actual code transition point and its
corresponding ideal transition point after offset and
gain errors have been removed. These endpoints are
from 0x00 to 0x3F. Refer to Figure 6-5.
Positive INL means higher resistance than ideal.
Negative INL means lower resistance than ideal.
111
110
101
Digital
Input
Code
100
011
010
Actual
Transfer
Function
Ideal Transfer
Function
Wide Code, > 1 LSb
001
INL < 0
000
111
110
Narrow Code < 1 LSb
Actual
Transfer
Function
Digital Pot Output
101
Digital
Input
Code
FIGURE 6-6:
100
6.3.1.3
011
Ideal Transfer
Function
010
001
000
INL < 0
Digital Pot Output
FIGURE 6-5:
INL Accuracy.
© 2006 Microchip Technology Inc.
DNL Accuracy.
Ratiometric Temperature Coefficient
The ratiometric temperature coefficient quantifies the
error in the ratio RAW/RWB due to temperature drift.
This is typically the critical error when using a
potentiometer device (MCP4021 and MCP4023) in a
voltage divider configuration.
6.3.1.4
Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end resistance (nominal resistance
RAB) due to temperature drift. This is typically the
critical error when using a rheostat device (MCP4022
and MCP4024) in an adjustable resistor configuration.
DS21945E-page 45
MCP4021/2/3/4
6.3.2
MONOTONIC OPERATION
Monotonic operation means that the device’s
resistance increases with every step change (from
terminal A to terminal B or terminal B to terminal A).
The wiper resistance is different at each tap location.
When changing from one tap position to the next (either
increasing or decreasing), the ΔRW is less than the
ΔRS. When this change occurs, the device voltage and
temperature are “the same” for the two tap positions.
RS63
0x3F
RS62
Digital Input Code
0x3E
0x3D
RS3
0x03
RS1
0x02
RS0
0x01
0x00
RW
n=?
(@ tap) R
=
RSn + RW(@ Tap n)
BW
n=0
Resistance (RBW)
FIGURE 6-7:
DS21945E-page 46
Resistance, RBW.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
7.0
DESIGN CONSIDERATIONS
In the design of a system with the MCP402X devices,
the following considerations should be taken into
account:
• The Power Supply
• The Layout
7.1
Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy.
7.2
Layout Considerations
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP402X’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the silicon is capable of providing.
Particularly harsh environments may require shielding
of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
0.1 µF
VDD
W
B
VSS
FIGURE 7-1:
Connections.
U/D
CS
PIC® Microcontroller
A
MCP4021/2/3/4
0.1 µF
VSS
Typical Microcontroller
© 2006 Microchip Technology Inc.
DS21945E-page 47
MCP4021/2/3/4
8.0
APPLICATIONS EXAMPLES
VDD
Non-volatile digital potentiometers have a multitude of
practical uses in modern electronic circuits. The most
popular uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP4021/2/3/4 devices can be
used to replace the common mechanical trim pot in
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
8.1
R1
MCP4021
A
CS
U/D
W
VOUT
B
R2
Set Point Threshold Trimming
Applications that need accurate detection of an input
threshold event often need several sources of error
eliminated. Use of comparators and operational
amplifiers (op amps) with low offset and gain error can
help achieve the desired accuracy, but in many applications, the input source variation is beyond the
designer’s control. If the entire system can be
calibrated after assembly in a controlled environment
(like factory test), these sources of error are minimized,
if not entirely eliminated.
Figure 8-1 illustrates a common digital potentiometer
configuration. This configuration is often referred to as
a “windowed voltage divider”. Note that R1 and R2 are
not necessary to create the voltage divider, but their
presence is useful when the desired threshold has
limited range. It is “windowed” because R1 and R2 can
narrow the adjustable range of VTRIP to a value much
less than VDD – VSS. If the output range is reduced, the
magnitude of each output step is reduced. This
effectively increases the trimming resolution for a fixed
digital potentiometer resolution. This technique may
allow a lower-cost digital potentiometer to be utilized
(64 steps instead of 256 steps).
The MCP4021’s and
MCP4023’s low DNL
performance is critical to meeting calibration accuracy
in production without having to use a higher precision
digital potentiometer.
EQUATION 8-1:
V TRIP
CALCULATING THE
WIPER SETTING FROM
THE DESIRED VTRIP
R 2 + R WB
= V DD ⎛ -----------------------------------⎞
⎝ R 1 + R AB + R 2⎠
FIGURE 8-1:
Using the Digital
Potentiometer to Set a Precise Output Voltage.
8.1.1
TRIMMING A THRESHOLD FOR AN
OPTICAL SENSOR
If the application has to calibrate the threshold of a
diode, transistor or resistor, a variation range of 0.1V is
common. Often, the desired resolution of 2 mV or
better is adequate to accurately detect the presence of
a precise signal. A “windowed” voltage divider, utilizing
the MCP4021 or MCP4023, would be a potential
solution as shown in Figure 8-2.
VDD
VDD
Rsense
VCC+
R1
MCP4021 A
CS
U/D
VTRIP
W
B
R2
FIGURE 8-2:
Calibration.
Comparator
MCP6021
0.1 µF
VCC–
Set Point or Threshold
R AB = R Nominal
D
R WB = R AB • ⎛ ------⎞
⎝ 63⎠
V TRIP
D = ⎛ ⎛ --------------⎞ • ( ( R 1 + R AB + R 2 ) – R 2 )⎞ • 63
⎝ ⎝ V DD ⎠
⎠
Where:
D = Digital Potentiometer Wiper Setting (0-63)
DS21945E-page 48
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
8.2
Operational Amplifier
Applications
Figure 8-3, Figure 8-4 and Figure 8-5 illustrate typical
amplifier circuits that could replace fixed resistors with
the MCP4021/2/3/4 to achieve digitally-adjustable
analog solutions.
A
B
A
A
W
A
W
R3
B
MCP4022
MCP4021
R3
A
R4
B
W
Pot2
VDD
–
Op Amp
VIN
W
Pot1
MCP4022
+
VOUT
MCP6021
1
fc = -----------------------------
2 π ⋅ R Eq ⋅ C
R2
Op Amp
R1
VOUT
–
FIGURE 8-4:
Trimming Offset and Gain in
a Non-Inverting Amplifier.
B
–
MCP6291
Op Amp
VW
R2
A
W
VDD
MCP402X
R4
+
R1
R1
MCP4021
VIN
VDD
MCP4021
Figure 8-4 shows a circuit that allows a non-inverting
amplifier to have its’ offset and gain to be independently
trimmed. The MCP4021 is used along with resistors R1
and R2 to set the offset voltage. The sum of R1 + R2
resistance should be significantly greater (> 100 times)
the resistance value of the MCP4021. This allows each
increment or decrement in the MCP4021 to be a fine
adjustment of the offset voltage. The input voltage of
the op amp (VIN) should be centered at the op amps VW
voltage. The gain is adjusted by the MCP4022. If the
resistance value of the MCP4022 is small compared to
the resistance value of R3, then this is a fine
adjustment of the gain. If the resistance value of the
MCP4022 is equal (or large) compared to the
resistance value of R3, then this is a course adjustment
of the gain. In gerneral, trim the course adjustments
first and then trim the fine adjustments.
R3
VDD
VIN
VOUT
+
MCP6001
W
B
Thevenin R
= ( R 1 + R AB – R WB ) || ( R 2 + R WB ) + R w
Equivalent Eq
FIGURE 8-5:
Programmable Filter.
R2
FIGURE 8-3:
Trimming Offset and Gain in
an Inverting Amplifier.
© 2006 Microchip Technology Inc.
DS21945E-page 49
MCP4021/2/3/4
8.3
Temperature Sensor Applications
VDD
Thermistors are resistors with very predictable
variation with temperature. Thermistors are a popular
sensor choice when a low-cost, temperature-sensing
solution is desired. Unfortunately, thermistors have
non-linear characteristics that are undesirable, typically
requiring trimming in an application to achieve greater
accuracy. There are several common solutions to trim
and linearize thermistors. Figure 8-6 and Figure 8-7
are simple methods for linearizing a 3-terminal NTC
thermistor. Both are simple voltage dividers using a
Positive Temperature Coefficient (PTC) resistor (R1)
with a transfer function capable of compensating for the
lineararity error in the Negative Temperature
Coefficient (NTC) thermistor.
The circuit, illustrated by Figure 8-6, utilizes a digital
rheostat for trimming the offset error caused by the
thermistor’s part-to-part variation. This solution puts the
digital potentiometer’s RW into the voltage divider
calculation. The MCP4021/2/3/4’s RAB temperature
coefficient is 50 ppm (-20°C to +70°C). RW’s error is
substantially greater than RAB’s error because RW
varies with VDD, wiper setting and temperature. For the
50 kΩ devices, the error introduced by RW is, in most
cases, insignificant as long as the wiper setting is > 6.
For the 2 kΩ devices, the error introduced by RW is
significant because it is a higher percentage of RWB.
For these reasons, the circuit illustrated in Figure 8-6 is
not the most optimum method for “exciting” and
linearizing a thermistor.
VDD
R1
NTC
Thermistor
MCP4021
VOUT
R2
FIGURE 8-7:
Thermistor Calibration using
a Digital Potentiometer in a Potentiometer
Configuration.
8.4
Wheatstone Bridge Trimming
Another common configuration to “excite” a sensor
(such as a strain gauge, pressure sensor or thermistor)
is the wheatstone bridge configuration. The wheatstone bridge provides a differential output instead of a
single-ended output. Figure 8-8 illustrates a
wheatstone bridge utilizing one to three digital
potentiometers. The digital potentiometers in this
example are used to trim the offset and gain of the
wheatstone bridge.
VDD
R1
NTC
Thermistor
VOUT
2.1 kΩ
MCP4022
R2
A
W
MCP4022
FIGURE 8-6:
Thermistor Calibration using
a Digital Potentiometer in a Rheostat
Configuration.
The circuit illustrated by Figure 8-7 utilizes a digital
potentiometer for trimming the offset error. This
solution removes RW from the trimming equation along
with the error associated with RW. R2 is not required,
but can be utilized to reduce the trimming “window” and
reduce variation due to the digital potentiometer’s RAB
part-to-part variability.
DS21945E-page 50
VOUT
MCP4022
50 kΩ
FIGURE 8-8:
Trimming.
MCP4022
50 kΩ
Wheatstone Bridge
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
9.0
DEVELOPMENT SUPPORT
9.1
Evaluation/Demonstration Boards
Currently there are three boards that are available that
can be used to evaluate the MCP4021/2/3/4 family of
devices.
1.
The MCP402X Digital Potentiomenter Evaluation Board kit (MCP402XEV) contains a simple
demonstration board utilizing a PIC10F206, the
MCP4021 and a blank PCB, which can be
populated with any desired MCP4021/2/3/4
device in a SOT-23-5, SOT-23-6 or 150 mil
SOIC 8-pin package.
This board has two push buttons to control when
the PIC® microcontroller generates MCP402X
serial commands. The example firmware demonstrates the following commands:
• Increment
• Decrement
• High-Voltage Increment and Enable
WiperLock Technology
• High-Voltage Decrement and Enable
WiperLock Technology
• High-Voltage Increment and Disable
WiperLock Technology
• High-Voltage Decrement and Disable
WiperLock Technology
The populated board (with the MCP4021) can
be used to evaluate the other MCP402X devices
by appropriately jumpering the PCB pads.
2.
3.
4.
The SOT-23-5/6 Evaluation Board (VSUPEV2)
can be used to evaluate the characteristics of
the MCP4022, MCP4023 and MCP4024
devices.
The 8-pin SOIC/MSOP/TSSOP/DIP Evaluation
Board (SOIC8EV) can be used to evaluate the
characteristics of the MCP4021 device in either
the SOIC or MSOP package.
The MCP4XXX Digital Potentiometer Daughter
Board allows the system designer to quickly
evaluate the operation of Microchip Technology's MCP42XXX and MCP402X Digital Potentiometers. The board supports two MCP42XXX
devices and an MCP402X device, which can be
replaced with an MCP401X device.
The board also has a voltage doubler device
(TC1240A), which can be used to show the
WiperLock™ Technology feature of the
MCP4021.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
© 2006 Microchip Technology Inc.
DS21945E-page 51
MCP4021/2/3/4
10.0
PACKAGING INFORMATION
10.1
Package Marking Information
5-Lead SOT-23 (MCP4024)
XXNN
Example:
DP25
Part Number
Code
MCP4024T-202E/OT
DPNN
MCP4024T-502E/OT
DQNN
MCP4024T-103E/OT
DRNN
MCP4024T-503E/OT
DSNN
Note: Applies to 5-Lead SOT-23
6-Lead SOT-23 (MCP4022 / MCP4023)
XXNN
Example:
BA25
Code
Part Number
MCP4022 MCP4023
MCP402xT-202E/CH
BANN
MCP402xT-502E/CH
BBNN
BENN
BFNN
MCP402xT-103E/CH
BCNN
BGNN
MCP402xT-503E/CH
BDNN
BHNN
Note: Applies to 6-Lead SOT-23
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS21945E-page 52
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
Package Marking Information
8-Lead DFN (2x3) (MCP4021)
Example:
AAA
530
256
XXX
YWW
NNN
Part Number
Code
MCP4021T-202E/MC
AAA
MCP4021T-502E/MC
AAB
MCP4021T-103E/MC
AAC
MCP4021T-503E/MC
AAD
Note: Applies to 8-Lead DFN
Example:
8-Lead MSOP (MCP4021)
XXXXXX
402122
YWWNNN
530256
8-Lead SOIC (150 mil) (MCP4021)
Example:
XXXXXXXX
XXXXYYWW
NNN
402153E
e3 0530
SN^^
256
Part Numbers
8L-MSOP
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Code
8L-SOIC
MCP4021-202E/MS MCP4021-202E/SN
22
MCP4021-502E/MS MCP4021-502E/SN
52
MCP4021-103E/MS MCP4021-103E/SN
13
MCP4021-503E/MS MCP4021-503E/SN
53
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2006 Microchip Technology Inc.
DS21945E-page 53
MCP4021/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
B
p1
n
D
1
α
c
A
φ
L
β
A1
INCHES*
Units
Dimension Limits
A2
MIN
MILLIMETERS
NOM
MAX
MIN
NOM
Pitch
n
p
.038
0.95
Outside lead pitch (basic)
p1
.075
1.90
Number of Pins
Overall Height
5
MAX
5
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
.014
.018
.022
0.35
0.45
Foot Angle
L
f
Lead Thickness
c
.004
Lead Width
B
a
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
b
0
5
.006
.017
10
0
0.55
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Revised 09-12-05
Drawing No. C04-091
DS21945E-page 54
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
6-Lead Plastic Small Outline Transistor (CH) (SOT-23)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
B
p1
n
D
1
α
c
A
φ
β
A1
L
INCHES*
Units
Dimension Limits
MIN
Pitch
.038 BSC
Outside lead pitch
p1
.075 BSC
Overall Height
MILLIMETERS
NOM
n
p
Number of Pins
A2
MAX
MIN
NOM
6
MAX
6
0.95 BSC
1.90 BSC
A
.035
.046
.057
0.90
1.18
1.45
Molded Package Thickness
A2
.035
.043
.051
0.90
1.10
1.30
Standoff
A1
.000
.003
.006
0.00
0.08
0.15
Overall Width
E
.102
.110
.118
2.60
2.80
3.00
Molded Package Width
E1
.059
.064
.069
1.50
1.63
1.75
Overall Length
D
.110
.116
.122
2.80
2.95
3.10
Foot Length
L
φ
.014
.022
0.35
Foot Angle
Lead Thickness
c
.004
Lead Width
B
α
.014
Mold Draft Angle Top
Mold Draft Angle Bottom
β
.018
0
5
.006
.017
10
0.45
0
0.55
5
.008
0.09
0.15
.020
0.35
0.43
10
0.20
0.50
0
5
10
0
5
10
0
5
10
0
5
10
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
See ASME Y14.5M
JEITA (formerly EIAJ) equivalent: SC-74A
Drawing No. C04-120
© 2006 Microchip Technology Inc.
Revised 09-12-05
DS21945E-page 55
MCP4021/2/3/4
8-Lead Plastic Dual-Flat No-Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
e
D
b
N
N
L
K
E
E2
EXPOSED PAD
NOTE 1
1
2
2
1
NOTE 1
D2
TOP VIEW
BOTTOM VIEW
A
A3
A1
NOTE 2
Units
Dimension Limits
Number of Pins
N
Pitch
e
Overall Height
A
Standoff
A1
Contact Thickness
A3
Overall Length
D
Overall Width
E
Exposed Pad Length
D2
Exposed Pad Width
E2
Contact Width
b
Contact Length §
L
Contact-to-Exposed Pad §
K
MIN
0.80
0.00
1.30
1.50
0.18
0.30
0.20
MILLIMETERS
NOM
8
0.50 BSC
0.90
0.02
0.20 REF
2.00 BSC
3.00 BSC
—
—
0.25
0.40
—
MAX
1.00
0.05
1.75
1.90
0.30
0.50
—
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package may have one or more exposed tie bars at ends.
3. § Significant Characteristic
4. Package is saw singulated
5. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–123, Sept. 8, 2006
DS21945E-page 56
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
e
b
A2
A
ϕ
c
L1
A1
Number of Pins
Pitch
Overall Height
Molded Package
Standoff
Overall Width
Molded Package
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
Units
Dimension Limits
N
e
A
Thickness
A2
A1
E
Width
E1
D
L
L1
ϕ
c
b
MIN
—
0.75
0.00
0.40
0°
0.08
0.22
MILLIMETERS
NOM
8
0.65 BSC
—
0.85
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
—
—
—
L
MAX
1.10
0.95
0.15
0.80
8°
0.23
0.40
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
© 2006 Microchip Technology Inc.
DS21945E-page 57
MCP4021/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
INCHES*
NOM
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
.009
.017
12
12
MAX
MILLIMETERS
NOM
8
1.27
1.35
1.55
1.32
1.42
0.10
0.18
5.79
6.02
3.71
3.91
4.80
4.90
0.25
0.38
0.48
0.62
0
4
0.20
0.23
0.33
0.42
0
12
0
12
MAX
Number of Pins
Pitch
Overall Height
A
.053
.069
1.75
Molded Package Thickness
A2
.052
.061
1.55
Standoff
§
A1
.004
.010
0.25
Overall Width
E
.228
.244
6.20
Molded Package Width
E1
.146
.157
3.99
Overall Length
D
.189
.197
5.00
Chamfer Distance
h
.010
.020
0.51
Foot Length
L
.019
.030
0.76
φ
Foot Angle
0
8
8
c
Lead Thickness
.008
.010
0.25
Lead Width
B
.013
.020
0.51
α
Mold Draft Angle Top
0
15
15
β
Mold Draft Angle Bottom
0
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21945E-page 58
MIN
A1
MIN
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
APPENDIX A:
REVISION HISTORY
Revision E (December 2006)
• Added device designators in conditions column to
associate units (MHz) in Bandwidth -3 dB
parameter in AC/DC Characteristics table
• Added device designations in conditions column
for R-INL and R-DNL specifications.
• Added disclaimers to package outline drawings.
Revision D (October 2006)
• Changed the EEPROM write cycle time (TWC)
from a maximum of 5 ms to a maximum of 10 ms
(overvoltage and temperature) with a typical of
5 ms
• For the 10 kΩ device, the rheostat differential
non-linearity specification at 2.7V was changed
from ±0.5 LSb to ±1.0 LSb
• Figure 2-9 in Section 2.0 “Typical Performance
Curves” was updated with the correct data.
• Added Figure 2-48 for -3 db Bandwidth
information.
• Updated available Development Tools.
• Added disclaimer to package outline drawings.
Revision C (November 2005)
• Enhanced Descriptions
• Reordered Sections
• Added 8-lead MSOP and DFN packages
Revision B (April 2005)
• Updated part numbers in Product Identifcation
Section (PIS)
• Added Appendix A: Revision History
Revision A (April 2005)
• Original Release of this Document
© 2006 Microchip Technology Inc.
DS21945E-page 59
MCP4021/2/3/4
NOTES:
DS21945E-page 60
© 2006 Microchip Technology Inc.
MCP4021/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
XXX
X
/XX
Resistance Temperature Package
Version
Range
Device:
MCP4021:
MCP4021T:
MCP4022:
MCP4022T:
MCP4023:
MCP4023T:
MCP4024:
MCP4024T:
Single Potentiometer with U/D Interface
Single Potentiometer with U/D Interface
(Tape and Reel) (SOIC, MSOP)
Single Rheostat with U/D interface
Single Rheostat with U/D interface
(Tape and Reel) (SOT-23-6)
Single Potentiometer to GND with U/D
Interface
Single Potentiometer to GND with U/D
Interface (Tape and Reel) (SOT-23-6)
Single Rheostat to GND with U/D
Interface
Single Rheostat to GND with U/D
Interface (Tape and Reel)(SOT-23-5)
Examples:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
m)
n)
o)
p)
q)
r)
s)
t)
MCP4021-103E/MS:
MCP4021-103E/SN:
MCP4021T-103E/MC:
MCP4021T-103E/MS:
MCP4021T-103E/SN:
MCP4021-202E/MS:
MCP4021-202E/SN:
MCP4021T-202E/MC:
MCP4021T-202E/MS:
MCP4021T-202E/SN:
MCP4021-502E/MS:
MCP4021-502E/SN:
MCP4021T-502E/MC:
MCP4021T-502E/MS:
MCP4021T-502E/SN:
MCP4021-503E/MS:
MCP4021-503E/SN:
MCP4021T-503E/MC:
MCP4021T-503E/MS:
MCP4021T-503E/SN:
10 kΩ, 8-LD MSOP
10 kΩ, 8-LD SOIC
T/R, 10 kΩ, 8-LD DFN
T/R, 10 kΩ, 8-LD MSOP
T/R, 10 kΩ, 8-LD SOIC
2.1 kΩ, 8-LD MSOP
2.1 kΩ, 8-LD SOIC
T/R, 2.1 kΩ, 8-LD DFN
T/R, 2.1 kΩ, 8-LD MSOP
T/R, 2.1 kΩ, 8-LD SOIC
5 kΩ, 8-LD MSOP
5 kΩ, 8-LD SOIC
T/R, 5 kΩ, 8-LD DFN
T/R, 5 kΩ, 8-LD MSOP
T/R, 5 kΩ, 8-LD SOIC
50 kΩ, 8-LD MSOP
50 kΩ, 8-LD SOIC
T/R, 50 kΩ, 8-LD DFN
T/R, 50 kΩ, 8-LD MSOP
T/R, 50 kΩ, 8-LD SOIC
a)
b)
c)
d)
MCP4022T-202E/CH
MCP4022T-502E/CH
MCP4022T-103E/CH
MCP4022T-503E/CH
2.1 kΩ, 6-LD SOT-23
5 kΩ, 6-LD SOT-23
10 kΩ, 6-LD SOT-23
50 kΩ, 6-LD SOT-23
Resistance Version:
202 = 2.1 kΩ
502 = 5 kΩ
103 = 10 kΩ
503 = 50 kΩ
Temperature Range:
E
= -40°C to +125°C
a)
b)
c)
d)
MCP4023T-202E/CH
MCP4023T-502E/CH
MCP4023T-103E/CH
MCP4023T-503E/CH
2.1 kΩ, 6-LD SOT-23
5 kΩ, 6-LD SOT-23
10 kΩ, 6-LD SOT-23
50 kΩ, 6-LD SOT-23
Package:
CH
MC
MS
SN
OT
=
=
=
=
=
a)
b)
c)
d)
MCP4024T-202E/OT
MCP4024T-502E/OT
MCP4024T-103E/OT
MCP4024T-503E/OT
2.1 kΩ, 5-LD SOT-23
5 kΩ, 5-LD SOT-23
10 kΩ, 5-LD SOT-23
50 kΩ, 5-LD SOT-23
Plastic Small Outline Transistor, 6-lead
Plastic Dual Flat No Lead (2x3x0.9 mm), 8-lead
Plastic MSOP, 8-lead
Plastic SOIC, (150 mil Body), 8-lead
Plastic Small Outline Transistor, 5-lead
© 2006 Microchip Technology Inc.
DS21945E-page 61
MCP4021/2/3/4
NOTES:
DS21945E-page 62
© 2006 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
© 2006 Microchip Technology Inc.
DS21945E-page 63
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Habour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Gumi
Tel: 82-54-473-4301
Fax: 82-54-473-4302
China - Fuzhou
Tel: 86-591-8750-3506
Fax: 86-591-8750-3521
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-646-8870
Fax: 60-4-646-5086
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Shunde
Tel: 86-757-2839-5507
Fax: 86-757-2839-5571
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7250
Fax: 86-29-8833-7256
12/08/06
DS21945E-page 64
© 2006 Microchip Technology Inc.