Fairchild FAN48632 2.5 mhz, 2.0 a pulsed-load synchronous tinyboost Datasheet

FAN48632
2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™
Regulator with Bypass Mode for GSM PA Supply
Features
Description

Few External Components: 0.47 µH Inductor and
0603 Case Size Input and Output Capacitors



Input Voltage Range: 2.35 V to 5.5 V

Maximum Pulsed Load current :of 2.0 A for GSM 217 Hz
repetition rate ,boosting VOUT to 3.3 V or 3.5 V









Up to 96% Efficient
The FAN48632 allows systems to take advantage of new
battery chemistries that can supply significant energy when
the battery voltage is lower than the required voltage for
system power ICs. By combining built-in power transistors,
synchronous rectification, and low supply current; this IC
provides a compact solution for systems using advanced
Li-Ion battery chemistries.
Fixed Output Voltage : 3.3 V, 3.5 V
Maximum Continuous Load Current of: 1.5 A
at VIN of 2.6 V
True Bypass Operation when VIN > Target VOUT
Internal Synchronous Rectifier
Soft-Start with True Load Disconnect
Forced Bypass Mode
VSEL Control to Optimize Target VOUT
The FAN48632 is a boost regulator designed to provide a
minimum output voltage (VOUT(MIN)) from a single-cell Li-Ion
battery, even when the battery voltage is below system
minimum. In boost mode, output voltage regulation is
guaranteed to a maximum load current of 1.5 A continuous
and 2.0 A pulsed. Quiescent current in Shutdown Mode is less
than 3 µA, which maximizes battery life. The regulator
transitions smoothly between Bypass and normal Boost Mode.
The device can be forced into Bypass Mode to reduce
quiescent current.
The FAN48632 is available in a 16-bump, 0.4 mm pitch,
Wafer-Level Chip-Scale Package (WLCSP).
Short-Circuit Protection
Low Operating Quiescent Current
VIN
Battery
Applications
Boost for Low-Voltage Li-ion Batteries, Brownout
Prevention, Supply GSM RF PA.

Cell Phones, Smart Phones, Tablets
COUT
10F
40F
SW
0.47H

VOUT
CIN
L1
16-Bump, 0.4 mm Pitch WLCSP
+
FAN48632
VSEL
SYSTEM
LOAD
PGND
AGND
EN
PG
BYP
Figure 1. Typical Application
Ordering Information
Part Number
FAN48632UC33X
Output Voltage
VSEL0 / VSEL1
Soft-Start
Forced
Operating
Bypass Temperature
3.30 / 3.49
FAST
Low IQ
FAN48632BUC33X
3.30 / 3.49
FAST
Low IQ
FAN48632UC35X
3.50 / 3.70
FAST
Low IQ
(1)
-40°C to 85°C
Package
Packing
16-Ball, 4x4 Array, 0.4 mm
Pitch, 250 µm Ball, Wafer-Level
Chip-Scale Package (WLCSP)
Tape
and
Reel
Note:
1. The FAN48632BUC33X includes backside lamination.
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
April 2014
Q3B Q3A
VIN
CIN
Q3
L1
BYPASS
CONTROL
Q1B
Q1A
SW
VOUT
Q2
COUT
Q1
Synchronous
Rectifier
Control
GND
VSEL
EN
MODULATOR
LOGIC
AND CONTROL
BYP
PG
Figure 2. Block Diagram
Table 1.
Recommended Components
Component
Description
Vendor
Parameter
Typ.
Unit
0.47
µH
0.47 µH, 30%
Toko: DFE201612C
DFR201612C
Cyntec: PIFE20161B
L
L1
DCR (Series R)
40
m
CIN
10 µF, 10%, 10 V, X5R, 0603
TDK: C1608X5R1A106K
C
10
µF
COUT
2 x 22 µF, 20%, 6.3 V, X5R, 0603
TDK: C1608X5R0J226M
C
44
µF
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
2
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Typical Application
EN
PG
A1
A2
VIN
VSEL AGND
B1
B2
A2
A1
B3
B4
B4
B3
B2
B1
C4
C4
C3
C2
C1
D4
D4
D3
D2
D1
SW
C2
AGND
D1
A3
VOUT
BYP
C1
A4
A4
A3
C3
PGND
D2
D3
Figure 3. Top Through View (Bumps Down)
Figure 4. Bottom View (Bumps Up)
Pin Definitions
Pin #
Name
Description
A1
EN
Enable. When this pin is HIGH, the circuit is enabled.
A2
PG
Power Good. This is an open-drain output. PG is actively pulled LOW if output falls out of
regulation due to overload or if thermal protection threshold is exceeded.
A3–A4
VIN
Input Voltage. Connect to Li-Ion battery input power source.
B1
VSEL
Output Voltage Select. When boost is running, this pin can be used to select output voltage.
B2, C2
D1
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured
with respect to this pin.
B3–B4
VOUT
Output Voltage. Place COUT as close as possible to the device.
C1
BYP
Bypass. This pin can be used to activate Forced Bypass Mode. When this pin is LOW, the
bypass switches (Q3 and Q1) are turned on and the IC is otherwise inactive.
C3–C4
SW
Switching Node. Connect to inductor.
D2–D4
PGND
(2)
(2)
Power Ground. This is the power return for the IC. The COUT bypass capacitor should be
returned with the shortest path possible to these pins.
Note:
2. The EN pin can be tied to VIN, but it is recommended to tie EN to the 1.8 V logic voltage.
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
3
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Pin Configuration
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above
the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended
exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings
are stress ratings only.
Symbol
VIN
VOUT
Parameter
VIN Input Voltage
Min.
Max.
Unit
-0.3
6.5
V
6.0
V
8.0
V
8.0
V
VOUT Output Voltage
SW Node
DC
-0.3
Transient: 10 ns, 3 MHz
-1.0
Other Pins
-0.3
Human Body Model per JESD22-A114
6.5
(3)
3.0
V
kV
ESD
Electrostatic Discharge
Protection Level
TJ
Junction Temperature
–40
+150
°C
TSTG
Storage Temperature
–65
+150
°C
+260
°C
TL
Charged Device Model per JESD22-C101
1.5
Lead Soldering Temperature, 10 Seconds
kV
Note:
3. Lesser of 6.5 V or VIN + 0.3 V.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding
them or designing to absolute maximum ratings.
Symbol
Parameter
Min.
Max.
Unit
VIN
Supply Voltage
2.35
5.50
V
IOUT
Output Current
0
1500
mA
TA
Ambient Temperature
–40
+85
°C
TJ
Junction Temperature
–40
+125
°C
Thermal Properties
Junction-to-ambient thermal resistance is a function of application and board layout. This data is measured with four-layer
Fairchild evaluation boards (1 oz copper on all layers). Special attention must be paid not to exceed junction temperature TJ(max) at
a given ambient temperate TA.
Symbol
Parameter
Typical
JA
Junction-to-Ambient Thermal Resistance
80
JB
Junction-to-Board Thermal Resistance
42
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
Unit
°C/W
www.fairchildsemi.com
4
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Absolute Maximum Ratings
Recommended operating conditions, unless otherwise noted, circuit per Figure 1, VIN = 2.35 V to VOUT, TA = -40˚C to 85˚C.
Typical values are given VIN = 3.0 V and TA = 25˚C.
Symbol
IQ
Parameter
VIN Quiescent Current
Conditions
Typ.
Max.
Unit
Bypass Mode VOUT=3.5 V, VIN=4.2 V
140
190
A
Boost Mode VOUT=3.5 V, VIN=2.5 V
150
250
A
Shutdown: EN=0, VIN=3.0 V
1.5
5.0
A
4
10
A
Forced Bypass Mode,
VIN=3.5 V
Min.
Low IQ
VOUT to VIN Reverse Leakage
VOUT=5 V, EN=0
0.2
1.0
A
ILK_OUT
VOUT Leakage Current
VOUT=0, EN=0, VIN=4.2 V
0.1
1.0
A
VUVLO
Under-Voltage Lockout
VIN Rising
2.20
2.35
V
ILK
VUVLO_HYS
Under-Voltage Lockout Hysteresis
200
mV
VPG(OL)
PG Low
IPG=5 mA
0.4
V
IPG_LK
PG Leakage Current
VPG=5 V
1
µA
VIH
Logic Level High EN, VSEL, BYP
VIL
Logic Level Low EN, VSEL, BYP
1.2
V
0.4
V
Logic Control Pin Pull Downs
(LOW Active)
BYP, VSEL, EN
300
k
Weak Current Source Pull-Down
BYP, VSEL, EN
100
nA
VREG
Output Voltage Accuracy
Target VOUT relative to GND, DC,
VOUT-VIN > 100 mV
VTRSP
Load Transient Response
500 – 1250 mA, VIN=3.0 V
tON
On-Time
VIN=3.0 V, VOUT=3.5 V, Load >1 A
fSW
Switching Frequency
VIN=3.0 V, VOUT=3.5 V, Load=1 A
2.0
2.5
3.0
MHz
Boost Valley Current Limit
VIN=2.6 V
3.3
3.7
4.1
A
Boost Valley Current Limit During
SS
VIN=2.6 V
RLOW
IPD
IV_LIM
IV_LIM_SS
ISS_PK
tSS
Soft-Start Input Current Limit
Soft-Start EN HIGH to Regulation
–2
4
±4
%
%
80
ns
1.8
A
LIN1
Fast
900
mA
LIN2
Fast
1800
mA
600
s
Fast, 50  Load
VOVP
Output Over-Voltage Protection
Threshold
6.0
VOVP_HYS
Output Over-Voltage Protection
Hysteresis
300
RDS(ON)N
N-Channel Boost Switch RDS(ON)
VIN=3.5 V
85
120
mΩ
RDS(ON)P
P-Channel Sync Rectifier RDS(ON)
VIN=3.5 V
65
85
mΩ
RDS(ONBYP
P-Channel Bypass Switch RDS(ON)
VIN=3.5 V
65
85
mΩ
6.3
V
mV
T120A
T120 Activation Threshold
120
°C
T120R
T120 Release Threshold
100
°C
T150T
T150 Threshold
150
°C
T150H
T150 Hysteresis
20
°C
tRST
FAULT Restart Timer
20
ms
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
5
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Electrical Specifications
100%
100%
95%
95%
90%
90%
Efficiency
Efficiency
Unless otherwise specified; VIN = 3.0 V,VOUT = 3.5 V, VSEL=0 V,and TA = 25°C; circuit and components according to Figure 1.
85%
2.5 VIN
80%
85%
80%
2.7 VIN
- 40C
3.0 VIN
75%
75%
+25C
3.3 VIN
+85C
3.0 VIN, VSEL1
Pulse Load only
Pulse Load only
70%
70%
0
500
1000
1500
2000
0
500
Load Current (mA)
2000
Figure 6. Efficiency vs. Load Current and Temperature
100%
95%
95%
90%
90%
Efficiency
100%
85%
80%
85%
80%
2.5 VIN
- 40C
2.7 VIN
75%
+25C
75%
3.0 VIN
+85C
3.0 VIN, VSEL1
Pulse Load only
Pulse Load only
70%
70%
0
500
1000
1500
2000
0
500
Load Current (mA)
1000
1500
2000
Load Current (mA)
Figure 7. Efficiency vs. Load Current and Input Voltage,
VOUT=3.3 V
Figure 8. Efficiency vs. Load Current and Temperature,
VOUT=3.3 V
3
3
2.5 VIN
- 40C
2.7 VIN
+25C
3.0 VIN
+85C
2
Output Regulation (%)
2
3.3 VIN
Output Regulation (%)
1500
Load Current (mA)
Figure 5. Efficiency vs. Load Current and Input Voltage
Efficiency
1000
1
0
-1
1
0
-1
Pulse Load only
Pulse Load only
-2
-2
0
500
1000
1500
2000
0
Load Current (mA)
1000
1500
2000
Load Current (mA)
Figure 9. Output Regulation vs. Load Current and Input
Voltage (Normalized to 3.0 VIN, 500 mA Load)
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
500
Figure 10. Output Regulation vs. Load Current and
Temperature (Normalized to 3.0 VIN, 500 mA Load,
TA=25°C)
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FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Typical Characteristics
Unless otherwise specified; VIN = 3.0 V, VOUT = 3.5 V, VSEL=0 V, and TA = 25°C; circuit and components according to Figure 1.
200
10
- 40C
- 40C
+25C
+25C
8
+85C
Input Current (A)
Input Current (A)
180
160
140
120
+85C
6
4
2
100
0
2.0
2.5
3.0
3.5
4.0
4.5
2.0
2.5
3.0
Input Voltage (V)
3.5
4.0
4.5
Input Voltage (V)
Figure 12. Quiescent Current vs. Input Voltage,
Temperature, Forced Bypass (Low IQ)
Figure 11. Quiescent Current vs. Input Voltage and
Temperature, Auto Bypass
60
3500
2.5 VIN
2.7 VIN
50
3000
Switching Frequency (KHz)
Output Ripple (mVpp)
3.0 VIN
3.3 VIN
40
30
20
10
2500
2000
1500
2.5 VIN
1000
2.7 VIN
500
3.0 VIN
3.3 VIN
Pulse Load only
0
Pulse Load only
0
0
500
1000
1500
2000
0
Load Current (mA)
500
1000
1500
2000
Load Current (mA)
Figure 13. Output Ripple vs. Load Current and
Input Voltage
Figure 14. Switching Frequency vs. Load Current and
Input Voltage
Figure 15. Startup, 50 Ω Load
Figure 16. Overload Protection
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
7
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Typical Characteristics (Continued)
Unless otherwise specified; VIN = 3.0 V, VOUT = 3.5 V, VSEL=0 V, and TA = 25°C; circuit and components according to Figure 1.
Figure 17. Load Transient, 100-500 mA, 100 ns Edge
Figure 18. Transient Overload, 1.0-2.5 A, 100 ns Edge
Figure 19. Line Transient, 3.0-3.6 VIN, 10 µs Edge,
1.0 A Load
Figure 20. Line Transient, 3.3-3.9 VIN, 10 µs Edge,
1.0 A Load
Figure. 21 Bypass Entry / Exit, Slow VIN Ramp 1 ms Edge,
500 mA Load, 3.2 - 3.8 VIN
Figure 22. VSEL Step, VIN=3.0 V, 500 mA Load
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
8
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Typical Characteristics (Continued)
FAN48632 is a synchronous boost regulator, typically
operating at 2.5 MHz in Continuous Conduction Mode (CCM),
which occurs at moderate to heavy load current and low VIN
voltages. The regulator includes a Bypass Mode that activates
when VIN is above the boost regulator’s set point.
In LIN2 Mode, the current source is incremented to 2 A. If
VOUT fails to reach VIN-300 mV after 1024 s, a fault condition
is declared.
SS State
Upon the successful completion of the LIN state (VOUT>VIN300 mV), the regulator begins switching with boost pulses
current limited to 50% of nominal level.
In anticipation of a heavy load transition, the set point can be
adjusted upward by fixed amounts with the VSEL pin to
reduce the required system headroom during lighter-load
operation to save power.
Table 2.
During SS state, VOUT is ramped up by stepping the internal
reference. If VOUT fails to reach regulation during the SS ramp
sequence for more than 64 µs, a fault condition is declared. If
large COUT is used, the reference is automatically stepped
slower to avoid excessive input current draw.
Operating States
Mode
Description
Invoked When
LIN
Linear Startup
VIN > VOUT
SS
Boost Soft-Start
VOUT < VOUT(MIN)
This is a normal operating state of the regulator.
BST
Boost Operating Mode
VOUT = VOUT(MIN)
BPS State
BPS
True Bypass Mode
VIN > VOUT(MIN)
BST State
If VIN is above VREG when the SS Mode successfully
completes, the device transitions directly to BPS Mode.
Boost Mode
The FAN48632 uses a current-mode modulator to achieve
excellent transient response and smooth transitions between
CCM and Discontinuous Conduction Mode (DCM) operation.
During CCM operation, the device maintains a switching
frequency of about 2.5 MHz. In light-load operation (DCM),
frequency is reduced to maintain high efficiency.
Table 3.
FAULT State
The regulator enters the FAULT state under any of the
following conditions:
Boost Startup Sequence
Start
State
Entry
Exit
LIN1
VIN > UVLO,
EN=1
VOUT > VIN300 mV
End
State
SS
LIN1 Exit
LIN1 or
LIN2 Exit
VOUT > VIN300 mV
SS
TIMEOUT
FAULT
VOUT=VOUT(MIN)
BST
OVERLOAD
TIMEOUT
FAULT
VOUT fails to achieve the voltage required to advance from
LIN state to SS state.

VOUT fails to achieve the voltage required to advance from
SS state to BST state.


Boost current limit triggers for 2 ms during the BST state.
VDS protection threshold is exceeded during BPS state.
Once a fault is triggered, the regulator stops switching and
presents a high-impedance path between VIN and VOUT. After
waiting 20 ms, a restart is attempted.
SS
LIN2
LIN2
Timeout
(µs)

512
1024
Power Good
Power good is 0 FAULT, 1 POWER GOOD, open-drain input.
The Power good pin is provided for signaling the system when
the regulator has successfully completed soft-start and no
faults have occurred. Power good also functions as an early
warning flag for high die temperature and overload conditions.
64
Shutdown and Startup

PG is released HIGH when the soft-start sequence is
successfully completed.

PG is pulled LOW when PMOS current limit has triggered
for 64 µs OR the die the temperature exceeds 120°C. PG
is re-asserted when the device cools below to 100°C.
LIN State

Any FAULT condition causes PG to be de-asserted.
When EN is HIGH and VIN > UVLO, the regulator attempts to
bring VOUT within 300 mV of VIN using the internal fixed current
source from VIN (Q3). The current is limited to LIN1 set point.
Over-Temperature
If EN is LOW, all bias circuits are off and the regulator is in
Shutdown Mode. During shutdown, current flow is prevented
from VIN to VOUT, as well as reverse flow from VOUT to VIN.
During startup, it is recommended to keep DC current draw
below 500 mA.
The regulator shuts down when the die temperature exceeds
150°C. Restart occurs when the IC has cooled by
approximately 20°C.
If VOUT reaches VIN-300 mV during LIN1 Mode, the SS state is
initiated. Otherwise, LIN1 times out after 512 s and LIN2
Mode is entered.
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
9
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Circuit Description
Forced Bypass
In normal operation, the device automatically transitions from
Boost Mode to Bypass Mode, if VIN goes above target VOUT. In
Bypass Mode, the device fully enhances both Q1 and Q3 to
provide a very low impedance path from VIN to VOUT. Entry to
the Bypass Mode is triggered by condition where VIN > VOUT
and no switching has occurred during past 5 µs. To soften the
entry to Bypass Mode, Q3 is driven as a linear current source
for the first 5 µs. Bypass Mode exit is triggered when VOUT
reaches the target VOUT voltage. During Automatic Bypass
Mode, the device is short-circuit protected by voltage
comparator tracking the voltage drop from VIN to VOUT; if the
drop exceeds 200 mV, a FAULT is declared.
Entry to Forced Bypass Mode initiates with a current limit on
Q3 and then proceeds to a true bypass state. To prevent
reverse current to the battery, the device waits until output
discharges below VIN before entering Forced Bypass Mode.
Low-IQ Forced Bypass Mode is available for the FAN48632.
After the transition is complete, most of the internal circuitry is
disabled to minimize quiescent current draw. OCP, UVLO,
output OVP and over-temperature protections are inactive in
Forced Bypass Mode.
In Forced Bypass Mode, VOUT can follow VIN below VOUT(MIN).
VSEL
With sufficient load to enforce CCM operation, the Bypass
Mode to Boost Mode transition occurs at the target VOUT. The
corresponding input voltage at the transition point is:
VIN  VOUT  I LOAD  ( DCRL  RDS (ON ) P ) || RDS (ON ) BYP
VSEL can be asserted in anticipation of a positive load
transient. Raising VSEL increases VOUT(MIN) by a fixed amount
and VOUT is stepped to the corresponding target output voltage
in 20 µs. The functionality can also be utilized to mitigate
undershoot during severe line transients, while minimizing
VOUT during more benign operating conditions to save power.
EQ. 1
The Bypass Mode entry threshold has 25 mV hysteresis
imposed at VOUT to prevent cycling between modes. The
transition from Boost Mode to Bypass Mode occurs at the
target VOUT+25 mV. The corresponding input voltage is:
VIN  VOUT  25mV  I LOAD  ( DCRL  RDS (ON ) P )
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
EQ. 2
www.fairchildsemi.com
10
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Bypass Operation
Output Capacitance (COUT)
2.0 A Pulsed Loads for GSM Applications
Stability
The FAN48632 can support 2 A load pulses for GSM and
GSM Edge applications, according to the minimum VIN levels
shown in Figure 23.
The effective capacitance (CEFF) of small, high-value, ceramic
capacitors decreases as bias voltage increases.
FAN48632 is guaranteed for stable operation with the
minimum value of CEFF (CEFF(MIN)) of 14 F.
CEFF varies with manufacturer, material, and case size.
Inductor Selection
The recommended nominal inductance value is 0.47 H.
FAN48632 employs valley-current limiting; peak inductor
current can exceed4.4 A for a short duration during overload
conditions. Saturation effects cause the inductor current ripple
to become higher under high loading as only valley of the
inductor current ripple is controlled..
Startup
Input current limiting is in effect during soft-start, which limits
the current available to charge COUT and any additional
capacitance on the VOUT line. If the output fails to achieve
regulation within the limits described in the Startup section, a
FAULT occurs, causing the circuit to shut down then restart
after a significant time period. If the total combined output
capacitance is very high, the circuit may not start on the first
attempt, but eventually achieves regulation if no load is
present. If a high-current load and high capacitance are both
present during soft-start, the circuit may fail to achieve
regulation and continually attempts soft-start, only to have
the output capacitance discharged by the load when in a
FAULT state.
Figure 23. Minimum VIN for 2 A GSM Pulse, 3.5 VOUT
Results shown use circuit/components of Figure 1 with device
mounted on standard evaluation platform (layout Figure 24).
Layout Recommendation
Output Voltage Ripple
To minimize spikes at VOUT, COUT must be placed as close as
possible to PGND and VOUT, as shown in Figure 24. The
associated PGND and VOUT routes are best made directly on
the top copper layer, rather than thru vias.
Output voltage ripple is inversely proportional to COUT. During
tON, when the boost switch is on, all load current is supplied by
COUT. Output ripple is calculated as:
VRIPPLE ( PP )  tON 
I LOAD
COUT
For thermal reasons, it is suggested to maximize the pour
area for all planes other than SW. Especially the ground pour
should be set to fill all available PCB surface area and tied to
internal layers with a cluster of thermal vias.
EQ. 3
and

V
tON  t SW  D  t SW  1  IN
 VOUT



EQ. 4
therefore:

V
VRIPPLE ( P  P )  tSW  1  IN
 VOUT
 I LOAD
 
 COUT
EQ. 5
and
t SW 
1
f SW
EQ. 6
As can be seen from EQ. 5, the maximum VRIPPLE occurs
when VIN is at minimum and ILOAD is at maximum.
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
Figure 24. Layout Recommendation
www.fairchildsemi.com
11
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Application Information
0.03 C
E
2X
F
A
B
0.40
A1
BALL A1
INDEX AREA
D
0.40
(Ø0.21)
Cu Pad
(Ø0.30) Solder
Mask Opening
0.03 C
2X
RECOMMENDED LAND PATTERN
(NSMD PAD TYPE)
TOP VIEW
0.06 C
0.625
0.547
0.05 C
C
SEATING
PLANE
0.378±0.018
0.208±0.021
E
D
SIDE VIEWS
0.005
NOTES
A. NO JEDEC REGISTRATION APPLIES.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCE PER
ASME Y14.5M, 1994.
D. DATUM C IS DEFINED BY THE
SPHERICAL CROWNS OF THE BALLS.
E. PACKAGE NOMINAL HEIGHT IS
586 ± 39 MICRONS (547-625 MICRONS).
F. FOR DIMENSIONS D,E,X, AND Y SEE
PRODUCT DATASHEET.
G. DRAWING FILNAME: MKT-UC016AF rev1
C A B
Ø0.260±0.02
16X
0.40
D
C
B
0.40
(Y) ±0.018
A
F
1 2 3 4
(X) ±0.018
BOTTOM VIEW
Figure 25. 16-Ball, 4x4 Array, 0.4 mm Pitch, 250 µm Ball, Wafer-Level Chip-Scale Package (WLCSP)
Product-Specific Dimensions
D
E
X
Y
1.780 ±0.030
1.780 ±0.030
0.290
0.290
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/UC/UC016AF.pdf
For current packing container specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packing_dwg/PKG-UC016AF.pdf
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3
www.fairchildsemi.com
12
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
Physical Dimensions
FAN48632 — 2.5 MHz, 2.0 A Pulsed-Load Synchronous TinyBoost™ Regulator with Bypass Mode for GSM PA Supply
13
www.fairchildsemi.com
© 2013 Fairchild Semiconductor Corporation
FAN48632 • Rev. 1.0.3