EL5178, EL5378 ® Data Sheet May 16, 2007 FN7491.3 700MHz Differential Twisted-Pair Drivers Features The EL5178 and EL5378 are single and triple high bandwidth amplifiers with an output in differential form. They are primarily targeted for applications such as driving twisted-pair lines in component video applications. The inputs can be in either single-ended or differential form but the outputs are always in differential form. • Fully differential inputs, outputs, and feedback • Differential input range ±2.3V • 700MHz 3dB bandwidth • 1000V/µs slew rate • Low distortion at 5MHz and 20MHz On the EL5178 and EL5378, two feedback inputs provide the user with the ability to set the gain of each device (stable at minimum gain of 2). • Single 5V or dual ±5V supplies • 60mA maximum output current The output common mode level for each channel is set by the associated REF pin, which have a -3dB bandwidth of over 110MHz. Generally, these pins are grounded but can be tied to any voltage reference. • Low power - 12.5mA per channel All outputs are short circuit protected to withstand temporary overload condition. • Twisted-pair driver The EL5178 is available in 8 Ld MSOP and SOIC packages and EL5378 is available in a 28 Ld QSOP package. All are specified for operation over the full -40°C to +85°C temperature range. • Pb-Free plus anneal available (RoHS compliant) Applications • Differential line driver • VGA over twisted-pair • ADSL/HDSL driver • Single ended to differential amplification • Transmission of analog signals in a noisy environment Pinouts EL5378 (28 LD QSOP) TOP VIEW EL5178 (8 LD MSOP, SOIC) TOP VIEW FBP 1 IN+ 2 REF 3 8 OUT+ + - FBN 4 NC 1 7 VS- INP1 2 6 VS+ INN1 3 5 OUT- REF1 4 + - 27 FBP1 26 FBN1 25 OUT1B NC 5 24 VSP INP2 6 23 VSN INN2 7 22 OUT2 REF2 8 NC 9 + - 21 FBP2 20 FBN2 INP3 10 19 OUT2B INN3 11 18 OUT3 REF3 12 NC 13 EN 14 1 28 OUT1 + - 17 FBP3 16 FBN3 15 OUT3B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL5178, EL5378 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL5178IS 5178IS - 8 Ld SOIC (150 mil) MDP0027 EL5178IS-T7 5178IS 7” 8 Ld SOIC (150 mil) MDP0027 EL5178IS-T13 5178IS 13” 8 Ld SOIC (150 mil) MDP0027 EL5178ISZ (Note) 5178ISZ - 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5178ISZ-T7 (Note) 5178ISZ 7” 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5178ISZ-T13 (Note) 5178ISZ 13” 8 Ld SOIC (150 mil) (Pb-Free) MDP0027 EL5178IY BBGAA - 8 Ld MSOP (3.0mm) MDP0043 EL5178IY-T7 BBGAA 7” 8 Ld MSOP (3.0mm) MDP0043 EL5178IY-T13 BBGAA 13” 8 Ld MSOP (3.0mm) MDP0043 EL5178IYZ (Note) BBHAA - 8 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5178IYZ-T7 (Note) BBHAA 7” 8 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5178IYZ-T13 (Note) BBHAA 13” 8 Ld MSOP (3.0mm) (Pb-Free) MDP0043 EL5378IU EL5378IU - 28 Ld QSOP (150 mil) MDP0040 EL5378IU-T7 EL5378IU 7” 28 Ld QSOP (150 mil) MDP0040 EL5378IU-T13 EL5378IU 13” 28 Ld QSOP (150 mil) MDP0040 EL5378IUZ (Note) EL5378IUZ - 28 Ld QSOP (150 mil) (Pb-Free) MDP0040 EL5378IUZ-T7 (Note) EL5378IUZ 7” 28 Ld QSOP (150 mil) (Pb-Free) MDP0040 EL5378IUZ-T13 (Note) EL5378IUZ 13” 28 Ld QSOP (150 mil) (Pb-Free) MDP0040 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN7491.3 May 16, 2007 EL5178, EL5378 Absolute Maximum Ratings (TA = +25°C) Thermal Information Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA Input Current (all inputs and references) . . . . . . . . . . . . . . . . . . 4mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1kΩ, CLD = 2.7pF, [RF = 604Ω, RG = 402Ω (EL5178)], [RF = 402Ω, RG = 274Ω (EL5378)], unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW -3dB Bandwidth AV = 2, CLD = 2.7pF 700 MHz AV = 5, CLD = 2.7pF 80 MHz AV = 2, CLD = 2.7pF, RLD = 200Ω 320 MHz 45 MHz BW ±0.1dB Bandwidth AV = 2, CLD = 2.7pF SR Slew Rate, Differential (EL5178) VOUT = 3VP-P, 20% to 80% 650 850 V/µs Slew Rate, Differential (EL5378) VOUT = 3VP-P, 20% to 80% 650 1000 V/µs TSTL Settling Time to 0.1% VOUT = 2VP-P 35 ns TOVR Output Overdrive Recovery Time AV = 2 20 ns GBWP Gain Bandwidth Product 350 MHz VREFBW (-3dB) VREF -3dB Bandwidth (EL5378) CLD = 2.7pF 110 MHz VREFSR+ VREF Slew Rate - Rise (EL5378) VOUT = 2VP-P, 20% to 80% 134 V/µs VREFSR- VREF Slew Rate - Fall (EL5378) VOUT = 2VP-P, 20% to 80% 70 V/µs VN Input Voltage Noise at 10kHz 18 nV/√Hz IN Input Current Noise at 10kHz 1.5 pA/√Hz HD2 Second Harmonic Distortion VOUT = 2VP-P, 5MHz -83 dBc VOUT = 2VP-P, 20MHz -72 dBc VOUT = 2VP-P, 5MHz -88 dBc VOUT = 2VP-P, 20MHz -70 dBc HD3 Third Harmonic Distortion dG Differential Gain at 3.58MHz RLD = 300Ω, AV =2 0.06 % dθ Differential Phase at 3.58MHz RLD = 300Ω, AV =2 0.13 ° eS Channel Separation (EL5378) at F = 1MHz 90 dB INPUT CHARACTERISTICS VOS Input Referred Offset Voltage IIN Input Bias Current (VIN+, VIN-) IREF Input Bias Current (VREF) (EL5378) RIN Differential Input Resistance CIN Differential Input Capacitance DMIR Differential Mode Input Range (EL5378) 3 VREF = ±3.0V ±1.9 ±30 mV -20 -14 -7 µA 0.05 2.3 4 µA 150 kΩ 1 pF ±2.3 V FN7491.3 May 16, 2007 EL5178, EL5378 Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 1kΩ, CLD = 2.7pF, [RF = 604Ω, RG = 402Ω (EL5178)], [RF = 402Ω, RG = 274Ω (EL5378)], unless otherwise specified. (Continued) DESCRIPTION CONDITIONS CMIR+ Common Mode Positive Input Range at VIN+, VIN- (EL5378) CMIR- Common Mode Negative Input Range at VIN+, VIN- (EL5378) VREFIN + Positive Reference Input Voltage Range (EL5378) VIN+ = VIN- = 0V VREFIN - Negative Reference Input Voltage Range (EL5378) VIN+ = VIN- = 0V VREFOS Output Offset Relative to VREF (EL5378) CMRR Input Common Mode Rejection Ratio MIN TYP 3.1 3.4 -4.4 VIN = ±2.5V 3.2 MAX UNIT V -4.1 3.7 V V -3.3 -3.2 V ±50 ±100 mV 65 78 dB V OUTPUT CHARACTERISTICS VOUT Output Voltage Swing RL = 1kΩ ±3.4 ±3.7 IOUT(Max) Maximum Output Current RL = 10Ω, VIN+ = ±3.2V ±50 ±60 ROUT Output Impedance ±100 130 mA mΩ SUPPLY VSUPPLY Supply Operating Range IS(ON) Power Supply Current - Per Channel IS(OFF)+ Positive Power Supply Current - Disabled (EL5378) IS(OFF)- Negative Power Supply Current - Disabled (EL5378) PSRR Power Supply Rejection Ratio VS+ to VS- 4.75 10 EN pin tied to 4.8V VS from ±4.5V to ±5.5V 11 V 12.5 14 mA 1.7 10 µA -200 -120 µA 60 75 dB ENABLE (EL5378 ONLY) tEN Enable Time 130 ns tDS Disable Time 1.2 µs VIH EN Pin Voltage for Power-Up VIL EN Pin Voltage for Shut-Down IIH-EN EN Pin Input Current High At VEN = 5V IIL-EN EN Pin Input Current Low At VEN = 0V 4 VS+ -1.5 VS+ -0.5 V 123 -20 V -8 200 µA µA FN7491.3 May 16, 2007 EL5178, EL5378 Pin Descriptions EL5178 EL5378 PIN NAME PIN FUNCTION 1 17, 21, 27 FBP1, 2, 3 Feedback from non-inverting outputs 2 2, 6, 10 INP1, 2, 3 Non-inverting inputs 3 3, 7, 11 INN1, 2, 3 Inverting inputs, note that on EL5178, this pin is also the REF pin 4 16, 20, 26 FBN1, 2, 3 Feedback from inverting outputs 5 15, 19, 25 OUT1B, 2B, 3B 6 24 VSP Positive supply 7 23 VSN Negative supply 8 18, 22, 28 OUT1, 2, 3 1, 5, 9, 13 NC No connect; grounded for best crosstalk performance 4, 8, 12 REF1, 2, 3 Reference inputs, sets common-mode output voltage 14 EN Inverting outputs Non-inverting outputs ENABLE Typical Performance Curves 20 VS=±5V 15 RLD=1kΩ CLD=0pF RF=422Ω 10 RF=1kΩ RF=422Ω GAIN (dB) VS=±5V RLD=1kΩ CLD=0pF AV=2 RF=2kΩ 5 AV=2 0 -5 AV=5 -10 -15 100K 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 1. EL5178 FREQUENCY RESPONSE FOR VARIOUS RF VS=±5V RLD=200Ω RF=422Ω AV=2 FIGURE 2. EL5178 FREQUENCY RESPONSE FOR VARIOUS GAIN CLD=22pF CLD=12pF CLD=5.6pF CLD=0pF FIGURE 3. EL5178 FREQUENCY RESPONSE FOR VARIOUS CLD 5 FIGURE 4. EL5178 FREQUENCY RESPONSE FOR VARIOUS RLD FN7491.3 May 16, 2007 EL5178, EL5378 Typical Performance Curves (Continued) FIGURE 5. EL5178 FREQUENCY RESPONSE FOR VARIOUS VOPP FIGURE 6. EL5378 FREQUENCY RESPONSE FOR VARIOUS RF 20 GAIN (dB) VS=±5V 15 RLD=1kΩ CLD=0pF RF=422Ω 10 AV=2 5 0 -5 AV=5 -10 -15 100K 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 7. EL5378 FREQUENCY RESPONSE FOR VARIOUS GAIN VS=±5V CLD=0pF RF=422Ω AV=2 FIGURE 8. EL5378 FREQUENCY RESPONSE FOR VARIOUS CLD RLD=1kΩ RLD=200Ω FIGURE 9. EL5378 FREQUENCY RESPONSE FOR VARIOUS RLD 6 FIGURE 10. VOLTAGE AND CURRENT NOISE vs FREQUENCY FN7491.3 May 16, 2007 EL5178, EL5378 Typical Performance Curves (Continued) FIGURE 11. CMRR vs FREQUENCY FIGURE 12. DIFFERENTIAL PSRR vs FREQUENCY IMPEDANCE (Ω) 100 10 1 0.1 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 14. OUTPUT IMPEDANCE [DISABLED] INPUT TO OUTPUT DELAY (ns) FIGURE 13. OUTPUT IMPEDANCE vs FREQUENCY VS=±5V RF=422Ω AV=+2 tdFALL tdRISE VIN-PP (V) FIGURE 15. CHANNEL SEPARATION vs FREQUENCY 7 FIGURE 16. INPUT TO OUTPUT DELAY FN7491.3 May 16, 2007 EL5178, EL5378 Typical Performance Curves VS=±5V RLD=1kΩ RF=422Ω AV=2 (Continued) VS=±5V RLD=1kΩ CLD=0pF RF=422Ω F=40MHz 6VOPP-DM F=20MHz 4VOPP-DM F=10MHz 2VOPP-DM F=5MHz F=2.2MHz FIGURE 17. TOTAL HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT SWING FIGURE 18. TOTAL HARMONIC DISTORTION vs FREQUENCY VIN VIN 200mV/DIV 1V/DIV VOUT VOUT 5ns/DIV FIGURE 19. SMALL SIGNAL TRANSIENT RESPONSE 2V/DIV 10ns/DIV FIGURE 20. LARGE SIGNAL TRANSIENT RESPONSE VOUT VOUT 2V/DIV EN EN 4V/DIV 4V/DIV 100ns/DIV FIGURE 21. EL5378 ENABLED RESPONSE 8 400ns/DIV FIGURE 22. EL5378 DISABLED RESPONSE FN7491.3 May 16, 2007 EL5178, EL5378 Typical Performance Curves (Continued) VS=±5V RL=50Ω VS=±5V RL=50Ω f1 f2 2f2-f1 FIGURE 23. IP3 vs FREQUENCY -VOUT FIGURE 24. THIRD ORDER INTERCEPT POINT +/- SUPPLY CURRENT (mA) +VOUT 2f1-f2 +IS -IS TEMPERATURE (°C) FIGURE 25. OUTPUT SWING vs TEMPERATURE FIGURE 26. +/- SUPPLY CURRENT vs TEMPERATURE VS=±5.5V FIGURE 27. OFFSET VOLTAGE vs TEMPERATURE 9 FIGURE 28. INPUT BIAS CURRENT vs TEMPERATURE FN7491.3 May 16, 2007 EL5178, EL5378 Typical Performance Curves (Continued) 1.4 POWER DISSIPATION (W) VOUT=3Vpp JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.2 1.263W QSOP28 θJA=99°C/W 1 781mW 0.8 SO8 θJA=160°C/W 607mW 0.6 MSOP8 θJA=206°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 29. SLEW RATE vs TEMPERATURE 1.8 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.6 POWER DISSIPATION (W) FIGURE 30. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 1.583W 1.4 QSOP28 θJA=79°C/W 1.2 1.136W 1 1.087W 0.8 MSOP8 θJA=115°C/W 0.6 SO8 θJA=110°C/W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 31. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 10 FN7491.3 May 16, 2007 Connection Diagrams EL5178 RF1 CL1 5pF 422Ω IN+ REF RG 845Ω 11 RS2 50Ω RS2 50Ω -5V 1 FBP OUT 8 2 INP VSN 7 3 REF VSP 6 4 FBN OUTB 5 OUT RLD 1kΩ OUTB CL2 5pF +5V RF2 422Ω EL5378 +5V OUT1 28 INP1 2 INP1 FBP1 27 INN1 3 INN1 FBN1 26 REF1 4 REF1 OUT1B 25 5 NC VSP 24 INP2 6 INP2 VSN 23 INN2 7 INN2 OUT2 22 REF2 8 REF2 FBP2 21 9 NC FBN2 20 INP3 10 INP3 OUT2B 19 INN3 11 INN3 OUT3 18 12 REF3 FBP3 17 13 NC FBN3 16 14 EN OUT3B 15 REF3 RSP1 50Ω RSN1 50Ω RSR1 50Ω RSP2 50Ω RSN2 50Ω RSR2 50Ω RSP3 50Ω RSN3 50Ω RSR3 50Ω ENABLE RF -5V 422Ω RG 845Ω RF 422Ω RLD1 1kΩ RF 422Ω RG 845Ω RF 422Ω RF 422Ω RG 845Ω RF 422Ω RLD2 1kΩ RLD3 1kΩ CL1 CL1B CL2 CL2B CL3 CL3B 5pF 5pF 5pF 5pF 5pF 5pF EL5178, EL5378 1 NC FN7491.3 May 16, 2007 EL5178, EL5378 Simplified Schematic VS+ R3 R1 R4 R2 R7 IN+ IN- FBP R8 FBN VB1 OUT+ RCD REF RCD R9 VB2 CC R10 OUTCC R5 R6 VS- Description of Operation and Application Information Product Description The EL5178 and EL5378 are wide bandwidth, low power and single/differential ended to differential output amplifiers. The EL5178 is a single channel differential amplifier. Since the IN- pin and REF pin are tired together internally, the EL5178 can be used as a single ended to differential converter. The EL5378 is a triple channel differential amplifier. The EL5378 have a separate IN- pin and REF pin for each channel. It can be used as single/differential ended to differential converter. The EL5178 and EL5378 are internally compensated for closed loop gain of 1 of greater. Connected in gain of 2 and driving a 1kΩ differential load, the EL5178 and EL5378 have a -3dB bandwidth of 700MHz. Driving a 200Ω differential load at gain of 2, the bandwidth is about 320MHz. The EL5378 is available with a power down feature to reduce the power while the amplifier is disabled. Input, Output, and Supply Voltage Range The EL5178 and EL5378 have been designed to operate with a single supply voltage of 5V to 10V or a split supplies with its total voltage from 5V to 10V. The amplifiers have an input common mode voltage range from -4.3V to 3.4V for ±5V supply. The differential mode input range (DMIR) between the two inputs is from -2.3V to +2.3V. The input voltage range at the REF pin is from -3.3V to 3.7V. If the input common mode or differential mode signal is outside the above-specified ranges, it will cause the output signal distorted. Differential and Common Mode Gain Settings For EL5178, since the IN- pin and REF pin are bounded together as the REF pin in an 8 Ld package, the signal at the REF pin is part of the common mode signal and also part of the differential mode signal. For the true balance differential outputs, the REF pin must be tired to the same bias level as the IN+ pin. For a ±5V supply, just tire the REF pin to GND if the IN+ pin is biased at 0V with a 50Ω or 75Ω termination resistor. For a single supply application, if the IN+ is biased to half of the rail, the REF pin should be biased to half of the rail also. The gain setting for EL5178 is: R F1 + R F2⎞ ⎛ V ODM = V IN + × ⎜ 1 + ----------------------------⎟ RG ⎝ ⎠ 2R F⎞ ⎛ V ODM = V IN + × ⎜ 1 + -----------⎟ RG ⎠ ⎝ V OCM = V REF = 0V Where: VREF = 0V RF1 = RF2 = RF EL5378 have a separate IN- pin and REF pin. It can be used as a single/differential ended to differential converter. The voltage applied at REF pin can set the output common mode voltage and the gain is one. The output of the EL5178 and EL5378 can swing from -3.8V to +3.8V at 1kΩ differential load at ±5V supply. As the load resistance becomes lower, the output swing is reduced. 12 FN7491.3 May 16, 2007 EL5178, EL5378 Driving Capacitive Loads and Cables The gain setting for EL5378 is: The EL5178 and EL5378 can drive 23pF differential capacitor in parallel with 200Ω differential load with less than 5dB of peaking at gain of 2. If less peaking is desired in applications, a small series resistor (usually between 5Ω to 50Ω) can be placed in series with each output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 2, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. R F1 + R F2⎞ ⎛ V ODM = ( V IN + – V IN - ) × ⎜ 1 + ----------------------------⎟ RG ⎝ ⎠ 2R F⎞ ⎛ V ODM = ( V IN + – V IN - ) × ⎜ 1 + -----------⎟ RG ⎠ ⎝ V OCM = V REF Where: RF1 = RF2 = RF RF1 FBP VIN+ VIN- V O+ IN+ RG VREF INREF V O- FBN RF2 FIGURE 32. Choice of Feedback Resistor and Gain Bandwidth Product For gains greater than 1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. The bandwidth of the EL5178 and EL5378 depends on the load and the feedback network. RF and RG appear in parallel with the load for gains other than 1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum bandwidth performance. For the gains other than 1, optimum response is obtained with RF between 500Ω to 1kΩ. The EL5178 and EL5378 have a gain bandwidth product of 350MHz for RLD = 1kΩ. For gains ≥5, its bandwidth can be predicted by the following equation: When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking. Disable/Power-Down (for EL5378 only) The EL5378 can be disabled and placed its outputs in a high impedance state. The turn off time is about 1.2µs and the turn on time is about 130ns. When disabled, the amplifier's supply current is reduced to 1.7µA for IS+ and 120µA for IStypically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard CMOS signal levels at the EN pin. The applied logic signal is relative to VS+ pin. Letting the EN pin float or applying a signal that is less than 1.5V below VS+ will enable the amplifier. The amplifier will be disabled when the signal at EN pin is above VS+ - 0.5V. Output Drive Capability The EL5178 and EL5378 have internal short circuit protection. Its typical short circuit current is ±60mA. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds ±60mA. This limit is set by the design of the internal metal interconnections. Power Dissipation With the high output drive capability of the EL5178 and EL5378. It is possible to exceed the +135°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: Gain × BW = 300MHz T JMAX – T AMAX PD MAX = --------------------------------------------Θ JA 13 FN7491.3 May 16, 2007 EL5178, EL5378 Power Supply Bypassing and Printed Circuit Board Layout Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature θJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: ΔV O⎞ ⎛ PD = i × ⎜ V S × I SMAX + V S × ------------⎟ R LD ⎠ ⎝ Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current per channel ΔVO = Maximum differential output voltage of the application RLD = Differential load resistance ILOAD = Load current i = Number of channels As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces. By setting the two PDMAX equations equal to each other, we can solve the output current and RLD to avoid the device overheat. Typical Applications RF FBP 50 TWISTED PAIR IN+ IN+ RT RG IN- EL5178/ EL5378 REF 50 IN- ZO = 100Ω FBN EL5175/ EL5375 VO REF RF RFR RGR FIGURE 33. TWISTED PAIR CABLE RECEIVER As the signal is transmitted through a cable, the high frequency signal will be attenuated. One way to compensate this loss is to boost the high frequency gain at the receiver side. 14 FN7491.3 May 16, 2007 EL5178, EL5378 RF GAIN (dB) FBP RT 75 VO+ IN+ RGC RG IN- CL REF VO- FBN FREQUENCY RF fL 2R F DC Gain = 1 + ----------RG 1 f L ≅ ------------------------2πR G C C 2R F ( HF )Gain = 1 + -------------------------R G || R GC 1 f H ≅ ----------------------------2πR GC C C fH FIGURE 34. TRANSMIT EQUALIZER 15 FN7491.3 May 16, 2007 EL5178, EL5378 Small Outline Package Family (SO) A D h X 45° (N/2)+1 N A PIN #1 I.D. MARK E1 E c SEE DETAIL “X” 1 (N/2) B L1 0.010 M C A B e H C A2 GAUGE PLANE SEATING PLANE A1 0.004 C 0.010 M C A B L b 0.010 4° ±4° DETAIL X MDP0027 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL SO-14 SO16 (0.300”) (SOL-16) SO20 (SOL-20) SO24 (SOL-24) SO28 (SOL-28) TOLERANCE NOTES A 0.068 0.068 0.068 0.104 0.104 0.104 0.104 MAX - A1 0.006 0.006 0.006 0.007 0.007 0.007 0.007 ±0.003 - A2 0.057 0.057 0.057 0.092 0.092 0.092 0.092 ±0.002 - b 0.017 0.017 0.017 0.017 0.017 0.017 0.017 ±0.003 - c 0.009 0.009 0.009 0.011 0.011 0.011 0.011 ±0.001 - D 0.193 0.341 0.390 0.406 0.504 0.606 0.704 ±0.004 1, 3 E 0.236 0.236 0.236 0.406 0.406 0.406 0.406 ±0.008 - E1 0.154 0.154 0.154 0.295 0.295 0.295 0.295 ±0.004 2, 3 e 0.050 0.050 0.050 0.050 0.050 0.050 0.050 Basic - L 0.025 0.025 0.025 0.030 0.030 0.030 0.030 ±0.009 - L1 0.041 0.041 0.041 0.056 0.056 0.056 0.056 Basic - h 0.013 0.013 0.013 0.020 0.020 0.020 0.020 Reference - 16 20 24 28 Reference - N SO-8 SO16 (0.150”) 8 14 16 Rev. M 2/07 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994 16 FN7491.3 May 16, 2007 EL5178, EL5378 Mini SO Package Family (MSOP) 0.25 M C A B D MINI SO PACKAGE FAMILY (N/2)+1 N E MDP0043 A E1 MILLIMETERS PIN #1 I.D. 1 B (N/2) e H C SEATING PLANE 0.10 C N LEADS SYMBOL MSOP8 MSOP10 TOLERANCE NOTES A 1.10 1.10 Max. - A1 0.10 0.10 ±0.05 - A2 0.86 0.86 ±0.09 - b 0.33 0.23 +0.07/-0.08 - c 0.18 0.18 ±0.05 - D 3.00 3.00 ±0.10 1, 3 E 4.90 4.90 ±0.15 - E1 3.00 3.00 ±0.10 2, 3 e 0.65 0.50 Basic - L 0.55 0.55 ±0.15 - L1 0.95 0.95 Basic - N 8 10 Reference - 0.08 M C A B b Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. L1 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. A 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c SEE DETAIL "X" A2 GAUGE PLANE L A1 0.25 3° ±3° DETAIL X 17 FN7491.3 May 16, 2007 EL5178, EL5378 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES E PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. F 2/07 NOTES: L1 A 1. Plastic or metal protrusions of 0.006” maximum per side are not included. 2. Plastic interlead protrusions of 0.010” maximum per side are not included. c SEE DETAIL "X" 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 FN7491.3 May 16, 2007