AD AD9230 12-bit, 170/210/250 msps 1.8 v a/d converter Datasheet

12-Bit, 170/210/250 MSPS
1.8 V A/D Converter
AD9230
Preliminary Technical Data
AVDD
AGND (1.8V)
FEATURES
SNR = 65.5 dBFs @ fIN up to 70 MHz @ 250 MSPS
ENOB of 10.6 @ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS)
SFDR = 82 dBc@ fIN up to 70 MHz @ 250 MSPS (–0.5 dBFS)
Excellent Linearity
DNL = ±0.3 LSB (Typical)
INL = ±0.5 LSB (Typical)
LVDS at 250 MSPS (ANSI-644 levels)
900 MHz Full Power Analog Bandwidth
On-Chip Reference and Track-and-Hold
Power Dissipation = 425 mW Typical @ 250 MSPS
1.25 V Input Voltage Range
1.8 V Analog Supply Operation
Output Data Format Option
Data Clock Output Provided
Clock Duty Cycle Stabilizer
APPLICATIONS
Wireless and Wired Broadband Communications
Cable Reverse Path
Communications Test Equipment
Radar and Satellite Subsystems
Power Amplifier Linearization
PRODUCT DESCRIPTION
The AD9230 is a 12-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates up to a 250 MSPS conversion rate
and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary
functions, including a track-and-hold (T/H) and voltage
reference, are included on the chip to provide a complete signal
conversion solution.
The ADC requires a 1.8 V analog voltage supply and a
differential clock for full performance operation. The digital
outputs are LVDS (ANSI-644) compatible and support either
twos complement, offset binary format or gray code. A data
clock output is available for proper output data timing.
DrVDD
Ref
DGND
(Pin 0)
VIN+
VIN-
CLK+
CLK-
T/H
ADC 12
12-bit
Core
Output 12
Staging LVDS
D11-D0
OTR+
OTR-
Clock
Mgmt
Serial Port
DCO+
DCO-
RESET SCLK SDIO CSB
Figure 1. Functional Block Diagram
Fabricated on an advanced CMOS process, the AD9230 is
available in a 56-lead chip scale package (56 LFCSP) specified
over the industrial temperature range (–40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
High Performance—Maintains 65.5 dB SNR @ 250 MSPS
with a 65 MHz input.
2.
Low Power—Consumes only 425 mW @ 250 MSPS.
3.
Ease of Use—LVDS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample/hold provide flexibility in system
design. Use of a single 1.8 V supply simplifies system
power supply design. Supported DDR mode reduces
number of output data traces
4.
Serial Port Control - Standard serial port interface
supports various product functions such as data
formatting, enabling a clock duty cycle stabilizer, power
down, gain adjust and output test pattern generation.
5.
Pin compatible family – 10-bit pin compatible family
offered as AD9211.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2006 Analog Devices, Inc. All rights reserved.
AD9230
Preliminary Technical Data
TABLE OF CONTENTS
AD9230–Specifications.................................................................... 3
Power Dissipation and POWER DOWN Mode .................... 16
AC Specifications.............................................................................. 4
Digital Outputs ........................................................................... 17
Digital Specifications........................................................................ 5
Timing ......................................................................................... 17
Switching Specifications .................................................................. 6
RBIAS........................................................................................... 18
Absolute Maximum Ratings1 .......................................................... 7
AD9230 Configuration Using the SPI ..................................... 18
ESD Caution.................................................................................. 7
Hardware Interface..................................................................... 19
Pin Configurations and Function Descriptions ........................... 8
Reading the Memory Map Table.............................................. 19
Terminology .................................................................................... 10
Open Locations .......................................................................... 19
Equivalent circuits .......................................................................... 12
Default Values ............................................................................. 19
Typical Performance CHARACTERISTICS ............................... 13
Logic Levels................................................................................. 19
Theory of Operation .................................................................. 14
Outline Dimensions ....................................................................... 21
Analog Input and Reference Overview ................................... 14
Ordering Guide .......................................................................... 21
Clock Input Considerations ...................................................... 15
Rev. PrE | Page 2 of 21
Preliminary Technical Data
AD9230
AD9230–SPECIFICATIONS
Table 1. DC SPECIFICATIONS (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, Internal Reference,
Full Scale = 1.25 V, DCS Enabled, unless otherwise noted.)
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUTS (VIN+, VIN–)
Differential Input Voltage Range
Input Common-Mode Voltage
Input Resistance (differential)
Input Capacitance
POWER SUPPLY (LVDS Mode)
AVDD
DRVDD
Supply Currents
IANALOG(AVDD = 1.8 V) 1
IDIGITAL (DRVDD = 1.8 V)3
Power Dissipation3
Power Supply Rejection
Temp
Min
AD9230-170/-210
Typ
12
Max
Min
AD9230-250
Typ
12
Max
Unit
Bits
Full
25°C
25°C
25°C
Full
25°C
Full
Guaranteed
TBD
TBD
± 0.3
± 0.3
± 0.5
± 0.5
Guaranteed
TBD
TBD
± 0.3
± 0.3
± 0.5
± 0.5
mV
% FS
LSB
LSB
LSB
LSB
Full
Full
TBD
TBD
TBD
TBD
μV/°C
%/°C
Full
Full
Full
25°C
1.25
1.3
4
2
1.25
1.3
4
2
V
V
kΩ
pF
Full
Full
Full
Full
Full
25°C
1.7
1.7
1.8
1.8
150
60
378
TBD
1
IAVDD and IDRVDD are measured with a dc input at rated Clock rate. See Typical Performance
Characteristics and Applications sections for IANALOG and IDRVDD with dynamic input vs clock rate
Rev. PrE | Page 3 of 21
1.9
1.9
1.7
1.7
1.8
1.8
176
60
425
TBD
1.9
1.9
V
V
mA
mA
mW
mV/V
AD9230
Preliminary Technical Data
AC SPECIFICATIONS1
Table 2. (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, Internal Reference, Full Scale = 1.25 V, Ain
= -0.5dBFS, DCS Enabled unless otherwise noted.)
Parameter
SNR
fin=10 MHz
fin=70 MHz
fin=100 MHz
fin=240 MHz
Temp
Min
AD9230-170/-210
Typ
Max
Min
AD9230-250
Typ
Max
Unit
25°C
Full
25°C
Full
25°C
25°C
65.5
65
65.5
65
64
63
65.5
65
65.5
65
64
63
dB
dB
dB
dB
dB
dB
25°C
Full
25°C
Full
25°C
25°C
65
64.8
65
64.8
63.5
62.5
65
64.7
65
64.7
63.5
62.5
dB
dB
dB
dB
dB
dB
25°C
Full
25°C
Full
25°C
25°C
10.6
10.6
10.6
10.6
10.3
10.2
10.6
10.6
10.6
10.6
10.3
10.2
Bits
Bits
Bits
Bits
Bits
Bits
25°C
Full
25°C
Full
25°C
25°C
–82
–80
–82
–80
–78
–75
–82
–80
–82
–80
–77
–75
dBc
dBc
dBc
dBc
dBc
dBc
25°C
Full
25°C
Full
25°C
25°C
–85
–85
–85
–85
–83
–78
–85
–85
–85
–85
–83
–78
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
–75
900
–75
900
dBc
MHz
SINAD
fin=10 MHz
fin=70 MHz
fin=100 MHz
fin=240 MHz
EFFECTIVE NUMBER OF BITS
(ENOB)
fin=10 MHz
fin=70 MHz
fin=100 MHz
fin=240 MHz
WORST HARMONIC (2nd or 3rd)
fin=10 MHz
fin=70 MHz
fin=100 MHz
fin=240 MHz
WORST HARMONIC (4th or
Higher)
fin=10 MHz
fin=70 MHz
fin=100 MHz
fin=240 MHz
TWO-TONE IMD2
F1, F2 @ –7 dBFS
ANALOG INPUT BANDWIDTH
1
2
All ac specifications tested by driving CLK+ and CLK– differentially.
F1 = 28.3 MHz, F2 = 29.3 MHz.
Rev. PrE | Page 4 of 21
Preliminary Technical Data
AD9230
DIGITAL SPECIFICATIONS
Table 3 (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, DCS Enabled unless otherwise noted.)
AD9230-170/-210
Typ
Max
Parameter
CLOCK INPUTS
Temp
Min
Differential Input Voltage1
Common-Mode Voltage2
Input Resistance
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current
Logic 0 Input Current
Input Capacitance
LOGIC OUTPUTS3
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Full
Full
Full
25°C
tbd
Full
Full
Full
Full
25°C
.8 x VDD
Full
Full
247
454
1.125
1.375
Twos Complement,Gray or Binary
1
2
3
Min
AD9230-250
Typ
Max
tbd
tbd
tbd
4
V
V
kΩ
pF
tbd
tbd
4
2.0
.2 x AVDD
10
10
4
All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+)– (CLK–)| > 200 mV.
Clock inputs’ common mode can be externally set, such that xx.xV < (Clk+ or Clk- ) < zzz V.
LVDS RTermination = 100 Ω
Rev. PrE | Page 5 of 21
Unit
0.8
10
10
4
247
454
1.125
1.375
Twos Complement,Gray or Binary
V
V
μA
μA
pF
mV
V
AD9230
Preliminary Technical Data
SWITCHING SPECIFICATIONS
Table 4. (AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = –40°C, TMAX = +85°C, DCS Enabled unless otherwise noted.)
Parameter (Conditions)
Maximum Conversion Rate1
Minimum Conversion Rate
CLK+ Pulsewidth High (tEH)
CLK+ Pulsewidth Low (tEL)
OUTPUT (LVDS)
Valid Time (tV)
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tPD– tCPD)
Latency
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Out of Range Recovery Time
1
1
1
1
Temp
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
25°C
Min
170/210
AD9230-170/-210
Typ
Max
AD9230-250
Typ
Max
Min
250
40
40
TBD
TBD
TBD
TBD
TBD
TBD
3.9
0.4
0.4
3.2
3.9
0.4
0.4
3.2
TBD
TBD
5
TBD
0.2
5
TBD
0.2
TBD
TBD
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
Cycles
All ac specifications tested by driving CLK+ and CLK– differentially.
N–1
tA
N+L+2
N+L+3
N
N+L+1
AIN
N+1
N+L
L CYCLES
tEH
tEL
1/fS
CLK+
CLK–
tPD
tV
DATA
N–L
OUT
N-L+1
tCPD
DCO+
DCO–
Figure 2. Timing Diagram (L=5 Cycles)
Rev. PrE | Page 6 of 21
N
N+1
N+2
Preliminary Technical Data
AD9230
ABSOLUTE MAXIMUM RATINGS1
Parameter
AVDD
DRVDD
Analog Inputs
Digital Inputs
REFIN Inputs
Digital Output Current
Operating Temperature
Storage Temperature
Maximum Junction
Temperature
Maximum Case Temperature
θJA 2
Rating
2.0 V
2.0V
–0.5 V to AVDD + 0.5 V
–0.5 V to DRVDD + 0.5 V
–0.5 V to AVDD + 0.5 V
20 mA
–40ºC to +125°C
–65ºC to +150°C
150°C
150°C
TBD°C/W
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions outside of those
indicated in the operation sections of this specification is not implied.
Exposure to absolute maximum ratings for extended periods may affect
device reliability.
2 Typical θJA = TBD C/W (heat slug soldered) for multilayer board in still air
with solid ground plane.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 7 of 21
AD9230
Preliminary Technical Data
DCO-
DRGND
DRVDD
AVDD
CLK-
CLK+
AVDD
49
48
47
46
45
44
43
50
D0+
D153
D0DCO+
D1+
54
51
D255
52
D2+
56
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
D3-
1
42
2
AVDD
D3+
41
3
AVDD
D4D4+
40
CML
39
AVDD
D5-
4
5
D5+
6
38
37
DRVDD
7
AVDD
AVDD
36
8
VIN-
DRGND
35
VIN+
AD9230
56 Lead for
LFCSP
TOP VIEW
(Not to Scale)
D6D6+
9
10
D7D7+
11
12
32
31
D8-
13
30
14
AVDD
D8+
29
PWDN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D9-
D9+
D10-
D10+
D11-
(MSB) D11+
OTR-
OTR+
DRGND
DRVDD
SDIO
SCLK
CSB
RESET
Pin 0 (exposed paddle) = AGND
34
AVDD
33
AVDD
AVDD
RBIAS
Figure 3. Pinout )
Table 5. PIN FUNCTION DESCRIPTIONS
Pin Number
30,32,33,34,37,38,39,41,
42,43,46
7, 24,47
0
8, 23,48
35
36
40
44
45
31
28
25
26
27
29
49
50
51
52
53
1
Mnemonic
AVDD
Description
1.8 V Analog Supply.
DRVDD
AGND1
DRGND1
VIN+
VIN–
CML
CLK+
CLK–
RBIAS
RESET
SDIO
SCLK
CSB
PWDN
DCO–
DCO+
D0–
D0+
D1–
1.8 V Digital Output Supply.
Analog Ground.
Digital Output Ground.
Analog Input—True.
Analog Input—Complement.
Analog input common mode output pin
Clock Input—True.
Clock Input—Complement.
Set Pin for Chip Bias Current. (Place 1% X kohm resistor terminated to ground).
Chip Reset ( Active high)
Serial port input/output pin
Serial port clock
Serial port chip select (Active low)
Chip power down
Data Clock Output—Complement.
Data Clock Output—True.
D0 Complement Output Bit (LSB).
D0 True Output Bit (LSB).
D1 Complement Output Bit.
AGND and DRGND should be tied to a common quiet ground plane.
Rev. PrE | Page 8 of 21
Preliminary Technical Data
Pin Number
54
55
56
1
2
3
4
5
5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Mnemonic
D1+
D2–
D2+
D3–
D3+
D4–
D4+
D5–
D5+
D6–
D6+
D7–
D7+
D8–
D8+
D9–
D9+
D10–
D10+
D11–
D11+
OTR–
OTR+
AD9230
Description
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
Overrange Complement Output Bit.
Overrange True Output Bit.
Rev. PrE | Page 9 of 21
AD9230
Preliminary Technical Data
TERMINOLOGY
Analog Bandwidth
Full-Scale Input Power
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Expressed in dBm. Computed using the following equation:
Aperture Delay
PowerFULLSCALE
The delay between the 50% point of the rising edge of the Clock
and the instant at which the analog input is sampled.
Gain Error
Aperture Uncertainty (Jitter)
⎛
⎜V2
FULLSCALE RMS
= 10 log⎜
Z INPUT
⎜
⎜
0.001
⎝
⎞
⎟
⎟
⎟
⎟
⎠
The difference between the measured and ideal full-scale input
voltage range of the ADC.
The sample-to-sample variation in aperture delay.
Harmonic Distortion, Second
Crosstalk
Coupling onto one channel being driven by a low level (–40
dBFS) signal when the adjacent interfering channel is driven by
a fullscale signal.
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Differential Analog Input Voltage Range
Minimum Conversion Rate
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input’s phase 180° and again taking the peak measurement.
The difference is then computed between both peak
measurements.
The Clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The Clock rate at which parametric testing is performed.
Output Propagation Delay
Differential Nonlinearity
The delay between a differential crossing of CLK+ and CLK–
and the time when all output data bits are within valid logic
levels.
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
ENOB =
Noise (for Any Range within the ADC)
SNR MEASURED − 1.76dB
6.02
Calculated as follows:
Clock Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time the ENCODE
pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time the Clock
pulse should be left in low state. At a given clock rate, these
specifications define an acceptable Clock duty cycle.
− SNRdBc − SignaldBFS ⎞
⎛ FS
VNOISE = Z × 0.001 × 10⎜ dBM
⎟
10
⎝
⎠
where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value of the particular
input level, and Signal is the signal level within the ADC
Rev. PrE | Page 10 of 21
Preliminary Technical Data
AD9230
reported in dB below full scale. This value includes both
thermal and quantization noise.
of the worst third-order intermodulation product; reported in
dBc.
Power Supply Rejection Ratio
Two-Tone SFDR
The ratio of a change in input offset voltage to a change in
power supply voltage.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered) or in dBFS (always
related back to converter full scale).
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
Signal-to-Noise Ratio (without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Transient Response Time
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. May be reported in
dBc (i.e., degrades as signal level is lowered) or dBFS (always
related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to 10%
below positive full scale.
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to 10%
below positive full scale.
The ratio of the rms value of either input tone to the rms value
Rev. PrE | Page 11 of 21
AD9230
Preliminary Technical Data
EQUIVALENT CIRCUITS
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
IN
Vcm
CLK-
CLK+
10k
10k
Figure 6. Logic Inputs
DRVDD
Figure 4 Clock Inputs
V+
DataoutV–
V–
Dataout+
V+
AVDD
VIN+
BUF
AVDD
1000 Ω
Figure 7. Data Outputs (LVDS Mode)
BUF
AVDD
VIN-
1000 Ω
BUF
Figure 5. Analog Inputs (VX=~ 1.3V)
Rev. PrE | Page 12 of 21
Preliminary Technical Data
AD9230
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DrVDD = 1.8 V, rated sample rate, , DCS enabled, TA = 25°C, 1.25 V p-p differential
input, AIN = −1dBFS, unless otherwise noted.
0
0
Analog: 30.4MHz @ 1dBFS
SNR: 63.4dB
SFDR 87 5dBc
-10
Analog: 5.1MHz @ -1dBFS
SNR: 63.88dB
SFDR 82dBc
-20
-30
-30
-40
-40
-50
-50
-60
-60
dBFS
dBFS
-20
-10
-70
-80
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
0
21.25
42.5
63.75
85
0
31.25
Frequency (MHz)
62.5
93.75
125
Frequency (MHz)
Figure 8. AD9230-170 64k Point Single-Tone FFT/170 MSPS/30.3 MHz
Figure 11. AD9230-250 64k Point Single-Tone FFT/250 MSPS 5.1 MHz
0
0
Analog: 30.4MHz @ 1dBFS
SNR: 64.1dB
SFDR 80dBc
-10
-20
Analog: 30.4MHz @ 1dBFS
SNR: 63.6dB
SFDR 79dBc
-10
-20
-30
-30
-40
-40
-50
-50
-60
dBFS
dBFS
-60
-70
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
-140
0
0
26.25
52.5
78.75
31.25
105
62.5
93.75
125
Frequency (MHz)
Frequency (MHz)
Figure 12. AD9230-250 64k Point Single-Tone FFT/250 MSPS 30.3 MHz
Figure 9. AD9230-210 64k Point Single-Tone FFT/210 MSPS/30.3 MHz
0
1
Analog: 73.3MHz @ -1dBFS
SNR: 62.75dB
SFDR 73dBc
-10
-20
0.8
-30
0.6
-40
-50
0.4
dBFS
DNLR error (LSBs)
-60
0.2
-70
-80
0
0
500
1000
1500
2000
2500
3000
3500
4000
-0.2
-90
-100
-110
-0.4
-120
-0.6
-130
-140
-0.8
0
31.25
62.5
93.75
125
Frequency (MHz)
-1
Output Code
Figure 13. AD9230-250 64k Point Single-Tone FFT/250 MSPS 70.3 MHz
Figure 10. AD9230-250 64k Point Single-Tone FFT/250 MSPS/5.1 MHz z
Rev. PrE | Page 13 of 21
AD9230
Preliminary Technical Data
THEORY OF OPERATION
provide band limiting of the input signal.
The AD9230 architecture consists of a front-end sample and
hold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The outputstaging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9230 is a differential buffer. For
best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common mode
settling errors are symmetrical. The analog input is optimized
to provide superior wideband performance and requires that
the analog inputs be driven differentially. SNR and SINAD
performance degrades significantly if the analog input is driven
with a single-ended signal.
Differential Input Configurations
Optimum performance is achieved while driving the AD9230
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2+0.5V, and the
driver can be configured in a Sallen-Key filter topology to
499 Ω
AVDD
33 Ω
499 Ω
VIN+
AD8138
0.1μF
20pF
AD9230
33 Ω
523 Ω
VIN –
CML
499 Ω
05491-004
Figure 14. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers is not adequate to achieve the
true performance of the AD9230. This is especially true in IF
under-sampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few MHz, and excessive signal power can
also cause core saturation, which leads to distortion.
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
33Ω
1.25V p-p
10pF
49.9Ω
33Ω
A wideband transformer, such as Mini-Circuits’ ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 1.3 V.
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.25Vp-p fixed span
of the ADC core. This internal voltage reference can be
adjusted by means of SPI control. See SPI control section for
more details.
49.9 Ω
1V p-p
VIN+
AD9230
VIN–
0.1μF
05491-005
Figure 15. Differential Transformer—Coupled Configuration
Single-Ended Input Configuration
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input
common-mode swing. However, if the source impedances
on each input are matched, there should be little effect on
SNR performance. Figure 16 details a typical single-ended
input configuration.
Rev. PrE | Page 14 of 21
Preliminary Technical Data
AD9230
10µF
150Ω
AVDD
R
VIN+
1.25Vp-p
49.9 Ω
0.1µF
CLK+
AD9230
VIN-
PECL
AD9512
0.1uF
AD9230
CML
CLK-
AGND
0.1uF
0.1uF
Figure 16. Single-Ended Input Configuration using SPI enabled CML function
150Ω
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9230 the sample clock inputs
(CLK+ and CLK-) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK- pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias (See Figure X).
AVDD
1.2V
CLK-
CLK+
2pF
2pF
Figure .Equivalent Clock Input Circuit
Figure X shows one preferred method for clocking the AD9230.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD9230 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9230 while preserving the
fast rise and fall times of the signal, which are critical to a low
jitter performance.
CLK+
Clock
Source
AD9230
CLK-
Figure X. Transformer Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure X. The AD9512 (or same family) from offers excellent
jitter performance.
Rev. PrE | Page 15 of 21
Figure X. Differential PECL Sample Clock
AD9230
Preliminary Technical Data
Clock Input Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic
performance
characteristics. The AD9230 contains a DCS (duty cycle
stabilizer) that retimes the non-sampling edge, providing an
internal clock signal with a nominal 50% duty cycle. This allows
a wide range of clock input duty cycles without affecting the
performance of the AD9230. Noise and distortion performance
are nearly flat for a wide range duty cycles with the DCS on.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the non-sampling edge. As a result, any changes to the
sampling frequency require approximately TBD clock cycles to
allow the DLL to acquire and lock to the new rate.
AD9230. Power supplies for clock drivers should be separated
from the ADC output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other
methods), it should be retimed by the original clock at the last
step.
POWER DISSIPATION AND POWER DOWN MODE
As shown in Figure 18 and Figure 20, the power dissipated by
the AD9230 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fINPUT) due only to aperture jitter (tJ) can be
calculated by
π
SNR = 20 log ⎡⎢ f INPUT × t J ⎤⎥
⎣2
⎦
In the equation, the rms aperture jitter represents the rootmean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
under-sampling applications are particularly sensitive to jitter,
see Figure 17.
Figure 18. AD9230-170, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
75
0.2ps
70
65
SNR (dBc)
0.5ps
60
1.0ps
1.5ps
55
2.0ps
2.5ps
50
Figure 19. AD9230-210, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
3.0ps
45
40
1
10
100
INPUT FREQUENCY (MHz)
1000
Figure 17. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
Rev. PrE | Page 16 of 21
Preliminary Technical Data
AD9230
The format of the output data is offset binary. An example of
the output coding format can be found in Table 7.
Table 7. Digital Output Coding
Code
4095
2048
2047
0
(VIN+) − (VIN−),
Input Span =
1.252 V p-p (V)
1.000
0
−0.000488
−1.00
Digital Output
Offset Binary
(D11 ... D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
As detailed in Interfacing to ADC SPI, the data format can be
selected for either offset binary or twos complement, or Gray
code (SPI access only).
Figure 20. AD9230-250, Supply Current vs. fSAMPLE for fIN = 10.3 MHz
By asserting the PDWN pin high, the AD9230 is placed in
standby mode. In this state, the ADC typically dissipates
1 mW even if the CLK and analog inputs are static. During
standby, the output drivers are placed in a high impedance state.
Reasserting the PDWN pin low returns the AD9230 into its
normal operational mode.
An additional stand by mode is supported by means of varying
the clock input. When the clock rate falls below 20MHz, the
AD9230 will assume a standby state. In this case, the biasing
network and internal reference remain on but digital circuitry is
powered down. Upon reactivating the clock, the AD9230 will
resume normal operation after allowing for the pipeline latency.
Out-of-Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OTR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OTR has the same
pipeline latency as the digital data. OTR is low when the analog
input voltage is within the analog input range and high when
the analog input voltage exceeds the input range as shown in
Figure 21. OTR will remain high until the analog input returns
to within the input range and another conversion is completed.
By logically AND-ing OTR with the MSB and its complement,
over-range high or under-range low conditions can be detected.
DIGITAL OUTPUTS
The AD9228’s differential outputs conform to the ANSI-644
LVDS standard on default power up. The LVDS driver current
is derived on-chip and sets the output current at each output
equal to a nominal 3.5 mA. A 100 Ω differential termination
resistor placed at the LVDS receiver inputs results in a nominal
350 mV swing at the receiver.
Figure 21. OTR Relation to Input Voltage and Output Data
The AD9230’s LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments. Single point-to-point net topologies are recommended
with a 100 Ω termination resistor placed as close to the receiver
as possible. It is recommended to keep the trace length no
longer than 12 inches and to keep differential output traces
close together and at equal lengths.
TIMING
The AD9230 provides latched data outputs with a pipeline delay
of five clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Rev. PrE | Page 17 of 21
AD9230
Preliminary Technical Data
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9230.
These transients can degrade the converter’s dynamic performance.
The AD9230 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO.
Spec
Name
Meaning
tDS
Setup time between data and rising edge of SCLK
tDH
Hold time between data and rising edge of SCLK
tCLK
Period of the clock
The lowest typical conversion rate of the AD9230 is 40 MSPS.
At clock rates below 1 MSPS, the AD9230 will assume standby
mode.
tS
Setup time between CSB and SCLK
tH
Hold time between CSB and SCLK
RBIAS
tHI
Minimum period that SCLK should be in a logic high
state
tLO
Minimum period that SCLK should be in a logic low
state
The AD9230 requires the user to place a 10KΩ resistor between
the RBIAS pin and ground. This resister should have a 1%
tolerance, and is used to set the master current reference of the
ADC core.
AD9230 CONFIGURATION USING THE SPI
The AD9230 serial port interface allows the user to configure
the converter for specific functions or operations through a
structured register space inside the ADC. This gives the user
added flexibility to customize device operation depending on
the application. Addresses are accessed (programmed or read
back) serially in one-byte words. Each byte may be further
divided down into fields which are documented in the Memory
Map Section below.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SPI SCLK / DFS, SPI SDIO
/ DCS, and CSB pins. The SCLK/DFS (serial clock) is used to
synchronize the read and write data presented the ADC.. The
SDIO / DCS (serial data input/output) is a dual purpose pin
that allows data to be sent and read from the internal ADC
memory map registers. The CSB or chip select bar is an active
low control that enables or disables the read and write cycles.
See Table X.
During an instruction phase a 16bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits which is 1 or more bytes of data. All data is
composed of 8bit words. The first bit of each individual byte of
serial data indicates whether this is a read or write command.
This allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
Data may be sent in MSB or in LSB first mode. MSB first is
default on power up and may be changed by changing the
configuration register. For more information about this feature
and others see SPI Doc at www.analog.com.
Table X. Serial Port Pins
Pin
SCLK
SDIO
CSB
RESET
Function
SCLK (Serial Clock) is the serial shift clock in. SCLK is
used to synchronize serial interface reads and writes.
SDIO (Serial Data Input/Output) is a dual purpose pin.
The typical role for this pin is an input and output
depending on the instruction being sent and the
relative position in the timing frame.
CSB (Chip Select Bar) is active low controls that gates
the read and write cycles.
Master device reset. When asserted, device assumes
default settings.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure X
and Table X. Table X. SPI Timing Diagram specifications
Rev. PrE | Page 18 of 21
Preliminary Technical Data
AD9230
HARDWARE INTERFACE
The pins described in Table X comprise the physical interface
between the user’s programming device and the serial port of
the AD9230. All serial pins are inputs, which is an open-drain
output and should be tied to an external pull-up or pull-down
resistor (suggested value 10 kΩ).
This interface is flexible enough to be controlled by either
PROMS or PIC mirocontrollers as well. This provides the user
to use an alternate method to program the ADC other than a
SPI controller.
If the user chooses to not use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device power
on. The section below describes the strappable functions
supported on the AD9230. AD9230
CONFIGURATION WITHOUT THE SPI
SPI SDIO / DCS
SPI SCLK / DFS
All locations marked as “open” are currently not supported for
this particular device. When required, these locations should be
written with 0s. Writing to these locations is required only when
part of an address location is open (for example, Address 0x14).
If the whole address location is open (for example, Address
0x13), then this address location does not need to be written.
DEFAULT VALUES
Table 6. Mode Selection
External
Voltage
AVDD
AGND
AVDD
AGND
Starting from the right hand column, the memory map register
in Table X documents the default hex value for each hex address
shown. The column with the heading Byte 7 (MSB) is the start
of the default hex value giving. For example, hex address 0x14,
flex_output_phase has a hex default value of 00h. This means
Bit 3 = 0, Bit 2 = 0, Bit 1 = 1, and Bit 0 = 1 or 0011 in binary.
This setting is the default output clock or DCO phase adjust
option. The default value adjusts the DCO phase 90deg relative
to the Nominal DCO edge and 180deg relative to the data edge.
For more information on this function and others consult the
SPI Doc at www.analog.com.
OPEN LOCATIONS
In applications that do not interface to the SPI control registers,
the SPI SDIO / DCS and SPI SCLK / DFS pins can alternately
serve as stand alone CMOS compatible control pins When the
device is powered up, it is assumed that the user intends to use
the pins as static control lines for the duty cycle stabilizer. In
this mode the SPI CSB chip select should be connected to
AVDD, which will disable the serial port interface.
Pin
configuration register map (Address 0x00 to Address 0x02),
device index and transfer register map (Address 0x04 to
Address 0x05, and Address 0xFF), global ADC function register
map (Address 0x08 to Address 0x09), and flexible ADC
functions register map (Address 0x0B to Address 0x25). The
flexible ADC functions register map is product specific.
Configuration
Duty Cycle Stabilizer Enabled
Duty Cycle Stabilizer Disabled
2’s Complement Enabled
Offset Binary Enabled
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into four sections: chip
Coming out of reset, some of the address locations (but not all)
are loaded with default values. The default values for the
registers are given in the Table X.
LOGIC LEVELS
An explanation of various registers, “bit is set” is synonymous
with “bit is set to Logic 1” or “writing Logic 1 for the bit.”
Similarly “clear a bit” is synonymous with “bit is set to Logic 0”
or “writing Logic 0 for the bit.”
Figure X. Serial Port Interface Timing Diagram
Rev. PrE | Page 19 of 21
AD9230
Preliminary Technical Data
Table X. AD9230 Device Configuration Register Memory Map
.
Rev. PrE | Page 20 of 21
Preliminary Technical Data
AD9230
OUTLINE DIMENSIONS
a
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 x 8 mm Body, Very Thin Quad
(CP-56-2)
Dimensions shown in millimeters
8.00
BSC SQ
0.30
0.23
0.18
0.60 MAX
0.60 MAX
56
43
42
PIN 1
INDICATOR
TOP
VIEW
1
4.45
4.30 SQ
4.15
EXPOSED
PAD
(BOTTOM VIEW)
7.75
BSC SQ
0.50
0.40
0.30
PIN 1
INDICATOR
14
29
28
15
0.30 MIN
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
0.50 BSC
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
112805-0
1.00
0.85
0.80
6.50
REF
Figure 22. Mechanical Drawing (Subject to change)
ORDERING GUIDE
Model
AD9230BCPZ-1701
AD9230BCPZ-2101
AD9230BCPZ-2501
Temperature
Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
56-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
56-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
56-Lead Lead Frame Chip Scale Package (LFCSP-VQ)
AD9230-250EB
AD9230-210EB
AD9230-170EB
25°C
25°C
25°C
LVDS Evaluation Board with AD9230BCPZ-250
LVDS Evaluation Board with AD9230BCPZ-210
LVDS Evaluation Board with AD9230BCPZ-170
1
Z=Pb-free part
© 2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
PR06002-0-3/06(PrE)
Rev. PrE | Page 21 of 21
Package Option
CP-56
CP-56
CP-56