STMicroelectronics L9826 Octal low-side driver for resistive and inductive loads with serial/parallel input control, output protection and diagnostic Datasheet

L9826
Octal Low-Side Driver for Resistive and Inductive Loads with
Serial/Parallel Input Control, Output Protection and Diagnostic
Features
■
OUTPUTS CURRENT CAPABILITY UP TO
450mA
■
TYPICAL RON = 1.5Ω AT TJ = 25°C
■
PARALLEL CONTROL INPUTS FOR
OUTPUTS 1 AND 2
■
SPI CONTROL FOR OUTPUTS 1 TO 8
■
RESET FUNCTION WITH RESET SIGNAL AT
NRES PIN OR UNDERVOLTAGE AT VCC
■
INTRINSIC OUTPUT VOLTAGE CLAMPING
AT TYP. 50V
SO20
■
OVERCURRENT SHUTDOWN AT OUTPUTS
3 TO 8
■
SHORT CIRCUIT CURRENT LIMITATION
AND SELECTIVE THERMAL SHUTDOWN AT
OUTPUTS 1 AND 2
■
OUTPUT STATUS DATA AVAILABLE ON
THE SPI
Description
The L9826 is a Octal Low-Side Driver Circuit,
dedicated for automotive applications. Output
voltage clamping is provided for flyback current
recirculation, when inductive loads are driven.
Chip Select and Serial Peripheral Interface for
outputs control and diagnostic data transfer.
Parallel Control inputs for two outputs.
.
Order codes
Part number
July 2005
Temp range, °C
Package
Packing
L9826
SO20 (16+2+2)
Tube
L9826TR
SO20
Tape & Reel
CD00002120
Rev 8
1/17
www.st.com
17
L9826
Contents
1
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pins Description and Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . 4
3
4
2.1
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Pins connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2
Output Stages Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3
Power outputs characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4
Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6
Package Informations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
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L9826
Block Diagram
Figure 1.
Block diagram
VCC
VCC
NON1
OUT1
1
3
S
2
IOL
Latch / Driver
Q1
R
Overtemperature Detection
+
Fault Latch
Diag1
-
VDG
CH1
NON2
VCC
CLK
VCC
SDI
CH2
Output Latch
NCS
Q2
Diag2
SPI
Interface
VCC
Shift Register
1
1 Block Diagram
VCC
SDO
OUT3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
VCC
Reset
Q3
S
Latch / Driver
Reset
Undervoltage
RESET
IOL
R
+
Diag1 Diag3
Diag2
Diag3
Diag4
Q4
Diag5 Diag4
Diag6
Diag7
Q5
Diag8
Diag5
GND
NRES
OUT2
-
VDG
CH3
CH4
CH5
Q6
Diag6
CH6
Q7
Diag7
CH7
Q8
Diag8
CH8
OUT4
OUT5
OUT6
OUT7
OUT8
GND
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L9826
2 Pins Description and Connection Diagrams
2
Pins Description and Connection Diagrams
2.1
Pin description
Table 1.
4/17
Pin description
N°
Pin
Description
1
Out 6
output 6
2
Out 1
output 1
3
NRes
asynchronous reset
4
NCS
chip select (active low)
5
GND
device ground
6
GND
device ground
7
NON1
control input 1
8
SDO
serial data output
9
Out 8
output 8
10
Out 3
output 3
11
Out 5
output 5
12
Out 2
output 2
13
SDI
serial data input
14
CLK
serial clock
15
GND
device ground
16
GND
device ground
17
NON2
control input 2
18
VCC
supply voltage
19
Out 7
output 7
20
Out 4
output 4
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L9826
2.2
2 Pins Description and Connection Diagrams
Pins connection
Figure 2.
Connection diagram
OUT6
1
20
OUT4
OUT1
2
19
OUT7
nRES
3
18
Vcc
NCS
4
17
NON2
GND
5
16
GND
GND
6
15
GND
NON1
7
14
CLK
SDO
8
13
SDI
OUT8
9
12
OUT2
OUT3
10
11
OUT5
PINCON_L9826
2.3
Thermal data
Table 2.
Thermal data
Symbol
Parameter
Test Condition
Min.
Typ.
150
165
Max.
Unit
Thermal shutdown
TJSC
Thermal shutdown threshold
°C
Thermal resistance
RthjA-one
Single output (junction
ambient)
90
°C/W
RthjA-all
All outputs (junction
ambient)
75
°C/W
Rthj-pin
Junction to Pin
18
°C/W
CD00002120
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L9826
3 Electrical Specifications
3
Electrical Specifications
3.1
Absolute maximum ratings
Table 3.
For voltages and currents applied externally to the device
Symbol
VCC
Parameter
Test Condition
Max.
Unit
-0.3
7
V
-0.3
7
V
-20
20
mA
Continuous output voltage
-0.7
45
V
Output current 2)
-2
1.0
A
10
mJ
Supply voltage
Min.
Typ.
Inputs and data lines
(NONx, NCS, CLK, SDI, nRes)
VIN
Voltage
(NONx, NCS, CLK, SDI,
nRes)
IIN
Protection diodes current 1)
T ≤ 1ms
Outputs (Out1 ... Out8)
VOUTc
IOUT
EOUTcl
Output clamp energy
IOUT ≤ 150mA
Note: 1 All inputs are protected against ESD according to MIL 883C; tested with HBM at 2KV.
It corresponds to a dissipated energy E ≤ 0,2mJ.
2 Transient pulses in accordance to DIN40839 part 1, 3 and ISO 7637 Part 1, 3.
Figure 3.
Symbol
For currents determined within the device:
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Output current (Out1, Out2)
ILIM
A
Output current (Out3 ... Out8)
ISCB
A
Outputs (Out1 ... Out8)
IOUT
ΣIOUT1 Total average-current all
i = 1-8 outputs 3)
Tamb = 60°C
2.0
A
3 When operating the device with short circuit at more than 2 outputs at the same time, damage
due to electrical overstress may occur.
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L9826
3.2
Table 4.
3 Electrical Specifications
Electrical characteristics
Electrical Characteristcs
(4.5V ≤ VCC ≤ 5,5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified).
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
70
µA
5
mA
100
mA
3
4
V
Supply voltage
IccSTB
Standby current
without load (nRes = Low)
IOUT1 ... 8 = 500mA
IccOPM
∆ICC
Operating mode
∆ICC during reverse output
current
VDDRES Undervoltage Reset
SPI - CLK = 3MHz
NCS = LOW
SDO no load
Iout = -2A
Reset of all registers and disable
of all outputs
Inputs (NONx. NCS, CLK, SDI, nRes)
VINL
Low level
-0.3
0.2·VCC
V
VINH
High level
0.7·VCC
VCC
+0,3
V
Vhyst
Hysteresis voltage
IIN
RIN
CIN
Input current
0.85
NONx, NCS, CLK, SDI
VIN = VCC
V
10
NRES (VIN = 0V)
-10
Pullup resistance
(NONx, NCS, CLK, SDI)
Pulldown resistance (NRes)
50
Input capacitance
Guaranteed by design
µA
µA
250
kΩ
10
pF
Serial data outputs
VSDOH
High output level
ISDO = -4mA
VSDOL
Low output level
ISDO = 3,2mA
ISDOL
Tristate leakage current
NCS = high; 0V ≤ VSDO ≤ VCC
CSDO
Output capacitance
VCC -0.4
V
0.4
V
10
µA
fSDO = 300kHz, Guaranteed by
design
10
pF
IOUTL1 - 8 Leakage current
OUTx = OFF; VOUTx = 25V;
VCC = 5V
100
µA
IOUTL1 - 8 Leakage current
OUTx = OFF; VOUTx = 16V;
VCC = 5V
100
µA
-10
Outputs OUT 1 ... 8
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L9826
3 Electrical Specifications
Table 4.
Electrical Characteristcs (continued)
(4.5V ≤ VCC ≤ 5,5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified).
Symbol
Parameter
IOUTL1 - 8 Leakage current
Test Condition
Min.
Typ.
OUTx = OFF; VOUTx = 16V;
VCC = 1V
Max.
Unit
10
µA
62
V
Output clamp voltage
1mA ≤ Iclp ≤ Ioutp; Itest = 10mA with
correlation
RDSon
On resistance OUT 1 ... 8
IOUT = 250mA; Tj = +150°C
3.0
Ω
COUT
Output capacitance
VOUT = 16V; f = 1MHz
guaranteed by design
300
pF
Vclp
45
Outputs short circuit protection
ISBC
Overcurrent shutoff threshold
OUT3 ... OUT8
0.45
1.1
A
ILIM
Short circuit current limitation
OUT1; OUT2
0.5
1.1
A
tSCB
Delay shutdown
12
µs
0.32
·VCC
0.4·VCC
V
0.2
3,0
Diagnostics
VDG
Diagnostic threshold voltage
IOL
Open load detection sink
current
Vout = VDG
20
100
µA
tdf
Diagnostic detection filter time
for output 1 & 2 on each
diagnostic condition
15
50
µs
5
µs
10
µs
10
µs
Outputs timing
NON1, 2 = 50% to VOUT = 0,9·Vbat
tdon1
Turn ON delay of OUT 1 and 2 NCS = 50% to VOUT = 0,9·Vbat
(VBAT = 16V, RL = 500Ω)
tdon2
Turn ON delay of OUT 3 to 8
tdoff
Turn OFF delay of OUT 1 to 8
NCS = 50% to VOUT = 0,9·Vbat
(VBAT = 16V, RL = 500Ω)
NCS = 50% to VOUT = 0,1·Vbat
NON1, 2 = 50% to VOUT = 0,1·Vbat
(VBAT = 16V, RL = 500Ω)
dUon1/dt Turn ON voltage slew-rate
For output 3 to 8; 90% to 30% of
Vbat; RL = 500Ω; Vbat = 16V
0.7
3.5
V/µs
dUon2/dt Turn ON voltage slew-rate
For output 1 and 2; 90% to 30%
of Vbat; RL = 500Ω; Vbat = 16V
2
10
V/µs
dUoff1/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 90% of
Vbat; RL = 500Ω; Vbat = 16V
2
10
V/µs
dUoff2/dt Turn OFF voltage slew-rate
For output 1 to 8; 30% to 80% of
Vbat; RL = 500Ω; Vbat = 0.9 · Vclp
2
15
V/µs
Serial diagnostic link (Load capacitor at SDO = 100pF)
8/17
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L9826
Table 4.
Symbol
3 Electrical Specifications
Electrical Characteristcs (continued)
(4.5V ≤ VCC ≤ 5,5V; -40°C ≤ TJ ≤ 150°C; unless otherwise specified).
Parameter
Test Condition
Min.
Typ.
Max.
Unit
3
MHz
fclk
Clock frequency
tclh
Minimum time CLK = HIGH
160
ns
tcll
Minimum time CLK = LOW
160
ns
50% duty cycle
tpcld
Propagation delay
CLK to data at SDO valid
tcsdv
NCS = LOW to data at SDO
active
tsclch
CLK low before NCS low
thclcl
CLK change L/H after NCS =
low
tscld
SDI input setup time
CLK change H/L after SDI data
valid
thcld
SDI input hold time
SDI data hold after CLK change
H/L
tsclcl
CLK low before NCS high
150
ns
thclch
CLK high after NCS high
150
ns
tpchdz
NCS L/H to output data float
NCS pulse filter time
4,9V ≤ VCC ≤ 5,1V
Setup time CLK to NCS change
H/L
100
ns
100
ns
100
ns
100
ns
20
ns
20
100
ns
ns
Multiple of 8 CLK cycles inside
NCS period
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L9826
4 Functional Description
4
Functional Description
4.1
General
The L9826 integrated circuit features 8 power low-side-driver outputs. Data is transmitted to the
device using the Serial Peripheral Interface, SPI protocol. Outputs 1 and 2 can be controlled
parallel or serial. The power outputs features voltage clamping function for flyback current
recirculation and are protected against short circuit to Vbat.
The diagnostics recognizes two outputs fault conditions: 1) overcurrent for outputs 3 to 8 ,
overcurrent and thermal overload for outputs 1 and 2 in switch-on condition and 2) open load
or short to GND in switch-off condition for all outputs. The outputs status can be read out via
the serial interface.
The chip internal reset is a OR function of the external nRes signal and internally generated
undervoltage nRes signal.
4.2
Output Stages Control
Each output is controlled with its latch and with common reset line, which enables all eight
outputs. Outputs 1 and 2 can be controlled also by its NON1, NON2 inputs. It allows PWM
control independently on the SPI. These inputs features internal pull-up resistors to assure that
the outputs are switched off, when the inputs are open.
The control data are transmitted via the SDI input, the timing of the serial interface is shown in
Figure 4..
The device is selected with low NCS signal and the input data are transferred into the 8 bit shift
register at every falling CLK edge. The rising edge of the NCS latches the new data from the
shift register to the drivers.
Figure 4.
Timing of the Serial Interface
NCS
tsclch
thclcl
tclh
tcll
tsclcl
thclch
CLK
tcsdv
SDO
tpcld
not defined
tpchdz
D8
D1
thcld
tscld
SDI
D8
D7
D1
The SPI register data are transferred to the output latch at rising NCS edge. The digital filter
between NCS and the output latch ensures that the data are transferred only after 8 CLK cycles
or multiple of 8 CLK cycles since the last NCS falling edge. The NCS changes only at low CLK.
10/17
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L9826
4 Functional Description
Outputs Control Tables :
Table 5.
Outputs 1, 2:
Outputs 3 to 8:
NON1, 2
1
0
0
1
SPI-bit 1, 2
0
0
1
1
SPI-bit 3 ... 8
0
1
Output 1, 2
off
on
on
on
Output 3 ... 8
off
on
Figure 5.
Output control register structure
MSB
Q2
LSB
Q4
Q6
Q8
Q1
Q3
Q5
Q7
Control-bit output 7
Control-bit output 5
Control-bit output 3
Control-bit output 1
Control-bit output 8
Control-bit output 6
Control-bit output 4
Control-bit output 2
4.3
Power outputs characteristics
for flyback current, outputs short circuit protection and diagnostics
For output currents flowing into the circuit the output voltages are limited. The typical value of
this voltage is 50V. This function allows that the flyback current of a inductive load recirculates
into the circuit; the flyback energy is absorbed in the chip.
Output short circuit protection for outputs 3 to 8 (dedicated for loads without inrush current):
when the output current exceeds the short circuit threshold, the corresponding output overload
latch is set and the output is switched off immediately.
Output short circuit protection for outputs 1 and 2 (dedicated for loads with inrush current, as
lamps): when the load current would exceed the short circuit limit value, the corresponding
output goes in a current regulation mode.
The output current is determined by the output characteristics and the output voltage depends
on the load resistance. In this mode high power is dissipated in the output transistor and its
temperature increases rapidly. When the power transistor temperature exceeds the thermal
shutdown threshold, the overload latch is set and the corresponding output switched off.
For the load diagnostic in output off condition each output features a diagnostic current sink, typ
60µA.
CD00002120
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L9826
4 Functional Description
4.4
Diagnostics
The output voltage at all outputs is compared with the diagnostic threshold, typ 0,38 · VCC.
Outputs 1 and 2 features dedicated fault latches. The output status signal is filtered and
latched. The fault latches are cleared during NCS low. The latch stores the status bit, so the
first reading after the error occurred might be wrong. The second reading is right.
Table 6.
Diagnostic Table for outputs 1 and 2 in parallel controlled mode:
Output 1, 2
Output-voltage
Status-bit
Output-mode
off
> DG-threshold
high
correct operation
off
< DG-threshold
low
fault condition 2)
on
< DG-threshold
high
correct operation
on
> DG-threshold
low
fault condition 1)
Fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage at
the output exceeds the diagnostics threshold. The output operates in current regulation mode
or has been switched off due to thermal shutdown. The status bit is low.
Fault condition 2) "open load" or "output short circuit to GND" : the output is switched off and
the voltage at the output drops below the diagnostics threshold, because the load current is
lower than the output diagnostic current source, the load is interrupted. The diagnostic bit is
low.
For outputs 3 to 8 the output status signals, are fed directly to the SPI register.
Table 7.
Diagnostic Table for outputs 1 to 8 in SPI controlled mode:
Output 1 ... 8
Output-voltage
Status-bit
Output-mode
off
> DG-threshold
high
correct operation
off
< DG-threshold
low
fault condition 2)
on
< DG-threshold
low
correct operation
on
> DG-threshold
high
fault condition 1)
The fault condition 1) "output short circuit to Vbat" : the output was switched on and the voltage
at the output exceeded the diagnostics threshold due to overcurrent, the output overload latch
was set and the output has been switched off. The diagnostic bit is high.
Fault condition 2) "open load" or "output short circuit to GND" is the same as of outputs 1 and
2. At the falling edge of NCS the output status data are transferred to the shift register.
When NSC is low, data bits contained in the shift register are transferred to SDO output et
every rising CLK edge.
12/17
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L9826
4 Functional Description
Figure 6.
The Pulse Diagram to Read the Outputs Status Register
NCS
CLK
SDO
SDI
Table 8.
MSB
6
MSB
5
6
4
5
3
4
2
3
1
2
LSB
1
LSB
The Structure of the Outputs Status Register
MSB
LSB
Diag2 Diag4 Diag6 Diag8 Diag1 Diag3 Diag5 Diag7
Diagnostic-bit output 7
Diagnostic-bit output 5
Diagnostic-bit output 3
Diagnostic-bit output 1
Diagnostic-bit output 8
Diagnostic-bit output 6
Diagnostic-bit output 4
Diagnostic-bit output 2
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L9826
5 Application Information
5
Application Information
The typical application diagram is shown in Figure 7..
Figure 7.
Typical Application Circuit Diagram for the L9826 Circuit
VCC
VOLTAGE
REGULATOR
VBAT
VCC
VCC
NON1
OUT1
1
3
S
2
IOL
Latch / Driver
Q1
R
Overtemperature Detection
+
Fault Latch
Diag1
-
VDG
CH1
NON2
CLK
VCC
SDI
CH2
Output Latch
VCC
SPI
Interface
NCS
Q2
Diag2
Shift Register
VCC
VCC
SDO
OUT3
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
µP
VCC
Reset
Reset
Undervoltage
RESET
S
Latch / Driver
IOL
R
+
-
CH3
CH5
Q6
Diag6
CH6
Q7
Diag7
CH7
Q8
Diag8
CH8
OUT4
OUT5
OUT6
OUT7
OUT8
R, L loads
GND
NRES
SDI
SDO
VDG
CH4
L9826
CLOCK
NCS2 ... 7
Q3
Diag1 Diag3
Diag2
Diag3
Diag4
Q4
Diag5 Diag4
Diag6
Diag7
Q5
Diag8
Diag5
GND
nRES
OUT2
L9826
For higher current driving capability two outputs of the same kind can be paralleled. In this case
the maximum flyback energy should not exceed the limit value for single output.
The immunity of the circuit with respect to the transients at the output is verified during the
characterization for Test Pulses 1, 2 and 3a, 3b, DIN40839 or ISO7637 part 3. The Test Pulses
are coupled to the outputs with 200pF series capacitor. All outputs withstand testpulses without
damage.
The correct function of the circuit with the Test Pulses coupled to the outputs is verified during
the characterization for the typical application with R = 30Ω to 100Ω, L= 0 to 600mH loads. The
Test Pulses are coupled to the outputs with 200pF series capacitor.
14/17
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6
Figure 8.
6 Package Informations
Package Informations
PowerSO20 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.10
0.30
0.004
0.012
B
0.33
0.51
0.013
0.200
C
0.23
0.32
0.009
0.013
D (1)
12.60
13.00
0.496
0.512
E
7.40
7.60
0.291
0.299
e
1.27
0.050
H
10.0
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.40
1.27
0.016
0.050
k
ddd
OUTLINE AND
MECHANICAL DATA
0˚ (min.), 8˚ (max.)
0.10
0.004
(1) “D” dimension does not include mold flash, protusions or gate
burrs. Mold flash, protusions or gate burrs shall not exceed
0.15mm per side.
SO20
0016022 D
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L9826
7 Revision history
7
16/17
Revision history
Date
Revision
Changes
22 April 2004
7
Initial release in EDOCS.
26 July 2005
8
Updated the Layout look & feel.
Modify value RON in Features
CD00002120
L9826
7 Revision history
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