Cypress CY8C20396-24LQXI Capsense application Datasheet

CY8C20X36/46/66/96
®
CapSense Applications
Features
■
1.71V to 5.5V Operating Range
■
Versatile Analog Mux
❐ Common Internal Analog Bus
❐ Simultaneous Connection of I/O
❐ High PSRR Comparator
❐ Low Dropout Voltage Regulator for All Analog Resources
■
Additional System Resources
❐ I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• No Clock Stretching Required (under most conditions)
• Implementation During Sleep Modes with Less Than
100 µA
• Hardware Address Validation
❐ SPI™ Master and Slave: Configurable 46.9 kHz to 12 MHz
❐ Three 16-Bit Timers
❐ Watchdog and Sleep Timers
❐ Internal Voltage Reference
❐ Integrated Supervisory Circuit
❐ 8-bit Delta-Sigma Analog-to-Digital Converter
❐ Two General Purpose High Speed, Low Power Analog
Comparators
■
Complete Development Tools
❐ Free Development Tool (PSoC Designer™)
❐ Full Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128K Trace Memory
■
Package Options
❐ CY8C20x36:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN
❐ CY8C20x46:
• 16-Pin 3 x 3 x 0.6 mm QFN
• 24-Pin 4 x 4 x 0.6 mm QFN
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin SSOP
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
❐ CY8C20x96:
• 24-Pin 4 x 4 x 0.6 mm QFN (with USB)
• 32-Pin 5 x 5 x 0.6 mm QFN (with USB)
❐ CY8C20x66:
• 32-Pin 5 x 5 x 0.6 mm QFN
• 48-Pin 7 x 7 x 1.0 mm QFN (with USB)
• 48-Pin SSOP
®
■
Low Power CapSense Block
❐ Configurable Capacitive Sensing Elements
❐ Supports Combination of CapSense Buttons, Sliders,
Touchpads, Touch Screens, and Proximity Sensor
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds Running to 24 MHz
❐ Low Power at High Speed
❐ Interrupt Controller
❐ Temperature Range: -40°C to +85°C
■
Flexible On-Chip Memory
❐ Three Program/Data Storage Size Options:
• CY8C20x36: 8K Flash / 1K SRAM
• CY8C20x46, CY8C20x96: 16K Flash / 2K SRAM
• CY8C20x66: 32K Flash / 2K SRAM
❐ 50,000 Flash Erase/Write Cycles
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ In-System Serial Programming (ISSP)
■
Full Speed USB
❐ Available on CY8C20646, CY8C20666, CY8C20x96 Only
❐ 12 Mbps USB 2.0 Compliant
❐ Eight Unidirectional Endpoints
❐ One Bidirectional Control Endpoint
❐ Dedicated 512 Byte Buffer
❐ Internally Regulated at 3.3V
■
Precision, Programmable Clocking
❐ Internal Main Oscillator: 6/12/24 MHz ± 5%
❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and
Sleep Timers
❐ Precision 32 kHz Oscillator for Optional External Crystal
❐ 0.25% Accuracy for USB with No External Components
(CY8C20646, CY8C20666, CY8C20x96 only)
■
Programmable Pin Configurations
❐ Up to 36 GPIO (Depending on Package)
❐ Dual Mode GPIO: All GPIO Support Digital I/O and Analog
Input
❐ 25 mA Sink Current on All GPIO
❐ Pull up, High Z, Open Drain Modes on All GPIO
❐ CMOS Drive Mode (5 mA Source Current) on Ports 0 and 1:
• 20 mA (at 3.0V) Total Source Current on Port 0
• 20 mA (at 3.0V) Total Source Current on Port 1
❐ Selectable, Regulated Digital I/O on Port 1
❐ Configurable Input Threshold on Port 1
❐ Hot Swap Capability on all Port 1 GPIO
Cypress Semiconductor Corporation
Document Number: 001-12696 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 09, 2009
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Logic Block Diagram
Port 4
Port 3
Port 2
Port 1
Port 0
1.8/2.5/3V
LDO
PWRSYS
(Regulator)
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2K
SRAM
Supervisory ROM (SROM)
Interrupt
Controller
8K/16K/32K Flash
Nonvolatile Memory
Sleep and
Watchdog
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Two
Comparators
Analog
Reference
CapSense
Module
Analog
Mux
SYSTEM BUS
USB
I2C
Slave
Internal
Voltage
References
System
Resets
POR
and
LVD
SPI
Master/
Slave
Three 16-Bit
Programmable
Timers
Digital
Clocks
SYSTEM RESOURCES
Document Number: 001-12696 Rev. *F
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PSoC® Functional Overview
Figure 1. Analog System Block Diagram
The PSoC family consists of on-chip Controller devices. These
devices are designed to replace multiple traditional MCU-based
components with one, low cost single-chip programmable
component. A PSoC device includes configurable analog and
digital blocks, and programmable interconnect. This architecture
allows the user to create customized peripheral configurations,
to match the requirements of each individual application.
Additionally, a fast CPU, Flash program memory, SRAM data
memory, and configurable I/O are included in a range of
convenient pinouts.
Analog Global Bus
IDAC
Vr
The architecture for this device family, as shown in the Logic
Block Diagram on page 2, is comprised of three main areas: the
Core, the CapSense Analog System, and the System Resources
(including a full speed USB port). A common, versatile bus allows
connection between I/O and the analog system. Each
CY8C20x36/46/66/96 PSoC Device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 general purpose IO (GPIO) are also
included. The GPIO provides access to the MCU and analog
mux.
Reference
Buffer
Comparator
Cinternal
Mux
Mux
Refs
PSoC Core
CapSenseCounters
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO
(internal main oscillator) and ILO (internal low speed oscillator).
The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard architecture microprocessor.
System Resources provide additional capability, such as
configurable USB and I2C slave/SPI master-slave
communication interface, three 16-bit programmable timers, and
various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block
and an internal 1.2V analog reference, which together support
capacitive sensing of up to 36 inputs.
CapSense Analog System
The Analog System contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. Capacitive sensing is configurable on
each GPIO pin. Scanning of enabled CapSense pins are
completed quickly and easily across multiple ports.
CSCLK
IMO
CapSense
Clock Select
Oscillator
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Complex capacitive sensing interfaces, such as sliders and
touchpads.
■
Chip-wide mux that allows analog input from any I/O pin.
■
Crosspoint connection between any I/O pin combinations.
When designing capacitive sensing applications, refer to the
latest signal-to-noise signal level requirements Application
Notes, which can be found under http://www.cypress.com >
Documentation > Application Notes. In general, and unless
otherwise noted in the relevant Application Notes, the minimum
signal-to-noise ratio (SNR) for CapSense applications is 5:1.
Document Number: 001-12696 Rev. *F
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Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include low voltage detection and
power on reset. The merits of each system resource are listed
here:
■
The I2C slave/SPI master-slave module provides 50/100/400
kHz communication over two wires. SPI communication over
three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower
for a slower system clock).
■
The I2C hardware address recognition feature reduces the
already low power consumption by eliminating the need for
CPU intervention until a packet addressed to the target device
is received.
■
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power-On-Reset) circuit eliminates the need for a system
supervisor.
■
An internal reference provides an absolute reference for capacitive sensing.
■
A register-controlled bypass mode allows the user to disable
the LDO.
■
Standard Cypress PSoC IDE tools are available for debugging
the CY8C20x36/46/66/96 family of parts. However, the
additional trace length and a minimal ground plane in the FlexPod can create noise problems that make it difficult to debug
the design. A custom bonded On-Chip Debug (OCD) device is
available in an 48-pin QFN package. The OCD device is
recommended for debugging designs that have high current
and/or high analog accuracy requirements. The QFN package
is compact and is connected to the ICE through a high density
connector.
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in depth information, along with detailed programming
details, see the PSoC® Programmable System-on-Chip™
Technical Reference Manual for CY8C20x36/46/66/96 PSoC
Devices.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at www.cypress.com/psoc.
Application Notes
Application notes are an excellent introduction to the wide variety
of possible PSoC designs. They are located here:
www.cypress.com/psoc. Select Application Notes under the
Documentation tab.
Development Kits
PSoC Development Kits are available online from Cypress at
www.cypress.com/shop and through a growing number of
regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops) is available online at www.cypress.com/training. The
training covers a wide variety of topics and skill levels to assist
you in your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various
application designs that include firmware and hardware design
files that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at 1-800541-4736.
Document Number: 001-12696 Rev. *F
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Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development environment for the Programmable System-onChip (PSoC) devices. The PSoC Designer IDE and application
runs on Windows XP and Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System-Level View
The system-level view is a drag-and-drop visual embedded
system design environment based on PSoC Express. In this
view you solve design problems the same way you might think
about the system. Select input and output devices based upon
system requirements. Add a communication interface and define
the interface to the system (registers). Define when and how an
output device changes state based upon any/all other system
devices. Based upon the design, PSoC Designer automatically
selects one or more PSoC devices that match your system
requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip-Level View
The chip-level view is a more traditional integrated development
environment (IDE) based on PSoC Designer 4.x. You choose a
base device to work with and then select different onboard
analog and digital components called user modules that use the
PSoC blocks. Examples of user modules are ADCs, DACs,
Amplifiers, and Filters. You configure the user modules for your
chosen application and connect them to each other and to the
proper pins. Then you generate your project. This prepopulates
your project with APIs and libraries that you can use to program
your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over onchip resources. All views of the project share common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-12696 Rev. *F
Code Generation Tools
PSoC Designer supports multiple third-party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to be
merged seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write I/O
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog-todigital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces (I2Cbus, for example), and the logic to control how they interact with
one another (called valuators).
Generate, Verify, and Debug
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by
selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-12696 Rev. *F
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
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Document Conventions
Acronyms Used
Units of Measure
The following table lists the acronyms that are used in this
document.
A units of measure table is located in the Electrical Specifications
section. Table 11 on page 17 lists all the abbreviations used to
measure the PSoC devices.
Table 1. Acronyms
Acronym
Description
AC
alternating current
API
application programming interface
CPU
central processing unit
DC
direct current
FSR
full scale range
GPIO
general purpose I/O
GUI
graphical user interface
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
I/O
input/output
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip™
SLIMO
slow IMO
SRAM
static random access memory
Document Number: 001-12696 Rev. *F
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are
decimal.
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Pinouts
The CY8C20x36/46/66/96 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, and XRES
are not capable of Digital I/O.
16-Pin QFN (No E-Pad)
Table 2. Pin Definitions - CY8C20236, CY8C20246 PSoC Device [2]
P1[7] I2C SCL, SPI SS
4
IOHR
I
P1[5] I2C SDA, SPI MISO
5
IOHR
I
P1[3] SPI CLK
6
IOHR
I
P1[1] ISSP CLK[1], I2C SCL, SPI
MOSI
7
Power
Vss
Ground connection
8
IOHR
I
P1[0] ISSP DATA[1], I2C SDA, SPI
CLK
9
IOHR
I
P1[2]
10
IOHR
I
P1[4] Optional external clock
(EXTCLK)
11
12
13
Input
IOH
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
1
2
3
4
I
12
QFN
(Top View) 11
XRES Active high external reset with
internal pull down
Power
14
13
P2[3] Crystal input (XIn)
I
10
9
8
I
IOHR
7
I/O
3
Vss
2
AI, DATA1, I2C SDA, SPI CLK, P1[0]
P2[5] Crystal output (XOut)
P0[1], AI
P0[3], AI
P0[7], AI
Vdd
I
Figure 2. CY8C20236, CY8C20246 PSoC Device
16
15
Analog
I/O
Description
5
6
Digital
1
Name
AI, SPI CLK, P1[3]
AI, CLK1, SPI MOSI, P1[1]
Type
Pin
No.
P0[4], AI
XRES
P1[4], EXTCLK, AI
P1[2], AI
P0[4]
Vdd
Supply voltage
14
IOH
I
P0[7]
15
IOH
I
P0[3] Integrating input
16
IOH
I
P0[1] Integrating input
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Notes
1. These are the ISSP pins, which are not High Z at POR (Power On Reset).
2. During power up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues.
Document Number: 001-12696 Rev. *F
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24-Pin QFN
Table 3. Pin Definitions - CY8C20336, CY8C20346 [2, 3]
I
P1[7]
I2C SCL, SPI SS
5
IOHR
I
P1[5]
I2C SDA, SPI MISO
6
IOHR
I
P1[3]
SPI CLK
7
IOHR
I
P1[1]
ISSP CLK[1], I2C SCL, SPI
MOSI
8
9
Power
NC
No connection
Vss
Ground connection
ISSP DATA[1], I2C SDA, SPI
CLK
10
IOHR
I
P1[0]
11
IOHR
I
P1[2]
12
IOHR
I
P1[4]
13
IOHR
I
P1[6]
14
Input
XRES
15
I/O
I
P2[0]
16
IOH
I
P0[0]
17
IOH
I
P0[2]
18
IOH
I
P0[4]
19
IOH
I
P0[6]
20
Power
Vdd
1
18
17
2
3
QFN
16
4
(Top View)
15
5
14
6
13
P0[4], AI
P0[2], AI
P0[0], AI
P2[0], AI
XRES
P1[6], AI
Active high external reset with
internal pull down
Supply voltage
IOH
I
P0[7]
22
IOH
I
P0[5]
23
IOH
I
P0[3]
Integrating input
24
IOH
I
P0[1]
Integrating input
Vss
Center pad must be connected
to ground
Power
AI, P2[1]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
Optional external clock input
(EXTCLK)
21
CP
AI, XOut, P2[5]
AI, XIn, P2[3]
19
IOHR
21
4
20
Crystal input (XIn)
P2[1]
11
12
P2[3]
I
22
I
I/O
9
I/O
3
10
2
AI, DATA2, I2C SDA, SPI CLK, P1[0]
AI, P1[2]
AI, EXTCLK, P1[4]
Crystal output (XOut)
P0[1], AI
P0[3], AI
P0[5], AI
P0[7], AI
Vdd
P0[6], AI
P2[5]
24
I
23
I/O
8
1
Figure 3. CY8C20336, CY8C20346 PSoC Device
7
Description
AI, CLK2, I2C SCL
SPI MOSI, P1[1]
NC
Vss
Type
Pin
No. Digital Analog Name
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Note
3. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
must be electrically floated and not connected to any other signal.
Document Number: 001-12696 Rev. *F
Page 9 of 39
[+] Feedback
CY8C20X36/46/66/96
24-Pin QFN with USB
Table 4. Pin Definitions - CY8C20396 PSoC Device [2, 3]
Name
Description
1
I/O
I
P2[5]
2
I/O
I
P2[3]
3
I/O
I
P2[1]
4
IOHR
I
P1[7]
I2C SCL, SPI SS
5
IOHR
I
P1[5]
I2C SDA, SPI MISO
6
IOHR
I
P1[3]
SPI CLK
ISSP CLK, I2C SCL, SPI MOSI
VSS
Ground
9
I/O
I
D+
USB D+
10
I/O
I
D-
USB D-
VDD
Supply
12
11
IOHR
Power
I
P1[0]
ISSP DATA, I2C SDA
13
IOHR
I
P1[2]
14
IOHR
I
P1[4]
15
IOHR
I
16
RESET INPUT
Optional external clock input
(EXTCLK)
P1[6]
XRES
Active high external reset with
internal pull down
17
IOH
I
P0[0]
18
IOH
I
P0[2]
19
IOH
I
P0[4]
20
IOH
I
P0[6]
21
IOH
I
P0[7]
22
IOH
I
P0[5]
23
IOH
I
P0[3]
Integrating input
24
IOH
I
P0[1]
Integrating input
VSS
Thermal pad must be
connected to Ground
CP
Power
21
20
22
24
23
19
16
( Top View) 15
5
14
6
13
12
P1[1]
QFN
3
4
11
I
Power
18
17
2
9
IOHR
P2[1]
I2 C SCL, SPI SS, P1[7]
I2 C SDA, SPI MISO, P1[5]
SPI CLK, P1[3]
1
10
8
P2[5]
P2[3]
8
7
Figure 4. CY8C20396 PSoC Device
P0[1], AI
P0[3]
P0[5]
P0[7]
P0[6]
P0[4]
Analog
7
Type
Digital
P0[2]
P0[0]
XRES
P1[6]
P1[4] , EXTCLK
P1[2]
ISSP CLK, I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVDD
ISSP DATA, I2C SDA, P1[0]
Pin No.
LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output
Document Number: 001-12696 Rev. *F
Page 10 of 39
[+] Feedback
CY8C20X36/46/66/96
32-Pin QFN
Table 5. Pin Definitions - CY8C20436, CY8C20446,
CY8C20466 PSoC Device [2, 3]
Crystal output (XOut)
4
I/O
I
P2[3]
Crystal input (XIn)
5
I/O
I
P2[1]
6
I/O
I
P3[3]
7
I/O
I
P3[1]
8
IOHR
I
P1[7]
9
IOHR
I
P1[5]
I2C SDA, SPI MISO
10
IOHR
I
P1[3]
SPI CLK.
11
IOHR
I
P1[1]
ISSP CLK[1], I2C SCL, SPI MOSI.
12
Power
I2C SCL, SPI SS
Vss
Ground connection.
13
IOHR
I
P1[0]
ISSP DATA[1], I2C SDA., SPI CLK
14
IOHR
I
P1[2]
15
IOHR
I
P1[4]
16
IOHR
I
P1[6]
17
Input
XRES
18
I/O
I
P3[0]
19
I/O
I
P3[2]
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
28
Power
Vdd
29
IOH
I
P0[7]
30
IOH
I
P0[5]
31
IOH
I
AI, P0[1]
AI, P2[7]
AI, XOut, P2[5]
AI, XIn, P2[3]
AI, P2[1]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull down
1
2
3
4
5
6
7
8
P0 [4 ], AI
P0 [2 ], AI
P2[5]
26
25
I
QFN
(Top View)
24
23
22
21
20
19
18
17
15
16
I/O
AI, E XTCLK , P 1[4]
AI, P 1[6]
3
Integrating input
P0 [7 ], AI
Vd d
P0 [6 ], AI
P2[7]
28
27
I
13
14
P0[1]
I/O
30
29
I
2
AI, CLK4, I2C SCL, SPI MOSI, P1[1]
V ss
AI, DATA1, I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
Analog
IOH
Vss
P0 [3 ], AI
P0 [5 ], AI
Digital
1
Figure 5. CY8C20436, CY8C20446, CY8C20466 PSoC Device
32
31
Description
9
Name
10
11
12
Type
AI, I2C SDA , SP I MISO , P 1[5]
A I, SP I CLK , P 1[3]
Pin
No.
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[2], AI
P3[0], AI
XRES
Supply voltage
P0[3]
Integrating input
32
Power
Vss
Ground connection
CP
Power
Vss
Center pad must be connected to
ground
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *F
Page 11 of 39
[+] Feedback
CY8C20X36/46/66/96
32-Pin QFN (with USB)
Table 6. Pin Definitions - CY8C20496 PSoC Device [2, 3]
2
I/O
I
P2[5]
XTAL Out
3
I/O
I
P2[3]
XTAL In
4
I/O
I
P2[1]
5
IOHR
I
P1[7]
I2C SCL, SPI SS
6
IOHR
I
P1[5]
I2C SDA, SPI MISO
7
IOHR
I
P1[3]
SPI CLK
8
IOHR
I
P1[1]
TC CLK, I2C SCL, SPI MOSI
Ground Pin
I
I
D+
USB PHY
D-
USB PHY
11
12
Vdd
Power pin
13
IOHR
Power
I
P1[0]
TC DATA*, I2C SDA, SPI CLKI
14
IOHR
I
P1[2]
15
IOHR
I
P1[4]
16
IOHR
I
P1[6]
17
Input
XRES
18
I/O
I
P3[0]
19
I/O
I
P3[2]
20
I/O
I
P2[0]
21
I/O
I
P2[2]
22
I/O
I
P2[4]
23
I/O
I
P2[6]
24
IOH
I
P0[0]
25
IOH
I
P0[2]
26
IOH
I
P0[4]
27
IOH
I
P0[6]
28
Power
Vdd
29
IOH
I
P0[7]
30
IOH
I
P0[5]
31
IOH
I
P0[3]
32
Power
Vss
EXTCLK
Active high external reset with
internal pull down
32
31
30
29
15
16
10
AI, E XTCLK, P1[4]
AI, P1[6]
VSS
SPI CLK , P1[3]
TC CLK, I2C SCL, SPI MOSI,P1[ 1]
QFN
( Top View)
24
23
22
21
20
19
18
17
13
14
Power
XTAL IN , P2[ 3]
AI , P2[ 1]
I2C SCL, SPI SS, P 1[ 7]
I2C SDA, SPI MISO , P1[ 5]
1
2
3
4
5
6
7
8
10
11
12
9
AI , P0[ 1]
XTAL OUT, P 2[ 5]
P0[4], AI
P0[2], AI
P0[1]
26
25
I
28
27
IOH
Vss
P0[3], AI
P0[5], AI
1
P0[7], AI
Vdd
P0[6], AI
Figure 5. CY8C20496 PSoC Device
Description
USB PHY DVdd
TC, DATA1 , I2C SDA, SPI CLK, P1[0]
AI, P1[2]
Name
Analog
9
Type
Digital
Vss
USB PHY, D+
Pin
No.
P0[0] , AI
P2[6] , AI
P2[4] , AI
P2[2] , AI
P2[0] , AI
P3[2] , AI
P3[0] , AI
XRES
Power Pin
Ground Pin
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *F
Page 12 of 39
[+] Feedback
CY8C20X36/46/66/96
48-Pin SSOP
Analog
Digital
Pin No.
Table 7. Pin Definitions - CY8C20536, CY8C20546,
and CY8C20566 PSoC Device[2]
Figure 6. CY8C20536, CY8C20546, and CY8C20566 PSoC Device
Name
Description
1
IOH
I
P0[7]
2
IOH
I
P0[5]
3
IOH
I
P0[3]
4
IOH
I
P0[1]
5
I/O
I
P2[7]
6
I/O
I
P2[5]
XTAL Out
7
I/O
I
P2[3]
XTAL In
8
I/O
I
P2[1]
9
NC
No connection
10
NC
No connection
11
I/O
I
P4[3]
12
I/O
I
P4[1]
14
I/O
I
P3[7]
15
I/O
I
P3[5]
16
I/O
I
P3[3]
17
I/O
I
P3[1]
13
NC
No connection
18
NC
No connection
19
NC
No connection
I2C SCL, SPI SS
20
IOHR I
P1[7]
21
IOHR I
P1[5]
I2C SDA, SPI MISO
22
IOHR I
P1[3]
SPI CLK
23
IOHR I
P1[1]
TC CLK[1], I2C SCL, SPI MOSI
24
VSS
Ground Pin
25
IOHR I
P1[0]
TC DATA[1], I2C SDA, SPI CLK
26
IOHR I
P1[2]
27
IOHR I
P1[4]
28
IOHR I
P1[6]
AI, P0[7]
AI, P0[5]
AI, P0[3]
AI P0[1]
AI, P2[7]
XTALOUT, P2[5]
XTALIN, P2[3]
AI, P2[1]
NC
NC
AI, P4[3]
AI, P4[1]
NC
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
NC
NC
I2C SCL, SPI SS, P1[7]
I2C SDA, SPI MISO, P1[5]
SPI CLK, P1[3]
TC CLK, I2C SCL, SPI MOSI, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD
P0[6], AI
P0[4], AI
P0[2], AI
P0[0], AI
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P3[6], AI
P3[4], AI
P3[2], AI
P3[0], AI
XRES
NC
NC
NC
NC
NC
NC
P1[6], AI
P1[4], EXT CLK
P1[2], AI
P1[0], TC DATA, I2C SDA, SPI CLK
EXT CLK
No connection
31
NC
No connection
32
NC
No connection
Analog
No connection
NC
Digital
NC
30
Pin No.
29
Name
33
NC
No connection
41
I/O
I
P2[2]
34
NC
No connection
42
I/O
I
P2[4]
35
XRES
Active high external reset with internal 43
pull down
I/O
I
P2[6]
36
I/O
I
P3[0]
44
IOH I
P0[0]
37
I/O
I
P3[2]
45
IOH I
P0[2]
38
I/O
I
P3[4]
46
IOH I
P0[4]
39
I/O
I
P3[6]
47
IOH I
P0[6]
40
I/O
I
P2[0]
48
Power
Vdd
Description
Power Pin
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option.
Document Number: 001-12696 Rev. *F
Page 13 of 39
[+] Feedback
CY8C20X36/46/66/96
48-Pin QFN
Table 8. Pin Definitions - CY8C20636 PSoC Device [2, 3]
Crystal output (XOut)
4
I/O
I
P2[3]
Crystal input (XIn)
5
I/O
I
P2[1]
6
I/O
I
P4[3]
7
I/O
I
P4[1]
8
I/O
I
P3[7]
9
I/O
I
P3[5]
10
I/O
I
P3[3]
11
I/O
I
P3[1]
12
IOHR
I
P1[7]
13
IOHR
I
P1[5]
I2C SDA, SPI MISO
NC
No connection
15
NC
No connection
IOHR
I
P1[3]
SPI CLK
17
IOHR
I
P1[1]
ISSP CLK[1], I2C SCL, SPI MOSI
Vss
Ground connection
Power
19
Vdd
Supply voltage
22
IOHR
I
P1[0]
ISSP DATA[1], I2C SDA, SPI CLK
23
IOHR
I
P1[2]
24
IOHR
I
P1[4]
25
IOHR
I
P1[6]
26
P2[6] , AI
P2[4] ,AI
P2[2] ,AI
P2[0] ,AI
P4[2] ,AI
P4[0] ,AI
P3[6] ,AI
P3[4] , AI
P3[2] ,AI
P3[0 ] , AI
XRES
P1[6] , AI
DNU
Power
Input
XRES
27
I/O
I
P3[0]
28
I/O
I
P3[2]
29
I/O
I
P3[4]
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull down
Pin
No.
IOH
Analog
20
21
QFN
( Top View)
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
DNU
Digital
18
P0[1], AI
I2C SCL, SPI SS
16
1
2
3
4
5
6
I2C SDA, SPI MISO, A I, P1[5]
14
NC
AI , P2[7]
AI , XOut, P2[5]
AI , XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI , P3[7]
AI , P3[5]
AI , P3[3]
AI P3[1]
AI, I2 C SCL, SPI SS, P1[7]
P0[2], AI
P0[0], AI
P2[5]
Vdd
P0[6], AI
P0[4], AI
I
42
41
40
39
38
37
I/O
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
NC
NC
3
No connection
46
45
44
43
P2[7]
NC
48
47
I
Description
13
14
15
16
17
18
19
20
21
22
23
24
Analog
I/O
1
Name
NC
NC
SPI CLK, A I, P1[3]
AI, CLK6 , I2C SCL, SPI MOSI, P1[1]
Vss
DNU
DNU
Vdd
AI, DATA1, I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
AI, EXTCLK, P1[4]
Digital
Figure 7. CY8C20636 PSoC Device
2
Pin
No.
Name
I
P0[6]
Description
30
I/O
I
P3[6]
40
31
I/O
I
P4[0]
41
Vdd
Supply voltage
32
I/O
I
P4[2]
42
NC
No connection
33
I/O
I
P2[0]
43
NC
No connection
34
I/O
I
P2[2]
44
IOH
I
P0[7]
35
I/O
I
P2[4]
45
IOH
I
P0[5]
36
I/O
I
P2[6]
46
IOH
I
P0[3]
Integrating input
37
IOH
I
P0[0]
47
Vss
Ground connection
38
IOH
I
P0[2]
48
39
IOH
I
P0[4]
CP
Power
Power
IOH
I
Power
P0[1]
Vss
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *F
Page 14 of 39
[+] Feedback
CY8C20X36/46/66/96
48-Pin QFN with USB
Table 9. Pin Definitions - CY8C20646, CY8C20666 PSoC Device [2, 3]
I/O
I
P2[5]
Crystal output (XOut)
4
I/O
I
P2[3]
Crystal input (XIn)
5
I/O
I
P2[1]
6
I/O
I
P4[3]
7
I/O
I
P4[1]
8
I/O
I
P3[7]
9
I/O
I
P3[5]
10
I/O
I
P3[3]
11
I/O
I
P3[1]
12
IOHR
I
P1[7]
13
IOHR
I
P1[5]
I2C SDA, SPI MISO
NC
No connection
No connection
IOHR
I
P1[3]
SPI CLK
17
IOHR
I
P1[1]
ISSP CLK[1], I2C SCL, SPI MOSI
Vss
Ground connection
19
I/O
D+
USB D+
20
I/O
D-
USB D-
Vdd
Supply voltage
ISSP DATA[1], I2C SDA, SPI CLK
21
Power
Power
22
IOHR
I
P1[0]
23
IOHR
I
P1[2]
24
IOHR
I
P1[4]
25
IOHR
I
P1[6]
26
Input
XRES
27
I/O
I
P3[0]
28
I/O
I
P3[2]
29
I/O
I
P3[4]
P0[1], AI
48
47
46
45
44
43
36
35
34
33
32
31
30
29
28
27
26
25
QFN
(Top View)
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
I2C SDA, SPI MISO, A I, P1[5]
NC
16
18
3
4
5
6
P2[6], AI
P2[4],AI
P2[2],AI
P2[0],AI
P4[2], AI
P4[0],AI
P3[6],AI
P3[4], AI
P3[2], AI
P3[0 ], AI
XRES
P1[6], AI
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull down
Pin
No.
IOH
Analog
15
1
2
I2C SCL, SPI SS
Digital
14
NC
AI , P2[7]
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI, P4[3]
AI, P4[1]
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
P0[2], AI
P0[0], AI
3
No connection
Vdd
P0[6], AI
P0[4], AI
P2[7]
NC
42
41
40
39
38
37
I
Description
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
NC
NC
Analog
I/O
1
Name
NC
NC
SPI CLK, A I, P1[3]
AI, CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVdd
AI, DATA1, I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
AI, EXTCLK, P1[4]
Digital
Figure 8. CY8C20646, CY8C20666 PSoC Device
2
Pin
No.
Name
I
P0[6]
Description
30
I/O
I
P3[6]
40
31
I/O
I
P4[0]
41
Vdd
Supply voltage
32
I/O
I
P4[2]
42
NC
No connection
33
I/O
I
P2[0]
43
NC
No connection
34
I/O
I
P2[2]
44
IOH
I
P0[7]
35
I/O
I
P2[4]
45
IOH
I
P0[5]
36
I/O
I
P2[6]
46
IOH
I
P0[3]
Integrating input
37
IOH
I
P0[0]
47
Vss
Ground connection
38
IOH
I
P0[2]
48
39
IOH
I
P0[4]
CP
Power
Power
IOH
I
Power
P0[1]
Vss
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Document Number: 001-12696 Rev. *F
Page 15 of 39
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CY8C20X36/46/66/96
48-Pin QFN OCD
The 48-pin QFN part is for the CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit
debugging.[4]
Table 10. Pin Definitions - CY8C20066 PSoC Device [2, 3]
3
I/O
I
P2[5]
Crystal output (XOut)
4
I/O
I
P2[3]
Crystal input (XIn)
5
I/O
I
P2[1]
6
I/O
I
P4[3]
7
I/O
I
P4[1]
8
I/O
I
P3[7]
9
I/O
I
P3[5]
10
I/O
I
P3[3]
11
I/O
I
P3[1]
12
IOHR
I
P1[7]
I2C SCL, SPI SS
13
IOHR
I
P1[5]
I2C SDA, SPI MISO
HCLK
OCD high speed clock output
16
IOHR
I
P1[3]
SPI CLK.
17
IOHR
I
P1[1]
ISSP CLK[1], I2C SCL, SPI MOSI
18
Vss
Ground connection
19
I/O
D+
USB D+
20
I/O
D-
USB D-
Vdd
Supply voltage
ISSP DATA(1), I2C SDA, SPI CLK
21
Power
Power
22
IOHR
I
P1[0]
23
IOHR
I
P1[2]
24
IOHR
I
P1[4]
25
IOHR
I
P1[6]
26
Input
XRES
Optional external clock input
(EXTCLK)
Active high external reset with
internal pull down
P0[1], AI
QFN
(Top View)
13
14
15
16
17
18
19
20
21
22
23
24
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
P2[6], AI
P2[4], AI
P2[2], AI
P2[0], AI
P4[2], AI
P4[0], AI
P3[6], AI
P3[4], AI
P3[2], AI
P3[0], AI
XRES
P1[6], AI
I2C SDA, SPI MISO, AI, P1[5]
CCLK
HCLK
SPI CLK, A I, P1[3]
AI, CLK6, I2C SCL, SPI MOSI, P1[1]
Vss
D+
DVdd
AI, DATA1, I2C SDA, SPI CLK, P1[0]
AI, P 1[2]
AI, EXTCLK, P1[4]
OCD CPU clock output
15
3
4
5
6
Pin
No.
Analog
CCLK
1
2
Digital
14
OCDO
A E
, P2[7]
I
AI, XOut, P2[5]
AI, XIn , P2[3]
AI , P2[1]
AI , P4[3]
AI , P4[1]
AI, P3[7]
AI, P3[5]
AI, P3[3]
AI, P3[1]
AI, I2C SCL, SPI SS, P1[7]
48
47
46
45
44
43
OCD mode direction pin
P0[2], AI
P0[0], AI
P2[7]
OCDOE
OCDO
Vdd
P0[6], AI
P0[4], AI
I
Description
42
41
40
39
38
37
Analog
I/O
1
Name
Vss
P0[3], AI
P0[5 ], AI
P0[7], AI
OCDE
Digital
Figure 9. CY8C20066 PSoC Device
2
Pin
No.
37
IOH
I
P0[0]
38
IOH
I
P0[2]
39
IOH
I
P0[4]
IOH
I
P0[6]
Name
Description
27
I/O
I
P3[0]
40
28
I/O
I
P3[2]
41
29
I/O
I
P3[4]
42
30
I/O
I
P3[6]
43
31
I/O
I
P4[0]
44
IOH
I
P0[7]
32
I/O
I
P4[2]
45
IOH
I
P0[5]
33
I/O
I
P2[0]
46
IOH
I
P0[3]
Integrating input
34
I/O
I
P2[2]
47
Vss
Ground connection
35
I/O
I
P2[4]
48
36
I/O
I
P2[6]
CP
Power
Power
IOH
Power
I
Vdd
Supply voltage
OCDO
OCD even data I/O
OCDE
OCD odd data output
P0[1]
Vss
Center pad must be connected to ground
LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output.
Note
4. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes.
Document Number: 001-12696 Rev. *F
Page 16 of 39
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CY8C20X36/46/66/96
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C20x36/46/66/96 PSoC devices. For the latest electrical
specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc.
Figure 10. Voltage versus CPU Frequency
Figure 11. IMO Frequency Trim Options
5.5V
5.5V
Vdd Voltage
Vdd Voltage
l id g
Va ratin n
pe io
O Reg
1.71V
SLIMO
Mode
= 01
SLIMO
Mode
= 00
SLIMO
Mode
= 10
1.71V
750 kHz
3 MHz
750 kHz
24 MHz
3 MHz
6 MHz 12 MHz 24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this section.
Table 11. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
°C
degree Celsius
mA
milli-ampere
dB
decibels
ms
milli-second
fF
femto farad
mV
milli-volts
Hz
hertz
nA
nanoampere
KB
1024 bytes
ns
nanosecond
Kbit
1024 bits
nV
nanovolts
kHz
kilohertz
Ω
ohm
ksps
kilo samples per second
pA
picoampere
kΩ
kilohm
pF
picofarad
MHz
megahertz
pp
peak-to-peak
MΩ
megaohm
ppm
parts per million
μA
microampere
ps
picosecond
μF
microfarad
sps
samples per second
μH
microhenry
s
sigma: one standard deviation
μs
microsecond
V
volts
μW
microwatts
Document Number: 001-12696 Rev. *F
Page 17 of 39
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CY8C20X36/46/66/96
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 12. Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Typ
Max
Units
Higher storage temperatures reduces data
retention time. Recommended Storage
Temperature is +25°C ± 25°C. Extended
duration storage temperatures above 85oC
degrades reliability.
–55
+25
+125
°C
–0.5
–
+6.0
V
TSTG
Storage Temperature
Vdd
Supply Voltage Relative to Vss
VIO
DC Input Voltage
Vss – 0.5
–
Vdd + 0.5
V
VIOZ
DC Voltage Applied to Tri-state
Vss –0.5
–
Vdd + 0.5
V
IMIO
Maximum Current into any Port Pin
ESD
Electro Static Discharge Voltage
Human Body Model ESD
LU
Latch up Current
In accordance with JESD78 standard
–25
–
+50
mA
2000
–
–
V
–
–
200
mA
Min
Typ
Max
Units
–40
–
+85
°C
–40
–
+100
°C
Operating Temperature
Table 13. Operating Temperature
Symbol
Description
TA
Ambient Temperature
TJ
Operational Die Temperature
Document Number: 001-12696 Rev. *F
Conditions
The temperature rise from ambient to junction
is package specific. Refer the table Thermal
Impedances per Package on page 34. The
user must limit the power consumption to
comply with this requirement.
Page 18 of 39
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CY8C20X36/46/66/96
DC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 14. DC Chip-Level Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
1.71
–
5.5
V
Conditions are Vdd <= 3.0V, TA = 25°C,
CPU = 24 MHz. CapSense running at 12
MHz, no I/O sourcing current
–
2.88
4.0
mA
Supply Current, IMO = 12 MHz
Conditions are Vdd <= 3.0V, TA = 25°C,
CPU = 12 MHz. CapSense running at 12
MHz, no I/O sourcing current
–
1.71
2.6
mA
IDD6
Supply Current, IMO = 6 MHz
Conditions are Vdd <= 3.0V, TA = 25°C,
CPU = 6 MHz. CapSense running at 6 MHz,
no I/O sourcing current
–
1.16
1.8
mA
ISB0
Deep Sleep Current
Vdd <= 3.0V, TA = 25°C, I/O regulator turned
off
–
0.1
–
μA
ISB1
Standby Current with POR, LVD and Vdd <= 3.0V, TA = 25°C, I/O regulator turned
Sleep Timer
off
–
1.07
1.5
μA
Vdd[5]
Supply Voltage
Refer the table DC POR and LVD
Specifications on page 24
IDD24
Supply Current, IMO = 24 MHz
IDD12
DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0V to 5.5V and
–40°C ≤ TA ≤ 85°C, 2.4V to 3.0V and –40°C ≤ TA ≤ 85°C, or 1.71V to 2.4V and –40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V and 3.3V at 25°C and are for design guidance only.
Table 15. 3.0V to 5.5V DC GPIO Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
RPU
Pull up Resistor
4
5.6
8
kΩ
VOH1
High Output Voltage
Port 2 or 3 Pins
IOH < 10 μA, maximum of 10 mA source
current in all IOs
Vdd - 0.2
–
–
V
VOH2
High Output Voltage
Port 2 or 3 Pins
IOH = 1 mA, maximum of 20 mA source
current in all IOs
Vdd - 0.9
–
–
V
VOH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH < 10 μA, maximum of 10 mA source
current in all IOs
Vdd - 0.2
–
–
V
VOH4
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 5 mA, maximum of 20 mA source
current in all IOs
Vdd - 0.9
–
–
V
VOH5
High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH < 10 μA, Vdd > 3.1V, maximum of
4 IOs all sourcing 5 mA
2.85
3.00
3.3
V
VOH6
High Output Voltage
Port 1 Pins with LDO Regulator
Enabled for 3V Out
IOH = 5 mA, Vdd > 3.1V, maximum of
20 mA source current in all IOs
2.20
–
–
V
VOH7
IOH < 10 μA, Vdd > 2.7V, maximum of
High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs
Out
2.35
2.50
2.75
V
VOH8
IOH = 2 mA, Vdd > 2.7V, maximum of
High Output Voltage
Port 1 Pins with LDO Enabled for 2.5V 20 mA source current in all IOs
Out
1.90
–
–
V
Note
5. When Vdd remains in the range from 1.71V to 1.9V for more than 50 usec, the slew rate when moving from the 1.71V to 1.9V range to greater than 2V must be
slower than 1V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the TRAMP parameter.
Document Number: 001-12696 Rev. *F
Page 19 of 39
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CY8C20X36/46/66/96
Table 15. 3.0V to 5.5V DC GPIO Specifications (continued)
Symbol
Description
Conditions
Min
Typ
Max
Units
VOH9
High Output Voltage
IOH < 10 μA, Vdd > 2.7V, maximum of
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
1.60
1.80
2.1
V
VOH10
High Output Voltage
IOH = 1 mA, Vdd > 2.7V, maximum of
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
1.20
–
–
V
VOL
Low Output Voltage
–
–
0.75
V
VIL
Input Low Voltage
–
–
0.80
V
2.00
–
–
80
–
mV
–
0.001
1
μA
0.5
1.7
5
pF
VIH
Input High Voltage
VH
Input Hysteresis Voltage
IIL
Input Leakage (Absolute Value)
CPIN
Pin Capacitance
Document Number: 001-12696 Rev. *F
IOL = 25 mA, Vdd > 3.3V, maximum of
60 mA sink current on even port pins (for
example, P0[2] and P1[4]) and 60 mA sink
current on odd port pins (for example, P0[3]
and P1[5])
Package and pin dependent
Temp = 25°C
V
Page 20 of 39
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CY8C20X36/46/66/96
Table 16. 2.4V to 3.0V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
4
5.6
8
kΩ
IOH < 10 μA, maximum of 10 mA
source current in all IOs
Vdd - 0.2
–
–
V
High Output Voltage
Port 2 or 3 Pins
IOH = 0.2 mA, maximum of 10 mA
source current in all IOs
Vdd - 0.4
–
–
V
VOH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH < 10 μA, maximum of 10 mA
source current in all IOs
Vdd - 0.2
–
–
V
VOH4
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all IOs
Vdd - 0.5
–
–
V
VOH5A
IOH < 10 μA, Vdd > 2.4V, maximum of
High Output Voltage
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
1.50
1.80
2.1
V
VOH6A
High Output Voltage
IOH = 1 mA, Vdd > 2.4V, maximum of
Port 1 Pins with LDO Enabled for 1.8V 20 mA source current in all IOs
Out
1.20
–
–
V
VOL
Low Output Voltage
–
–
0.75
V
VIL
Input Low Voltage
–
–
0.72
V
VIH
Input High Voltage
1.4
–
VH
Input Hysteresis Voltage
–
80
–
mV
IIL
Input Leakage (Absolute Value)
CPIN
Capacitive Load on Pins
RPU
Pull up Resistor
VOH1
High Output Voltage
Port 2 or 3 Pins
VOH2
Conditions
IOL = 10 mA, maximum of 30 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
Package and pin dependent
Temp = 25oC
V
–
0.001
1
μA
0.5
1.7
5
pF
Min
Typ
Max
Units
Table 17. 1.71V to 2.4V DC GPIO Specifications
Symbol
Description
Conditions
RPU
Pull up Resistor
4
5.6
8
kΩ
VOH1
High Output Voltage
Port 2 or 3 Pins
IOH = 10 μA, maximum of 10 mA
source current in all I/Os
Vdd - 0.2
–
–
V
VOH2
High Output Voltage
Port 2 or 3 Pins
IOH = 0.5 mA, maximum of 10 mA
source current in all I/Os
Vdd - 0.5
–
–
V
VOH3
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 100 μA, maximum of 10 mA
source current in all I/Os
Vdd - 0.2
–
–
V
VOH4
High Output Voltage
Port 0 or 1 Pins with LDO Regulator
Disabled for Port 1
IOH = 2 mA, maximum of 10 mA source
current in all I/Os
Vdd - 0.5
–
–
V
VOL
Low Output Voltage
IOL = 5 mA, maximum of 20 mA sink
current on even port pins (for example,
P0[2] and P1[4]) and 30 mA sink
current on odd port pins (for example,
P0[3] and P1[5])
–
–
0.4
V
VIL
Input Low Voltage
–
–
0.3 x Vdd
VIH
Input High Voltage
0.65 x Vdd
–
Document Number: 001-12696 Rev. *F
V
V
Page 21 of 39
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CY8C20X36/46/66/96
Table 17. 1.71V to 2.4V DC GPIO Specifications (continued)
Symbol
Description
Conditions
Min
Typ
Max
Units
VH
Input Hysteresis Voltage
–
80
–
mV
IIL
Input Leakage (Absolute Value)
–
0.001
1
μA
CPIN
Capacitive Load on Pins
0.5
1.7
5
pF
Package and pin dependent
Temp = 25oC
Table 18.DC Characteristics – USB Interface
Symbol
Min
Typ
Max
Units
USB D+ Pull Up Resistance
With idle bus
0.900
-
1.575
kΩ
Rusba
USB D+ Pull Up Resistance
While receiving traffic
1.425
-
3.090
kΩ
Vohusb
Static Output High
2.8
-
3.6
V
-
0.3
Rusbi
Description
Conditions
Volusb
Static Output Low
Vdi
Differential Input Sensitivity
0.2
-
Vcm
Differential Input Common Mode
Range
0.8
-
2.5
Vse
Single Ended Receiver Threshold
0.8
Cin
Transceiver Capacitance
Iio
Hi-Z State Data Line Leakage
Rps2
PS/2 Pull Up Resistance
Rext
External USB Series Resistor
On D+ or D- line
In series with each USB pin
V
V
V
-
2.0
V
-
50
pF
-10
-
+10
μA
3
5
7
kΩ
21.78
22.0
22.22
Ω
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 19. DC Analog Mux Bus Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
RSW
Switch Resistance to Common Analog
Bus
–
–
800
Ω
RGND
Resistance of Initialization Switch to
Vss
–
–
800
Ω
The maximum pin voltage for measuring RSW and RGND is 1.8V
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 20. DC Comparator Specifications
Symbol
Description
Conditions
Min
Typ
Max
Units
0.0
–
1.8
V
VLPC
Low Power Comparator (LPC)
common mode
ILPC
LPC supply current
–
10
40
μA
VOSLPC
LPC voltage offset
–
2.5
30
mV
Document Number: 001-12696 Rev. *F
Maximum voltage limited to Vdd
Page 22 of 39
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CY8C20X36/46/66/96
Comparator User Module Electrical Specifications
The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the
entire device voltage and temperature operating range: –40°C <= TA <= 85°C, 1.71V <= Vdd <= 5.5V.
Table 21. Comparator User Module Electrical Specifications
Symbol
TCOMP
Description
Comparator Response Time
Conditions
Min
50 mV overdrive
Offset
Max
Units
70
100
ns
2.5
30
mV
Average DC current, 50 mV
overdrive
20
80
µA
Supply voltage >2V
Power Supply Rejection Ratio
80
Supply voltage <2V
Power Supply Rejection Ratio
Current
PSRR
Typ
Input
Range
dB
40
0
dB
1.5
V
Max
Units
Vss
1.3
V
5
pF
8
10
Bits
ADC Electrical Specifications
Table 22. ADC User Module Electrical Specifications
Symbol
Description
Conditions
Min
Typ
Input
VIN
Input Voltage Range
This gives 72% of maximum
code
CIN
Input Capacitance
RES
Resolution
Settings 8, 9, or 10
S8
8-Bit Sample Rate
Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data clock)
23.4375
ksps
S10
10-Bit Sample Rate
Data Clock set to 6 MHz.
Sample Rate = 0.001/
(2^Resolution/Data clock)
5.859
ksps
DC Accuracy
DNL[6]
INL
Eoffset
Differential Nonlinearity
For any configuration
-1
Integral Nonlinearity
For any configuration
-2
Offset Error
IADC
Operating Current
FCLK
Data Clock
PSRR
Power Supply Rejection Ration
0
Source is chip’s internal main
oscillator. See device data
sheet for accuracy.
RIN
LSB
+2
LSB
15
90
mV
275
350
μA
12
MHz
2.25
PSRR (Vdd>3.0V)
24
dB
PSRR (2.2 < Vdd < 3.0)
30
dB
PSRR (2.0 < Vdd < 2.2)
12
dB
0
dB
PSRR (Vdd < 2.0)
Egain
+2
Gain Error
For any resolution
Input Resistance
Equivalent switched cap input
resistance for 8-, 9-, or 10-bit
resolution.
1
1/(500fF*
Data-Clock)
1/(400fF*
Data-Clock)
5
%FSR
1/(300fF*
Data-Clock)
Ω
Note
6. Monotonicity is not guaranteed.
Document Number: 001-12696 Rev. *F
Page 23 of 39
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CY8C20X36/46/66/96
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 23. DC POR and LVD Specifications
Symbol
Description
VPPOR0
VPPOR1
VPPOR2
VPPOR3
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b, HPOR = 0
PORLEV[1:0] = 00b, HPOR = 1
PORLEV[1:0] = 01b, HPOR = 1
PORLEV[1:0] = 10b, HPOR = 1
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Conditions
Min
Typ
Max
Units
Vdd must be greater than or equal to
1.71V during startup, reset from the XRES
pin, or reset from watchdog.
1.61
1.66
2.36
2.60
2.82
1.71
2.41
2.66
2.95
V
V
V
V
2.45
2.71
2.92
3.02
3.13
1.90
1.80
4.73
2.51
2.78
2.99
3.09
3.20
2.32
1.84
4.83
V
V
V
V
V
V
V
V
–
2.40[7]
2.64[8]
2.85[9]
2.95
3.06
1.84
1.75[10]
4.62
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 24. DC Programming Specifications
Symbol
Description
Conditions
VddIWRITE Supply Voltage for Flash Write
Operations
Min
Typ
Max
Units
1.71
–
5.25
V
–
5
25
mA
IDDP
Supply Current During
Programming or Verify
VILP
Input Low Voltage During
Programming or Verify
See the appropriate DC General Purpose
IO Specifications on page 19
–
–
VIL
V
VIHP
Input High Voltage During
Programming or Verify
See appropriate DC General Purpose IO
Specifications on page 19 table on pages
15 or 16
VIH
–
–
V
IILP
Input Current when Applying Vilp Driving internal pull down resistor
to P1[0] or P1[1] During
Programming or Verify
–
–
0.2
mA
IIHP
Input Current when Applying Vihp Driving internal pull down resistor
to P1[0] or P1[1] During
Programming or Verify
–
–
1.5
mA
VOLP
Output Low Voltage During
Programming or Verify
–
–
Vss + 0.75
V
VOHP
Output High Voltage During
Programming or Verify
VOH
–
Vdd
V
50,000
–
–
-
10
20
–
Years
See appropriate DC General Purpose IO
Specifications on page 19 table on page
16. For Vdd > 3V use VOH4 in Table 13 on
page 18.
FlashENPB Flash Write Endurance
Erase/write cycles per block
FlashDR
Following maximum Flash write cycles;
ambient temperature of 55°C
Flash Data Retention
Notes
7. Always greater than 50 mV above VPPOR1 voltage for falling supply.
8. Always greater than 50 mV above VPPOR2 voltage for falling supply.
9. Always greater than 50 mV above VPPOR3 voltage for falling supply.
10. Always greater than 50 mV above VPPOR0 voltage for falling supply.
Document Number: 001-12696 Rev. *F
Page 24 of 39
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CY8C20X36/46/66/96
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 25. AC Chip-Level Specifications
Min
Typ
Max
Units
FCPU
Symbol
CPU Frequency
Description
Conditions
5.7
–
25.2
MHz
F32K1
Internal Low Speed Oscillator Frequency
19
32
50
kHz
FIMO24
Internal Main Oscillator Frequency at 24
MHz Setting
22.8
24
25.2
MHz
FIMO12
Internal Main Oscillator Frequency at 12
MHz Setting
11.4
12
12.6
MHz
FIMO6
Internal Main Oscillator Frequency at 6
MHz Setting
5.7
6.0
6.3
MHz
DCIMO
Duty Cycle of IMO
40
50
60
%
TRAMP
Supply Ramp Time
20
–
–
μs
TXRST
External Reset Pulse Width at Power Up After supply voltage is valid
1
ms
TXRST2
External Reset Pulse Width after Power Applies after part has booted
Up[11]
10
μs
Note
11. The minimum required XRES pulse length is longer when programming the device (see Table 32 on page 28).
Document Number: 001-12696 Rev. *F
Page 25 of 39
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CY8C20X36/46/66/96
AC General Purpose IO Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 26. AC GPIO Specifications
Symbol
FGPIO
TRise23
TRise23L
TRise01
TRise01L
TFall
TFallL
Description
GPIO Operating Frequency
Conditions
Normal Strong Mode Port 0, 1
Rise Time, Strong Mode, Cload = 50 pF
Ports 2 or 3
Rise Time, Strong Mode Low Supply,
Cload = 50 pF, Ports 2 or 3
Rise Time, Strong Mode, Cload = 50 pF
Ports 0 or 1
Rise Time, Strong Mode Low Supply,
Cload = 50 pF, Ports 0 or 1
Fall Time, Strong Mode, Cload = 50 pF
All Ports
Fall Time, Strong Mode Low Supply,
Cload = 50 pF, All Ports
Min
0
Typ
–
0
–
Vdd = 3.0 to 3.6V, 10% – 90%
15
Vdd = 1.71 to 3.0V, 10% – 90%
Max
Units
6 MHz for
MHz
1.71V<Vdd<2.4V
–
12 MHz for
2.4V<Vdd<5.5V
80
ns
15
–
80
ns
Vdd = 3.0 to 3.6V, 10% – 90%
LDO enabled or disabled
Vdd = 1.71 to 3.0V, 10% – 90%
LDO enabled or disabled
Vdd = 3.0 to 3.6V, 10% – 90%
10
–
50
ns
10
–
80
ns
10
–
50
ns
Vdd = 1.71 to 3.0V, 10% – 90%
10
–
70
ns
Figure 12. GPIO Timing Diagram
90%
GPIO Pin
Output
Voltage
10%
TRise23
TRise01
TRise23L
TRise01L
Document Number: 001-12696 Rev. *F
TFall
TFallL
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CY8C20X36/46/66/96
Table 27.AC Characteristics – USB Data Timings
Min
Typ
Max
Units
Tdrate
Symbol
Full speed data rate
Description
Average bit rate
Conditions
12–0.25%
12
12 + 0.25%
MHz
Tdjr1
Receiver data jitter tolerance
To next transition
-18.5
–
18.5
ns
Tdjr2
Receiver data jitter tolerance
To pair transition
-9
–
9
ns
Tudj1
Driver differential jitter
To next transition
-3.5
–
3.5
ns
Tudj2
Driver differential jitter
To pair transition
-4.0
–
4.0
ns
Tfdeop
Source jitter for differential
transition
To SE0 transition
-2
–
5
ns
175
ns
Tfeopt
Source SE0 interval of EOP
160
–
Tfeopr
Receiver SE0 interval of EOP
82
–
Tfst
Width of SE0 interval during
differential transition
ns
–
14
ns
Min
Typ
Max
Units
4
–
20
ns
Table 28.AC Characteristics – USB Driver
Symbol
Tr
Description
Conditions
Transition rise time
50 pF
Tf
Transition fall time
50 pF
TR
Rise/fall time matching
Vcrs
Output signal crossover voltage
4
–
20
ns
90.00
–
111.1
%
1.3
–
2.0
V
AC Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 29. AC Low Power Comparator Specifications
Symbol
TLPC
Description
Conditions
Min
Typ
Comparator Response Time, 50 50 mV overdrive does not include
mV Overdrive
offset voltage.
Max
Units
100
ns
AC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 30. AC Analog Mux Bus Specifications
Symbol
FSW
Description
Switch Rate
Conditions
Min
Typ
Max
Units
Maximum pin voltage when measuring
switch rate is 1.8Vp-p
–
–
6.3
MHz
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 31. AC External Clock Specifications
Min
Typ
Max
Units
FOSCEXT Frequency
Symbol
Description
Conditions
0.750
–
25.2
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Document Number: 001-12696 Rev. *F
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CY8C20X36/46/66/96
AC Programming Specifications
Figure 13. AC Waveform
SCLK (P1[1])
T RSCLK
T FSCLK
SDATA (P1[0])
TSSCLK
T HSCLK
TDSCLK
The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 32. AC Programming Specifications
Symbol
TRSCLK
TFSCLK
TSSCLK
THSCLK
FSCLK
TERASEB
TWRITE
TDSCLK
TDSCLK3
TDSCLK2
TXRST3
Description
Rise Time of SCLK
Fall Time of SCLK
Data Set up Time to Falling Edge of SCLK
Data Hold Time from Falling Edge of SCLK
Frequency of SCLK
Flash Erase Time (Block)
Flash Block Write Time
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
Data Out Delay from Falling Edge of SCLK
External Reset Pulse Width after Power Up
Document Number: 001-12696 Rev. *F
Conditions
3.6 < Vdd
3.0 ≤ Vdd ≤ 3.6
1.71 ≤ Vdd ≤ 3.0
Required to enter programming mode
when coming out of sleep
Min
1
1
40
40
0
–
–
–
–
–
263
Typ
–
–
–
–
–
–
–
–
–
–
–
Max
20
20
–
–
8
18
25
60
85
130
–
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ns
μs
Page 28 of 39
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CY8C20X36/46/66/96
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 33. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Description
FSCLI2C
SCL Clock Frequency
THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is
generated.
TLOWI2C
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
THIGHI2C
TSUSTAI2C Setup Time for a Repeated START Condition
THDDATI2C Data Hold Time
TSUDATI2C Data Setup Time
TSUSTOI2C Setup Time for STOP Condition
TBUFI2C
Bus Free Time Between a STOP and START Condition
TSPI2C[13] Pulse Width of spikes are suppressed by the input filter.
Standard
Mode
Min
Max
0
100
4.0
–
4.7
4.0
4.7
0
250
4.0
4.7
–
–
–
–
–
–
–
–
–
Fast Mode
Units
Min
0
0.6
Max
400
–
kHz
μs
1.3
0.6
0.6
0
100[12]
0.6
1.3
0
–
–
–
–
–
–
–
50
μs
μs
μs
μs
ns
μs
μs
ns
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Notes
12. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This automatically be the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
13. In I2C sleep mode, wherein the part can wake up from sleep when the address matches its own slave address, there is no glitch/spike filtering on SCL and SDA lines
on the 7-bit address + R/W bit. Once, the part wakes up there is glitch/spike filtering on SCL and SDA lines.
Document Number: 001-12696 Rev. *F
Page 29 of 39
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CY8C20X36/46/66/96
Table 34. SPI Master AC Specifications
Symbol
Description
FSCLK
SCLK clock frequency
DC
SCLK duty cycle
TSETUP
MISO to SCLK setup time
THOLD
SCLK to MISO hold time
TOUT_VAL
SCLK to MOSI valid time
TOUT_HIGH
MOSI high time
Conditions
Min
Typ
VDD ≥ 2.4V
VDD < 2.4V
Max
Units
6
3
MHz
50
VDD ≥ 2.4V
VDD < 2.4V
%
60
100
ns
40
ns
40
40
ns
ns
Table 35. SPI Slave AC Specifications
Symbol
Description
Conditions
Min
VDD ≥ 2.4V
VDD < 2.4V
Typ
Max
Units
12
6
MHz
FSCLK
SCLK clock frequency
TLOW
SCLK low time
41.67
ns
THIGH
SCLK high time
41.67
ns
TSETUP
MOSI to SCLK setup time
30
ns
THOLD
SCLK to MOSI hold time
50
ns
TSS_MISO
SS high to MISO valid
153
ns
TSCLK_MISO
SCLK to MISO valid
125
ns
TSS_HIGH
SS high time
50
ns
TSS_CLK
Time from SS low to first SCLK
2/SCLK
ns
TCLK_SS
Time from last SCLK to SS high
2/SCLK
ns
Document Number: 001-12696 Rev. *F
Page 30 of 39
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CY8C20X36/46/66/96
Packaging Information
This section illustrates the packaging specifications for the CY8C20x36/46/66/96 PSoC device, along with the thermal impedances
for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Figure 15. 16-pin QFN No E-pad 3x3mm Package Outline (Sawn)
001-09116 *D
Figure 16. 24-Pin (4x4 x 0.6 mm) QFN
001-13937 *B
Document Number: 001-12696 Rev. *F
Page 31 of 39
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CY8C20X36/46/66/96
Figure 17. 32-Pin (5x5 x 0.6 mm) QFN
001-42168 *C
Figure 18. 48-Pin (300 MIL) SSOP
.020
24
1
0.395
0.420
0.292
0.299
25
DIMENSIONS IN INCHES MIN.
MAX.
48
0.620
0.630
0.088
0.092
0.095
0.110
0.025
BSC
SEATING PLANE
0.005
0.010
.010
GAUGE PLANE
0.004
0.008
0.0135
Document Number: 001-12696 Rev. *F
0.008
0.016
0°-8°
0.024
0.040
51-85061 *C
Page 32 of 39
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CY8C20X36/46/66/96
Figure 19. 48-Pin (7x7 mm) QFN
001-13191 *D
Important Notes
■
For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
■
Pinned vias for thermal conduction are not required for the low power PSoC device.
Document Number: 001-12696 Rev. *F
Page 33 of 39
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CY8C20X36/46/66/96
Thermal Impedances
Table 36. Thermal Impedances per Package
Package
Typical θJA [14]
16 QFN
32.69oC/W
24 QFN[15]
20.90oC/W
32 QFN[15]
19.51oC/W
48 SSOP
69oC/W
48 QFN[15]
17.68oC/W
Solder Reflow Peak Temperature
This table lists the minimum solder reflow peak temperature to achieve good solderability.
Table 37. Solder Reflow Peak Temperature
Package
Minimum Peak Temperature[16]
Maximum Peak Temperature
16 QFN
240oC
260oC
24 QFN
240oC
260oC
32 QFN
240oC
260oC
48 SSOP
220oC
260oC
48 QFN
240oC
260oC
Capacitance on Crystal Pins
Table 38. Typical Package Capacitance on Crystal Pins
Package
Package Capacitance
32 QFN
3.2 pF
48 QFN
3.3 pF
Notes
14. TJ = TA + Power x θJA.
15. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane.
16. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
Document Number: 001-12696 Rev. *F
Page 34 of 39
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Development Tool Selection
Evaluation Tools
Software
All evaluation tools are sold at the Cypress Online Store.
PSoC Designer™
CY3210-MiniProg1
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at
http://www.cypress.com/psocdesigner and includes a free C
compiler.
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
PSoC Programmer
PSoC Programmer is flexible enough and is used on the bench
in development and is also suitable for factory programming.
PSoC Programmer works either as a standalone programming
application or operates directly from PSoC Designer or PSoC
Express. PSoC Programmer software is compatible with both
PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC
programmer is available free of cost at
http://www.cypress.com/psocprogrammer.
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Development Kits
CY3210-PSoCEval1
All development kits are sold at the Cypress Online Store.
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation and the software
interface enables users to run, halt, and single step the
processor and view the content of specific memory locations.
PSoC Designer supports the advance emulation features also.
The kit includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
ICE Flex-Pod for CY8C29x66 Family
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
Special features of the board include both USB and capacitive
sensing development and debugging support. This evaluation
board also includes an LCD module, potentiometer, LEDs, an
enunciator and plenty of bread boarding space to meet all of your
evaluation needs. The kit includes:
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
■
PSoC Designer and Example Projects CD
■
Getting Started Guide
■
Wire Pack
Document Number: 001-12696 Rev. *F
CY3214-PSoCEvalUSB
Page 35 of 39
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Device Programmers
CY3207ISSP In-System Serial Programmer (ISSP)
All device programmers are purchased from the Cypress Online
Store.
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
Modular Programmer Base
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
Three Programming Module Cards
■
USB 2.0 Cable
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 39. Emulation and Programming Accessories
Part Number
Pin Package
Flex-Pod Kit[17]
Foot Kit[18]
Adapter[19]
CY8C20236-24LKXI
16 QFN
CY3250-20266QFN
CY3250-16QFN-RK
See note 15
CY8C20246-24LKXI
16 QFN
CY3250-20266QFN
CY3250-16QFN-FK
See note 19
CY8C20336-24LQXI
24 QFN
CY3250-20366QFN
CY3250-24QFN-FK
See note 15
CY8C20346-24LQXI
24 QFN
CY3250-20366QFN
CY3250-24QFN-FK
See note 19
CY8C20396-24LQXI
24 QFN
CY8C20436-24LQXI
32 QFN
CY3250-20466QFN
CY3250-32QFN-RK
See note 15
CY8C20446-24LQXI
32 QFN
CY3250-20466QFN
CY3250-32QFN-FK
See note 19
CY8C20466-24LQXI
32 QFN
CY3250-20466QFN
CY3250-32QFN-FK
See note 19
CY8C20496-24LQXI
32 QFN
CY8C20536-24PVXI
48 SSOP
CY3250-20566
CY3250-48SSOP-FK
See note 19
CY8C20546-24PVXI
48 SSOP
CY3250-20566
CY3250-48SSOP-FK
See note 19
CY8C20566-24PVXI
48 SSOP
CY3250-20566
CY3250-48SSOP-FK
See note 19
CY8C20636-24LTXI
48 QFN
CY3250-20666QFN
CY3250-48QFN-FK
See note 19
CY8C20646-24LTXI
48 QFN
CY3250-20666QFN
CY3250-48QFN-FK
See note 19
CY8C20666-24LTXI
48 QFN
CY3250-20666QFN
CY3250-48QFN-FK
See note 19
Not Available
Not Available
Third-Party Tools
Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and
production. Specific details for each of these tools can be found at http://www.cypress.com under Documentation > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, refer Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/?rID2748.
Notes
17. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
18. Foot kit includes surface mount feet that can be soldered to the target PCB.
19. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-12696 Rev. *F
Page 36 of 39
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Ordering Information
The following table lists the CY8C20x36/46/66/96 PSoC devices' key package features and ordering codes.
Table 40. PSoC Device Key Features and Ordering Information
Package
Ordering Code
Flash
(Bytes)
SRAM
(Bytes)
CapSense
Blocks
Digital I/O
Pins
Analog
Inputs[20]
XRES
Pin
USB
16-Pin (3x3x0.6mm) QFN
CY8C20236-24LKXI
8K
1K
1
13
13
Yes
No
16-Pin (3x3x0.6mm) QFN
(Tape and Reel)
CY8C20236-24LKXIT
8K
1K
1
13
13
Yes
No
16 Pin (3x3 x 0.6 mm) QFN
CY8C20246-24LKXI
16K
2K
1
13
13
Yes
No
16 Pin (3x3 x 0.6 mm) QFN
(Tape and Reel)
CY8C20246-24LKXIT
16K
2K
1
13
13
Yes
No
24-Pin (4x4x0.6mm) QFN
CY8C20336-24LQXI
8K
1K
1
20
20
Yes
No
24-Pin (4x4x0.6mm) QFN
(Tape and Reel)
CY8C20336-24LQXIT
8K
1K
1
20
20
Yes
No
24 Pin (4x4 x 0.6 mm) QFN
CY8C20346-24LQXI
16K
2K
1
20
20
Yes
No
24 Pin (4x4 x 0.6 mm) QFN
(Tape and Reel)
CY8C20346-24LQXIT
16K
2K
1
20
20
Yes
No
24-Pin (4x4x0.6mm) QFN
CY8C20396-24LQXI
16K
2K
1
19
19
Yes
Yes
24-Pin (4x4x0.6mm) QFN
(Tape and Reel)
CY8C20396-24LQXIT
16K
2K
1
19
19
Yes
Yes
32-Pin (5x5x0.6mm) QFN
CY8C20436-24LQXI
8K
1K
1
28
28
Yes
No
32-Pin (5x5x0.6mm) QFN
(Tape and Reel)
CY8C20436-24LQXIT
8K
1K
1
28
28
Yes
No
32 Pin (5x5 x 0.6 mm) QFN
CY8C20446-24LQXI
16K
2K
1
28
28
Yes
No
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
CY8C20446-24LQXIT
16K
2K
1
28
28
Yes
No
32 Pin (5x5 x 0.6 mm) QFN
CY8C20466-24LQXI
32K
2K
1
28
28
Yes
No
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
CY8C20466-24LQXIT
32K
2K
1
28
28
Yes
No
32 Pin (5x5 x 0.6 mm) QFN
CY8C20496-24LQXI
16K
2K
1
25
25
Yes
Yes
32 Pin (5x5 x 0.6 mm) QFN
(Tape and Reel)
CY8C20496-24LQXIT
16K
2K
1
25
25
Yes
Yes
48-Pin SSOP
CY8C20536-24PVXI
8K
1K
1
34
34
Yes
No
48-Pin SSOP
(Tape and Reel)
CY8C20536-24PVXIT
8K
1K
1
34
34
Yes
No
48-Pin SSOP
CY8C20546-24PVXI
16K
2K
1
34
34
Yes
No
48-Pin SSOP
(Tape and Reel)
CY8C20546-24PVXIT
16K
2K
1
34
34
Yes
No
48-Pin SSOP
CY8C20566-24PVXI
32K
2K
1
34
34
Yes
No
48-Pin SSOP
(Tape and Reel)
CY8C20566-24PVXIT
32K
2K
1
34
34
Yes
No
48 Pin (7x7 mm) QFN
CY8C20636-24LTXI
8K
1K
1
36
36
Yes
No
48 Pin (7x7 mm) QFN
(Tape and Reel)
CY8C20636-24LTXIT
8K
1K
1
36
36
Yes
No
48 Pin (7x7 mm) QFN
CY8C20646-24LTXI
16K
2K
1
36
36
Yes
Yes
48 Pin (7x7 mm) QFN
(Tape and Reel)
CY8C20646-24LTXIT
16K
2K
1
36
36
Yes
Yes
48 Pin (7x7 mm) QFN
CY8C20666-24LTXI
32K
2K
1
36
36
Yes
Yes
48 Pin (7x7 mm) QFN
(Tape and Reel)
CY8C20666-24LTXIT
32K
2K
1
36
36
Yes
Yes
48 Pin (7x7 mm) QFN (OCD)[4]
CY8C20066-24LTXI
32K
2K
1
36
36
Yes
Yes
Notes
20. Dual-function Digital I/O Pins also connect to the common analog mux.
Document Number: 001-12696 Rev. *F
Page 37 of 39
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CY8C20X36/46/66/96
Document History Page
Document Title: CY8C20x36/46/66/96 CapSense® Applications
Document Number: 001-12696
Revision
ECN
Origin of Change
Submission Date
Description of Change
**
766857
HMT
See ECN
New silicon and document (Revision **).
*A
1242866
HMT
See ECN
Add features. Update all applicable sections. Update specs.
Fix 24-pin QFN pinout moving pins inside. Update package
revisions. Update and add to Emulation and Programming
Accessories table.
*B
2174006
AESA
See ECN
Added 48-Pin SSOP Part Pinout
Modified symbol RVDD to RGND in Table DC Analog Mux Bus
Specification
Added footnote in Table DC Analog Mux Bus Specification
Added 16K FLASH Parts. Updated Notes, Package Diagrams
and Ordering Information table. Updated Thermal Impedance
and Solder Reflow tables
*C
2587518
TOF/JASM/MNU/
HMT
10/13/08
Converted from Preliminary to Final
Fixed broken links. Updated data sheet template.
Added operating voltage ranges with USB
ADC resolution changed from 10-bit to 8-bit
Included ADC specifications table
Included Comparator specification table
Included Voh7, Voh8, Voh9, Voh10 specs
Flash data retention – condition added to Note
Input leakage spec changed to 1 μA max
GPIO rise time for ports 0,1 and ports 2,3 made common
AC Programming specifications updated
Included AC Programming cycle timing diagram
AC SPI specification updated
The VIH for 3.0<Vdd<2.4 changed to 1.6 from 2.0
Added USB specification
Added SPI CLK to P1[0]
Updated package diagrams
Updated thermal impedances for QFN packages
Updated FGPIO parameter in Table 23
Updated voltage ranges for FSPIM and FSPIS in Table 30
Update Development Tools, add Designing with PSoC
Designer. Edit, fix links, notes and table format. Update RIN
formula, fix TRise parameter names in GPIO figure, fix Switch
Rate note. Update maximum data in Table 20. DC POR and
LVD Specifications.
*D
2649637
SNV/AESA
03/17/2009
Changed title to “CY8C20x36/46/66, CY8C20396
CapSense™ Applications”. Updated data sheet Features, pin
information, and ordering information sections. Updated
package diagram 001-42168 to *C.
*E
2700196
SNV/PYRS
04/30/2009
Added part numbers CY8C20496, CY8C20536, CY8C20546,
CY8C20636, CY8C20646. Updated Features on page 1
Added 48-Pin QFN without USB pin Diagram and Pin Definition
table. Added 32-Pin QFN (with USB) package
Added SPI Master and Slave AC Specifications
Updated Emulations and Programming Accessories Table on
page 33. Updated Ordering Information on page 37
Removed reference to Hi-Tech C Compiler in Development
Tool Selection on page 35
*F
2761504
MATT/AESA
09/09/2009
Added Note 5 and 13. Updated Table 14, 38, 39, and Ordering
Information table. Updated Figure 19.
Document Number: 001-12696 Rev. *F
Page 38 of 39
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CY8C20X36/46/66/96
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Document Number: 001-12696 Rev. *F
Revised September 09, 2009
Page 39 of 39
PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are
property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these
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