ispLSI 5256VE ® In-System Programmable 3.3V SuperWIDE™ High Density PLD Functional Block Diagram Input Bus Generic Logic Block Boundary Scan Interface Input Bus Generic Logic Block Input Bus Input Bus Input Bus Generic Logic Block Generic Logic Block • Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE — 3.3V Power Supply — User Selectable 3.3V/2.5V I/O — 12000 PLD Gates / 256 Macrocells — Up to 144 I/O Pins — 256 Registers — High-Speed Global Interconnect — SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance — SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc. — PCB Efficient Ball Grid Array (BGA) Package Options — Interfaces with Standard 5V TTL Devices Generic Logic Block Features • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 165 MHz Maximum Operating Frequency — tpd = 6.0 ns Propagation Delay — TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels — Electrically Erasable and Reprogrammable — Non-Volatile — Programmable Speed/Power Logic Path Optimization • IN-SYSTEM PROGRAMMABLE — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality — Reprogram Soldered Devices for Faster Debugging Generic Logic Block Input Bus Global Routing Pool (GRP) Generic Logic Block Generic Logic Block Input Bus Input Bus ispLSI 5000VE Description The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs. • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE • ARCHITECTURE FEATURES — Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs — Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell — Macrocells Support Concurrent Combinatorial and Registered Functions — Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable — Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks — Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options — Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device. Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable. Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com 5256ve_10 1 January 2002 Specifications ispLSI 5256VE Functional Block Diagram Input Bus Generic Logic Block Input Bus Input Bus Generic Logic Block Generic Logic Block Generic Logic Block Input Bus Input Bus TCK TMS Input Bus I/O 32 I/O 33 I/O 34 I/O 35 Global Routing Pool (GRP) Generic Logic Block I/O 18 I/O 19 I/O 20 I/O 21 Input Bus I/O 14 I/O 15 I/O 16 I/O 17 Generic Logic Block Boundary Scan Interface Generic Logic Block 1TOE I/O 1 I/O 2 I/O 3 Input Bus Generic Logic Block VCCIO I/O 111 I/O 110 I/O 109 I/O 108 I/O 125 I/O 124 I/O 123 I/O 122 I/O 129 I/O 128 I/O 127 I/O 126 I/O 143 I/O 142 I/O 141 I/O 140 GOE1 GOE0 Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option) 1CLK 2 1CLK 3 CLK 0 CLK 1 I/O 68 I/O 69 I/O 70 I/O 71 I/O 54 I/O 55 I/O 56 I/O 57 I/O 50 I/O 51 I/O 52 I/O 53 I/O 36 I/O 37 I/O 38 I/O 39 RESET 1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine which I/O is shared by package type. Package Type 100 TQFP 128 TQFP 256 fpBGA 272 BGA 1/O 44 / CLK2 I/O 59 / CLK2 I/O 119 / CLK2 I/O 119 / CLK2 Multplexed Signals I/O 49 / CLK 3 I/O 65 / CLK3 I/O 131 / CLK3 I/O 131 / CLK3 2 I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE I/O 0 / TOE TDI TDO I/O 107 I/O 106 I/O 105 I/O 104 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 75 I/O 74 I/O 73 I/O 72 Specifications ispLSI 5256VE The ispLSI 5000VE Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface. ispLSI 5000VE Description (Continued) The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers. An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction. ispLSI 5000VE Family Members Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also available to each register, eliminating the need to gate the clock to the macrocell registers. Reset for the macrocell register is provided from the global signal, its polarity is userselectable. The macrocell register can be programmed to operate as a D-type register or a D-type latch. The ispLSI 5000VE Family ranges from 128 macrocells to 512 macrocells and operates from a 3.3V power supply. All family members will be available with multiple package options. The ispLSI 5000VE Family device matrix showing the various bondout options is shown in the table below. The interconnect structure (GRP) is very similar to Lattice's existing ispLSI 1000, 2000 and 3000 families, but with an enhanced interconnect structure for optimal pin locking and logic routing. This eliminates the need for registered I/O cells or an Output Routing Pool. The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one input from each macrocell output and one input from each I/O pin. The ispLSI 5000VE encompasses the innovative features of the ispLSI 5000VA family with several enhancements. The macrocell is optimized and the Ttype flip flop option is removed. To improve the efficiency of design fits, the Product Term Reset Logic is simplified and the polarity option as well as the Global Preset function are removed. The programmable output-delay feature (skew option) is also removed. As a result, the ispLSI 5000VE is not JEDEC compatible with the ispLSI 5000VA. ispLSI 5000VA and 5000VE pinouts may differ in the same package, however all programming and power/ground pins are located in the same locations. The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows individual output drivers to drive either 3.3V (from the device VCC) or 2.5V (from the VCCIO pin) output levels while the device logic and the output current drive are powered from device supply (VCC). The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs. Additionally, a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device. Table 1. ispLSI 5000VE Family Package Type Device GLBs Macrocells 100 TQFP 128 TQFP 256 fpBGA 272 BGA 388 fpBGA 388 BGA ispLSI 5128VE 4 128 — 96 I/O — — — — ispLSI 5256VE 8 256 72 I/O 96 I/O 144 I/O 144 I/O — — ispLSI 5384VE 12 384 — — 192 I/O 192 I/O — — ispLSI 5512VE 16 512 — — 192 I/O 192 I/O 256 I/O 256 I/O 3 Specifications ispLSI 5256VE Figure 2. ispLSI 5256VE Block Diagram (144 I/O Version) 18 CLK2 18 I/O 18 32 GLB3 32 18 32 Q 32 D D 160 3 PT 160 PT GLB2 32 Q 32 D D 160 3 PT 160 PT 18 GLB1 32 32 D D 160 3 PT 160 PT 18 18 I/O 32 GLB7 IO0/TOE GLB0 32 Q 3 18 32 32 18 68 68 18 32 3 PT 160 160 18 I/O Q 160 160 PT 3 18 I/O 32 GLB6 Q 3 18 32 32 18 68 68 18 32 3 PT 160 160 18 I/O Q 160 160 PT 3 18 I/O 32 GLB5 32 3 18 32 18 18 68 18 18 I/O 32 3 PT 160 160 68 CLK3 Q 160 160 PT 3 18 I/O 32 GLB4 32 D D Q 32 18 400 160 3 PT 3 160 160 PT 160 PT 160 160 68 68 4 3 PT 3 CLK0 CLK1 GOE0 GOE1 RESET Specifications ispLSI 5256VE Figure 3. ispLSI 5000VE Generic Logic Block (GLB) From GRP 0 1 2 66 67 Global PTOE Bus PTSA Macrocell 0 PT 0 PT 1 From PTSA PT 2 PTSA bypass PT 3 To I/O Pad PT 4 PTOE PT Clock PT Reset PT Preset 4 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP Macrocell 1 PT 9 PT 8 From PTSA PT 7 PTSA bypass PT 6 To I/O Pad PT 5 PTOE PT Clock PT Reset PT Preset 4 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 PT 79 Macrocell 15 PT 78 From PTSA PT 77 PTSA bypass PT 76 To GRP To I/O Pad PT 75 PTOE PT Clock PT Reset PT Preset 4 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 PT 159 Macrocell 31 PT 158 From PTSA PT 157 PTSA bypass PT 156 To GRP To I/O Pad PT 155 PTOE PT Clock PT Reset PT Preset PT 160 PT 161 4 PT 162 5 Shared PT Clock Shared PT Reset Global PTOE 0 ... 3 To GRP Specifications ispLSI 5256VE Figure 4. ispLSI 5000VE Macrocell VCCIO VCC VCCIO Global PTOE 0 Global PTOE 1 Global PTOE 2 Global PTOE 3 PTOE GOE0 GOE1 TOE PTSA bypass I/O Pad D Q PTSA Slew rate Open drain Clk En PT Clock To GRP 2.5V/3.3V Output R/L Shared PT Clock CLK0 CLK1 CLK2 CLK3 Input threshold 2.5V/3.3V Clk R P PT Reset Shared PT Reset Global Reset PT Preset speed/ power Note: Not all macrocells have I/O pads. 6 To GRP Specifications ispLSI 5256VE speed. The clock inversion is available on the remaining CLK1 - CLK3 signals. By sharing the pins with the I/O pins, CLK2 and CLK3 can not only be inverted but are also available for logic implementation through GRP signal routing. Figure 5 shows these different clock distribution options. Global Clock Distribution The ispLSI 5000VE Family has four dedicated clock input pins: CLK0 - CLK3. CLK0 input is used as the dedicated master clock that has the lowest internal clock skew with no clock inversion to maintain the fastest internal clock Figure 5. ispLSI 5000VE Global Clock Structure CLK 0 (dedicated pin) CLK0 CLK 1 (dedicated pin) CLK1 IO/CLK 2 (shared pin) to/from GRP CLK2 CLK3 IO/CLK 3 (shared pin) to/from GRP RESET (dedicated pin) Global Reset IO0/TOE (shared pin) to/from GRP TOE 7 Specifications ispLSI 5256VE Figure 6. Boundary Scan Register Circuit for I/O Pins HIGHZ EXTEST SCANIN (from previous cell) BSCAN Registers 1 D TOE BSCAN Latches Q D Normal Function OE Q 0 1 0 EXTEST PROG_MODE Normal Function 1 0 D Q D Q D Q 0 I/O Pin 1 1 0 Shift DR Clock DR SCANOUT (to next cell) Update DR Reset Figure 7. Boundary Scan Register Circuit for Input-Only Pins Input Pin SCANIN (from previous cell) 0 D 1 Shift DR Clock DR 8 Q SCANOUT (to next cell) Specifications ispLSI 5256VE Figure 8. Boundary Scan Waveforms and Timing Specifications TMS TDI Tbtsu Tbtch Tbth Tbtcl Tbtcp TCK Tbtvo Tbtco TDO Valid Data Tbtcpsu Data to be captured Valid Data Tbtcph Data Captured Tbtuov Tbtuco Data to be driven out SYMBOL Tbtoz Valid Data Tbtuoz Valid Data PARAMETER MIN MAX UNITS tbtcp TCK [BSCAN test] clock pulse width 125 – ns tbtch tbtcl TCK [BSCAN test] pulse width high 62.5 – ns TCK [BSCAN test] pulse width low 62.5 – ns tbtsu TCK [BSCAN test] setup time 25 – ns tbth TCK [BSCAN test] hold time 25 – ns trf TCK [BSCAN test] rise and fall time 50 – mV/ns tbtco TAP controller falling edge of clock to valid output – 25 ns tbtoz TAP controller falling edge of clock to data output disable – 25 ns tbtvo TAP controller falling edge of clock to data output enable – 25 ns tbtcpsu BSCAN test Capture register setup time 25 – ns tbtcph BSCAN test Capture register hold time 25 – ns tbtuco BSCAN test Update reg, falling edge of clock to valid output – 50 ns tbtuoz BSCAN test Update reg, falling edge of clock to output disable – 50 ns tbtuov BSCAN test Update reg, falling edge of clock to output enable – 50 ns 9 Specifications ispLSI 5256VE Absolute Maximum Ratings 1, 2 Supply Voltage Vcc .................................. -0.5 to +5.4V Input Voltage Applied ............................... -0.5 to +5.6V Tri-Stated Output Voltage Applied ........... -0.5 to +5.6V Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C Max. Junction Temp. (TJ) with Power Applied ... 150°C 1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). 2. Compliance with the Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM is a requirement. DC Recommended Operating Condition SYMBOL MIN. MAX. UNITS Commercial TA = 0°C to +70°C 3.00 3.60 V Industrial TA = -40°C to +85°C 3.00 3.60 V 2.3 3.60 PARAMETER VCC Supply Voltage VCCIO I/O Reference Voltage V Table 2-0005/5KVE Capacitance (TA=25°C,f=1.0 MHz) TYPICAL UNITS I/O Capacitance 10 pf VCC = 3.3V, VI/O = 0.0V Clock Capacitance 10 pf VCC = 3.3V, VCK = 0.0V Global Input Capacitance 10 pf VCC = 3.3V, VG = 0.0V SYMBOL C1 C2 C3 PARAMETER TEST CONDITIONS Table 2-0006/5KVE Erase Reprogram Specification PARAMETER ispLSI Erase/Reprogram Cycles MINIMUM MAXIMUM UNITS 10000 – Cycles Table 2-0008/5KVE 10 Specifications ispLSI 5256VE Switching Test Conditions Figure 9. Test Load Input Pulse Levels GND to VCCIOmin Input Rise and Fall Time VCCIO ≤ 1.5ns 10% to 90% Input Timing Reference Levels 1.5V Ouput Timing Reference Levels 1.5V Output Load R1 See Figure 9 Device Output Table 2-0003/5KVE 3-state levels are measured 0.5V from steady-state active level. Test Point C L* R2 Output Load Conditions (See Figure 9) 3.3V TEST CONDITION R1 R2 R1 316Ω 348Ω 511Ω 475Ω 35pF Active High ∞ 348Ω ∞ 475Ω 35pF Active Low 316Ω ∞ 511Ω ∞ 35pF Active High to Z at VOH -0.5V ∞ 348Ω ∞ 475Ω 5pF Active Low to Z at VOL+0.5V 316Ω ∞ 511Ω ∞ 5pF ∞ ∞ ∞ ∞ 35pF A B C D *CL includes Test Fixture and Probe Capacitance. 2.5V Slow Slew R2 0213D CL Table 2-0004A/5KVE DC Electrical Characteristics for 3.3V Range1 Over Recommended Operating Conditions SYMBOL VCCIO VIL VIH VOL VOH MIN. TYP. I/O Reference Voltage CONDITION 3.0 – 3.6 V Input Low Voltage -0.3 – 0.8 V Input High Voltage 2.0 – 5.25 V PARAMETER MAX. UNITS Output Low Voltage VCCIO = min, IOL = 8 mA – – 0.4 V Output High Voltage VCCIO = min, IOH = -4 mA 2.4 – – V Table 2-0007/5KVE 1. I/O voltage configuration must be set to VCC. 11 Specifications ispLSI 5256VE DC Electrical Characteristics for 2.5V Range1 Over Recommended Operating Conditions SYMBOL CONDITION PARAMETER MIN. TYP. MAX. UNITS VCCIO VIL VIH I/O Reference Voltage 2.3 – 2.7 V Input Low Voltage -0.3 – 0.7 V Input High Voltage 1.7 – 5.25 V VOL Output Low Voltage – – 0.2 V VOH VCCIO=min, IOL= 100µA VCCIO=min, IOL= 2mA Output High Voltage – – 0.6 V VCCIO=min, IOH= -100µA 2.1 – – V VCCIO=min, IOH= -2mA 1.8 – – V 2.5V/5KVE 1. I/O voltage configuration must be set to VCCIO. DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL IIL IIH 1 IPU IBHL IBHH IBHLO IBHLH IBHT IVCCIO CONDITION PARAMETER MIN. TYP. MAX. UNITS Input or I/O Low Leakage Current 0V ≤ VIN≤ VIL(Max.) – – -10 µA Input or I/O High Leakage Current (VCCIO-0.2)V ≤ VIN ≤ VCCIO – – 10 µA VCCIO ≤ VIN ≤ 5.25V – – 50 µA I/O Active Pullup Current 0V ≤ VIN ≤ VIL – – -200 µA Bus Hold Low Sustaining Current VIN = VIL(max) 40 – – µA Bus Hold High Sustaining Current -40 – – µA Bus Hold Low Overdrive Current VIN = VIH(min) 0V ≤ VIN ≤ VCCIO – – 550 µA Bus Hold High Overdrive Current 0V ≤ VIN ≤ VCCIO – – -550 µA VIL – VIH V – – 30 mA Bus Hold Trip Points Current Needed for VCCIO Pin All I/Os Pulled-up, (Total I/Os * IPUmax) 1. Pullup is capable of pulling to a minimum voltage of VOH under no-load conditions. 12 DC Char_5KVE Specifications ispLSI 5256VE External Switching Characteristics Over Recommended Operating Conditions PARAM. tpd16 tpd26 fmax fmax (Ext.) fmax (Tog.) tsu1 tco16 th1 tsu2 th2 tsu3 th3 tr1 trw17 tpten/dis6 tgpten/dis6 TEST3 COND. DESCRIPTION -165 4,5 -125 MIN. MAX. MIN. MAX. UNITS A Data Prop. Delay, 5PT Bypass — 6.0 — 7.5 ns A Data Propagation Delay — 7.5 — 9.5 ns 1 A Clock Frequency with Internal Feedback 165 — 125 — MHz — Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 118 — 87 — MHz 2 — Clock Frequency, Max Toggle 200 — 167 — MHz — GLB Reg. Setup Time before Clk, 5PT bypass 4.0 — 5.0 — ns A GLB Reg. Clock to Output Delay — 3. 0 — 4.5 ns — GLB Reg. Hold Time after Clock, 5PT bypass 0.0 — 0.0 — ns — GLB Reg. Setup Time before Clock 5. 5 — 7.0 — ns — GLB Reg. Hold Time after Clock 0. 0 — 0.0 — ns — GLB Reg. Setup Time before Clock, Input Reg. Path 2.5 — 3.5 — ns — GLB Reg. Hold Time after Clock, Input Reg. Path 0. 5 — 0.5 — ns A Ext. Reset Pin to Output Delay — 8.0 — 10.0 ns — Ext. Reset Pulse Duration 4.0 — 5.0 — ns B/C Local Product Term Output Enable/Disable — 7.0 — 8.5 ns B/C Global Product Term Output Enable/Disable — 12.0 — 14.0 ns tgen/dis B/C Global OE Input to Output Enable/Disable — 4.5 — 5.5 ns tten/dis B/C Test OE Input to Output Enable/Disable — 7.5 — 10.5 ns twh — Ext. Sync. Clock Pulse Duration, High 2.5 — 3.0 — ns twl — Ext. Sync. Clock Pulse Duration, Low 2.5 — 3.0 — ns 6 6 Timing Ext.5256ve1.eps 1. Standard 16-bit counter using GRP feedback. 2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Timing v.2.0 3. Reference Switching Test Conditions section. 4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and highspeed AND array. 5. Timing parameters measured using normal active output driver. 6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O voltage reference. 7. Pulse widths less than minimum may cause unknown output behavior. 13 Specifications ispLSI 5256VE External Switching Characteristics Over Recommended Operating Conditions PARAM. tpd16 tpd26 fmax fmax (Ext.) fmax (Tog.) tsu1 tco16 th1 tsu2 th2 tsu3 th3 tr1 trw17 tpten/dis6 tgpten/dis6 tgen/dis6 TEST3 COND. DESCRIPTION 4,5 -100 -80 MIN. MAX. MIN. MAX. UNITS A Data Prop. Delay, 5PT Bypass — 10.0 — 12.0 ns A Data Propagation Delay — 12.0 — 15.0 ns 1 A Clock Frequency with Internal Feedback 100 — 80 — MHz — Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 67 — 56 — MHz 2 — Clock Frequency, Max Toggle 125 — 100 — MHz — GLB Reg. Setup Time before Clk, 5PT bypass 7.0 — 8.0 — ns A GLB Reg. Clock to Output Delay — 6.0 — 7.0 ns — GLB Reg. Hold Time after Clock, 5PT bypass 0.0 — 0.0 — ns — GLB Reg. Setup Time before Clock 9.0 — 11.0 — ns — GLB Reg. Hold Time after Clock 0.0 — 0.0 — ns — GLB Reg. Setup Time before Clock, Input Reg. Path 4.5 — 5.5 — ns — GLB Reg. Hold Time after Clock, Input Reg. Path 1.0 — 1.0 — ns A Ext. Reset Pin to Output Delay — 11.5 — 13.0 ns — Ext. Reset Pulse Duration 6.5 — 8.0 — ns B/C Local Product Term Output Enable/Disable — 10.0 — 12.0 ns B/C Global Product Term Output Enable/Disable — 15.5 — 17.0 ns B/C Global OE Input to Output Enable/Disable — 7.5 — 9.0 ns tten/dis B/C Test OE Input to Output Enable/Disable — 11.5 — 12.5 ns twh — Ext. Sync. Clock Pulse Duration, High 4.0 — 5.0 — ns twl — Ext. Sync. Clock Pulse Duration, Low 4.0 — 5.0 — ns 6 Timing Ext.5256ve2.eps 1. Standard 16-bit counter using GRP feedback. 2. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Timing v.2.0 3. Reference Switching Test Conditions section. 4. Unless noted otherwise, all timing numbers are taken with worst case PTSA fanout, a GRP load of 1 GLB, CLK0, and highspeed AND array. 5. Timing parameters measured using normal active output driver. 6. The delay parameters are measured with Vcc as I/O voltage reference. An additional 0.5ns delay is incurred when Vccio is used as I/O reference. 7. Pulse widths less than minimum may cause unknown output behavior. used as I/O voltage reference. 14 Specifications ispLSI 5256VE Internal Timing Parameters Over Recommended Operating Conditions PARAMETER In/Out Delays tin tgclk_in trst tgoe tbuf ten tdis -165 -125 -100 -80 MIN MAX MIN MAX MIN MAX MIN MAX UNIT DESCRIPTION Input Buffer Delay – 0.6 – 1.3 – 2.3 – 2.3 ns Global Clock Buffer Input Delay (clk0) – 0.7 – 1.3 – 1.8 – 1.8 ns Global Reset Pin Delay – 4.9 – 6.6 – 7.1 – 7.1 ns Global OE Pin Delay – 3.2 – 3.9 – 5.9 – 7.4 ns Output Buffer Delay – 1.9 – 2.2 – 2.7 – 3.7 ns Output Enable Delay – 1.3 – 1.6 – 1.6 – 1.6 ns Output Disable Delay – 1.3 – 1.6 – 1.6 – 1.6 ns – 3.2 – 3.6 – 4.0 – 4.5 ns Routing/GLB Delays troute tpdb tpdi tptsa tfbk tinreg GRP and Logic Delay 5-pt Bypass Propagation Delay – 0.3 – 0.4 – 1.0 – 1.5 ns Combinatorial Propagation Delay – 0.0 – 0.0 – 0.0 – 0.0 ns Product Term Sharing Array – 1.8 – 2.4 – 3.0 – 4.5 ns Internal Feedback Delay – 0.0 – 0.0 – 0.0 – 0.5 ns Input Buffer to Macrocell Register Delay – 2.0 – 2.5 – 2.5 – 3.5 ns Register/Latch Delays ts ts_pt th tcoi tsl thl tgoi tpdli tces tceh tsri tsrr Register Setup Time 0.6 – 1.0 – 1.5 – 1.5 – ns Register Setup Time (Product Term Clock) 0.6 – 1.0 – 1.5 – 1.5 – ns Register Hold Time 2.4 – 3.0 – 4.0 – 5.0 – ns – 0.4 – 1.0 – 1.5 – 1.5 ns Latch Setup Time 0.6 – 1.0 – 1.5 – 1.5 – ns Latch Hold Time 2.4 – 3.0 – 4.0 – 5.0 – ns Register Clock to GLB Output Delay Latch Gate to GLB Output Delay – 0.4 – 1.0 – 1.5 – 1.5 ns GLB Latch propagation Delay – 1.0 – 1.5 – 2.0 – 2.5 ns Clock Enable Setup Time 4.1 – 4.3 – 5.3 – 6.3 – ns Clock Enable Hold Time 0.9 – 1.7 – 2.7 – 3.7 – ns Asynchronous Set/Reset to GLB Output Delay – 1.2 – 1.2 – 1.7 – 2.2 ns 0.8 – 1.2 – 1.2 – 2.2 – ns Macrocell PT Clock Delay – 0.4 – 0.4 – 0.5 – 0.5 ns Block PT Clock Delay – 1.4 – 1.9 – 2.5 – 2.5 ns Macrocell PT Set/Reset Delay – 2.1 – 3.7 – 4.8 – 4.8 ns Block PT Set/Reset Delay – 3.1 – 5.7 – 6.8 – 6.8 ns Macrocell PT OE Delay – 1.9 – 2.0 – 2.1 – 3.6 ns Global PT OE Delay – 6.9 – 7.5 – 7.6 – 8.6 Asynchronous Set/Reset Recovery Time Control Delays tptclk tbclk tptsr tbsr tptoe tgptoe Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for further details. 15 ns Timing v.2.0 Specifications ispLSI 5256VE ispLSI 5256VE Timing Parameters (continued) ADDER ADDER TYPE BASE PARAMETER -165 -125 -100 -80 UNITS troute 1.0 1.5 1.5 1.5 ns tgclk_in tgclk_in tgclk_in 1.4 1.7 1.7 1.7 ns 1.4 1.7 1.7 1.7 ns 1.4 1.7 1.7 1.7 ns tbuf, ten tbuf, ten, tdis tbuf, ten, tdis tbuf, ten, tdis 4.0 4.0 4.0 4.0 ns 0.0 0.0 0.0 0.0 ns 0.5 0.5 0.5 0.5 ns 0.0 0.0 0.0 0.0 ns 0.1 0.1 0.1 0.1 ns 0.1 0.2 0.2 0.2 ns 0.2 0.3 0.3 0.3 ns 0.3 0.4 0.4 0.4 ns 0.4 0.5 0.5 0.5 ns 0.4 0.6 0.6 0.6 ns 0.5 0.7 0.7 0.7 Routing Adders tlp Tioi Input Adders clk1 clk2 clk3 Tioo Output Adders1 Slow Slew I/O LVTTL_out LVCMOS25_out LVCMOS33_out Tbla Additional Block Loading Adders 1 2 3 4 5 6 7 troute troute troute troute troute troute troute 1Timing for open drain configurations is the same as non-open drain configurations. Note: Internal Timing Parameters are not tested and are for reference only. Refer to Timing Model in this data sheet for details. 16 ns Timing Table/5256VE Timing v.2.0 Specifications ispLSI 5256VE ispLSI 5256VE Timing Model Routing/ GLB Delays tPDb From Feedback Feedback tPDi tFBK tROUTE IN tBLA tIN tPTSA DATA Q tLP tINREG CLK OUT In/Out Delays tGCLK_IN tIOI tBUF tEN tDIS tIOO tPTCLK tBCLK CE tPTSR tBSR S/R MC Reg RST tRST Register/ Latch Delays tGPTOE tPTOE OE tGOE Control Delays 5000VE Timing Model In/Out Delays Note: Italicized parameters are delay adders above and beyond default conditions (i.e. GRP load of one GLB, CLK0, high-speed AND Array and VCC I/O option). 17 Specifications ispLSI 5256VE Power Consumption Power consumption in the ispLSI 5256VE device depends on two primary factors: the speed at which the device is operating and the number of product terms used. The product terms have a fuse-selectable speed/ power tradeoff setting. Each group of five product terms has a single speed/power tradeoff control fuse that acts on the complete group of five. The fast “high-speed” setting operates product terms at their normal full power consumption. For portions of the logic that can tolerate longer propagation delays, selecting the slower “lowpower” setting will reduce the power dissipation for these product terms. Figure 10 shows the relationship between power and operating frequency. Figure 10. Typical Device Power Consumption vs fmax ispLSI 5256VE High Speed Mode 300 275 ICC (mA) 250 225 ispLSI 5256VE Low Power Mode 200 175 150 0 25 50 75 100 125 150 175 200 fmax (MHz) Notes: Configuration of 16 16-bit Counters Typical Current at 3.3V, 25° C ICC can be estimated for the ispLSI 5256VE using the following equation: High Speed Mode: ICC = 21 + (# of PTs * 0.313) + (# of nets * Fmax * 0.00282) Low Power Mode: ICC = 21 + (# of PTs * 0.258) + (# of nets * Fmax * 0.00282) # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Fmax = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of one GLB load on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 0127/5256VE 18 Specifications ispLSI 5256VE Signal Descriptions Signal Name TMS Description Input - This pin is the Test Mode Select input, which is used to control the JTAG state machine. TCK Input - This pin is the Test Clock input pin used to clock through the JTAG state machine. TDI Input - This pin is the JTAG Test Data In pin used to load data. TDO Output - This pin is the JTAG Test Data Out pin used to shift data out. TOE / I/O0 Input/Output - This pin functions as either the Test Output Enable pin or an I/O pin based upon customer's design. TOE tristates all I/O pins when a logic low is driven. GOE0, GOE1 Input - These two pins are the Global Output Enable input pins. RESET Dedicated Reset Input - This pin resets all registers in the device. The global polarity (active high or low input) for this pin is selectable. I/O Input/Output – These are the general purpose I/O used by the logic array. GND Ground NC1 No connect. VCC Vcc CLK0, CLK1 Dedicated clock inputs for all registers. Both clocks are muxed before being used as the clock input to all registers in the device. CLK2 / I/O, CLK3 / I/O Input/Output - These pins share functionality. They can be used as dedicated clock inputs for all registers, as well as I/O pins. VCCIO Input - This pin is used for optional 2.5V outputs. Every I/O can independently select either 3.3V or the optional voltage as its output level. If the optional output voltage is not required, this pin must be connected to the Vcc supply. Programmable pull-up resistors and bus-hold latches only draw current from this supply. 1. NC pins are not to be connected to any active signals, VCC or GND. 19 Specifications ispLSI 5256VE Pin Configuration ispLSI 5256VE Top View 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC I/O 42 I/O 41 I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 VCC RESET VCCIO TDO GND I/O 35 I/O 34 I/O 33 I/O 32 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 GND I/O 26 VCC I/O 7 I/O 8 I/O 9 GND I/O 10 VCC I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 GND GOE 0 GOE 1 VCC I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 GND I/O 66 VCC I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 GND TMS TCK TDI VCC I/O 0/TOE I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 I/O 60 VCC I/O 59 GND I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 VCC CLK1 CLK0 I/O 52 GND I/O 51 I/O 50 I/O 49/CLK3 I/O 48 I/O47 I/O 46 I/O 45 GND I/O 44/CLK2 I/O 43 ispLSI 5256VE 100-Pin TQFP (0.5mm Lead Pitch / 14.0mm x 14.0mm Body Size) 100 TQFP/5256VE 20 Specifications ispLSI 5256VE Pin Configuration 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 I/O 81 I/O 80 I/O 79 VCC I/O 78 GND I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 VCC CLK1 CLK0 I/O 70 I/O 69 GND I/O 68 I/O 67 I/O 66 I/O 65/CLK3 I/O 64 I/O 63 I/O 62 I/O 61 I/O 60 GND I/O 59/CLK2 I/O 58 I/O 57 ispLSI 5256VE 128-Pin TQFP (0.4mm Lead Pitch / 14.0mm x 14.0mm Body Size) ispLSI 5256VE Top View 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VCC I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 VCC RESET VCCIO TDO GND I/O 47 I/O 46 I/O 45 I/O 44 I/O 43 I/O 42 VCC I/O 41 GND I/O 40 I/O 39 I/O 38 I/O 37 I/O 36 GND I/O 35 VCC 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O 9 I/O 10 I/O 11 I/O 12 GND I/O 13 I/O 14 VCC I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 GND GOE0 GOE1 VCC I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 GND I/O 88 VCC I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 GND TMS TCK TDI VCC I/O 0/TOE I/O 1 I/O 2 I/O 3 I/O 4 GND I/O 5 VCC I/O 6 I/O 7 I/O 8 128 TQFP/5256VE 21 Specifications ispLSI 5256VE Signal Configuration ispLSI 5256VE 256-Ball fpBGA (1.0mm Ball Pitch / 17.0mm x 17.0mm Body Size) 16 15 14 13 12 A I/O 113 I/O 116 I/O 121 I/O 125 B I/O 108 I/O 115 I/O I/O 119/ 117 CLK2 C I/O 106 I/O 114 NC1 D I/O 105 I/O 109 E I/O 104 F 11 10 9 8 7 6 5 4 3 2 1 I/O I/O 131/ I/O 126 CLK3 133 I/O 139 I/O 140 CLK0 I/O 145 I/O 147 I/O 151 I/O 152 I/O 153 I/O 165 A I/O 124 I/O 129 I/O 132 I/O 136 CLK1 I/O 144 I/O 149 I/O 156 I/O 157 I/O 163 I/O 164 I/O 168 B I/O 120 I/O 123 I/O 128 I/O 135 I/O 138 I/O 141 I/O 143 I/O 148 I/O 155 I/O 159 I/O 160 I/O 161 I/O 172 C I/O 111 GND GND VCC GND VCC GND GND VCC GND VCC I/O 169 I/O 167 I/O 175 D NC1 I/O 101 VCC NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 GND I/O 173 I/O 171 I/O 177 E I/O 100 I/O 102 I/O 97 GND NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 VCC I/O 181 I/O 176 I/O 179 F G I/O 96 I/O 98 TDO VCC NC1 NC1 VCC GND GND VCC NC1 NC1 GND I/O 185 I/O 180 I/O 187 G H I/O 94 VCCIO RESET GND NC1 NC1 GND VCC VCC GND NC1 NC1 VCC I/O 184 I/O 183 I/O 188 H J I/O 93 I/O 92 I/O 90 GND NC1 NC1 GND VCC VCC GND NC1 NC1 GND I/O 191 I/O 190 TMS J K I/O 89 I/O 88 I/O 86 VCC NC1 NC1 VCC GND GND VCC NC1 NC1 VCC TDI TCK I/O 0/ TOE K L I/O 85 I/O 84 I/O 82 GND NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 GND I/O 4 I/O 1 I/O 2 L M I/O 81 I/O 80 I/O 77 GND NC1 NC1 NC1 NC1 NC1 NC1 NC1 NC1 VCC I/O 8 I/O 6 I/O 5 M N I/O 78 I/O 74 I/O 76 VCC GND VCC GND VCC GND GND VCC GND GND I/O 11 I/O 12 I/O 9 N P I/O 73 I/O 70 I/O 65 I/O 66 I/O 57 I/O 56 I/O 41 I/O 42 I/O 36 I/O 26 I/O 22 I/O 20 I/O 13 I/O 14 P R I/O 72 I/O 69 I/O 62 I/O 67 I/O 64 I/O 58 I/O 48 I/O 46 I/O 40 I/O 34 I/O 29 I/O 25 I/O 24 I/O 18 I/O 17 I/O 16 R T I/O 61 I/O 60 I/O 54 I/O 53 I/O 52 I/O 50 I/O 49 I/O 45 I/O 44 I/O 38 I/O 37 I/O 33 I/O 32 I/O 30 I/O 28 I/O 21 T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 GOE1 GOE0 ispLSI 5256VE Bottom View 1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. 22 Specifications ispLSI 5256VE Signal Configuration ispLSI 5256VE 272-Ball BGA (1.27mm Ball Pitch / 27.0mm x 27.0mm Body Size) 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 A I/O 114 I/O I/O 119/ NC1 115 CLK2 NC1 I/O 126 I/O 129 I/O 132 I/O 136 I/O 139 I/O 140 NC1 NC1 I/O 149 I/O 151 NC1 NC1 I/O 160 I/O GND 164 A B NC1 NC1 NC1 I/O 116 I/O 121 I/O 125 I/O I/O 131/ I/O 128 CLK3 135 NC1 I/O 141 I/O 143 I/O 147 NC1 I/O 153 I/O 157 I/O 159 NC1 I/O 163 I/O 165 B C I/O 111 NC1 NC1 I/O 117 I/O 120 I/O 123 NC1 I/O I/O CLK0 138 144 I/O 148 I/O 152 I/O 156 NC1 NC1 NC1 NC1 I/O 169 C D I/O 109 NC1 I/O I/O I/O I/O I/O I/O GND NC1 VCC GND VCC CLK1 GND VCC GND NC1 113 124 133 145 155 161 I/O 167 NC1 D E I/O 105 I/O 108 NC1 NC1 F I/O 102 I/O 104 NC1 VCC G I/O 100 I/O 101 NC1 H I/O 97 I/O 98 NC1 GND J 18 NC1 NC1 2 1 I/O 168 I/O 171 NC1 I/O 172 E ispLSI 5256VE VCC I/O 173 I/O 175 I/O 176 F Bottom View NC1 I/O 177 NC1 I/O 179 G GND I/O 180 I/O 181 NC1 H GND GND GND GND I/O 183 I/O 184 I/O 185 NC1 J I/O 106 I/O TDO VCCIO RESET 96 K I/O 92 I/O 93 I/O 94 NC1 GND GND GND GND VCC I/O 188 I/O 187 NC1 K L NC1 I/O 89 I/O 90 VCC GND GND GND GND TCK TMS I/O 191 I/O 190 L M I/O 88 NC1 I/O 86 I/O 85 GND GND GND GND I/O 0/ TDI TOE M N I/O 84 NC1 I/O 82 P I/O 81 NC1 R NC1 I/O 2 I/O 1 GND GND I/O 5 I/O 4 NC1 N I/O 80 I/O 77 I/O 12 I/O 9 NC1 I/O 6 P I/O 78 I/O 76 VCC VCC NC1 NC1 I/O 8 R T NC1 NC1 I/O 74 NC1 NC1 I/O 14 I/O 11 T U I/O 73 I/O 70 NC1 GND GND NC1 NC1 NC1 U V I/O 72 I/O 69 NC1 W NC1 NC1 Y NC1 20 I/O 64 VCC I/O 58 GND I/O GOE1 VCC 48 I/O 37 GND I/O 65 I/O 62 NC1 NC1 NC1 NC1 GOE0 I/O 42 I/O 38 I/O 66 NC1 I/O 60 I/O 56 I/O 53 I/O 50 I/O 46 I/O 45 I/O 41 I/O 67 NC1 I/O 61 I/O 57 I/O 54 I/O 52 I/O 49 NC1 I/O 44 19 18 17 16 15 14 13 12 11 VCC I/O 21 I/O 34 NC1 NC1 I/O 24 I/O 20 I/O 17 NC1 V NC1 NC1 I/O 32 I/O 29 I/O 25 NC1 NC1 NC1 NC1 W NC1 I/O 40 I/O 36 I/O 33 I/O 30 I/O 26 NC1 I/O 22 NC1 I/O 18 Y 10 9 8 7 6 5 4 3 2 1 1. NCs are not to be connected to any active signals, Vcc or GND. Note: Ball A1 indicator dot on top side of package. 23 I/O 28 I/O 13 I/O 16 Specifications ispLSI 5256VE Part Number Description ispLSI 5256VE – XXX X XXXX X Device Family Grade Blank = Commercial I = Industrial Device Number Package T100 = 100-Pin TQFP T128 = 128-Pin TQFP F256 = 256-Ball fpBGA B272 = 272-Ball BGA Speed 165 = 165 MHz fmax 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 80 MHz fmax Power L = Low 0212/5256ve Ordering Information COMMERCIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 165 6.0 ispLSI 5256VE-165LT100 100-Pin TQFP 165 6.0 ispLSI 5256VE-165LT128 128-Pin TQFP 165 6.0 ispLSI 5256VE-165LF256 256-Ball fpBGA 165 6.0 ispLSI 5256VE-165LB272 272-Ball BGA 125 7.5 ispLSI 5256VE-125LT100 100-Pin TQFP 125 7.5 ispLSI 5256VE-125LT128 128-Pin TQFP 125 7.5 ispLSI 5256VE-125LF256 256-Ball fpBGA 125 7.5 ispLSI 5256VE-125LB272 272-Ball BGA 100 10 ispLSI 5256VE-100LT100 100-Pin TQFP 100 10 ispLSI 5256VE-100LT128 128-Pin TQFP 100 10 ispLSI 5256VE-100LF256 256-Ball fpBGA 100 10 ispLSI 5256VE-100LB272 272-Ball BGA Table 2-0041A/5256VE INDUSTRIAL FAMILY ispLSI fmax (MHz) tpd (ns) ORDERING NUMBER PACKAGE 125 7.5 ispLSI 5256VE-125LT100I 100-Pin TQFP 125 7.5 ispLSI 5256VE-125LT128I 128-Pin TQFP 125 7.5 ispLSI 5256VE-125LF256I 256-Ball fpBGA 125 7.5 ispLSI 5256VE-125LB272I 272-Ball BGA 100 10 ispLSI 5256VE-100LT100I 100-Pin TQFP 100 10 ispLSI 5256VE-100LT128I 128-Pin TQFP 100 10 ispLSI 5256VE-100LF256I 256-Ball fpBGA 100 10 ispLSI 5256VE-100LB272I 272-Ball BGA 80 12 ispLSI 5256VE-80LT100I 100-Pin TQFP 80 12 ispLSI 5256VE-80LT128I 128-Pin TQFP 80 12 ispLSI 5256VE-80LF256I 256-Ball fpBGA 80 12 ispLSI 5256VE-80LB272I 272-Ball BGA The ispLSI 5256VE is dual-marked with both Commercial and Industrial grades. The Commercial speed grade is faster (i.e. ispLSI 5256VE-165LF256) than the Industrial speed grade (i.e. ispLSI 5256VE-125LF256I). 24 Table 2-0041B/5256VE