ETC AD7312L 1/4 to 1/11 duty vfd controller/driver & standby master/slave Datasheet

AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Features
output)
˙Remote signal input port
˙Remote signal output port
˙3 STANDBY master output ports (controlled by
remote STANDBY-KEY, STANDBY-KEY and
STANDBY SCAN-KEY)
˙8 WAKE UP master output ports (controlled by 2
remote WAKE_UP-KEY, 3 WAKE_UP
SCAN-KEY, remote STANDBY-KEY,
STANDBY-KEY and STANDBY SCAN-KEY)
˙NEC 6121/6122 infrared protocol support
˙Serial interface (CLK, STB, DIN, DOUT)
˙Key scanning (6× 4 matrices)
˙Programming display modes (11-digit &
11-segment to 6-digit & 16-segment)
˙Programming dimming step
˙High-voltage output (VDD-35V max).
˙2 channels LED ports.
˙2-pin General-purpose input port
˙Built-in oscillator
˙No external resistor necessary for driver outputs
(provides PMOS open-drain and pull-low resistor
General Description
The AD7312 is a VFD (Vacuum Fluorescent Display) controller/driver with STANDBY controller. It is driven
on a 1/4 to 1/11 duty factor (include key scan). It consists of 5 segment output lines, 6 segment/key scan
output lines, 6 grid output lines, 5 segment/grid output drive lines, 2 LED output ports, a display memory, a
control circuit, and a key scan circuit. In addition, it includes 2 input ports, RMIN and SKEY, RMIN receives
the signal form the STANDBY-KEY of remote sensor, SKEY can be controlled by an external switch. Both of
them and STANBY SCAN-KEY can control the output level (High) of PSV port to realize the STANDBY
function. To leave the standby mode, we can use the 2 remote WAKE_UP-KEY, 3 WAKE_UP SCAN-KEY,
remote STANDBY-KEY, STANDBY-KEY and STANDBY SCAN-KEY to control the output level (Low) of PSV
port to realize the Wake Up function. Serial data is input to the AD7312 through a four-line serial interface.
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of
this product. No rights under any patent accompany the sale of the product.
Rev. A2 Dec 29, 2003
1/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Grid5
Grid6
Seg16 / Grid7
Seg15 / Grid8
Seg14 / Grid9
Seg13 / Grid10
VEE
Seg12 / Grid11
Seg11
Seg10
Seg9
33
32
31
30
29
28
27
26
25
24
23
Pin Assignments
Grid 4
34
Grid 3
Grid 2
22
Seg 8
35
21
Seg 7
36
20
Seg 6 / KS 6
Grid 1
37
19
Seg 5 / KS 5
VDD
38
18
Seg 4 / KS 4
LED 4
39
17
Seg 3 / KS 3
RMBUF
40
16
Seg 2 / KS 2
7
8
9
10
11
VSS
CLK
STB
Key1
Key2
Key3
6
12
DIN
44
5
OSC
DOUT
Key4
4
13
Sw4
43
3
VSS
SKEY
VDD
2
Seg 1 / KS 1
14
RMIN
15
42
1
41
Sw1
PSV
LED 1
Use all power pins.
Anachip Corp.
www.anachip.com.tw
Rev. A2 Dec 29, 2003
2/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Pin Descriptions
Symbol
Name
No.
DIN
Data input
6
DOUT
Data output
5
STB
Strobe
9
CLK
Clock input
8
OSC
Oscillator pin
44
Seg7 to Seg11
High-voltage output (Segment)
21 to 25
Segment output pins
Seg1/KS1 to
Seg6/KS6
High-voltage output
15 to 20
Multi-function pins, Segment output pins (Dual
function as key scan source)
Grid1 to Grid6
High-voltage output (Grid)
32 to 37
Grid output pins
Seg12/Grid11 to
Seg16/Grid7
High-voltage output (Segment/grid)
26,
28 to 31
These pins are selectable for segment or grid
driving.
LED1 and LED4
LED output
39 and 42
CMOS output
RMBUF
Remote Control Buffer
40
CMOS output
PSV
Power Saving Output
41
CMOS output
KEY1 to KEY4
Key data input
10 to 13
VDD
Logic power
14, 38
Logic power supply
VSS
Logic ground
7, 43
Connect this pin to system GND.
VEE
Pull-down level
27
SW1 and SW4
Switch input
1 and 4
RMIN
Remote Control Input
2
Input pin
SKEY
Standby Key Input
3
Input pin
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Description
Input serial data at rising edge of shift clock,
starting from the low order bit.
Output serial data at the falling edge of the shift
clock, starting from low order bit. This is N-ch
open-drain output pin.
Initializes serial interface at the rising or falling
edge of the AD7312. It then waits for reception of
a command. Data input after STB falling is
processed as a command. While command data
is processed, current processing is stopped, and
the serial interface is initialized. While STB is
high, CLK is ignored.
Reads serial data at the rising edge, and outputs
data at the falling edge.
Connect resistor in between this pin and Vdd to
set up the oscillation frequency.
Data input to these pins is latched at the end of
the display cycle.
Driver power supply
These pins constitute a 2-bit general-purpose
input port.
Rev. A2 Dec 29, 2003
3/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Ordering Information
AD7312 X X X
Package
Lead
Packing
Q: QFP-44L
L: LQFP-44L
Blank: Normal
F: Lead Free
Blank : Tray
CLK
STB
2
2-bit
latch
Key data memory
(4× 6)
2-bit latch
Remote Control
decoder
REBUF
2
Segment
driver
5
5
5
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Seg1/KS1
Seg6/KS6
Seg7
Seg11
Seg12/Grid11
Seg16/Grid7
5
11
6
PSV
LED1,4
Segment/grid
driver
SW1
SW4
4
16 11
Grid driver
OSC
KEY1
to
KEY4
Timing generator
key scan
6
Data selector
R
16-bit
output latch
STB
Display memory
16 bits×
11 Words
11-bit shift register
Serial
I/F
CLK
VDD
Dimming
circuit
Command
decoder
DIN
DOUT
Segment/
key scan
Block Diagram
Grid1
Grid6
VDD VSS VEE
(+5V) (0V) (-30V)
Rev. A2 Dec 29, 2003
4/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Absolute Maximum Ratings (TA=25oC,VSS=0V )
Parameter
Logic Supply Voltage
Driver Supply Voltage
Logic Input Voltage
VFD Driver Output Voltage
LED Driver Output Current
Symbol
VDD
VEE
VI1
VO2
IO1
VFD Driver Output Current
IO2
Operating Ambient Temperature
Storage Temperature
Rating
-0.5 to +7.0
VDD +0.5 to VDD -40
-0.5 to VDD +0.5
VEE-0.5 to VDD +0.5
+15
-40 (grid)
-15 (segment)
-25 to +85
-50 to +125
TOPT
TSTG
Unit
V
V
V
V
mA
mA
o
C
C
o
Operating Conditions (TA=0 to +70 oC,VSS=0V)
Parameter
Logic Supply Voltage
High-Level Input Voltage
Low-Level Input Voltage
Driver Supply Voltage
Symbol
VDD
VIH
VIL
VEE
Conditions
Min.
4.5
0.7·VDD
0
0
Typ.
5
Max.
5.5
VDD
0.3·VDD
VDD-35
Unit
V
V
V
V
DC Characteristics (TA=0 to 70 oC, VDD=4.5 to 5.5V, VSS=0V, VEE=VDD-35V)
Parameter
High-Level Output Voltage
Low-Level Output Voltage
Low-Level Output Voltage
High-Level Output Current
Symbol
VOH1
VOL1
VOL2
IOH21
High-Level Output Current
IOH22
Driver Leakage Current
Output Pull-Down Resistor
High-Level Input Voltage
Low-Level Input Voltage
IOLEAK
RL
VIH
VIL
Conditions
LED1/LED4, IOH1=-1mA
LED1/LED4, IOL1=12mA
DOUT, IOL2=2mA
VO=VDD-2V, Seg1 to Seg11
VO=VDD-2V, Grid 1 to Grid6
Seg12/Grid11 to Seg16/Grid7
VO=VDD-35V, driver off
Driver output
Min.
0.9VDD
-3
Unit
V
V
V
mA
-15
mA
50
0.7VDD
Typ.
Max.
1
0.4
100
-10
150
0.3VDD
μA
kΩ
V
V
AC Characteristics (Ta=0 to +70 oC,VDD=4.5 to 5.5 V, VEE=-30V)
Parameter
Oscillation Frequency
Maximum Clock Frequency
Clock Pulse Width
Strobe Pulse Width
Data Setup Time
Data Hold Time
Clock-Strobe Time
Wait Time
Propagation delay time
Rise time
Fall time
Note : Refer to page 8.
Symbol
fOSC
fmax.
PWCLK
PWSTB
tSETUP
tHOLD
tCLK-STB
tWAIT
tPHZ
tPZL
tTZH
tTHZ
Conditions
R=51 kΩ
Duty=50%
CLK↑→STB↑
CLK↑→CLK↓(Note)
CLK→DOUT
CL=15pF,RL=10 kΩ
CL=300pF
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Segn,Gridn
Min.
350
Typ.
500
Max.
650
1
500
1
100
100
1
1
300
100
2
160
Unit
KHZ
MHZ
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
Rev. A2 Dec 29, 2003
5/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Timing Diagram
(1) Serial Communication Format
Reception (command/write data)
If data continues
STB
b0
DIN
CLK
b1
1
b2
2
b6
3
b7
7
8
Transmission (read data)
STB
DIN
b0
b1
b2
b3
b4
b5
b6
b7
CLK
1
2
3
4
5
6
7
8
DOUT
A data read command is set.
tWAIT (Note)
1
2
3
4
5
6
b0
b1
b2
b3
b4
b5
Data is read.
Because the DOUT pin is an N-ch, open-drain output pin, be sure to connect an external pull-up resistor to
this pin (1kΩ to 10 kΩ).
Note : When data is read, a wait time tWAIT of 1 μs is necessary since the rising of the eighth clock that has set the command, until the
falling of the first clock that has read the data.
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www.anachip.com.tw
Rev. A2 Dec 29, 2003
6/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
(2) Key Scanning and Display Timing
On cycle of key scanning consists of one frame, and data in a 6× 4 matrix is stored in RAM.
TDISP ≅ 500μs
SEG Output
DIG1
Key scan data
DIG2
DIGn
DIG3
1 23 456
DIG1
Grid1
Grid2
1/16
TDISP
Grid3
Gridn
1 frame = TDISP× (n+1)
Switching characteristic waveforms
fosc
OSC
50%
PWSTB
STB
PWCLK
PWCLK
tSETUP
tHOLD
tCLK-STB
CLK
DIN
tPZL
tPLZ
DOUT
tTZH
tTHZ
Sn/Gn
90%
10%
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Rev. A2 Dec 29, 2003
7/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Applications
Updating display memory by incrementing address
STB
CLK
DIN
Command 1
Command 2
Command 3
Data 1
Data n
Command 4
Command 1: sets display mode
Command 2: sets data(write data to display memory)
Command 3: sets address
Data 1 to n: transfers display data (22bytes max.)
Command 4: controls display
Updating specific display memory and write registers
STB
CLK
DIN
Command 1
Command 2
Data
Command 2
Data
Command 1: sets data
Command 2: sets address
Data: display data
Anachip Corp.
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Rev. A2 Dec 29, 2003
8/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Reading specific registers
STB
CLK
DIN
Command 1
Command 2
Data1
Command2
Address2
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Data2
Commandn
Addressn
Rev. A2 Dec 29, 2003
9/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Package Information
(1) Package Type: QFP-44L
Dimension in millimeter (mm.)
13.2 ± 0.5
2.7(MAX.)
10.0 ± 0.5
33
23
34
22
10.0 13.2
± 0.5 ± 0.5
44
12
1
11
0.15 TYP.
1.6 TYP.
0.3 TYP.
0.8 TYP.
0.88 TYP.
Anachip Corp.
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Rev. A2 Dec 29, 2003
10/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
(2) Package Type: LQFP-44L
( Top View )
e
E
E1
b
PIN 1 INDENT
12o(4X)
C
D1
A
A2
D
R0.08 MIN.
A1
y
DETAIL A
L
θ
0.25
GAGE PLANE
L1
DETAIL A
Symbol
A
A1
A2
b
C
E
E1
D
D1
e
L
L1
θ
y
Dimensions In Millimeters
Min.
Nom.
Max.
1.60
0.05
0.10
0.15
1.35
1.40
1.45
0.30
0.37
0.45
0.09
0.20
11.50
12.00
12.50
9.50
10.00
10.50
11.80
12.00
12.20
9.90
10.00
10.10
0.80
0.45
0.60
0.75
1.00
0˚
3.5˚
7˚
0.00
0.08
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Dimensions In Inches
Min.
Nom.
Max.
0.063
0.002
0.004
0.006
0.053
0.055
0.057
0.012
0.015
0.018
0.004
0.008
0.453
0.472
0.492
0.374
0.394
0.413
0.465
0.472
0.480
0.390
0.394
0.398
0.031
0.018
0.024
0.030
0.039
0˚
3.5˚
7˚
0.000
0.003
Rev. A2 Dec 29, 2003
11/12
AD7312
1/4 to 1/11 Duty VFD Controller/Driver & Standby Master/Slave
(Preliminary)
Marking Information
Top view
Part Number
AC
AD7312 X
XX XX XXX
Logo
Blank: Normal
F: Lead Free Package
ID code: internal
Nth week: 01~52
Year: "01" = 2001
"02" = 2002
QFP44/LQFP44
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Rev. A2 Dec 29, 2003
12/12
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