ON FAN73896 3-phase half-bridge gate-drive ic Datasheet

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FAN73896
3-Phase Half-Bridge Gate-Drive IC
Features
Description


Floating Channel for Bootstrap Operation to +600 V

Extended Allowable Negative VS Swing to -9.8 V for
Signal Propagation at VDD=VBS=15 V










Output In- Phase with Input Signal
Typically 350 mA/650 mA Sourcing/Sinking
Current-Driving Capability for All Channels
Over-Current Shutdown Turns Off All Six Drivers
Matched Propagation Delay for All Channels
3.3 V and 5.0 V Input Logic Compatible
Adjustable Fault-Clear Timing
Built-in Advanced Input Filter
Built-in Shoot-Through Prevention Logic
Built-in Soft Turn-Off Function
Common-Mode dv/dt Noise-Canceling Circuit
Built-in UVLO Functions for All Channels
The FAN73896 is a monolithic three-phase half-bridge
gate-drive IC designed for high-voltage, high-speed,
driving MOSFETs and IGBTs operating up to +600 V.
Fairchild’s high-voltage process and common-mode
noise-canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS = -9.8 V (typical) for VBS =15 V.
The protection functions include under-voltage lockout
and inverter over-current trip with an automatic faultclear function. Over-current protection that terminates all
six outputs can be derived from an external currentsense resistor. An open-drain fault signal is provided to
indicate that an over-current or under-voltage shutdown
has occurred. The UVLO circuits prevent malfunction
when VDD and VBS are lower than the threshold voltage.
Output drivers typically source and sink 350 mA and
650 mA, respectively; which is suitable for three-phase
half-bridge applications in motor drive systems.
Applications


3-Phase Motor Inverter Driver


Industrial Inverter – Sewing Machine, Power Tool
Air Conditioner, Washing Machine, Refrigerator,
Dish Washer
Figure 1. 28-SOIC
General-Purpose Three-Phase Inverter
Ordering Information
Part Number
(1)
FAN73896MX
Package
28-Lead, Small Outline Integrated Circuit, (SOIC)
Operating
Temperature
Packing
Method
-40 to +125°C
Tape & Reel
Note:
1. These devices passed wave-soldering test by JESD22A-111.
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
www.fairchildsemi.com
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
October 2015
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Typical Application Diagram
VDD
5V Line
1
VDD
VB1 28
UU
2
HIN1
HO1 27
Uup
VU
3
HIN2
VS1 26
VS1
WU
4
HIN3
UL
5
LIN1
VL
6
LIN2
WL
7
LIN3
8
FO
9
CS
CONTROL
10 EN
11
FAN73896MX
3-Phase
BLDC Motor
Controller
VMOTOR
VB2 24
Uup
HO2 23
Vup
VS2 22
VS2
Vup
Wup
VS1
VB3 20
U
HO3 19
RCIN
VS3 18
VS3
LO1 16
Udn
LO2 15
Vdn
LO3 14
Wdn
CRCIN
12 VSS
3-Phase Inverter
Wup
V
VS2
W
VS3
Udn
Vdn
Wdn
13 COM
RCS
Figure 2. 3-Phase BLDC Motor Drive Application
Internal Block Diagram
VB1
HIN1
10K
UVLO
HIN2
10K
50K
HIN3
INPUT NOISE
FILTER
{TFLTIN=250ns}
Q
S
HO1
VS1
VDD
UVLO
SHOOT THOUGH
PREVENTION
ULIN
VSS-COM
LEVELSHIFTER
DRIVER
10K
R R
VDD
10K
50K
LIN1
NOISE
CANCELLER
DRIVER
UHIN
PULSE
GENERATOR
50K
DELAY
LO1
COM
50K
LIN2
10K
DEAD-TIME
{DT=320ns}
U Phase Driver
UVLO
ISOFT
50K
VB2
VDD
LIN3
10K
50K
VHIN
ENABLE INPUT
FILTER
{TFLTEN=250ns}
VH
V Phase Driver
VLIN
VS2
LO2
FO
COM
ISOFT
VSS
EN
VB3
VDD
LEB
WHIN
WLIN
HO3
W Phase Driver
VS3
ENABLE
150K
LO3
COM
ISOFT
VDD_UVLO
SOFT-OFF
VREF
CS
iRCIN
VRCIN,TH = 3.3V
VRCIN,HYS= 0.7V
RCIN
CS_COMP
Q
LATCH
S
LEB
R
100K
0.5V
3.3V
Protection Circuit
Figure 3. Functional Block Diagram
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
www.fairchildsemi.com
2
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
17 NC
16 LO1
11
12
13
14
RCIN
VSS
COM
LO3
15 LO2
18 VS3
10
EN
19 HO3
9
CS
21 NC
20 VB3
8
FO
22 VS2
7
LIN3
23 HO2
6
LIN2
24 VB2
5
LIN1
25 NC
26 VS1
28 VB1
27 HO1
Pin Configuration
1
2
3
4
VDD
HIN1
HIN2
HIN3
FAN73896MX
Figure 4. Pin Assignments
Pin Definitions
Pin
Name
1
VDD
2
HIN1
Logic Input 1 for high-side gate 1 driver.
3
HIN2
Logic Input 2 for high-side gate 2 driver.
4
HIN3
Logic Input 3 for high-side gate 3 driver.
5
LIN1
Logic Input 1 for low-side gate 1 driver.
6
LIN2
Logic Input 2 for low-side gate 2 driver.
7
LIN3
Logic Input 3 for low-side gate 3 driver.
8
FO
CS
Fault output with open drain (indicates over-current and low-side under-voltage).
10
EN
Logic input for shutdown functionality.
11
RCIN
12
VSS
13
COM
Low-side driver return.
14
LO3
Low-side gate driver 3 output.
15
LO2
Low-side gate driver 2 output.
16
LO1
Low-side gate driver 1 output.
17, 21, 25
NC
No connect.
18
VS3
High-side driver 3 floating supply offset voltage.
19
HO3
High-side driver 3 gate driver output.
20
VB3
High-side driver 3 floating supply.
22
VS2
High-side driver 2 floating supply offset voltage.
23
HO2
High-side driver 2 gate driver output.
24
VB2
High-side driver 2 floating supply.
26
VS1
High-side driver 1 floating supply offset voltage.
27
HO1
High-side driver 1 gate driver output.
28
VB1
High-side driver 1 floating supply.
9
Description
Logic and low-side gate driver power supply voltage.
Analog input for over-current shutdown.
An external RC network input used to define the fault-clear delay.
Logic ground.
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
www.fairchildsemi.com
3
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
Parameter
Min.
Max.
Unit
VS
High-Side Floating Offset Voltage
VB1,2,3-25
VB1,2,3+0.3
V
VB
High-Side Floating Supply Voltage
-0.3
625.0
V
VDD
Low-Side and Logic-Fixed supply voltage
-0.3
25.0
V
VHO
High-Side Floating Output Voltage VHO1,2,3
VS1,2,3-0.3
VB1,2,3+0.3
V
VLO
Low-Side Floating Output Voltage VLO1,2,3
-0.3
VDD+0.3
V
-0.3
5.5
V
-0.3
VDD+0.3
V
±50
V/ns
VIN
Input Voltage (HINx, LINx, CS, and EN)
VFO
Fault Output Voltage ( FO )
dVS/dt
(2)
Allowable Offset Voltage Slew Rate
(3,4)
PD
Power Dissipation
1.4
W
θJA
Thermal Resistance
70
°C/W
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
150
°C
-55
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
Notes:
2. All input voltage (HINx, LINx, CS, and EN) are referenced to VSS and do not exceed maximum voltage rating.
3. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). Refer to the following standards:
JESD51-2: Integral circuit’s thermal test method environmental conditions, natural convection;
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
4. Do not exceed maximum power dissipation (PD) under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VS1,2,3+10
VS1,2,3+20
V
VB1,2,3
High-Side Floating Supply Voltage
VS1,2,3
High-Side Floating Supply Offset Voltage
6-VDD
600
V
VDD
Low-Side and Logic Fixed Supply Voltage
12
20
V
VHO1,2,3
High-Side Output Voltage
VS1,2,3
VB1,2,3
V
VLO1,2,3
Low-Side Output Voltage
COM
VDD
V
VFO
Fault Output Voltage ( FO )
VSS
VDD
V
VCS
Current-Sense Pin Input Voltage
VSS
5
V
VIN
Logic Input Voltage (HIN1,2,3 and LIN1,2,3 )
VSS
5
V
COM
Low-Side driver return
-5
5
V
TA
Ambient Temperature
-40
+125
°C
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
www.fairchildsemi.com
4
VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to
VSS and are applicable to all six channels. The V O and IO parameters are referenced to VS1,2,3 and COM and are
applicable to the respective output leads: HO1,2,3 and LO1,2,3. The V DDUV parameters are referenced to VSS. The
VBSUV parameters are referenced to VS1,2,3.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Low-Side Power Supply Section
A
IQDD
Quiescent VDD Supply Current
VLIN1,2,3=0 V or 5V, EN=0 V
250
400
IPDD
Operating VDD Supply Current
CLOAD=1nF, fLIN1,2,3=20 kHz,
rms Value
550
750
VDDUV+
VDD Supply Under-Voltage Positive-Going
Threshold
VDD=Sweep
9.7
11.0
12.0
V
VDDUV-
VDD Supply Under-Voltage Negative-Going
Threshold
VDD=Sweep
9.2
10.5
11.4
V
VDDHYS
VDD Supply Under-Voltage Lockout
Hysteresis
VDD=Sweep
0.5
A
V
Bootstrapped Power Supply Section
VBSUV+
VBS Supply Under-Voltage Positive-Going
Threshold
VBS1,2,3=Sweep
9.7
11.0
12.0
V
VBSUV-
VBS Supply Under-Voltage Negative-Going
Threshold
VBS1,2,3=Sweep
9.2
10.5
11.4
V
VBSHYS
VBS Supply Under-Voltage Lockout
Hysteresis
VBS1,2,3=Sweep
ILK
Offset Supply Leakage Current
VB1,2,3=VS1,2,3=600 V
IQBS
Quiescent VBS Supply Current
VHIN1,2,3=0 V or 5 V, EN=0 V
10
IPBS
Operating VBS Supply Current
CLOAD=1 nF, fHIN1,2,3=20 kHz,
rms Value
200
0.5
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Electrical Characteristics
V
10
A
50
80
A
320
480
A
Gate Driver Output Section
VOH
High-Level Output Voltage, VBIAS-VO
IO=0 mA (No Load)
100
mV
VOL
Low-Level Output Voltage, VO
IO=0 mA (No Load)
100
mV
IO+
Output HIGH Short-Circuit Pulse Current
IO-
Output LOW Short-Circuit Pulse Current
VS
Allowable Negative VS Pin Voltage for HIN
Signal Propagation to HO
(5)
(5)
VO=15 V, VIN=0 V with
PW10 µs
250
350
mA
VO=0 V, VIN=5 V with PW10 µs
500
650
mA
-9.8
-9.0
V
Logic Input Section
VIH
Logic "1" Input Voltage HIN1,2,3, LIN1,2,3
VIL
Logic "0" Input Voltage HIN1,2,3, LIN1,2,3
2.5
IIN+
Logic Input Bias Current (HO=LO=HIGH)
VIN=5 V
IIN-
Logic Input Bias Current (HO=LO=LOW)
VIN=0 V
RIN
Logic Input Pull-Down Resistance
77
35
V
100
50
0.8
V
143
A
2
A
65
K
Enable Control Section (EN)
VEN+
Enable Positive-Going Threshold Voltage
VEN-
Enable Negative-Going Threshold Voltage
IEN+
Logic Enable “1” Input Bias Current
VEN=5 V (Pull-Down=150 K)
IEN-
Logic Enable “0” Input Bias Current
VEN=0 V
REN
Logic Input Pull-Down Resistance
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
2.5
15
100
V
33
150
0.8
V
50
A
2
A
333
K
www.fairchildsemi.com
5
VBIAS (VDD, VBS1,2,3) = 15.0 V and TA = 25°C unless otherwise specified. The VIN and IIN parameters are referenced to
VSS and are applicable to all six channels. The V O and IO parameters are referenced to VS1,2,3 and COM and are
applicable to the respective output leads: HO1,2,3 and LO1,2,3. The V DDUV parameters are referenced to VSS. The
VBSUV parameters are referenced to VS1,2,3.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Over-Current Protection Section
VCSTH+
Over-Current Detect Positive Threshold
VCSTH-
Over-Current Detect Negative Threshold
VCSHYS
Over-Current Detect Hysteresis
ICSIN
Short-Circuit Input Current
ISOFT
Soft Turn-Off Sink Current
450
500
550
440
mV
60
VCSIN=1 V
mV
mV
5
10
15
A
25
40
55
mA
2.7
3.3
3.9
V
Fault Output Section
VRCINTH+ RCIN Positive-Going Threshold Voltage
VRCINTH-
RCIN Negative-Going Threshold Voltage
VRCINHYS RCIN Hysteresis Voltage
(5)
(5)
V
0.7
V
IRCIN
RCIN Internal Current Source
CRCIN=2 nF
VFOL
Fault Output Low Level Voltage
VCS=1 V, IFO=1.5 mA
0.2
0.5
V
RCIN On Resistance
IRCIN=1.5 mA
50
75
100

Fault Output On Resistance
IFO=1.5 mA
90
130
170

RDSRCIN
RDSFO
3
2.6
5
7
µA
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Electrical Characteristics
Note:
5. These parameters are guaranteed by design.
Dynamic Electrical Characteristics
TA=25C, VBIAS (VDD, VBS1,2,3) = 15.0 V, VS1,2,3 = COM, CRCIN=2 nF, and CLoad = 1000 pF unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
tON
Turn-On Propagation Delay
VLIN1,2,3=VHIN1,2,3=5 V, VS1,2,3=0 V
350
500
650
ns
tOFF
Turn-Off Propagation Delay
VLIN1,2,3=VHIN1,2,3=0 V, VS1,2,3=0 V
350
500
650
ns
tR
Turn-On Rise Time
VLIN1,2,3=VHIN1,2,3=5 V
20
50
100
ns
tF
Turn-Off Fall Time
VLIN1,2,3=VHIN1,2,3=0 V
10
30
80
ns
tEN
Enable LOW to Output Shutdown Delay
400
500
600
ns
tCSBLT
CS Pin Leading-Edge Blanking Time
400
650
850
ns
tCSFO
Time from CS Triggering to FO
From VCSC=1 V to FO Turn-Off
850
1300
ns
tCSOFF
Time from CS Triggering to low-side Gate
Outputs Turn-Off
From VCSC=1 V to Starting Gate
Turn-Off
850
1300
ns
tFLTIN
Input Filtering Time
250
330
ns
1.30
2.35
ms
320
400
ns
50
ns
50
ns
100
ns
tFLTCLR
DT
MDT
MT
PM
(6)
(HINx, LINx, EN)
170
Fault-Clear Time
Dead Time
230
Dead-Time Matching (All Six Channels)
Delay Matching (All Six Channels)
Output Pulse-Width Matching
(9)
(7)
(8)
PW IN > 1 µs
50
Notes:
6. The minimum width of the input pulse should exceed 500 ns to ensure the filtering time of the input filter is exceeded.
7. MDT is defined as | DT1-DT2 | referenced to 0.
8. MT is defined as an absolute value of matching delay time between High-side and Low-side.
9. PM is defined as an absolute value of matching pulse-width between Input and Output.
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
www.fairchildsemi.com
6
650
600
600
550
550
tOFF [ns]
tON [ns]
650
500
500
450
450
400
350
-40
400
High-Side
Low-Side
-20
0
20
40
60
80
100
350
-40
120
High-Side
Low-Side
-20
0
Temperature [°C]
100
80
90
70
80
60
70
50
60
50
80
100
120
40
20
30
-20
0
20
40
60
80
100
High-Side
Low-Side
10
High-Side
Low-Side
0
-40
120
-20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 7. Turn-On Rise Time vs. Temperature
Figure 8. Turn-Off Fall Time vs. Temperature
2.0
600
1.8
tFLTCLR [ms]
550
tEN [ns]
60
30
40
500
450
400
-40
40
Figure 6. Turn-Off Propagation Delay
vs. Temperature
tF [ns]
tR [ns]
Figure 5. Turn-On Propagation Delay
vs. Temperature
20
-40
20
Temperature [°C]
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Typical Characteristics
1.6
1.4
1.2
-20
0
20
40
60
80
100
1.0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 9. Enable LOW to Output Shutdown Delay
vs. Temperature
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
-20
Figure 10. Fault-Clear Time vs. Temperature
www.fairchildsemi.com
7
50
350
25
MDT [ns]
DT [ns]
400
300
250
0
-25
DT1
DT2
200
-40
-20
0
20
40
60
80
100
-50
-40
120
-20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 11. Dead Time vs. Temperature
Figure 12. Dead-Time Matching vs. Temperature
50
-7
-8
30
20
-9
VS [V]
Delay Matching [ns]
40
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
10
0
-10
-10
-11
-20
-30
-50
-40
-12
MTON
MTOFF
-40
-20
0
20
40
60
80
100
-13
-40
120
-20
0
Temperature [°C]
20
40
60
80
100
120
Temperature [°C]
Figure 13. Delay Matching vs. Temperature
Figure 14. Allowable Negative VS Voltage
vs. Temperature
400
100
350
80
IQBS [A]
IQDD [A]
300
250
200
60
40
150
20
100
50
-40
-20
0
20
40
60
80
100
0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 15. Quiescent VDD Supply Current
vs. Temperature
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
-20
Figure 16. Quiescent VBS Supply Current
vs. Temperature
www.fairchildsemi.com
8
700
600
600
500
500
IPBS [A]
IPDD [A]
700
400
400
300
300
200
200
100
-40
-20
0
20
40
60
80
100
100
-40
120
-20
0
Temperature [°C]
12.0
11.5
11.5
11.0
11.0
10.5
80
100
120
10.0
-20
0
20
40
60
80
100
9.5
-40
120
-20
0
20
40
60
80
100
120
Temperature [°C]
Figure 19. VDD UVLO+ vs. Temperature
Figure 20. VDD UVLO- vs. Temperature
12.0
11.5
11.5
11.0
VBSUV- [V]
VBSUV+ [V]
60
10.5
Temperature [°C]
11.0
10.5
10.0
-40
40
Figure 18. Operating VBS Supply Current
vs. Temperature
VDDUV- [V]
VDDUV+ [V]
Figure 17. Operating VDD Supply Current
vs. Temperature
10.0
-40
20
Temperature [°C]
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
10.5
10.0
-20
0
20
40
60
80
100
9.5
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 21. VBS UVLO+ vs. Temperature
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
-20
Figure 22. VBS UVLO- vs. Temperature
www.fairchildsemi.com
9
20
20
High-Side
Low-Side
12
8
High-Side
Low-Side
16
VOL [mV]
VOH [mV]
16
4
12
8
4
0
-40
-20
0
20
40
60
80
100
0
-40
120
-20
0
Figure 23. High-Level Output Voltage
vs. Temperature
40
60
80
100
120
Figure 24. Low-Level Output Voltage
vs. Temperature
3.0
3.0
2.5
VIL [V]
2.5
VIH [V]
20
Temperature [°C]
Temperature [°C]
2.0
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
2.0
1.5
1.5
1.0
1.0
-40
-20
0
20
40
60
80
100
0.5
-40
120
-20
0
Temperature [°C]
Figure 25. Logic HIGH Input Voltage
vs. Temperature
40
60
80
100
120
Figure 26. Logic LOW Input Voltage
vs. Temperature
160
2.0
140
1.5
IIN- [A]
IIN+ [A]
20
Temperature [°C]
120
1.0
100
0.5
80
60
-40
-20
0
20
40
60
80
100
0.0
-40
120
Temperature [°C]
0
20
40
60
80
100
120
Temperature [°C]
Figure 27. Logic Input HIGH Bias Current
vs. Temperature
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
-20
Figure 28. Logic Input LOW Bias Current
vs. Temperature
www.fairchildsemi.com
10
200
80
180
REN [K]
RIN [K]
100
60
40
20
0
10
160
140
120
12
14
16
18
100
10
20
12
14
Supply Voltage [V]
16
18
20
Supply Voltage [V]
Figure 29. Input Pull-Down Resistance
vs. Supply Voltage
Figure 30. Enable Pin Pull-Down Resistance
vs. Supply Voltage
400
100
350
80
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Typical Characteristics (Continued)
IQBS [A]
IQDD [A]
300
250
200
60
40
150
20
100
50
10
12
14
16
18
0
10
20
12
14
Supply Voltage [V]
700
700
600
600
500
500
400
300
200
200
16
18
100
12
20
Supply Voltage [V]
14
16
18
20
Supply Voltage [V]
Figure 33. Operating VDD Supply Current
vs. Supply Voltage
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
20
400
300
14
18
Figure 32. Quiescent VBS Supply Current
vs. Supply Voltage
IPBS [A]
IPDD [A]
Figure 31. Quiescent VDD Supply Current
vs. Supply Voltage
100
12
16
Supply Voltage [V]
Figure 34. Operating VBS Supply Current
vs. Supply Voltage
www.fairchildsemi.com
11
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Switching Time Definitions
HINx
50%
50%
(LINx)
tON
tR
tOFF
90%
tF
90%
HOx
(LOx)
10%
10%
Figure 35. Switching Time Waveform Definitions
A
B
C
E
D
F
HINx
LINx
EN
Shutdown
CS
Shutdown
FO
VRCIN
HOx
Shoot-Through
Prevent
LOx
Shoot-Through
Prevent
Over-Current
Protection
Figure 36. Input / Output Timing Diagram
Interval B
CS
VCS,TH+
Interval C
VCS,TH+
50%
FO
50%
tCSFO
VRCIN,TH
VRCIN
tFLTCLR
90%
Any
Output
tCSOFF
Figure 37. Detailed View of B and C Intervals During Over-Current Protection
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
www.fairchildsemi.com
12
1. Dead Time
Dead time is automatically inserted whenever the dead
time of the external two input signals (between HINx
and LINx signals) is shorter than internal fixed dead
times (DT1 and DT2). Otherwise, external dead times
larger than internal dead times are not modified by the
gate driver and internal dead-time waveform definition is
shown in Figure 38.
2.2 Shoot-Through Protection
The shoot-through protection circuitry prevents both
high- and low-side switches from conducting at the
same time, as shown Figure 40.
HINx
LINx
Shoot-Through
Prevent
HINx
50%
50%
LINx
HOx
After DT
50%
50%
LOx
After DT
LOx
DT1
HOx
DT2
50%
Example A
50%
HINx
Figure 38. Internal Dead-Time Definitions
2. Protection Function
LINx
2.1 Fault Out ( FO ) and Under-Voltage Lockout
The high- and low-side drivers include under-voltage
lockout (UVLO) protection circuitry that monitors the
supply voltage for VDD and VBS independently. It can be
designed to prevent malfunction when VDD and VBS are
lower than the specified threshold voltage. The UVLO
hysteresis prevents chattering during power-supply
transitions. Moreover, the fault signal (power supply
voltage FO ) goes to LOW state to operate reliably
during power-on events when the power supply (VDD) is
below the under-voltage lockout high threshold voltage
for the circuit (during t1 ~ t2). The UVLO circuit is not
otherwise activated; shown Figure 39.
UVLO+
UVLOVDD < 3.5V
VDD
Lower Voltage
FO
FAN73896 — 3-Phase Half-Bridge Gate-Drive IC
Applications Information
Shoot-Through
Prevent
HOx
LOx
Example B
Figure 40. Shoot-Through Protection
An interlock function is a device used to prevent both
high- and low-side switches from conducting at the
same time as shown in Figure 41. In most applications
an interlock is used to help prevent a device from
harming its operator or damaging itself by when two
input signals of a same leg are activated
simultaneously, only one output is activated.
Lower Voltage
VRCINTH+
HINx
RCIN
LINx
LO
t0 t1
t2
t3
t4
Figure 39. Waveforms for Under-Voltage Lockout
HOx
LOx
S1
S1 : High-side first
S2 : Low-side noise
S3 : High-side noise
S4 : Low-side first
S5 : In-phase mode
S2
S3
S4
S5
à First input output mode
à No LOx output mode
à No HOx output mode
à First input output mode
à No HOx output
Figure 41. Interlock Function
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0
www.fairchildsemi.com
13
EN
VDD
LEB
Input
Stage ON
150K
RFO
To low side output
FO
ISOFT
Fault
SOFT-OFF
VREF
To COM
VDD_UVLO
iRCIN
RCIN
VRCIN,TH = 3.3V
VRCIN,HYS= 0.7V
CS_COMP
Q
Latch
S
LEB
R
100K
0.5V
3.3V
CRCIN
CS
VSS
Protection Circuit
50%
Figure 43. Over-Current Protection
EN
tEN
90%
HOx
LOx
Figure 42. Output Enable Timing Waveform
2.4 Fault-Out ( FO ) and Over-Current Protection
FAN73896 provides an integrated fault output (FO) and
an adjustable fault-clear timer (tFLTCLR). There are two
situations that cause the gate driver to report a fault via
the FO pin. The first is an under-voltage condition of
low-side gate driver supply voltage (VDD) and the
second is when the current-sense pin (CS) recognizes a
fault. If a fault condition occurs, the FO pin is internally
pulled to COM, the fault-clear timer is activated, and all
outputs (HO1, 2, 3 and LO1, 2, 3) of the gate driver are
turned off. The fault output stays LOW until the fault
condition has been removed and the fault-clear timer
expires. Once the fault-clear timer expires, the voltage
on the FO pin returns to pull-up voltage.
The fault-clear time (tFLTCLR) is determined by an internal
current source (IRCIN=5 A) and an external CRCIN at the
RCIN pin, as shown as:
t FLTCLR 
C RCIN  VRCIN,TH
I RCIN
[s ]
(1)
The RDSRCIN of the MOSFET is a characteristic
discharge curve with respect to the external capacitor
CRCIN. The time constant is defined by the external
capacitor CRCIN and the RDSRCIN of the MOSFET.
The output of current-sense comparator (CS_COMP)
passes a noise filter, which inhibits an over-current
shutdown caused by parasitic voltage spikes of VCS.
This corresponds to a voltage level at the comparator of
VCSTH+ - VCSHYS= 500 mV - 60 mV =440 mV, where
VCSHYS=60 mV is the hysteresis of the current
comparator (CS_COMP), as shown in Figure 43.
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0.
Figure 44 shows the waveform definitions of RCIN, FO ,
and the low-side driver; which uses a soft turn-off
method when an under-voltage condition of the low-side
gate driver supply voltage (VDD) or the current-sense pin
(CS) recognizes a fault. If a fault condition occurs, the
FO Pin is internally pulled to COM and all outputs
(HO1,2,3 and LO1,2,3) of the gate driver are turned off.
Low-side outputs decline linearly by the internal sink
current source (ISOFT=40mA) for soft turn-off, as shown
in Figure 44.
LINx
Leading Edge
Blanking Time
VCSC
440mV
FAN73896 — 3-Phase Half-Bridge Gate-Driver IC
2.3 Enable Input
When the EN pin is in HIGH state, the gate driver
operates normally. When a condition occurs that should
shut down the gate driver, the EN pin should be LOW.
The enable circuitry has an input filter; the minimum
input duration is specified by tFLTIN (typically 250 ns).
500mV
tCSBLT
FO
tFLTCLR
tCSFO
VRCINTH+
VRCIN
LO
tCSOFF
90%
Figure 44. RCIN and Fault-Clear Waveform Definition
3. Noise Filter
3.1 Input Noise Filter
Figure 45 shows the input noise filter method, which has
symmetry duration between the input signal (t INPUT) and
the output signal (tOUTPUT) and helps to reject noise
spikes and short pulses. This input filter is applied to the
HINx, LINx, and EN inputs. The upper pair of waveforms
(Example A) shows input signal duration (tINPUT) much
longer than input filter time (tFLTIN); it is approximately
the same duration between the input signal time (tINPUT)
and the output signal time (tOUTPUT). The lower pair of
waveforms (Example B) shows an input signal time
(tINPUT) slightly longer than input filter time (tFLTIN); it is
approximately the same duration between input signal
time (tINPUT) and the output signal time (tOUTPUT).
www.fairchildsemi.com
14
Figure 47 shows the characteristics of the input filters
while receiving narrow ON and OFF pulses. If input
signal pulse duration, PW IN, is less than input filter time,
tFLTIN; the output pulse, PW OUT, is zero. The input signal
is rejected by input filter. Once the input signal pulse
duration, PW IN, exceeds input filter time, tFLTIN, the
output pulse durations, PW OUT, matches the input pulse
durations, PW IN. FAN73896 input filter time, tFLTIN, is
about 250 ns for the high- and low-side outputs.
tFLTIN
tINPUT
tOUTPUT
OUTx
1000
tFLTIN
Input Pulse
Output Pulse
900
tINPUT
tOUTPUT
Output duration is
same as input duration
OUTx
Figure 45. Input Noise Filter Definition
3.2. Short-Pulsed Input Noise Rejection Method
The input filter circuitry provides protection against
short-pulsed input signals (HINx, LINx, and EN) on the
input signal lines by applied noise signal.
Output Pulse Width [ns]
Example B
INx
700
600
500
400
300
200
100
If the input signal duration is less than input filter time
(tFLTIN), the output does not change states.
Example A and B of the Figure 46 show the input and
output waveforms with short-pulsed noise spikes with a
duration less than input filter time; the output does not
change states.
800
0
100
FAN73896 — 3-Phase Half-Bridge Gate-Driver IC
Example A
INx
200 300 400 500 600 700 800 900 1000
Input Pulse Width [ns]
Figure 47. Input Filter Characteristic of Narrow ON
Example A
INx
tFLTIN
tFLTIN
tFLTIN
tFLTIN
tFLTIN
tFLTIN
OUTx
(LOW)
Example B
INx
OUTx
(HIGH)
Figure 46. Noise Rejecting Input Filter Definition
© 2015 Fairchild Semiconductor Corporation
FAN73896 • Rev.1.0.
www.fairchildsemi.com
15
A
16.51
16.510
28
15
B
10.325
9.400
2.00
1
14
0.51
0.35
1.27
0.635
1.270
0.25
M
0.60
C B A
TOP VIEW
RECOMMENDED LAND PATTERN
2.65 MAX
0.75
0.25
(R0.10)
C
GAGE PLANE
0.10 C
SEATING PLANE
(R0.10)
SIDE VIEW
28
0.25
28
28
SEATING PLANE
0.40~1.27
(1.40)
DETAIL A
SCALE: 2:1
NOTES:
PIN #1
INDICATOR
PIN #1
INDICATOR
A. THIS PACKAGE DOES NOT FULLY CONFORM
TO JEDEC REGISTRATION, MS-013.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
1
OPTION 1
HALF MOON & PIN 1
1
OPTION 2
HALF MOON ONLY
1
PIN #1
INDICATOR
SEE DETAIL A
0.33
0.20
SEATING PLANE
PIN#1 IDENTIFICATION OPTIONS
D. DIMENSIONS DO NOT INCLUDE MOLD
FLASH AND BURRS.
OPTION 3
PIN 1 ONLY
E. LAND PATTERN STANDARD :
SOIC127P1030X265-28N
F. DRAWING FILENAME: MKT-M28Brev4.
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