CY7C1020D 512K (32K x 16) Static RAM Functional Description [1] Features • Pin- and function-compatible with CY7C1020B The CY7C1020D is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected.The input and output pins (IO0 through IO15) are placed in a high-impedance state when: • High speed — tAA = 10 ns • Low active power — ICC = 80 mA @ 10ns • Deselected (CE HIGH) • Low CMOS Standby Power • Outputs are disabled (OE HIGH) — ISB2 = 3 mA • BHE and BLE are disabled (BHE, BLE HIGH) • 2.0V Data Retention • When the write operation is active (CE LOW, and WE LOW) • Automatic power-down when deselected Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A14). • CMOS for optimum speed/power • Independent control of upper and lower bits • Available in Pb-free 44-pin 400-Mil wide Molded SOJ and 44-pin TSOP II packages Reading from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 8 for a complete description of read and write modes. Logic Block Diagram SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K x 16 RAM Array IO0–IO7 IO8–IO15 BHE WE CE OE BLE A14 A12 A13 A8 A9 A10 A11 COLUMN DECODER Note 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05463 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 14, 2010 [+] Feedback CY7C1020D Pin Configuration [2] SOJ/TSOP II Top View NC A3 A2 A1 A0 CE IO0 IO1 IO2 IO3 VCC VSS IO4 IO5 IO6 IO7 WE A4 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE IO15 IO14 IO13 IO12 VSS VCC IO11 IO10 IO9 IO8 NC A8 A9 A10 A11 NC Selection Guide –10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 80 mA Maximum CMOS Standby Current 3 mA Note 2. NC pins are not connected on the die. Document #: 38-05463 Rev. *F Page 2 of 13 [+] Feedback CY7C1020D DC Input Voltage [3] ............................... –0.5V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65C to +150C Latch-Up Current..................................................... >200mA Ambient Temperature with Power Applied............................................. –55C to +125C Operating Range Supply Voltage on VCC to Relative GND [3] ... –0.5V to +6.0V DC Voltage Applied to Outputs in High Z State [3] ................................... –0.5V to VCC + 0.5V Range Ambient Temperature VCC Speed Industrial –40 C to +85 C 5V 0.5V 10 ns Electrical Characteristics (Over the Operating Range) Parameter Description –10 (Industrial) Test Conditions VOH Output HIGH Voltage IOH = –4.0 mA VOL Output LOW Voltage IOL = 8.0 mA VIH Input HIGH Voltage Min Unit Max 2.4 [3] V 0.4 V 2.2 VCC + 0.5V V –0.5 0.8 V VIL Input LOW Voltage IIX Input Load Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VI < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 80 mA 83 MHz 72 mA 66 MHz 58 mA 40 MHz 37 mA ISB1 Automatic CE Power-Down Current—TTL Inputs Max VCC, CE > VIH VIN > VIH or VIN < VIL, f = fmax 10 mA ISB2 Automatic CE Power-Down Current—CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 3 mA Note 3. VIL (min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05463 Rev. *F Page 3 of 13 [+] Feedback CY7C1020D Capacitance [4] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max Unit 8 pF 8 pF TA = 25C, f = 1 MHz, VCC = 5.0V Thermal Resistance [4] Parameter Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions SOJ TSOP II Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 59.52 53.91 C/W 36.75 21.24 C/W AC Test Loads and Waveforms [5] ALL INPUT PULSES 3.0V Z = 50 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 30 pF* 90% 10% 10% GND 1.5V Rise Time: 3 ns (a) (b) Fall Time: 3 ns High-Z characteristics: R1 480 5V OUTPUT INCLUDING JIG AND SCOPE R2 255 5 pF (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05463 Rev. *F Page 4 of 13 [+] Feedback CY7C1020D Switching Characteristics (Over the Operating Range) [6] Parameter Description –10 (Industrial) Min Max Unit Read Cycle tpower [7] VCC(typical) to the first access 100 s tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 ns tDOE OE LOW to Data Valid 5 ns OE LOW to Low Z tLZOE [9] OE HIGH to High Z tHZOE CE LOW to Low Z tLZCE tHZCE 3 tPU [10] CE LOW to Power-Up tPD [10] ns 5 3 [8, 9] ns ns 0 [8, 9] [9] CE HIGH to High Z 10 ns ns 5 0 ns ns CE HIGH to Power-Down 10 ns tDBE Byte Enable to Data Valid 5 ns tLZBE Byte Enable to Low Z Byte Disable to High Z tHZBE Write Cycle 0 ns 5 ns [11, 12] tWC Write Cycle Time 10 ns tSCE CE LOW to Write End 7 ns tAW Address Set-Up to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-Up to Write End 6 ns tHD Data Hold from Write End 0 ns 3 ns WE HIGH to Low Z [9] tHZWE WE LOW to High Z [8, 9] tBW Byte Enable to End of Write tLZWE 5 7 ns ns Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a write and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05463 Rev. *F Page 5 of 13 [+] Feedback CY7C1020D Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR [4] Chip Deselect to Data Retention Time tR [13] Min Max Unit 2.0 V 3 VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Operation Recovery Time mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 4.5V VCC VDR > 2V 4.5V tR tCDR CE Switching Waveforms Read Cycle No.1 (Address Transition Controlled) [14, 15] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No.2 (OE Controlled) [15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tHZBE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% 50% ICC ISB Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 s or stable at VCC(min) > 50 s. 14. Device is continuously selected. OE, CE, BHE and/or BLE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05463 Rev. *F Page 6 of 13 [+] Feedback CY7C1020D Switching Waveforms(continued) Write Cycle No. 1 (CE Controlled) [17, 18] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE t BW BHE, BLE tSD tHD DATA IO Write Cycle No. 2 (BLE or BHE Controlled) [17, 18] tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA IO Notes 17. Data IO is high impedance if OE or BHE and/or BLE= VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05463 Rev. *F Page 7 of 13 [+] Feedback CY7C1020D Switching Waveforms(continued) Write Cycle No. 3 (WE Controlled, OE LOW) [12, 18] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA IO tLZWE Truth Table CE OE WE H X X X X High Z High Z Power-Down Standby (ISB) L L H L L Data Out Data Out Read – All bits Active (ICC) L H Data Out High Z Read – Lower bits only Active (ICC) H L High Z Data Out Read – Upper bits only Active (ICC) L L Data In Data In Write – All bits Active (ICC) L H Data In High Z Write – Lower bits only Active (ICC) H L High Z Data In Write – Upper bits only Active (ICC) L X L BLE BHE IO0–IO7 IO8–IO15 Mode Power L H H X X High Z High Z Selected, Outputs Disabled Active (ICC) L X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Document #: 38-05463 Rev. *F Page 8 of 13 [+] Feedback CY7C1020D Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C1020D-10VXI 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) CY7C1020D-10ZSXI 51-85087 44-pin TSOP Type II (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 02 0 D - 10 XXX I Temperature Range: I = Industrial Package Type: XXX = VX or ZSX VX = 44-pin Molded SOJ (Pb-free) ZSX = 44-pin TSOP Type II (Pb-free) Speed: 10 ns D = C9, 90 nm Technology 0 = Data width × 16-bits 02 = 512-Kbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05463 Rev. *F Page 9 of 13 [+] Feedback CY7C1020D Package Diagrams Figure 1. 44-pin (400-Mil) Molded SOJ, 51-85082 51-85082 *C Document #: 38-05463 Rev. *F Page 10 of 13 [+] Feedback CY7C1020D Package Diagrams(continued) Figure 2. 44-Pin Thin Small Outline Package Type II, 51-85087 51-85087 *C All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05463 Rev. *F Page 11 of 13 [+] Feedback CY7C1020D Document History Page Document Title: CY7C1020D, 512K (32K x 16) Static RAM Document #: 38-05463 REV. ECN NO. Issue Date Orig. of Change ** 201560 See ECN SWI Advance Data sheet for C9 IPP *A 233695 See ECN RKF 1) DC parameters modified as per EROS (Spec # 01-0216) 2) Pb-free Offering in the ‘Ordering Information’ *B 263769 See ECN RKF 1) Corrected pin #18 on SOJ/TSOPII Pinout (Page #1) from A15 to A4 2) Changed IO1 - IO16 to IO0 - IO15 on the Pin-out diagram 3) Added Tpower Spec in Switching Characteristics Table 4) Added Data Retention Characteristics Table and Waveforms 5) Shaded ‘Ordering Information’ *C 307594 See ECN RKF Reduced Speed bins to –10, –12 and –15 ns *D 560995 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 12 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Updated Thermal Resistance table Updated Ordering Information Table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 *E 802877 See ECN VKN Changed ICC specs from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for 83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz *F 3109992 12/14/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. Document #: 38-05463 Rev. *F Description of Change Page 12 of 13 [+] Feedback CY7C1020D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive PSoC Solutions cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF Document #: 38-05463 Rev. *F cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless Page 13 of 13 © Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback