AD AD7233BN Lc2mos 12-bit serial mini-dip dacport Datasheet

a
FEATURES
12-Bit CMOS DAC with
On-Chip Voltage Reference
Output Amplifier
–5 V to +5 V Output Range
Serial Interface
300 kHz DAC Update Rate
Small Size: 8-Pin Mini-DIP
Nonlinearity: ⴞ1/2 LSB TMIN to TMAX
Low Power Dissipation: 100 mW Typ
APPLICATIONS
Process Control
Industrial Automation
Digital Signal Processing Systems
Input/Output Ports
LC2MOS
12-Bit Serial Mini-DIP DACPORT
AD7233
FUNCTIONAL BLOCK DIAGRAM
VDD
VOUT
12-BIT
DAC
12
GND
DAC
LATCH
12
AD7233
INPUT SHIFT
REGISTER
SDIN
SCLK
SYNC
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7233 is a complete 12-bit, voltage-output, digital-toanalog converter with output amplifier and Zener voltage reference
all in an 8-lead package. No external trims are required to
achieve full specified performance. The data format is two’s
complement, and the output range is –5 V to +5 V.
1. Complete 12-Bit DACPORT®.
The AD7233 features a fast, versatile serial interface which
allows easy connection to both microcomputers and 16-bit digital
signal processors with serial ports. When the SYNC input is
taken low, data on the SDIN pin is clocked into the input shift
register on each falling edge of SCLK. On completion of the
16-bit data transfer, bringing LDAC low updates the DAC latch
with the lower 12 bits of data and updates the output. Alternatively, LDAC can be tied permanently low, and in this case the
DAC register is automatically updated with the contents of the
shift register when all sixteen data bits have been clocked in.
The serial data may be applied at rates up to 5 MHz allowing a
DAC update rate of 300 kHz.
2R
2R
VSS
LDAC
2. The AD7233 is a complete, voltage output, 12-bit DAC on a
single chip. This single-chip design is inherently more reliable than multichip designs.
3. Simple 3-wire interface to most microcontrollers and DSP
processors.
4. DAC Update Rate—300 kHz.
5. Space Saving 8-Lead Package.
For applications which require greater flexibility and unipolar
output ranges with single supply operation, please refer to the
AD7243 data sheet.
The AD7233 is fabricated on Linear Compatible CMOS
(LC2MOS), an advanced, mixed-technology process. It is packaged in an 8-lead DIP package.
DACPORT is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
V to +15 V, V = –12 V to –15 V, GND = 0 V, R = 2 k⍀, C = 100 pF
AD7233–SPECIFICATIONS1 to(V GND.= +12All specifications
T to T unless otherwise noted.)
2
DD
2
SS
MIN
L
L
MAX
Parameter
A Version
B Version
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Relative Accuracy3
Differential Nonlinearity3
Bipolar Zero Error3
Full-Scale Error3
Full-Scale Temperature Coefficient4
12
±1
± 0.9
±6
±8
± 30
12
± 1/2
± 0.9
±6
±8
± 30
Bits
LSB max
LSB max
LSB max
LSB max
ppm of FSR/°C typ
Guaranteed Monotonic
DAC Latch Contents 0000 0000 0000
2.4
0.8
2.4
0.8
V min
V max
±1
8
±1
8
µA max
pF max
ANALOG OUTPUTS
Output Voltage Range
DC Output Impedance4
±5
0.5
±5
0.5
V
Ω typ
AC CHARACTERISTICS4
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change
Digital-to-Analog Glitch Impulse3
Digital Feedthrough3
10
10
30
10
10
10
30
10
µs max
µs max
nV secs typ
nV secs typ
Settling Time to Within ± 1/2 LSB of Final Value
Typically 4 µs; DAC Latch 100. . .000 to 011. . .111
Typically 5 µs; DAC Latch 011. . .111 to 100. . .000
DAC Latch Contents Toggled Between All 0s and all 1s
LDAC = High
POWER REQUIREMENTS
VDD Range
VSS Range
IDD
ISS
10.8/16.5
–10.8/–16.5
10
2
10.8/16.5
–10.8/–16.5
10
2
V min/V max
V min/V max
mA max
mA max
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
Output Unloaded; Typically 7 mA at Thresholds
Output Unloaded; Typically 1 mA at Thresholds
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IIN
Input Capacitance4
Guaranteed By Process
VIN = 0 V to VDD
NOTES
1
Temperature Ranges are as follows: A, B Versions: –40°C to +85°C.
2
Power Supply Tolerance: A, B Versions: ± 10%.
3
See Terminology.
4
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2
(VDD = +10.8 V to +16.5 V, VSS = –10.8 V to –16.5 V, GND = O V, RL = 2 k⍀, CL = 100 pF. All
Specifications TMIN to TMAX unless otherwise noted.)
Parameter
Limit at 25ⴗC, TMIN, TMAX
(All Versions)
Unit
Conditions/Comments
t1 3
t2
t3
t4
t5
t6
t7
t8
200
15
70
0
40
0
20
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle Time
SYNC to SCLK Falling Edge Setup Time
SYNC to SCLK Hold Time
Data Setup Time
Data Hold Time
SYNC High to LDAC Low
LDAC Pulsewidth
LDAC High to SYNC Low
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr and tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
See Figure 3.
3
SCLK Mark/Space Ratio range is 40/60 to 60/40.
–2–
REV. B
AD7233
ABSOLUTE MAXIMUM RATINGS 1
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
The output may be shorted to voltages in this range provided the power dissipation
of the package is not exceeded. Short circuit current is typically 80 mA.
(TA = 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
VOUT2 to GND . . . . . . . . . . . . . . . . . . . . –6 V to VDD +0.3 V
Digital Inputs to GND . . . . . . . . . . . . –0.3 V to VDD +0.3 V
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . 300°C
Power Dissipation to 75°C . . . . . . . . . . . . . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000 V
ORDERING GUIDE
Model
Temperature
Range
Relative
Accuracy
Package
Option*
AD7233AN
AD7233BN
–40°C to +85°C
–40°C to +85°C
± 1 LSB
± 1/2 LSB
N-8
N-8
*N = Plastic DIP.
TERMINOLOGY
RELATIVE ACCURACY (LINEARITY)
FULL-SCALE ERROR
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation of the DAC transfer function from a straight
line passing through the endpoints of the transfer function. It is
measured after allowing for zero and full-scale errors and is
expressed in LSBs or as a percentage of full-scale reading.
Full-scale error is a measure of the output error when the
amplifier output is at full scale (full scale is either positive or
negative full scale).
DIGITAL-TO-ANALOG GLITCH IMPULSE
This is the voltage spike that appears at the output of the DAC
when the digital code in the DAC latch changes before the output settles to its final value. The energy in the glitch is specified
in nV secs, and is measured for an all codes change (0000 0000
0000 to 1111 1111 1111).
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB or less
over the operating temperature range ensures monotonicity.
DIGITAL FEEDTHROUGH
This is a measure of the voltage spike that appears on VOUT as a
result of feedthrough from the digital inputs on the AD7233. It
is measured with LDAC held high.
BIPOLAR ZERO ERROR
Bipolar zero error is the voltage measured at VOUT when the
DAC is loaded with all 0s. It is due to a combination of offset
errors in the DAC, amplifier and mismatch between the internal
gain resistors around the amplifier.
REV. B
–3–
AD7233
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
Description
1
2
3
4
VDD
SCLK
SDIN
SYNC
5
LDAC
6
7
8
GND
VOUT
VSS
Positive Supply (12 V to 15 V).
Serial Clock, Logic Input. Data is clocked into the input register on each falling SCLK edge.
Serial Data In, Logic Input. The 16-bit serial data word is applied to this input.
Data Synchronization Pulse, Logic Input. Taking this input low initializes the internal logic in
readiness for a new data word.
Load DAC, Logic Input. Updates the DAC output. The DAC output is updated on the falling edge of
this signal, or alternatively if this line in permanently low, an automatic update mode is selected whereby
the DAC is updated on the 16th falling SCLK pulse.
Ground Pin = 0 V.
Analog Output Voltage. This is the buffered DAC output voltage (–5 V to +5 V).
Negative Supply (–12 V to –15 V).
VDD 1
SCLK 2
AD7233
8
VSS
7
VOUT
TOP VIEW
SDIN 3 (Not to Scale) 6 GND
5 LDAC
SYNC 4
CIRCUIT INFORMATION
D/A Section
DIGITAL INTERFACE
The AD7233 contains a 12-bit voltage-mode D/A converter
consisting of highly stable thin-film resistors and high-speed
NMOS single-pole, double-throw switches.
Op Amp Section
The output of the voltage-mode D/A converter is buffered by a
noninverting CMOS amplifier. The buffer amplifier is capable
of developing ± 5 V across a 2 kΩ load to GND.
2R
INTERNAL
REFERENCE
5V
R
R
2R
2R
DB0
DB1
R
R
R
2R
2R
2R
DB9
DB10
DB11
VOUT
2R
2R
GND
Figure 1. Simplified D/A Converter
The AD7233 contains an input serial to parallel shift register
and a DAC latch. A simplified diagram of the input loading circuitry is shown in Figure 2. Serial data on the SDIN input is
loaded to the input register under control of SYNC and SCLK.
When a complete word is held in the shift register it may then be
loaded into the DAC latch under control of LDAC. Only the
data in the DAC latch determines the analog output on the
AD7233.
A low SYNC input provides the frame synchronization signal
which tells the AD7233 that valid serial data on the SDIN input
will be available for the next 16 falling edges of SCLK. An internal counter/decoder circuit provides a low gating signal so that
only 16 data bits are clocked into the input shift register. After
16 SCLK pulses the internal gating signal goes inactive (high)
thus locking out any further clock pulses. Therefore, either a
continuous clock or a burst clock source may be used to clock in
the data.
The SYNC input should be taken high after the complete 16-bit
word is loaded in.
Although 16 bits of data are clocked into the input register, only
the latter 12 bits get transferred into the DAC latch. The first 4
bits in the 16-bit stream are don’t cares since their value does
not affect the DAC latch data. Therefore the data format is 4
don’t cares followed by the 12-bit data word with the LSB as the
last bit in the serial stream.
–4–
REV. B
AD7233
If LDAC = 1 then the automatic update is disabled and the
DAC latch is updated by taking LDAC low any time after the
16-bit data transfer is complete. The update now occurs on the
falling edge of LDAC. This facility is useful for simultaneous
update in multi-DAC systems. Note that the LDAC input must
be taken back high again before the next data transfer is initiated.
There are two ways in which the DAC latch and hence the analog output may be updated. The status of the LDAC input is
examined after SYNC is taken low. Depending on its status, one
of two update modes is selected.
If LDAC = 0 then the automatic update mode is selected. In
this mode the DAC latch and analog output are updated automatically when the last bit in the serial data stream is clocked in.
The update thus takes place on the sixteenth falling SCLK edge.
SYNC
RESET
ⴜ16
COUNTER/
DECODER
SCLK
GATING
SIGNAL
GATING
SCLK INPUT SHIFT REGISTER (16 BITS)
SDIN
AUTO-UPDATE
CIRCUITRY
DAC LATCH (12 BITS)
LDAC
Figure 2. Simplified Loading Structure
t1
SCLK
t3
t2
SYNC
t4
SDIN
DB15
DON’T CARE
DB14
DON’T CARE
DB13
DON’T CARE
DB12
DON’T CARE
t5
DB11
MSB
DB1
DB0
LSB
t6
LDAC
Figure 3. Timing Diagram
REV. B
–5–
t7
t8
AD7233–Typical Performance Characteristics
500
100
0.50
OUTPUT WITH ALL
0s ON DAC
90
80
PSRR – dB
70
0.30
0.20
TA = 25ⴗC
OUTPUT WITH ALL
1s ON DAC
200
NO DECOUPLING
DECOUPLING
60
nV/ Hz
0.40
LINEARITY – LSB
VDD = +15V
VSS = –15V
TA = 25ⴗC
DECOUPLING
50
40
50
NO DECOUPLING
30
20
0.10
10
0.00
10.5 11
12
13
14
VDD /VSS – Volts
15
0
10
16
20
OUTPUT WITH ALL
0s ON DAC
V DD
= 15V WITH
100mV p-p SIGNAL
1k
100k
10k
FREQUENCY – Hz
* POWER SUPPLY DECOUPLING CAPACITORS
ARE 10␮F AND 0.1␮F.
TPC 1. Linearity vs. Power Supply
Voltage
100
TPC 2. Power Supply Rejection
Ratio vs. Frequency
The AD7233 provides an output voltage range from –5 V to
+5 V without any external components. This configuration is
shown in Figure 4. The data format is two’s complement. The
output code table is shown in Table I. If offset binary coding is
required, it can be done by inverting the MSB in software before
the data is loaded to the AD7233.
+12V TO +15V
VDD
2R
50k
100k
TPC 3. Noise Spectral Density
vs. Frequency
VSS
–12V TO –15V
Input Data Word
MSB
LSB
Analog Output, VOUT
XXXX 0111 1111 1111
XXXX 0000 0000 0001
XXXX 0000 0000 0000
XXXX 1111 1111 1111
XXXX 1000 0000 0001
XXXX 1000 0000 0000
+5 V • (2047/2048)
+5 V • (1/2048)
0V
–5 V • (1/2048)
–5 V • (2047/2048)
–5 V • (2048/2048) = –5 V
X = Don’t Care
Note: 1 LSB = 5 V/2048 ≈ 2.4 mV
2R
VOUT
12-BIT
DAC
+5V
0
50 100 200 500 1k 2k 5k 10k 20k
FREQUENCY – Hz
Table I. AD7233 Bipolar Code Table
APPLYING THE AD7233
Bipolar (ⴞ5 V) Configuration
AD7233
100
GND
Figure 4. Circuit Configuration
Power Supply Decoupling
To achieve optimum performance when using the AD7233, the
VDD and VSS lines should each be decoupled to GND using
0.1 µF capacitors. In very noisy environments it is recommended that 10 µF capacitors be connected in parallel with
the 0.1 µF capacitors.
–6–
REV. B
AD7233
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD7233 is via a serial bus that
uses standard protocol compatible with DSP processors and
microcontrollers. The communications channel requires a
three-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD7233 requires a 16-bit data
word with data valid on the falling edge of SCLK. For all of the
interfaces, the DAC update may be done automatically when all
the data is clocked in or it may done under control of LDAC.
LDAC
DSP56000
Figures 5 to 8 show the AD7233 configured for interfacing to a
number of popular DSP processors and microcontrollers.
Figure 5 shows a serial interface between the AD7233 and the
ADSP-2101/ADSP-2102 DSP processor. The ADSP-2101/
ADSP-2102 contains two serial ports, and either port may be
used in the interface. The data transfer is initiated by TFS going
low. Data from the ADSP-2101/ADSP-2102 is clocked into the
AD7233 on the falling edge of SCLK. When the data transfer is
complete TFS is taken high. In the interface shown the DAC is
updated using an external timer which generates an LDAC pulse.
This could also be done using a control or decoded address line
from the processor. Alternatively, the LDAC input could be
hardwired low, and in this case the automatic update mode is
selected whereby the DAC update takes place automatically on
the 16th falling edge of SCLK.
TIMER
LDAC
AD7233*
TFS
SYNC
SCLK
SCLK
DT
SCK
SCLK
STD
SDIN
SC2
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7233–ADSP-2101/ADSP-2102 Interface
ADSP-2101/
ADSP-2102*
AD7233*
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. AD7233 to DSP56000 Interface
AD7233–87C51 Interface
A serial interface between the AD7233 and the 87C51 microcontroller is shown in Figure 7. TXD of the 87C51 drives
SCLK of the AD7233 while RXD drives the serial data line of
the part. The SYNC signal is derived from the port line P3.3.
The 87C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is arranged correctly so that
the don’t care bits are the first to be transmitted to the AD7233
and the last bit to be sent is the LSB of the word to be loaded to
the AD7233. When data is to be transmitted to the part, P3.3 is
taken low. Data on RXD is valid on the falling edge of TXD.
The 87C51 transmits its serial data in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. To load data
to the AD7233, P3.3 is kept low after the first eight bits are
transferred and a second byte of data is then transferred serially
to the AD7233. When the second serial transfer is complete, the
P3.3 line is taken high.
Figure 7 shows the LDAC input of the AD7233 hardwired low.
As a result, the DAC latch and the analog output will be updated
on the sixteenth falling edge of TXD after the SYNC signal for
the DAC has gone low. Alternatively, the scheme used in previous interfaces, whereby the LDAC input is driven from a timer,
can be used.
Figure 5. AD7233 to ADSP-2101/ADSP-2102 Interface
AD7233-DSP56000 Interface
LDAC
A serial interface between the AD7233 and the DSP56000 is
shown in Figure 6. The DSP56000 is configured for Normal Mode
Asynchronous operation with Gated Clock. It is also set up for a
16-bit word with SCK and SC2 as outputs and the FSL control bit
set to a 0. SCK is internally generated on the DSP56000 and
applied to the AD7233 SCLK input. Data from the DSP56000 is
valid on the falling edge of SCK. The SC2 output provides the
framing pulse for valid data. This line must be inverted before
being applied to the SYNC input of the AD7233.
87C51*
P3.3
SYNC
TXD
SCLK
RXD
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
The LDAC input of the AD7233 is connected to GND so the
update of the DAC latch takes place automatically on the 16th
falling edge of SCLK. An external timer could also be used as in
the previous interface if an external update is required.
REV. B
AD7233*
Figure 7. AD7233 to 87C51 Interface
–7–
AD7233
Figure 8 shows a serial interface between the AD7233 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7233 while the MOSI output drives the serial data line.
The SYNC signal is derived from a port line (PC7 shown).
will be updated on the sixteenth falling edge of SCK after the
respective SYNC signal has gone low. Alternatively, the scheme
used in previous interfaces, whereby the LDAC input is driven
from a timer, can be used.
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a
1. When data is to be transmitted to the part, PC7 is taken low.
When the 68HC11 is configured like this, data on MOSI is valid
on the falling edge of SCK. The 68HC11 transmits its serial
data in 8-bit bytes with only eight falling clock edges occurring
in the transmit cycle. To load data to the AD7233, PC7 is kept
low after the first eight bits are transferred and a second byte of
data is then transferred serially to the AD7233. When the second serial transfer is complete, the PC7 line is taken high. Figure 8 shows the LDAC input of the AD7233 hardwired low.
As a result, the DAC latch and the analog output of the DAC
C00989a-0-4/01(B)
AD7233-68HC11 Interface
LDAC
68HC11*
AD7233*
PC7
SYNC
SCK
SCLK
MOSI
SDIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. AD7233 to 68HC11 Interface
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic DIP (N-8) Package
0.430 (10.92)
0.348 (8.84)
8
5
1
0.280 (7.11)
0.240 (6.10)
4
0.325 (8.25)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.015 (0.381)
0.008 (0.204)
PRINTED IN U.S.A.
0.022 (0.558) 0.070 (1.77) SEATING
0.014 (0.356) 0.045 (1.15) PLANE
AD7233–Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
B Version column added to Specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
–8–
REV. B