DATASHEET ISL9005A FN6452 Rev 2.00 November 20, 2015 LDO with Low ISUPPLY, High PSRR ISL9005A is a high performance Low Dropout linear regulator capable of sourcing 300mA current. It has a low standby current and high-PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200m. Features The ISL9005A has a high PSRR of 75dB and an output noise of less than 45µVRMS. When coupled with a no load quiescent current of 50µA, (typical) and 0.1µA shutdown current, the ISL9005A is an ideal choice for portable wireless equipment. • Excellent load regulation: <0.1% voltage change across full range of load current Several different fixed voltage outputs are standard. Output voltage options for each LDO range are from 1.5V to 3.3V. Other output voltage options may be available upon request. • 300mA high performance LDO • Excellent transient response to large current steps • High PSRR: 75dB @ 1kHz • Wide input voltage capability: 2.3V to 6.5V • Very low quiescent current: 50µA • Low dropout voltage: typically 200mV @ 300mA • Low output noise: typically 45µVRMS @ 100µA (1.5V) • Stable with 1µF to 10µF ceramic capacitors Pinout ISL9005A (8 LD 2x3 DFN) TOP VIEW • Soft-start to limit input current surge during enable • Current limit and overheat protection • ±1.8% accuracy over all operating conditions VIN 1 8 VO EN 2 7 NC NC 3 6 NC NC 4 5 GND • Tiny 2mmx3mm 8 Ld DFN package • -40°C to +85°C operating temperature range • Pb-free (RoHS compliant) Applications • PDAs, cell phones and smart phones • Portable instruments, MP3 players • Handheld devices, including medical handhelds Ordering Information PART NUMBER (Notes 1, 2) PART MARKING VO VOLTAGE (V) (Note 3) TEMP RANGE (°C) PACKAGE Tape and Reel (Pb-Free) PKG. DWG. # ISL9005AIRNZ-T EBV 3.3 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRKZ-T EBR 2.85 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRJZ-T EBP 2.8 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRFZ-T EBN 2.5 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRCZ-T EBM 1.8 -40 to +85 8 Ld 2x3 DFN L8.2x3 ISL9005AIRBZ-T EBL 1.5 -40 to +85 8 Ld 2x3 DFN L8.2x3 NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Please refer to TB347 for details on reel specifications. 3. For other output voltages, contact Intersil Marketing. FN6452 Rev 2.00 November 20, 2015 Page 1 of 10 ISL9005A Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)V Thermal Resistance (Notes 4, 5) JA (°C/W) JC (°C/W) 8 Ld 2x3 DFN Package . . . . . . . . . . . . 69 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF. SYMBOL TEST CONDITIONS MIN MAX (Note 8) TYP (Note 8) UNITS DC CHARACTERISTICS Supply Voltage 2.3 VIN Ground Current 6.5 V Quiescent condition: IO = 0µA IDD LDO active 50 75 µA LDO disabled @ +25°C 0.1 1.0 µA Shutdown Current IDDS UVLO Threshold VUV+ 1.9 2.1 2.3 V VUV- 1.6 1.8 2.0 V Regulation Voltage Accuracy Maximum Output Current IMAX Internal Current Limit ILIM Dropout Voltage (Note 7) Thermal Shutdown Temperature Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = +25°C -0.8 +0.8 % VIN = VO + 0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C to +125°C -1.8 +1.8 % Continuous 300 350 mA 475 600 mA VDO1 IO = 300mA; VO 2.5V 300 500 mV VDO2 IO = 300mA; 2.5V VO 2.8V 250 400 mV VDO3 IO = 300mA; VO > 2.8V 200 325 mV TSD+ 145 °C TSD- 110 °C @ 1kHz 75 dB @ 10kHz 60 dB @ 100kHz 40 dB IO = 100µA, VO = 1.5V, TA = +25°C BW = 10Hz to 100kHz 45 µVRMS AC CHARACTERISTICS Ripple Rejection (Note 6) Output Noise Voltage (Note 6) FN6452 Rev 2.00 November 20, 2015 IO = 10mA, VIN = 2.8V (min), VO = 1.8V Page 2 of 10 ISL9005A Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF. (Continued) MIN MAX (Note 8) TYP (Note 8) UNITS Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO (nom) 250 500 µs Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V SYMBOL TEST CONDITIONS DEVICE START-UP CHARACTERISTICS Device Enable Time LDO Soft-start Ramp Rate tEN tSSR EN PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.5 V Input High Voltage VIH 1.4 VIN + 0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF NOTES: 6. Limits established by characterization and are not production tested. 7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. 8. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. FN6452 Rev 2.00 November 20, 2015 Page 3 of 10 ISL9005A Typical Performance Curves 0.10 0.8 VO = 3.3V ILOAD = 0mA OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.6 0.4 0.2 -40°C 0.0 +25°C -0.2 +85°C -0.4 VIN = 3.8V VO = 3.3V 0.08 -0.6 0.06 0.04 -40°C 0.02 +25°C 0.00 -0.02 +85°C -0.04 -0.06 -0.08 -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 -0.10 6.6 6.2 0 50 100 FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 300 250 400 350 FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT 0.10 3.4 VIN = 3.8V VO = 3.3V ILOAD = 0mA 0.08 0.06 VO = 3.3V IO = 0mA 3.3 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE CHANGE (%) 200 150 LOAD CURRENT - IO (mA) INPUT VOLTAGE (V) 0.04 0.02 0.00 -0.02 -0.04 -0.06 3.2 IO = 150mA 3.1 IO = 300mA 3.0 2.9 -0.08 -0.10 -40 2.8 -25 5 -10 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 2.9 DROPOUT VOLTAGE, VDO (mV) OUTPUT VOLTAGE, VO (V) IO = 150mA 2.6 IO = 300mA 2.5 2.4 3.6 4.1 4.6 5.1 5.6 INPUT VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT) FN6452 Rev 2.00 November 20, 2015 4.6 5.1 5.6 6.1 6.5 350 IO = 0mA 2.8 3.1 4.1 FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) VO = 2.8V 2.3 2.6 3.6 INPUT VOLTAGE (V) FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE 2.7 3.1 6.1 6.5 300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT Page 4 of 10 400 ISL9005A Typical Performance Curves (Continued) 80 350 VO = 3.3V 70 GROUND CURRENT (µA) DROPOUT VOLTAGE, VDO (mV) 300 250 +85°C +25°C -40°C 200 150 100 +125°C 60 +25°C 50 -40°C 40 VO = 3.3V 30 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 20 400 3.0 3.5 4.0 4.58 5.0 5.5 6.5 6.0 INPUT VOLTAGE (V) FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE 80 200 180 GROUND CURRENT (µA) GROUND CURRENT (µA) 70 +85°C 160 140 120 +25°C 100 -40°C 80 60 60 50 40 40 0 0 50 100 150 200 250 300 350 VIN = 3.8V VO = 3.3V ILOAD = 0µA 30 VIN = 3.8V VO = 3.3V 20 20 -40 -25 400 -10 5 LOAD CURRENT (mA) FIGURE 9. GROUND CURRENT vs LOAD 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 FIGURE 10. GROUND CURRENT vs TEMPERATURE VO = 2.85V VIN = 5.0V VO = 2.85V IL = 150mA IL = 150mA 4 2 VIN 3 2 1 0 VO VEN (V) 1 0 0 CL = 1µF 3 VO (V) VOLTAGE (V) 5 0.5 1.0 1.5 2.0 2.5 TIME (s) 3.0 3.5 4.0 FIGURE 11. POWER-UP/POWER-DOWN FN6452 Rev 2.00 November 20, 2015 4.5 5.0 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 1.4 1.6 1.8 2.0 FIGURE 12. TURN ON/TURN OFF RESPONSE Page 5 of 10 ISL9005A Typical Performance Curves (Continued) VO = 3.3V ILOAD = 300mA CLOAD = 1µF VO = 2.8V ILOAD = 300mA CLOAD = 1µF 4.3V 4.2V 3.6V 3.5V 10mV/DIV 10mV/DIV 400µs/DIV 400µs/DIV FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT VO (25mV/DIV) VO = 1.8V VIN = 2.8V 300mA ILOAD SPECTRAL NOISE DENSITY (µV/Hz) 10 1.000 0.100 VIN = 3.6V VO = 1.8V ILOAD = 10mA CIN = 1µF 0.010 CLOAD = 1µF 100µA 0.001 10 100 1k 10k FREQUENCY (Hz) 100µs/DIV FIGURE 15. LOAD TRANSIENT RESPONSE 100k FIGURE 16. SPECTRAL NOISE DENSITY vs FREQUENCY 100 VIN = 3.6V VO = 1.8V IO = 10mA CLOAD = 1µF 90 80 PSRR (dB) 70 60 50 40 30 20 10 0 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 17. PSRR vs FREQUENCY FN6452 Rev 2.00 November 20, 2015 1M Page 6 of 10 ISL9005A Pin Description PIN NUMBER PIN NAME 1 VIN Supply Voltage/LDO Input: Connect a 1µF capacitor to GND. 2 EN LDO Enable. 3 NC Do not connect. 4 NC Do not connect. 5 GND 6 NC Do not connect. 7 NC Do not connect. 8 VO LDO Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended). DESCRIPTION GND is the connection to system ground. Connect to PCB Ground plane. Typical Application ISL9005A VIN (2.3V TO 5V) 1 ON 2 ENABLE OFF 3 C1 4 VIN VO EN NC NC NC NC GND 8 VOUT 7 6 5 C2 C1, C2: 1µF X5R CERAMIC CAPACITOR FN6452 Rev 2.00 November 20, 2015 Page 7 of 10 ISL9005A During operation, whenever the VIN voltage drops below about 1.84V, the ISL9005A immediately disables the LDO output. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically. Block Diagram VIN VO UVLO CONTROL LOGIC Reference Generation The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and over-temperature detection. + EN The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. GND BANDGAP AND TEMPERATURE SENSOR VOLTAGE AND REFERENCE GENERATOR 1.0V 0.94V 0.9V GND Functional Description The ISL9005A contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9005A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart thermal shutdown protects the device against overheating. Power Control The ISL9005A has an enable pin (EN) to control power to the LDO output. When EN is low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1µA. When the enable pin is asserted, the device first monitors the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power-up. Once the references are stable, a fast-start circuit powers up the LDO. FN6452 Rev 2.00 November 20, 2015 LDO Regulation and Programmable Output Divider The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9005A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a tolerance better than 20% and ESR less than 200m, and the design is performance-optimized for a 1µF output capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9005A provides short-circuit protection by limiting the output current to about 425mA. The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory. Overheat Detection The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140°C, if the LDO is sourcing more than 50mA it shuts down until the die cools sufficiently. Once the die temperature falls back below about +110°C, the disabled LDO is re-enabled and soft-start automatically takes place. Page 8 of 10 ISL9005A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE November 20, 2015 FN6452.2 - Updated Ordering Information Table on page 1. - Added Revision History. - Added About Intersil Verbiage. - Updated POD L8.2X3 to latest revision changes are as follow: Bottom View: Changed exposed pad height from 1.80 +/-0.10 to 1.80 +0.10/-0.15 Changed exposed pad width from 1.65 +/-0.10 to 1.65 +0.10/-0.15 Side View: Changed 0.05 to 0.05 MAX Converted to new POD standards by adding land pattern and moving dimensions from table onto drawing. Tiebar Note 5 updated From: Tiebar shown (if present) is a non-functional feature. To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support. © Copyright Intersil Americas LLC 2007-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6452 Rev 2.00 November 20, 2015 Page 9 of 10 ISL9005A Package Outline Drawing L8.2x3 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 3/15 2.00 A 2X 1.50 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 6X 0.50 1 1.80 +0.10/-0.15 3.00 B (4X) 0.15 8 8X 0.40 ±0.10 TOP VIEW 1.65 +0.10/-0.15 8X 0.25 +0.07/-0.05 4 0.10 M C A B BOTTOM VIEW SEE DETAIL "X" 0.90 ±0.10 0.10 C (1.65) (1.50) (8X 0.60) C BASE PLANE SEATING PLANE 0.08 C 0.05 MAX SIDE VIEW (2.80)(1.80) 0.20 REF C (6X 0.50) 0.05 MAX (8X 0.25) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: FN6452 Rev 2.00 November 20, 2015 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends). 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Compies to JEDEC MO-229 VCED-2. Page 10 of 10