ON MC14050BDG Hex buffer Datasheet

MC14049B, MC14050B
Hex Buffer
The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P−Channel and N−Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, VDD.
The input−signal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS−to−TTL/DTL converter
(VDD = 5.0 V, VOL v 0.4 V, IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation.
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MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
Features
•
•
•
•
•
•
•
16
MC140xxBCP
AWLYYWWG
1
16
SOIC−16
D SUFFIX
CASE 751B
High Source and Sink Currents
High−to−Low Level Converter
Supply Voltage Range = 3.0 V to 18 V
VIN can exceed VDD
Meets JEDEC B Specifications
Improved ESD Protection On All Inputs
These Devices are Pb−Free and are RoHS Compliant
1
16
Parameter
1
Value
Unit
VDD
DC Supply Voltage Range
−0.5 to +18.0
V
Vin
Input Voltage Range (DC or Transient)
−0.5 to +18.0
V
Vout
Output Voltage Range (DC or Transient)
−0.5 to VDD +
0.5
V
Iin
Input Current (DC or Transient) per Pin
± 10
mA
Iout
Output Current (DC or Transient) per Pin
± 45
mA
PD
Power Dissipation, per Package (Note 1)
(Plastic)
(SOIC)
825
740
TA
Ambient Temperature Range
−55 to +125
°C
Tstg
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature (8−Second Soldering)
260
°C
mW
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high−impedance circuit. For proper operation, the
ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
June, 2011 − Rev. 7
16
SOEIAJ−16
F SUFFIX
CASE 966
MC140xxB
ALYWG
1
1. Temperature Derating: See Figure 3.
© Semiconductor Components Industries, LLC, 2011
14
050B
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
140xxBG
AWLYWW
1
xx
A
WL, L
YY, Y
WW, W
G or G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Publication Order Number:
MC14049B/D
MC14049B, MC14050B
LOGIC DIAGRAM
MC14049B
PIN ASSIGNMENT
VDD
1
16
NC
OUTA
2
15
OUTF
INA
3
14
INF
OUTB
4
13
NC
INB
5
12
OUTE
OUTC
6
11
INE
INC
7
10
OUTD
VSS
8
9
IND
MC14050B
3
2
3
2
5
4
5
4
7
6
7
6
9
10
9
10
11
12
11
12
14
15
14
15
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
NC = PIN 13, 16
VSS = PIN 8
VDD = PIN 1
ORDERING INFORMATION
Package
Shipping†
MC14049BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14049BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14049BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
MC14049BFELG
SOEIAJ−16
(Pb−Free)
2000 Units / Tape & Reel
MC14050BCPG
PDIP−16
(Pb−Free)
500 Units / Rail
MC14050BDG
SOIC−16
(Pb−Free)
48 Units / Rail
MC14050BDR2G
SOIC−16
(Pb−Free)
2500 Units / Tape & Reel
MC14050BDTG
TSSOP−16*
(Pb−Free)
96 Units / Rail
MC14050BDTR2G
TSSOP−16*
(Pb−Free)
2500 Units / Tape & Reel
MC14050BFELG
SOEIAJ−16
(Pb−Free)
2000 Units / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC14049B, MC14050B
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD
Symbol
– 55_C
+ 25_C
+ 125_C
VDD
Vdc
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
5.0
10
15
– 1.6
– 1.6
– 4.7
−
−
−
– 1.25
– 1.30
– 3.75
– 2.5
– 2.6
– 10
−
−
−
– 1.0
– 1.0
– 3.0
−
−
−
IOL
5.0
10
15
3.75
10
30
−
−
−
3.2
8.0
24
6.0
16
40
−
−
−
2.6
6.6
19
−
−
−
mAdc
Input Current
Iin
15
−
±0.1
−
±0.00001
±0.1
−
±1.0
mAdc
Input Capacitance (Vin = 0)
Cin
−
−
−
−
10
20
−
−
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
−
−
−
1.0
2.0
4.0
−
−
−
0.002
0.004
0.006
1.0
2.0
4.0
−
−
−
30
60
120
mAdc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
per package)
(CL = 50 pF on all outputs, all
buffers switching
IT
5.0
10
15
Vin = 0
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
“1” Level
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Source
Sink
VIH
IOH
Vdc
Vdc
mAdc
IT = (1.8 mA/kHz) f + IDD
IT = (3.5 mA/kHz) f + IDD
IT = (5.3 mA/kHz) f + IDD
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at + 25_C
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
Where: IT is in mA (per Package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency and k = 0.002.
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3
mAdc
MC14049B, MC14050B
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AC SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = + 25_C)
Characteristic
Symbol
Output Rise Time
tTLH = (0.7 ns/pF) CL + 65 ns
tTLH = (0.25 ns/pF) CL + 37.5 ns
tTLH = (0.2 ns/pF) CL + 30 ns
tTLH
Output Fall Time
tTHL = (0.2 ns/pF) CL + 30 ns
tTHL = (0.06 ns/pF) CL + 17 ns
tTHL = (0.04 ns/pF) CL + 13 ns
tTHL
Propagation Delay Time
tPLH = (0.33 ns/pF) CL + 63.5 ns
tPLH = (0.19 ns/pF) CL + 30.5 ns
tPLH = (0.06 ns/pF) CL + 27 ns
tPLH
Propagation Delay Time
tPHL = (0.2 ns/pF) CL + 30 ns
tPHL = (0.1 ns/pF) CL + 15 ns
tPHL = (0.05 ns/pF) CL + 12.5 ns
tPHL
VDD
Vdc
Min
Typ
(Note 6)
Max
5.0
10
15
−
−
−
100
50
40
160
80
60
5.0
10
15
−
−
−
40
20
15
60
40
30
5.0
10
15
−
−
−
80
40
30
140
80
60
5.0
10
15
−
−
−
40
20
15
80
40
30
Unit
ns
ns
ns
ns
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14049B
VDD
MC14050B
VDD
1
1
IOH
8
MC14049B
VDD
1
IOL
VOH
VSS
8
1
IOL
VOL
VSS
8
VDS = VOH - VDD
IOH
VOL
VSS
8
VOH
VSS
VDD = VOL
160
I OL, OUTPUT SINK CURRENT (mAdc)
0
I OH , OUTPUT SOURCE CURRNT (mAdc)
MC14050B
VDD
VGS = 5.0 Vdc
-10
VGS = 15 Vdc
120
-20
VGS = 10 Vdc
-30
-40
VGS = 15 Vdc
-50
-10
MAXIMUM CURRENT LEVEL
-8.0
-6.0
-4.0
-2.0
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
MAXIMUM CURRENT LEVEL
40
VGS = 5.0 Vdc
0
0
VGS = 10 Vdc
80
0
Figure 1. Typical Output Source Characteristics
2.0
4.0
6.0
8.0
VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)
Figure 2. Typical Output Sink Characteristics
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4
10
PD , MAXIMUM POWER DISSIPATION (mW)
PER PACKAGE
MC14049B, MC14050B
1200
1100
1000
900
825
800
740
700
600
(P) PDIP
500
400
300
(D) SOIC
200
100
0
25
175 mW (P)
120 mW (D)
50
75
100
125
TA, AMBIENT TEMPERATURE (°C)
150
175
Figure 3. Ambient Temperature Power Derating
20 ns
20 ns
INPUT
VDD
10%
#
Vin
Vout
VSS
tPLH
CL
tTHL
tPHL
10%
tTLH
Figure 4. Switching Time Test Circuit and Waveforms
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5
tTLH
tPHL
90%
50%
OUTPUT
MC14050B
#Invert on MC14049B only
VOH
90%
50%
10%
OUTPUT
MC14049B
8
VSS
tPLH
tPHL
1
PULSE
GENERATOR
VDD
90%
50%
VOL
VOH
VOL
tTHL
MC14049B, MC14050B
PACKAGE DIMENSIONS
PDIP−16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
H
SEATING
PLANE
K
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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6
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14049B, MC14050B
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B−05
ISSUE K
−A−
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
9
−B−
1
P
8 PL
0.25 (0.010)
8
B
M
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14049B, MC14050B
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F−01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
S
V
S
K
S
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
F
DETAIL E
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.007
0.011
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC14049B, MC14050B
PACKAGE DIMENSIONS
SOEIAJ−16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966−01
ISSUE A
16
LE
9
Q1
E HE
1
M_
L
8
Z
DETAIL P
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
--2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
--0.78
INCHES
MIN
MAX
--0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
--0.031
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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9
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MC14049B/D