AD AD8045 1 nv/â hz, low power, rail-to-rail output amplifier Datasheet

1 nV/√Hz, Low Power,
Rail-to-Rail Output Amplifiers
ADA4896-2/ADA4897-1
Low noise preamplifier
Ultrasound amplifiers
PLL loop filters
High performance ADC drivers
DAC buffers
8
DISABLE
7
+VS
+IN 3
6
OUT
–VS 4
5
NC
8
VS = ±5V
7
6
5
4
3
2
1
0
1
10
100
1k
10k
1M
5M
Figure 2. Voltage Noise vs. Frequency
GENERAL DESCRIPTION
Table 1. Other Low Noise Amplifiers
The ADA4896-2/ADA4897-1 are unity gain stable, low noise,
rail-to-rail output, high speed voltage feedback amplifiers
that have a quiescent current of 3 mA. With the 1/f noise of
2.4 nV/√Hz at 10 Hz and a spurious-free dynamic range of
−80 dBc at 2 MHz, the ADA4896-2/ADA4897-1 are an ideal
solution in a variety of applications, including ultrasound, low
noise preamplifiers, and drivers of high performance ADCs.
The Analog Devices, Inc., proprietary next generation SiGe
bipolar process and innovative architecture enable such high
performance amplifiers.
Part Number
AD797
AD8021
AD8099
AD8045
ADA4899-1
ADA4898-1/
ADA4898-2
TheADA4896-2/ADA4897-1 have 230 MHz bandwidth,
120 V/μs slew rate, and settle to 0.1% in 45 ns. With a wide
supply voltage range (3 V to 10 V), the ADA4896-2/ADA4897-1
are ideal candidates for systems that require high dynamic
range, precision, and high speed.
100k
FREQUENCY (Hz)
09447-102
APPLICATIONS
NC 1
–IN 2
Figure 1. 8-Lead SOIC (ADA4897-1)
VOLTAGE NOISE (nV/√Hz)
Low wideband noise
1 nV/√Hz
2.8 pA/√Hz
Low 1/f noise
2.4 nV/√Hz @ 10 Hz
Low distortion: −115 dBc @ 100 kHz, VOUT = 2 V p-p
Low power: 3 mA/amp
Low input offset voltage: 0.5 mV maximum
High speed
230 MHz, −3 dB bandwidth (G = +1)
120 V/μs slew rate
45 ns settling time to 0.1%
Rail-to-rail output
Wide supply range: 3 V to 10 V
Disable feature (ADA4897-1)
09447-101
FUNCTIONAL BLOCK DIAGRAM
FEATURES
VN (nV/√Hz)
@ 1 kHz
0.9
5
7
6
1.4
0.9
VN (nV/√Hz)
@ 100 kHz
0.9
2.1
0.95
3
1
0.9
BW (MHz)
8
490
510
1000
600
65
Supply
Voltage (V)
10 to 30
5 to 24
5 to 12
3.3 to 12
5 to 12
10 to 32
Table 2. Complementary ADCs
Part Number
AD7944
AD7985
AD7986
Bits
14
16
18
Speed (MSPS)
2.5
2.5
2
Power (mW)
15.5
15.5
15
The ADA4896-2 is available in 8-lead LFCSP and 8-lead MSOP
packages. The ADA4897-1 is available in 8-lead SOIC and
6-lead SOT-23 packages. Both the ADA4896-2 and ADA4897-1
work over the extended industrial temperature range of −40°C
to +125°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADA4896-2/ADA4897-1
TABLE OF CONTENTS
Features .............................................................................................. 1
Amplifier Description................................................................ 18
Applications....................................................................................... 1
Input Protection ......................................................................... 18
General Description ......................................................................... 1
Disable Operation ...................................................................... 18
Functional Block Diagram .............................................................. 1
DC Errors .................................................................................... 19
Revision History ............................................................................... 2
Noise Considerations................................................................. 19
Specifications..................................................................................... 3
Capacitance Drive ...................................................................... 20
±5 V Supply ................................................................................... 3
Applications Information .............................................................. 21
+5 V Supply ................................................................................... 5
Typical Performance Values...................................................... 21
+3 V Supply ................................................................................... 7
Low Noise Gain Selectable Amplifier...................................... 22
Absolute Maximum Ratings............................................................ 9
Medical Ultrasound Applications ............................................ 23
Thermal Resistance ...................................................................... 9
Layout Considerations............................................................... 24
Maximum Power Dissipation ..................................................... 9
Ground Plane.............................................................................. 24
ESD Caution.................................................................................. 9
Power Supply Bypassing ............................................................ 24
Pin Configurations and Function Descriptions ......................... 10
Outline Dimensions ....................................................................... 25
Typical Performance Characteristics ........................................... 12
Ordering Guide .......................................................................... 27
Theory of Operation ...................................................................... 18
REVISION HISTORY
7/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADA4896-2/ADA4897-1
SPECIFICATIONS
±5 V SUPPLY
TA = 25°C, G = +1, RL = 1 kΩ to ground, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (dBc) SFDR
Input Voltage Noise
Input Current Noise
0.1 Hz to 10 Hz Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time
+Output Voltage Swing
−Output Voltage Swing
+Output Voltage Swing
−Output Voltage Swing
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Positive Power Supply Rejection
Negative Power Supply Rejection
Conditions
Min
Typ
Max
Unit
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V p-p
G = +2, VOUT = 0.02 V p-p
G = +2, VOUT = 2 V p-p, RL = 100 Ω
G = +2, VOUT = 6 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 2 V step
230
30
90
7
120
45
90
MHz
MHz
MHz
MHz
V/μs
ns
ns
fC= 100 kHz, VOUT = 2 V p-p
fC= 1 MHz, VOUT = 2 V p-p
fC = 2 MHz, VOUT = 2 V p-p
fC = 5 MHz, VOUT = 2 V p-p
f = 10 Hz
f = 100 kHz
f = 10 Hz
f = 100 kHz
G = +101, RF = 1 kΩ, RG = 10 Ω
−115
−93
−80
−61
2.4
1
31
2.8
99
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
nV p-p
−500
−0.6
100
−28
0.2
−11
3
−0.02
110
−92
10 M/10 k
3/11
−4.9 to +4.1
−120
Ω
pF
V
dB
81
4.96
−4.97
4.73
−4.84
80
135
39
ns
V
V
V
V
mA
mA
pF
−17
VOUT = −4 V to +4 V
Common mode/differential
Common mode/differential
VCM = −2 V to +2 V
VIN = ±5 V, G = +2
RL = 1 kΩ
RL = 1 kΩ
RL = 100 Ω
RL = 100 Ω
45 dBc SFDR
Sinking/sourcing
30% overshoot, G = +2
4.85
−4.85
4.5
−4.5
2.8
DISABLE = −5 V
+VS = 4 V to 6 V, −VS = −5 V
+VS = 5 V, −VS = −4 V to −6 V
Rev. 0 | Page 3 of 28
−96
−96
3 to 10
3.0
0.25
−125
−121
+500
−4
+0.6
3.2
μV
μV/°C
μA
nA/°C
μA
dB
V
mA
mA
dB
dB
ADA4896-2/ADA4897-1
Parameter
DISABLE PIN (ADA4897-1)
DISABLE Voltage
Input Current
Enabled
Disabled
Switching Speed
Enabled
Disabled
Conditions
Min
Typ
Max
Unit
Enabled
Disabled
>+VS − 0.5
<+VS – 2
V
V
DISABLE = +5 V
DISABLE = −5 V
−2.5
−80
μA
μA
0.25
12
μs
μs
Rev. 0 | Page 4 of 28
ADA4896-2/ADA4897-1
+5 V SUPPLY
TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (dBc) SFDR
Input Voltage Noise
Input Current Noise
0.1 Hz to 10 Hz Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
+Output Voltage Swing
−Output Voltage Swing
+Output Voltage Swing
−Output Voltage Swing
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Positive Power Supply Rejection
Negative Power Supply Rejection
Conditions
Min
Typ
Max
Unit
G = +1, VOUT = 0.02 V p-p
G = +1, VOUT = 2 V p-p
G = +2, VOUT = 0.02 V p-p
G = +2, VOUT = 2 V p-p, RL = 100 Ω
G = +2, VOUT = 3 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 2 V step
230
30
90
7
100
45
95
MHz
MHz
MHz
MHz
V/μs
ns
ns
fC = 100 kHz, VOUT = 2 V p-p
fC = 1 MHz, VOUT = 2 V p-p
fC = 2 MHz, VOUT = 2 V p-p
fC = 5 MHz, VOUT = 2 V p-p
f = 10 Hz
f = 100 kHz
f = 10 Hz
f = 100 kHz
G = +101, RF = 1 kΩ, RG = 10 Ω
−115
−93
−80
−61
2.4
1
31
2.8
99
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
nV p-p
−500
−0.6
97
−30
0.2
−11
3
−0.02
110
−91
10 M/10 k
3/11
0.1 to 4.1
−118
Ω
pF
V
dB
96
4.98
0.014
4.88
0.08
70
125
39
ns
V
V
V
−17
VOUT = 0.5 V to 4.5 V
Common mode/differential
Common mode/differential
VCM = +1 V to +4 V
VIN = 0 V to 5 V, G = +2
RL = 1 kΩ
RL = 1 kΩ
RL = 100 Ω
RL = 100 Ω
45 dBc SFDR
Sinking/sourcing
30% overshoot, G = +2
4.85
0.15
4.8
0.2
2.6
DISABLE = 0 V
+VS = 4.5 V to 5.5 V, −VS = 0 V
+VS = 5 V, −VS = −0.5 V to +0.5 V
Rev. 0 | Page 5 of 28
−96
−96
3 to 10
2.8
0.18
−123
−121
+500
−4
+0.6
μV
μV/°C
μA
nA/°C
μA
dB
mA
mA
pF
2.9
V
mA
dB
dB
ADA4896-2/ADA4897-1
Parameter
DISABLE PIN (ADA4897-1)
DISABLE Voltage
Input Current
Enabled
Disabled
Switching Speed
Enabled
Disabled
Conditions
Min
Typ
Max
Unit
Enabled
Disabled
>+VS − 0.5
<+VS − 2
V
V
DISABLE = +5 V
DISABLE = 0 V
−2.5
−50
μA
μA
0.25
12
μs
μs
Rev. 0 | Page 6 of 28
ADA4896-2/ADA4897-1
+3 V SUPPLY
TA = 25°C, G = +1, RL = 1 kΩ to midsupply, unless otherwise noted.
Table 5.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion (dBc) SFDR
Input Voltage Noise
Input Current Noise
0.1 Hz to 10 Hz Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Bias Current Drift
Input Bias Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
+Output Voltage Swing
−Output Voltage Swing
+Output Voltage Swing
−Output Voltage Swing
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Positive Power Supply Rejection
Negative Power Supply Rejection
Conditions
Min
Typ
Max
Unit
G = +1, VOUT = 0.02 V p-p
G = −1, VOUT = 1 V p-p
G = +2, VOUT = 0.02 V p-p
G = +2, VOUT = 2 V p-p, RL = 100 Ω
G = +2, VOUT = 1 V step
G = +2, VOUT = 2 V step
G = +2, VOUT = 2 V step
230
45
90
7
85
45
96
MHz
MHz
MHz
MHz
V/μs
ns
ns
fC = 100 kHz, VOUT = 2 V p-p, G = +2
fC = 1 MHz, VOUT = 1 V p-p, G = −1
fC = 2 MHz, VOUT = 1 V p-p, G = −1
fC = 5 MHz, VOUT = 1 V p-p, G = −1
f = 10 Hz
f = 100 kHz
f = 10 Hz
f = 100 kHz
G = +101, RF = 1 kΩ, RG = 10 Ω
−105
−84
−77
−60
2.3
1
31
2.8
99
dBc
dBc
dBc
dBc
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
nV p-p
−500
−0.6
95
−30
0.2
−11
3
−0.02
108
−90
10M/10k
3/11
0.1 to 2.1
−124
Ω
pF
V
dB
83
2.97
0.01
2.92
0.05
60
120
39
ns
V
V
V
V
mA
mA
pF
−17
VOUT = 0.5 V to 2.5 V
Common mode/differential
Common mode/differential
VCM = +1.1 V to +1.9 V
VIN = 0 V to +3 V, G = +2
RL = 1 kΩ
RL = 1 kΩ
RL = 100 Ω
RL = 100 Ω
45 dBc SFDR
Sinking/sourcing
30% overshoot, G = +2
2.85
0.15
2.8
0.2
2.5
DISABLE = 0 V
+VS = 2.7 V to 3.7 V, −VS = 0 V
+VS = 3 V, −VS = −0.3 V to 0.7 V
Rev. 0 | Page 7 of 28
−96
−96
3 to 10
2.7
0.15
−121
−120
+500
−4
+0.6
2.9
uV
μV/°C
μA
nA/°C
μA
dB
V
mA
dB
dB
ADA4896-2/ADA4897-1
Parameter
DISABLE PIN (ADA4897-1)
DISABLE Voltage
Input Current
Enabled
Disabled
Switching Speed
Enabled
Disabled
Conditions
Min
Typ
Max
Unit
Enabled
Disabled
>+VS −0.5
<−VS + 2
V
V
DISABLE = +3 V
DISABLE = 0 V
−2.5
−40
μA
μA
0.25
12
μs
μs
Rev. 0 | Page 8 of 28
ADA4896-2/ADA4897-1
ABSOLUTE MAXIMUM RATINGS
Table 6.
Rating
11 V
See Figure 3
−VS − 0.7 V to +VS + 0.7 V
±0.7 V
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
⎛V
V
PD = (V S × I S ) + ⎜⎜ S × OUT
RL
⎝ 2
RMS output voltages should be considered. If RL is referenced to
−VS, as in single-supply operation, the total drive power is VS ×
IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS × I S ) +
(VS /4)2
RL
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes, reduces θJA.
3.5
Unit
°C/W
°C/W
°C/W
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4896-2/
ADA4897-1 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150°C, which
is the glass transition temperature, the properties of the plastic
change. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADA4896-2/
ADA4897-1. Exceeding a junction temperature of 175°C for an
extended period of time can result in changes in silicon devices,
potentially causing degradation or loss of functionality. The
power dissipated in the package (PD) is the sum of the quiescent
power dissipation and the power dissipated in the die due to the
ADA4896-2/ADA4897-1 drive at the output.
TJ = 150°C
3.0
2.5
2.0
8-LEAD LFCSP
1.5
8-LEAD SOIC
1.0
8-LEAD MSOP
0.5
6-LEAD SOT-23
0
–45 –35 –25 –15 –5
5
15
25
35
45
55
65 75 85 95 105 115 125
AMBIENT TEMPERAURE (°C)
09447-012
Table 7. Thermal Resistance
θJA
222
61
133
306
⎞ VOUT 2
⎟–
⎟
RL
⎠
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the dual 8-lead LFCSP
(61°C/W), the dual 8-lead MSOP (222°C/W), the single 8-lead
SOIC (133°C/W), and the single 6-lead SOT-23 (306°C/W) on a
JEDEC standard 4-layer board. θJA values are approximations.
θJA is specified for the worst-case conditions, that is, θJA is
specified for a device soldered in a circuit board for surfacemount packages. Table 7 lists the θJA for the ADA4896-2/
ADA4897-1.
Package Type
8-Lead Dual MSOP (ADA4896-2)
8-Lead Dual LFCSP (ADA4896-2)
8-Lead Single SOIC (ADA4897-1)
6-Lead Single SOT-23 (ADA4897-1)
PD = Quiescent Power + (Total Drive Power – Load Power)
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
The quiescent power is the voltage between the supply pins (VS)
multiplied by the quiescent current (IS).
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. 0 | Page 9 of 28
ADA4896-2/ADA4897-1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADA4896-2
7 OUT2
+IN1 3
6 –IN2
–VS 4
5 +IN2
NOTES
1. THE EXPOSED PAD CAN BE
CONNECTED TO GND OR
LEFT FLOATING.
OUT1 1
8
+VS
–IN1 2
7
OUT2
+IN1 3
6
–IN2
–VS
5
+IN2
4
TOP VIEW
(Not to Scale)
Figure 5. 8-Lead MSOP Pin Configuration
Figure 4. 8-Lead LFCSP Pin Configuration
Table 8. ADA4896-2 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
OUT1
−IN1
+IN1
−VS
+IN2
−IN2
OUT2
+VS
EPAD
09447-002
–IN1 2
ADA4896-2
8 +VS
09447-022
OUT1 1
Description
Output 1.
Inverting Input 1.
Noninverting Input 1.
Negative Supply.
Noninverting Input 2.
Inverting Input 2.
Output 2.
Positive Supply.
Exposed Pad. The exposed pad can be connected to GND or left floating.
Rev. 0 | Page 10 of 28
8
DISABLE
7
+VS
6
OUT
5
NC
+IN 3
–VS 4
ADA4897-1
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
09447-016
NC 1
–IN 2
Mnemonic
NC
−IN
+IN
−VS
OUT
+VS
DISABLE
+VS
–VS 2
5
DISABLE
4
–IN
ADA4897-1
Figure 7. 6-Lead SOT-23 Pin Configuration
Table 9. ADA4897-1Pin Function Descriptions
Pin No.
SOT-23
N/A
4
3
2
1
6
5
6
+IN 3
Figure 6. 8-Lead SOIC Pin Configuration
SOIC
1, 5
2
3
4
6
7
8
OUT 1
09447-017
ADA4896-2/ADA4897-1
Description
Do not connect to this pin.
Inverting Input.
Noninverting Input.
Negative Supply.
Output.
Positive Supply.
Disable.
Rev. 0 | Page 11 of 28
ADA4896-2/ADA4897-1
TYPICAL PERFORMANCE CHARACTERISTICS
RL = 1 kΩ,unless otherwise noted.When G > +1, RF = 249 Ω and when G = +1, RF = 0 Ω.
G = –1 OR
G = +2
G = +10
–2
–3
–4
–5
–6
0.1
1
10
100
FREQUENCY (MHz)
20mV p-p
0
100mV p-p
–1
400mV p-p
–2
2V p-p
–3
–4
–5
0.1
0.8
NORMALIZED CLOSED-LOOP GAIN (dB)
VS = +3V
VS = +5V
1
0
VS = ±5V
–1
–2
–3
–4
–5
0.1
1
10
100
FREQUENCY (MHz)
VS = +5V
0.7 VOUT = 2V p-p
G = +2
0.6 RL = 1kΩ
0.4
RF = RG = 49.9Ω
0.3
0.2
0.1
0
–0.1
–0.2
2
NORMALIZED CLOSED-LOOP GAIN (dB)
–2
+25°C
–3
–4
10M
100M
1G
FREQUENCY (Hz)
09447-038
NORMALIZED CLOSED-LOOP GAIN (dB)
–40°C
+125°C
1M
1
10
50
100
FREQUENCY (MHz)
Figure 12. 0.1 dB Bandwidth at Selected RF Value
0
–5
100k
RF = RG = 100Ω
–0.3
0.1
2
–1
RF = RG = 249Ω
0.5
Figure 9. Small Signal Frequency Response vs. Supply Voltage
VS = +5V
G = +1
1 VOUT = 20mV p-p
100
Figure 11. Frequency Response for Various VOUT
09447-005
NORMALIZED CLOSED LOOP GAIN (dB)
G = +1
VOUT = 20mV p-p
10
FREQUENCY (MHz)
Figure 8. Small Signal Frequency Response vs. Gain
2
1
09447-061
–1
1
09447-006
0
VS = ±5V
G = +1
09447-008
G = +1
NORMALIZED CLOSED-LOOP GAIN (dB)
1
2
VS = +5V
VOUT = 20mV p-p
09447-010
NORMALIZED CLOSED-LOOP GAIN (dB)
2
Figure 10. Small Signal Frequency Response vs. Temperature
1
VS = +5V
VOUT = 2V p-p
G = –1
G = +1
0
–1
G = +10
–2
–3
–4
–5
–6
0.1
1
10
FREQUENCY (MHz)
Figure 13. Large Signal Frequency Response vs. Gain
Rev. 0 | Page 12 of 28
ADA4896-2/ADA4897-1
–40
2
DISTORTION (dBc)
1
CL = 20pF
0
–60
–70
RL = 1kΩ, THIRD
–1
–80
RL = 1kΩ, SECOND
CL = 0pF
–2
10
100
–100
0.1
Figure 14. Small Signal Frequency Response vs. Capacitive Load
–60
Figure 17. Harmonic Distortion vs. Frequency, G = +10
–50
VS = +5V
VOUT = 2V p-p
G = +1
–70
–80
RL = 100Ω, THIRD
–90
RL = 1kΩ, THIRD
–70
–80
–100
–110
–110
RL = 1kΩ, SECOND
5
Figure 15. Harmonic Distortion vs. Frequency, G = +1
–40
–50
VS = +5V
VOUT = 2V p-p
G = +5
–50
G = +2
VS = +5V,
SECOND
–60
RL = 100Ω, SECOND
VS = +5V,
THIRD
–70
DISTORTION (dBc)
–70
–80
RL = 100Ω, THIRD
–90
–80
–90
–100
–120
09447-041
5
VS = ±5V,
SECOND
–100
RL = 1kΩ, SECOND
FREQUENCY (MHz)
VS = +3V,
SECOND
VS = ±5V,
THIRD
–110
RL = 1kΩ, THIRD
1
5
1
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Frequency for Various Output Voltages
–60
–110
0.1
2V p-p SECOND
2V p-p THIRD
4V p-p SECOND
4V p-p THIRD
–120
0.1
09447-021
1
FREQUENCY (MHz)
8V p-p THIRD
8V p-p SECOND
–90
–100
–120
0.1
VS = ±5V
G = +1
RL = 1kΩ
–60
RL = 100Ω, SECOND
DISTORTION (dBc)
–50
5
1
FREQUENCY (MHz)
09447-026
1
09447-067
–90
FREQUENCY (MHz)
DISTORTION (dBc)
RL = 100Ω, THIRD
RL = 100Ω, SECOND
–50
–3
0.1
DISTORTION (dBc)
VS = +5V
VOUT = 2V p-p
G = +10
CL = 39pF
–130
0.1
VS = +3V,
THIRD
1
5
FREQUENCY (MHz)
Figure 19. Harmonic Distortion vs. Frequency for Various Supplies
Figure 16. Harmonic Distortion vs. Frequency, G = +5
Rev. 0 | Page 13 of 28
09447-045
3
–30
VS = +5V
G = +2
RL = 100Ω
VOUT = 20mV p-p
09447-007
NORMALIZED CLOSED-LOOP GAIN (dB)
4
ADA4896-2/ADA4897-1
VS = ±5V
100 UNITS
16 σ = 309.2µV/°C
–100
MAGNITUDE
50
PHASE
–140
40
–160
30
–180
20
10
–200
0
14
NUMBER OF PARTS
–120
60
OPEN-LOOP PHASE (Degrees)
70
100k
1M
10M
–240
1G
100M
8
6
2
0
–600
09447-044
–20
10k
10
4
–220
–10
12
FREQUENCY (Hz)
VS = ±5V
VS = +3V
VS = +5V
OUTPUT VOLTAGE (mV)
VOLTAGE NOISE (nV/√Hz)
200
400
600
800
1000
G = +1
VOUT = 20mV p-p
TIME = 100ns/DIV
10
6
5
4
3
2
1
VS = ±5V
0
10
100
1k
10k
100k
1M
5M
09447-027
1
09447-050
–10
FREQUENCY (Hz)
Figure 24. Small Signal Transient Response for Various Supplies
Figure 21. Voltage Noise vs. Frequency
100
VS = ±5V
10
1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 22. Current Noise vs. Frequency
1M
5M
VS = ±5V
G = +2
TME = 100ns/DIV
10
0
–10
09447-039
OUTPUT VOLTAGE (mV)
CL = 39pF
CL = 20pF
CL = 0pF
09447-060
CURRENT NOISE (pA/√Hz)
0
Figure 23. Input Offset Voltage Drift Distribution
7
0
–200
OFFSET DRIFT DISTRIBUTION (nV/°C)
Figure 20. Open-Loop Gain and Phase vs. Frequency
8
–400
09447-066
80
OPEN-LOOP GAIN (dB)
18
–80
90
Figure 25. Small Signal Transient Response for Various Capacitive Loads
Rev. 0 | Page 14 of 28
ADA4896-2/ADA4897-1
VS = +3V
VS = +5V
3
2
10
VOUT
OUTPUT VOLTAGE (mV)
VS = ±5V
VOLTAGE (V)
1
0
0
–1
09447-040
09447-051
–2
–10
–3
VS = ±5V
VOUT = 2V p-p
TIME = 100ns/DIV
G = +2
1.0
G = +1
0.5
0
–0.5
09447-009
–1.0
–1.5
250
VS = +5V
G = +2
200
150
100
50
0
0
100
200
300
400
500
600
700
800
900
OVERLOAD DURATION (ns)
Figure 27. Large Signal Transient Response for Various Gains
VIN
3
TIME = 100ns/DIV
VS = +5V
G = +1
RISING EDGE
100.0
SLEW RATE (V/µs)
2
VOUT
0
–1
–2
97.5
95.0
FALLING EDGE
92.5
90.0
87.5
85.0
82.5
–3
–4
80.0
–40
–25
–10
5
20
35
50
65
80
95
TEMPERATURE (°C)
Figure 31. Slew Rate vs. Temperature
Figure 28. Input Overdrive Recovery
Rev. 0 | Page 15 of 28
110
125
09447-052
1
VOUT = 3V p-p
VS = +5V
G = +2
102.5
09447-049
INPUT AND OUTPUT VOLTAGE (V)
Figure 30. Output Recovery Time vs. Overload Duration
105.0
4
09447-055
1.5
Figure 29. Output Overdrive Recovery
AVERAGE OUTPUT OVERLOAD RECOVERY TIME (ns)
Figure 26. Small Signal Transient Response for Various Supplies, G = +2
OUTPUT VOLTAGE (V)
TIME = 100ns/DIV
VS = +5V
G = +2
2× VIN
G = +2
TIME = 100ns/DIV
ADA4896-2/ADA4897-1
100000
0.3
VS = +5V
G = +2
VOUT = 2V STEP
RL = 1kΩ
TIME = 10ns/DIV
10000
OUTPUT IMPEDANCE (Ω)
0.1
0
–0.1
PART DISABLED
1000
100
10
PART ENABLED
1
0.1
09447-028
–0.2
–0.3
0.01
0.1
1
10
09447-013
SETTLING (%)
0.2
VS = +5V
G = +1
PIN = –30dBm
100
FREQUENCY (MHz)
Figure 35. Output Impedance vs. Frequency
Figure 32. Settling Time to 0.1%
–20
–33.5
VS = +5V
∆VCM = 2V p-p
–40
INPUT OFFSET VOLTAGE (µV)
COMMON-MODE REJECTION (dB)
–30
–50
–60
–70
–80
–90
–100
–110
–31.0
VS = +3V
VS = +5V
–28.5
VS = ±5V
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–26.0
–40
09447-029
–130
1k
0
20
35
50
65
80
95
110
125
–10.50
VS = +5V
∆VS = 2V p-p
G = +1
VS = ±5V
INPUT BIAS CURRENT (µA)
–30
–40
–50
5
Figure 36. Input Offset Voltage vs. Temperature for Various Supplies
–PSRR
–60
–70
+PSRR
–80
–90
–100
–10.75
VS = +5V
–11.00
VS = +3V
–11.25
–110
–130
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 34. PSRR vs. Frequency
–11.50
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 37. Input Bias Current vs. Temperature for Various Supplies
Rev. 0 | Page 16 of 28
09447-046
–120
09447-030
POWER SUPPLY REJECTION (dB)
–20
–10
TEMPERATURE (°C)
Figure 33. CMRR vs. Frequency
–10
–25
09447-042
–120
ADA4896-2/ADA4897-1
3.1
5.0
TIME = 2µs/DIV
VS = +5V
G = +1
VIN = 1V
DISABLE PIN
SUPPLY CURRENT (mA)
4.5
+25°C
4.0
3.0
2.9
2.8
2.7
3.5
DISABLE PIN (V)
VS = +5V
VS = +3V
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
09447-043
–25
3.375
–40°C
3.250
2.5
3.125
2.0
3.000
1.5
2.875
2.750
+125°C
–50
2.625
0
2.500
–0.5
2.375
Figure 41. Turn-Off Time vs. Temperature
Figure 38. Supply Current vs. Temperature for Various Supplies
–40
3.625
3.0
0.5
2.5
–40
3.750
3.500
1.0
2.6
3.875
OUTPUT VOLTAGE (V)
5.5
VS = ±5V
09447-056
3.2
–30
VS = +5V
G = +2
VOUT = 2V p-p
–40
–50
–60
VS = +5V
G = +2
RL = 100Ω
VOUT = 2V p-p
ISOLATION (dB)
CROSSTALK (dB)
–60
–70
–80
–90
–100
–70
–80
–90
–100
–110
–110
–120
–120
0.1
1
10
100
FREQUENCY (MHz)
–140
0.01
09447-014
–130
0.01
3.500
3.0
2.5
+25°C
+125°C
–40°C
3.125
2.875
1.5
0.5
3.250
3.000
2.0
1.0
3.375
TIME = 200ns/DIV
VS = +5V
G = +1
VIN = 1V
0
2.750
2.625
2.500
2.375
–0.5
OUTPUT VOLTAGE (V)
3.625
4.0
09447-054
DISABLE PIN (V)
3.750
4.5
3.5
10
Figure 42. Forward Isolation vs. Frequency
3.875
DISABLE PIN
5.0
1
FREQUENCY (MHz)
Figure 39. Crosstalk OUT1 to OUT2 (ADA4896-2 Only)
5.5
0.1
Figure 40. Turn-On Time vs. Temperature
Rev. 0 | Page 17 of 28
100
09447-015
–130
ADA4896-2/ADA4897-1
THEORY OF OPERATION
AMPLIFIER DESCRIPTION
The ADA4896-2/ADA4897-1 are 1 nV/√Hz input noise
amplifiers that consume 3 mA from supplies ranging from
3 V to 10 V. Utilizing the Analog Devices XFCB3 process, the
bandwidth is in excess of 200 MHz and unity gain stable and
the input structure results in an extremely low input of 1/f noise
for a high speed amplifier. The rail-to-rail output stage is
designed to drive a heavy feedback load required to achieve an
overall low output referred noise. Unlike other low noise unity
gain stable amplifiers, the large signal bandwidth has been
enhanced beyond the typical fundamental limits to meet more
demanding system requirements. The maximum offset of 500 μV
and drift of 1 μV/°C make the ADA4896-2/ADA4897-1 an
excellent amplifier choice even when the noise is not needed
because there is minimal power penalty in achieving the low
input noise or the high bandwidth.
The ESD clamps start to conduct for input voltages that are
more than 0.7 V above the positive supply and input voltages
more than 0.7 V below the negative supply. It is recommended
that the fault current be limited to less than 10 mA if an
overvoltage condition is expected.
DISABLE OPERATION
Figure 44 shows the ADA4897-1 power-down circuitry. If the
DISABLE pin is left unconnected, the base of the input PNP
transistor is pulled high through the internal pull-up resistor to
the positive supply and the part is turned on. Pulling the
DISABLE pin to ≥2 V below the positive supply turns the part
off, reducing the supply current to approximately 18 μA for a
5 V voltage supply.
VCC
IBIAS
ESD
INPUT PROTECTION
DISABLE
The ADA4896-2/ADA4897-1 are fully protected from ESD
events, withstanding human body model ESD events of 2.5 kV
and charge device model events of 1 kV with no measured
performance degradation. The precision input is protected
with an ESD network between the power supplies and diode
clamps across the input device pair, as shown in Figure 43.
ESD
09447-037
TO
AMPLIFIER
BIAS
VEE
VCC
Figure 44. DISABLE Circuit
BIAS
ESD
VP
ESD
The DISABLE pin is protected with ESD clamps, as shown in
Figure 44. Voltages beyond the power supplies cause these
diodes to conduct. For protection of the DISABLE pin, the
voltage to this pin should not exceed 0.7 V of the supply voltage,
or the input current should be restricted to less than 10 mA
with a series resistor.
ESD
VN
ESD
TO THE REST OF THE AMPLIFIER
09447-068
VEE
Figure 43. Input Stage and Protection Diodes
For differential voltages above approximately 0.7 V, the diode
clamps start to conduct. Too much current can cause damage
due to excessive heating. If large differential voltages must
be sustained across the input terminals, it is recommended
that the current through the input clamps be limited to below
10 mA. Series input resistors that are sized appropriately for the
expected differential overvoltage provide the needed protection.
When the amplifier is disabled, its output goes to a high
impedance state. The output impedance decreases as frequency
increases; this effect can be observed in Figure 35. In disable
mode, a forward isolation of 50 dB can be achieved at 10 MHz.
Figure 42 shows the forward isolation vs. frequency data.
Rev. 0 | Page 18 of 28
ADA4896-2/ADA4897-1
DC ERRORS
NOISE CONSIDERATIONS
Figure 45 shows a typical connection diagram and the major dc
error sources.
Figure 46 illustrates the primary noise contributors for the
typical gain configurations. The total rms output noise is
the root-mean-square of all the contributions.
RF
+ VOUT –
IB–
ven
RG
vn _ RG = 4kT × RG
+ vout_en –
ien
RS
IB+
RS
vn _ RS = 4kT × RS
iep
Figure 45. Typical Connection Diagram and DC Error Sources
Figure 46. Noise Sources in Typical Connection
The ideal transfer function (all error sources set to 0 and
infinite dc gain) can be written as
⎞
⎛R
⎟ × VIP − ⎜ F
⎟
⎜R
⎠
⎝ G
The output noise spectral density can be calculated by
⎞
⎟ × VIN
⎟
⎠
(1)
This reduces to the familiar forms for inverting and
noninverting op amp gain expressions, as follows:
⎞
⎟ ×VIP
⎟
⎠
(2)
(Inverting gain, VIP = 0 V)
⎛ − RF
VOUT = ⎜⎜
⎝ RG
⎞
⎟ ×VIN
⎟
⎠
(3)
The total output voltage error is the sum of errors due to the
amplifier offset voltage and input currents. The output error
due to the offset voltage can be estimated as
VOUTERROR =
VCM VP − VPNOM VOUT ⎞ ⎛ R F ⎞
⎛
⎟
+
+
⎜ VOFFSET NOM +
⎟ × ⎜1 +
CMRR
PSRR
A ⎠ ⎜⎝ RG ⎟⎠
⎝
(4)
where:
VOFFSETNOM is the offset voltage at the specified supply voltage,
which is measured with the input and output at midsupply.
VCM is the common-mode voltage.
VP is the power supply voltage.
VPNOM is the specified power supply voltage.
CMRR is the common-mode rejection ratio.
PSRR is the power supply rejection ratio.
A is the dc open-loop gain.
⎞
⎛ R
⎟ I B − − RS × ⎜ 1 + F
⎟
⎜ R
G
⎠
⎝
⎞
⎟ × I B+
⎟
⎠
2
[
]
2
2
2
⎞
⎛R ⎞
⎟⎟ 4kTRs + iep RS 2 + ven + ⎜⎜ F ⎟⎟ 4kTRG + ien 2 RF 2
⎠
⎝ RG ⎠
where:
k is Boltzmann’s Constant.
T is the absolute temperature, degrees Kelvin.
ien is the amplifier input current noise spectral density, pA/√Hz.
ven is the amplifier input voltage spectral density, nV/√Hz.
RS is the source resistance, as shown in Figure 46.
RF and RG are the feedback network resistances, as shown in
Figure 46.
Source resistance noise, amplifier voltage noise (ven), and the
voltage noise from the amplifier current noise (iep × RS) are all
subject to the noise gain term (1 + RF/RG). Note that with a
1 nV/√Hz input voltage noise and 2.8 pA/√Hz input current,
the noise contributions of the amplifier are relatively small for
source resistances between approximately 50 Ω and 700 Ω.
Figure 47 shows the total RTI noise due to the amplifier vs. the
source resistance. In addition, the value of the feedback resistors
used impacts the noise. It is recommended that the value of the
feedback resistors be maintained between 250 Ω and 1 kΩ to
keep the total noise low.
500
The output error due to the input currents can be estimated as
⎛ R
VOUTERROR = (RF || RG ) × ⎜⎜ 1 + F
⎝ RG
⎛ R
4kTRF + ⎜⎜1 + F
⎝ RG
(6)
(Noninverting gain, VIN = 0 V)
⎛ R
VOUT = ⎜⎜ 1 + F
⎝ RG
vout _ en =
NOISE (nV/√Hz)
⎛ R
VOUT = ⎜⎜1 + F
⎝ RG
09447-034
09447-031
– VIP +
vn _ RF = 4kT × RF
RF
+ VOS –
RG
50
AMPLIFIER AND
RESISTOR NOISE
5
SOURCE
RESISTANCE NOISE
(5)
Note that setting RS equal to RF||RG compensates for the voltage
error due to the input bias current.
TOTAL
AMPLIFIER NOISE
0.5
50
500
5k
SOURCE RESISTANCE (Ω)
Figure 47. RTI Noise vs. Source Resistance
Rev. 0 | Page 19 of 28
50k
09447-057
– VIN +
ADA4896-2/ADA4897-1
Putting a small snub resistor (RSNUB) in series with the amplifier
output and the capacitive load mitigates the problem. Figure 48
shows the effect of using a snub resistor (RSNUB) on reducing the
peaking for the worst-case frequency response (gain of +2).
Using RSNUB = 100 Ω eliminates the peaking entirely, with the
trade-off that the closed-loop gain is reduced by 0.8 dB due to
attenuation at the output. RSNUB can be adjusted from 0 Ω to
100 Ω to maintain an acceptable level of peaking and closedloop gain, as shown in Figure 48.
CAPACITANCE DRIVE
Capacitance at the output of an amplifier creates a delay
within the feedback path that, if within the bandwidth of
the loop, can create excessive ringing and oscillation. The
ADA4897-1/ADA4896-2 show the most peaking at a gain
of +2, as demonstrated in Figure 8.
VS = 5V
VOUT = 200mV p-p
2 G = +2
RSNUB = 0Ω
1
RSNUB = 50Ω
RSNUB = 100Ω
0
–1
R2
249Ω
–2
R1
249Ω
–3
–4
ADA4896-2
VIN
–5
100k
RSNUB VOUT
RL
1kΩ
1M
10M
FREQUENCY (Hz)
CL
39pF
100M
09447-058
NORMALIZED CLOSED-LOOP GAIN (dB)
3
Figure 48. Using a Snub Resistor to Reduce Peaking Due to Output Capacitive Load
Rev. 0 | Page 20 of 28
ADA4896-2/ADA4897-1
APPLICATIONS INFORMATION
2
VS = +5V
VOUT = 200mV p-p
1 RF = 249Ω
RL = 1kΩ
G = +5
G = +2
0
–1
G = +10
G = +1
–2
G = +20
–3
–4
–5
–6
100k
1M
10M
100M
500M
FREQUENCY (Hz)
Figure 49. Small Signal Frequency Response at Various Gains
Table 10. Recommended Values and Typical Performance
Gain
+1
+2
+5
+10
+20
RF (Ω)
0
249
249
249
249
RG (Ω)
N/A
249
61.9
27.4
13.0
−3 dB BW
(MHz)
92
54
30
17
9
Slew Rate
(tR/tF) (V/μs)
78/158
101/140
119/137
87/88
37/37
Peaking
(dB)
0.8
1.2
0
0
0
Output Voltage Noise
Only (nV/√Hz)
1
2
5
10
20
Rev. 0 | Page 21 of 28
Total Output Noise
Including Resistors (nV/√Hz)
1.0
3.6
6.8
12.0
21.1
09447-020
To reduce design time and eliminate uncertainty, Table 10
provides a convenient reference for typical gains, component
values, and performance parameters. The supply voltage used
is 5 V. The bandwidth is obtained with a small signal output
of 200 mV p-p, and the slew rate is obtained with a 2 V
output step. Note that as the gain increases, the small-signal
bandwidth decreases, as is expected from the gain bandwidth
product relationship. In addition, the phase margin improves
with higher gains, and the amplifier becomes more stable. As
a result, the peaking in the frequency response is reduced (see
Figure 49).
NORMALIZED CLOSED-LOOP GAIN (dB)
TYPICAL PERFORMANCE VALUES
ADA4896-2/ADA4897-1
LOW NOISE GAIN SELECTABLE AMPLIFIER
USING S3B IS OPTIONAL
RF2
450Ω
S3B
RF1
150Ω
+5V
6
+5V
8
2
S1B
ADA4896-2
3
VIN
1
D1
V01
S1A
V1
V2
8
ADA4896-2
S2B
D2 5
7
V02
RL
4
S2A
–5V
4
09447-100
RG1
150Ω
D3
–5V
Figure 50. Using the ADA4896-2 and the ADG633 to Construct a Low Noise Gain Selectable Amplifier to Drive a Low Resistive Load
A gain selectable amplifier makes processing a wide range of
input signals possible. The traditional gain selectable amplifier
involves switches in the feedback loops connecting to the
inverting input. In this case the switch resistance degrades the
noise performance of the amplifier, as well as adding significant
capacitance on the inverting input node. The noise and capacitance issue can be especially bothersome when working with
low noise amplifiers. Also, the switch resistances contribute to
nonlinear gain error, which is undesirable.
Figure 50 presents an innovative switching technique used in
the gain selectable amplifier such that the 1 nV/Hz noise performance of the ADA4896-2 is preserved, while the nonlinear
gain error is much reduced. With this technique, one can also
choose switches with minimal capacitance, which optimizes the
bandwidth of the circuit. In this circuit, the switches are
implemented with the ADG633 and they are configured such
that either S1A and S2A are on, or S1B and S2B are on. In this
example, when the S1A and S2A switches are on, the first stage
amplifier gain is +4. When the S1B and S2B switches are on, the
first stage amplifier gain is +2. The first set of switches of the
ADG633 is put in the output side of the feedback loop and the
second set of switches is used to sample at a point (V1 and V2)
where switch resistances and nonlinear resistances do not matter.
This way, the gain error can be reduced while preserving the
noise performance of the ADA4896-2/ADA4897-1.
⎛
R + RS1 ⎞
⎟
V01 = VIN × ⎜⎜1 + F1
RG1 ⎟⎠
⎝
(1)
⎛ RF1 + RG1 ⎞
⎟⎟
V1 = V01 × ⎜⎜
⎝ RF1 + RG1 + RS1 ⎠
(2)
Substituting (1) into (2), the following derivation is obtained
⎛ R ⎞
V1 = VIN × ⎜⎜1 + F1 ⎟⎟
⎝ RG1 ⎠
Figure 51 compares the gain errors when the output signal is
sampled at V01 vs. V02 for a range of dc inputs. Note that
sampling at V02 reduces the gain error significantly, as predicted in
Equation 3. Figure 52 shows the normalized frequency response
of the circuit at V02.
–0.15
12.5
–0.20
V01
–0.25
12.0
–0.30
11.5
0
0.5
1.0
1.5
INPUT VOLTAGE (V)
2.0
11.0
09447-063
–0.35
VS = ±5V
3 VIN = 100mV p-p
RL = 1kΩ
0
–3
G = +4
–6
G = +2
–9
–12
–15
–18
–21
–24
–27
–30
100k
Figure 51. Gain Errors at V01 vs. V02
1M
10M
100M
FREQUENCY (Hz)
Figure 52. Frequency Response of V02/VIN
Rev. 0 | Page 22 of 28
500M
09447-064
13.0
GAIN ERROR AT V01 (%)
V02
NORMALIZED CLOSED-LOOP GAIN (dB)
13.5
–0.05
–0.10
(3)
6
0
GAIN ERROR AT V02 (%)
The following derivation shows that sampling at V1 yields the
desired signal gain without gain error. RS denotes the switch
resistance. V2 can be derived with the same method.
14.0
0.05
–0.40
It should be noted that the input bias current of the output
buffer can cause problems with the impedance of the S2A and
S2B sampling switches. Both sampling switches are not only
nonlinear with voltage but with temperature as well. If this is an
issue, place the unused switch of the ADG633 in the feedback
path of the output buffer, as shown in Figure 50, to balance the
bias currents.
ADA4896-2/ADA4897-1
MEDICAL ULTRASOUND APPLICATIONS
BEAMFORMER
CENTRAL CONTROL
Tx BEAMFORMER
AD9279
HV
MUX/
DEMUX
T/R
SWITCHES
LNA
ADC
VGA
AAF
Rx BEAMFORMER
(B AND F MODES)
TRANSDUCER
ARRAY
SPECTRAL
DOPPLER
PROCESSING
MODE
ADA4896-2/
ADA4897-1
AUDIO
OUTPUT
IMAGE AND
MOTION
PROCESSING
(B MODE)
COLOR
DOPPLER (PW)
PROCESSING
(F MODE)
DISPLAY
09447-033
CW (ANALOG)
BEAMFORMER
Figure 53. Simplified Ultrasound System Block Diagram
Overview of the Ultrasound System
Medical ultrasound systems are among the most sophisticated
signal processing systems in widespread use today. By transmitting acoustic energy into the body and receiving and processing
the returning reflections, ultrasound systems can generate
images of internal organs and structures, map blood flow
and tissue motion, and provide highly accurate blood velocity
information. Figure 53 shows a simplified block diagram of an
ultrasound system.
The ultrasound system consists of two main operations, the
time gain control (TGC) operation and the continuous wave
(CW) Doppler operation. The AD9279 integrates the essential
components of these two operations into a single IC. It contains
eight channels of a variable gain amplifier (VGA) with a low
noise preamplifier (LNA), an antialiasing filter (AAF), an
analog-to-digital converter (ADC), and an I/Q demodulator
with programmable phase rotation. For detailed information
about how to use the AD9279 in the ultrasound system, refer to
the AD9279 data sheet.
ADA4896-2/ADA4897-1 in the Ultrasound System
The ADA4896-2/ADA4897-1 are used in the CW Doppler path
in the ultrasound application after the I/Q demodulators of
the AD9279. Doppler signals can be typically between 100 Hz
to 100 kHz.The low noise floor, high dynamic range of the
ADA4896-2/ADA4897-1 makes them an excellent choice for
processing weak Doppler signals.
The rail-to-rail output feature and the high output current drive
of the ADA4896-2/ADA4897-1 make them a suitable candidate
for the I-to-V converter, summer, and as a ADC driver.
Figure 54 shows an interconnection block diagram of all eight
channels of the AD9279. Two stages of ADA4896-2 amplifiers
are used. The first stage does an I-to-V conversion and filters
the high frequency content that results from the demodulation
process. The second stage of ADA4896-2 amplifiers is used to
sum the output currents of multiple AD9279, to provide gain,
and to drive the AD7982, an 18-bit SAR ADC.
The output-referred noise of the CW signal path depends on
the LNA gain and the selection of the first stage summing
amplifier and the value of RFILT. To determine the output
referred noise, it is important to know the active low-pass
filter (LPF) values RA, RFILT, and CFILT, as shown as Figure 54.
Typical filter values for all eight channels of a single AD9279
are 100 Ω for RA, 500 Ω for RFILT, and 2.0 nF for CFILT; these
values implement a 100 kHz single-pole LPF.
The gain of the I-to-V converter can be increased by increasing
the filter resistor, RFILT. To keep the corner frequency the same,
decrease the filter capacitor, CFILT, by the same factor. The factor
limiting the magnitude of the gain is the output swing and drive
capability of the op amp selected for the I-to-V converter, in
this example, the ADA4896-2/ADA4897-1. Because any
amplifier has limited drive capability, there is a finite number of
channels that can be summed.
Rev. 0 | Page 23 of 28
ADA4896-2/ADA4897-1
RFILT
CHANNEL A
CFILT
CWI+
Φ
AD7982
50Ω
1.5V
LNA
1.5V
Φ
ADA4896-2/
ADA4897-1
2.5V
2.5V
ADA4896-2/
ADA4897-1
50Ω
18-BIT ADC
I
CWI–
RA
4nF
CFILT
RFILT
RFILT
CWQ+
RA
CFILT
AD7982
50Ω
Φ
CHANNEL H
1.5V
1.5V
LNA
ADA4896-2/
ADA4897-1
2.5V
2.5V
ADA4896-2/
ADA4897-1
50Ω
18-BIT ADC
Q
CWQ–
RA
Φ
CFILT
4nF
RFILT
4
LO
GENERATION
09447-032
4LO–
4LO+
RESET
AD9279
Figure 54. Using the ADA4896-2/ADA4897-1 as Filters, I-to-V Converters, Current Summers, and ADC Drivers After the I/Q Outputs of the AD9279
LAYOUT CONSIDERATIONS
To ensure optimal performance, careful and deliberate attention
must be paid to the board layout, signal routing, power supply
bypassing, and grounding.
GROUND PLANE
It is important to avoid ground in the areas under and around
the input and output of the ADA4896-2/ADA4897-1. Stray
capacitance created between the ground plane and the input
and output pads of a device are detrimental to high speed
amplifier performance. Stray capacitance at the inverting
input, along with the amplifier input capacitance, lowers the
phase margin and can cause instability. Stray capacitance at
the output creates a pole in the feedback loop. This can reduce
phase margin and can cause the circuit to become unstable.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect in the performance
of the ADA4896-2/ADA4897-1. A parallel connection of capacitors from each of the power supply pins to ground works best.
Smaller value capacitors offer better high frequency response,
whereas larger value electrolytics offer better low frequency
performance. Paralleling different values and sizes of capacitors
helps to ensure that the power supply pins are provided a low ac
impedance across a wide band of frequencies. This is important for
minimizing the coupling of noise into the amplifier. This can be
especially important when the amplifier PSR is starting to roll
off—the bypass capacitors can help lessen the degradation in
PSR performance.
Starting directly at the ADA4896-2/ADA4897-1 power supply
pins, the smallest value capacitor should be placed on the same
side of the board as the amplifier, and as close as possible to the
amplifier power supply pin. The ground end of the capacitor
should be connected directly to the ground plane. Keeping the
capacitor’s distance short but equal from the load is important
and can improve distortion performance. This process should
be repeated for the next largest value capacitor.
It is recommended that a 0.1 μF ceramic 0508 case be used. The
0508 case size offers low series inductance and excellent high
frequency performance. A 10 μF electrolytic capacitor should be
placed in parallel with the 0.1 μF capacitor. Depending on the
circuit parameters, some enhancement to performance can be
realized by adding additional capacitors. Each circuit is different
and should be individually analyzed for optimal performance.
Rev. 0 | Page 24 of 28
ADA4896-2/ADA4897-1
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497)
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
012407-A
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
3.20
3.00
2.80
3.20
3.00
2.80
8
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.23
0.09
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 56. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. 0 | Page 25 of 28
0.80
0.55
0.40
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
ADA4896-2/ADA4897-1
3.00
2.90
2.80
1.70
1.60
1.50
6
5
4
1
2
3
PIN 1
INDICATOR
3.00
2.80
2.60
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.30 MIN
0.20 MAX
0.08 MIN
10°
4°
0°
SEATING
PLANE
0.55
0.45
0.35
0.60
BSC
12-16-2008-A
1.30
1.15
0.90
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 57. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
2.44
2.34
2.24
3.10
3.00 SQ
2.90
0.50 BSC
8
5
0.50
0.40
0.30
0.80
0.75
0.70
0.30
0.25
0.20
1
4
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
1.70
1.60
1.50
EXPOSED
PAD
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 58. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-11)
Dimensions shown in millimeters
Rev. 0 | Page 26 of 28
PIN 1
INDICATOR
(R 0.15)
01-24-2011-B
PIN 1 INDEX
AREA
ADA4896-2/ADA4897-1
ORDERING GUIDE
Model 1
ADA4896-2ARMZ
ADA4896-2ARMZ-R7
ADA4896-2ARMZ-RL
ADA4896-2ACPZ-R2
ADA4896-2ACPZ-R7
ADA4896-2ACPZ-RL
ADA4896-2ACP-EBZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
ADA4896-2ARM-EBZ
ADA4897-1ARZ
ADA4897-1ARZ-R7
ADA4897-1ARZ-RL
ADA4897-1ARJZ-R2
ADA4897-1ARJZ-R7
ADA4897-1ARJZ-RL
ADA4897-1AR-EBZ
ADA4897-1ARJ-EBZ
1
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead MSOP
8-Lead MSOP
8-Lead MSOP
8-Lead LFCSP_WD
8-Lead LFCSP_WD
8-Lead LFCSP_WD
Evaluation Board for the
8-Lead LFCSP
Evaluation Board for the
8-Lead MSOP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
6-Lead SOT-23
6-Lead SOT-23
6-Lead SOT-23
Evaluation Board for the
8-Lead SOIC_N
Evaluation Board for the
6-Lead SOT-23
Z = RoHS Compliant Part.
Rev. 0 | Page 27 of 28
Package Option
RM-8
RM-8
RM-8
CP-8-11
CP-8-11
CP-8-11
Ordering Quantity
50
1,000
3,000
250
1,500
5,000
Branding
H2P
H2P
H2P
H2P
H2P
H2P
R-8
R-8
R-8
RJ-6
RJ-6
RJ-6
98
1,000
2,500
250
3,000
10,000
H2K
H2K
H2K
ADA4896-2/ADA4897-1
NOTES
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09447-0-7/11(0)
Rev. 0 | Page 28 of 28