Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD17570Q5B SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 CSD17570Q5B 30 V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • 1 Product Summary Ultra-Low Resistance Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5 mm × 6 mm Plastic Package TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 30 V Qg Gate Charge Total (4.5 V) 93 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage 3 Description 8 1 7 2 G 4 0.56 mΩ 1.5 V Device Qty Media Package Ship 2500 13-Inch Reel CSD17570Q5BT 250 7-Inch Reel SON 5 × 6 mm Plastic Package Tape and Reel Absolute Maximum Ratings VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 100 Continuous Drain Current (Silicon limited), TC = 25°C 407 D ID 3 VGS = 10 V TA = 25°C Top Icon S mΩ (1) For all available packages, see the orderable addendum at the end of the data sheet. This 30 V, 0.56 mΩ, SON 5 × 6 mm NexFET™ power MOSFET is designed to minimize resistance for ORing and hot swap applications and is not intended for switching applications. S nC 0.74 CSD17570Q5B ORing and Hot Swap Applications S 34 VGS = 4.5 V Ordering Information(1) 2 Applications • UNIT VDS D 6 D 5 D D P0093-01 A Continuous Drain Current, TA = 25°C(1) 53 IDM Pulsed Drain Current, TA = 25°C(2) 400 A PD Power Dissipation(1) 3.2 W TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 90 A, L = 0.1 mH, RG = 25 Ω 450 mJ (1) Typical RθJA = 40°C/W on a 1 inch2 , 2 oz. Cu pad on a 0.06 inch thick FR4 PCB. (2) Pulse duration ≤100 μs, duty cycle ≤2% . . . . RDS(on) vs VGS Gate Charge 10 TC = 25°C, I D = 50A TC = 125°C, I D = 50A 1.8 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 2 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 50A VDS = 15V 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 120 140 160 180 200 Qg - Gate Charge (nC) G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17570Q5B SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q5B Package Dimensions ........................................ 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Pattern ................................. 9 Q5B Tape and Reel Information ............................. 10 4 Revision History Changes from Revision B (August 2014) to Revision C • Page Corrected Pulsed Drain Current to read 400 A ..................................................................................................................... 1 Changes from Revision A (May 2014) to Revision B Page • Updated Figure 1 to state Max RθJC = 0.8ºC/W .................................................................................................................... 4 • Updated the SOA in Figure 10 .............................................................................................................................................. 6 Changes from Original (February 2014) to Revision A • 2 Page Updated the mechanical drawing .......................................................................................................................................... 8 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B CSD17570Q5B www.ti.com SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On-Resistance gƒs Transconductance 30 1.1 V 1.5 1.9 V VGS = 4.5 V, ID = 50 A 0.74 0.92 mΩ VGS = 10 V, ID = 50 A 0.56 0.69 mΩ VDS = 15 V, ID = 50 A 271 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance 10400 13600 pF 1450 1890 pF Crss RG Reverse Transfer Capacitance 877 1140 pF Series Gate Resistance 1.8 3.6 Ω Qg Gate Charge Total (4.5 V) 93 121 nC Qgd Gate Charge Gate-to-Drain Qgs Gate Charge Gate-to-Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tƒ Fall Time VGS = 0 V, VDS = 15 V, ƒ = 1 MHz VDS = 15 V, ID = 50 A VDS = 15 V, VGS = 0 V VDS = 15 V, VGS = 10 V, IDS = 50 A, RG = 0 Ω 34 nC 27 nC 17 nC 40 nC 5 ns 36 ns 144 ns 74 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage ISD = 50 A, VGS = 0 V 0.8 1 V Qrr Reverse Recovery Charge nC Reverse Recovery Time VDS= 15 V, IF = 50 A, di/dt = 300 A/μs 34 trr 51 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC MIN TYP MAX RθJC Junction-to-Case Thermal Resistance (1) 0.8 RθJA Junction-to-Ambient Thermal Resistance (1) (2) 50 (1) (2) UNIT °C/W RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B 3 CSD17570Q5B SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B CSD17570Q5B www.ti.com SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 Typical MOSFET Characteristics (continued) 200 200 180 180 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) (TA = 25°C unless otherwise stated) 160 140 120 100 80 60 VGS =10V VGS =6V VGS =4.5V 40 20 0 0 160 140 120 100 80 60 TC = 125°C TC = 25°C TC = −55°C 40 20 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 VDS - Drain-to-Source Voltage (V) G001 VDS = 5V 0 0.5 Figure 2. Saturation Characteristics G001 ID = 50A VDS = 15V 9 8 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 4 100000 7 6 5 4 3 10000 1000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 2 1 0 20 40 100 60 80 100 120 140 160 180 200 Qg - Gate Charge (nC) G001 0 3 6 Figure 4. Gate Charge 9 12 15 18 21 24 VDS - Drain-to-Source Voltage (V) 27 30 G001 Figure 5. Capacitance 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 −75 −50 −25 0 25 50 75 100 125 150 175 TC - Case Temperature (ºC) G001 Figure 6. Threshold Voltage vs Temperature RDS(on) - On-State Resistance (mΩ) 2 ID = 250uA VGS(th) - Threshold Voltage (V) 3.5 Figure 3. Transfer Characteristics 10 0 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) TC = 25°C, I D = 50A TC = 125°C, I D = 50A 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B 5 CSD17570Q5B SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 1.6 100 VGS = 4.5V VGS = 10V ISD − Source-to-Drain Current (A) Normalized On-State Resistance 1.8 1.4 1.2 1 0.8 0.6 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 ID =50A 0.4 −75 −50 −25 0 25 50 75 100 125 150 175 200 TC - Case Temperature (ºC) G001 0.0001 0 Figure 8. Normalized On-State Resistance vs Temperature 10us 100us 1ms 10ms DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) G001 200 100 10 1 Single Pulse Max RthetaJC = 0.8ºC/W 0.1 0.1 1 Figure 9. Typical Diode Forward Voltage 5000 1000 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25ºC TC = 125ºC 100 10 0.01 G001 Figure 10. Maximum Safe Operating Area 0.1 TAV - Time in Avalanche (mS) 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain- to- Source Current (A) 120 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 150 175 200 TC - Case Temperature (ºC) G001 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B CSD17570Q5B www.ti.com SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B 7 CSD17570Q5B SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q5B Package Dimensions K H D3 6 D1 4 5 e 6 4 3 3 5 D2 7 2 E 2 7 ө 1 8 1 8 L b (8x) c1 E1 d1 Top View d2 Bottom View Side View ө Front View DIM MILLIMETERS MIN NOM MAX A 0.80 1.00 1.05 b 0.36 0.41 0.46 c 0.15 0.20 0.25 c1 0.15 0.20 0.25 c2 0.20 0.25 0.30 D1 4.90 5.00 5.10 D2 4.12 4.22 4.32 D3 3.90 4.00 4.10 d 0.20 0.25 0.30 d1 0.085 TYP d2 0.319 0.369 0.419 E 4.90 5.00 5.10 E1 5.90 6.00 6.10 E2 3.48 3.58 3.68 e H 0.36 0.46 0.56 L 0.46 0.56 0.66 L1 0.57 0.67 0.77 θ 0° – – K 8 1.27 TYP 1.40 TYP Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B CSD17570Q5B www.ti.com SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 7.2 Recommended PCB Pattern (0.175) 4.440 5 (0.028) 0.710 (0.043) 1.100 C L 4 (0.023) 0.590 1.270 (0.028) SYM C L (0.178) 4.520 1 8 0.560 (0.022) (0.136) 3.456 0.710 (0.028) (0.054) (0.039) 0.984 1.372 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Pattern (0.020) 0.508 x4 (0.011) 0.286 (0.014) 0.350 (0.022) 0.562 x 4 (0.029) 0.746 x 8 2.186 (0.086) 4.318 (0.170) 0.300 (0.012) 1.270 (0.050) (0.030) 0.766 (0.051) 1.294 x8 (0.060) 1.525 1.270 (0.050) (0.042) 1.072 (0.259) 6.586 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B 9 CSD17570Q5B SLPS471C – FEBRUARY 2014 – REVISED FEBRUARY 2015 www.ti.com K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5B Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket. 10 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: CSD17570Q5B PACKAGE OPTION ADDENDUM www.ti.com 2-May-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD17570Q5B ACTIVE VSON-CLIP DNK 8 2500 Pb-Free (RoHS Exempt) CU NIPDAU Level-1-260C-UNLIM CSD17570 CSD17570Q5BT ACTIVE VSON-CLIP DNK 8 250 Pb-Free (RoHS Exempt) CU NIPDAU Level-1-260C-UNLIM CSD17570 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. 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