LODEV LMA1009 12 x 12-bit multiplier-accumulator Datasheet

LMA 1009/2009
LMA1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
12 x 12-bit Multiplier-Accumulator
DEVICES INCORPORATED
FEATURES
DESCRIPTION
❑ 20 ns Multiply-Accumulate Time
❑ Low Power CMOS Technology
❑ Replaces Fairchild TDC1009/
TMC2009
❑ Two’s Complement or Unsigned
Operands
❑ Accumulator Performs Preload,
Accumulate, and Subtract
❑ Three-State Outputs
❑ 68-pin PLCC, J-Lead
LMA1009/2009 BLOCK DIAGRAM
CLK A
CLK B
REGISTER
RND
TC
ACC
SUB
Data present at the A and B input registers is latched on the rising edges of
CLK A and CLK B respectively. RND,
TC, ACC, and SUB controls are latched
on the rising edge of the logical OR of
CLK A and CLK B. TC specifies the input
as two’s complement
(TC HIGH) or unsigned magnitude
(TC LOW). RND, when HIGH, adds ‘1’
to the most significant bit position of the
least significant half of the product. SubThe LMA1009/2009 produces the 24-bit
sequent truncation of the 12 least signifiproduct of two 12-bit numbers. The
cant bits produces a result correctly
results of a series of multiplications may
rounded to 12-bit precision.
be accumulated to form the sum of products. Accumulation is performed to The ACC and SUB inputs control accu27-bit precision with the multiplier prod- mulator operation. ACC HIGH results in
addition of the multiplier product and
uct sign extended as appropriate.
the accumulator contents, with the result
stored in the accumulator register on the
rising edge of CLK R. ACC and SUB
A 11-0
B 11-0
HIGH results in subtraction of the accu12
12
mulator contents from the multiplier
A REGISTER
B REGISTER
product, with the result stored in the
accumulator register. With ACC LOW
and SUB LOW, no accumulation occurs
and the next product is loaded directly
into the accumulator register. ACC LOW
and SUB HIGH is undefined.
The LMA1009 and LMA2009 are highspeed, low power 12-bit multiplier-accumulators. They are pin-for-pin equivalent to the TRW TDC1009/TMC2009
multiplier-accumulators. The LMA1009
and LMA2009 are functionally identical;
they differ only in packaging. Full ambient temperature range operation is
achieved by the use of advanced CMOS
technology.
R + A
OEX
OEM
OEL
PRELOAD
CONTROL
LOGIC
The LMA1009/2009 output register (accumulator register) is divided into three
independently controlled sections. The
least significant result (LSR) and most
significant result (MSR) registers are 12
bits in length. The extended result register (XTR) is 3 bits long.
24
R
3
A
R – A
PASS R
LEX
LEM
LEL
27
PREL
3
OEX
OEM
OEL
LEX
27
LEM
3
CLK R
LEL
12
12
ACCUMULATOR REGISTER
OEX
3
R 26-24
OEL
OEM
12
12
R 23-12
Each output register has an independent output enable control. In addition
to providing control of the three-state
output buffers, when OEX, OEM, or
OEL are HIGH and PREL is HIGH, data
can be preloaded via the bidirectional
output pins into the respective output
registers. Data present on the output
pins is latched on the rising edge of
CLK R. The interrelation of PREL and
the enable controls is summarized in
Table 1.
R 11-0
Multiplier-Accumulators
1
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
TABLE 1. PRELOAD TRUTH TABLE
PREL OEX
OEM
OEL
XTR
MSR LSR
L
L
L
L
OUT
OUT OUT
L
L
L
H
OUT
OUT
Z
L
L
H
L
OUT
Z
OUT
L
L
H
H
OUT
Z
Z
L
H
L
L
Z
OUT OUT
L
H
L
H
Z
OUT
Z
L
H
H
L
Z
Z
OUT
L
H
H
H
Z
Z
Z
H
L
L
L
Z
Z
Z
H
L
L
H
Z
Z
PREL
H
L
H
L
Z
PREL
Z
H
L
H
H
Z
PREL PREL
H
H
L
L
PREL
Z
Z
H
H
L
H
PREL
Z
PREL
H
H
H
L
PREL PREL
H
H
H
H
PREL PREL PREL
INPUT FORMATS
AIN
BIN
Fractional Two’s Complement (TC = 1)
11 10 9
–20 2–1 2–2
2 1 0
2–9 2–10 2–11
11 10 9
–20 2–1 2–2
2 1 0
2–9 2–10 2–11
(Sign)
(Sign)
Integer Two’s Complement (TC = 1)
11 10 9
–211 210 29
2 1 0
22 21 20
11 10 9
–211 210 29
2 1 0
22 21 20
(Sign)
(Sign)
Unsigned Fractional (TC = 0)
11 10 9
2–1 2–2 2–3
2 1 0
2–10 2–11 2–12
Z
PREL = Preload data to appropriate register
OUT = Register available on output pins
Z
= High impedance state
FIGURE 1B.
FIGURE 1A.
11 10 9
2–1 2–2 2–3
2 1 0
2–10 2–11 2–12
Unsigned Integer (TC = 0)
11 10 9
211 210 29
2 1 0
22 21 20
11 10 9
211 210 29
2 1 0
22 21 20
OUTPUT FORMATS
MSR
XTR
LSR
Fractional Two’s Complement
26 25 24
–24 23 22
23 22 21
21 20 2–1
14 13 12
2–8 2–9 2–10
11 10 9
2–11 2–12 2–13
2 1 0
2–20 2–21 2–22
11 10 9
211 210 29
2 1 0
22 21 20
11 10 9
2–13 2–14 2–15
2 1 0
2–22 2–23 2–24
11 10 9
211 210 29
2 1 0
22 21 20
(Sign)
Integer Two’s Complement
26 25 24
–226 225 224
23 22 21
223 222 221
14 13 12
214 213 212
(Sign)
Unsigned Fractional
26 25 24
22 21 20
23 22 21
2–1 2–2 2–3
14 13 12
2–10 2–11 2–12
Unsigned Integer
26 25 24
226 225 224
23 22 21
223 222 221
14 13 12
214 213 212
Multiplier-Accumulators
2
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
OPERATING CONDITIONS To meet specified electrical and switching characteristics
Mode
Temperature Range (Ambient)
Active Operation, Commercial
Active Operation, Military
Supply Voltage
0°C to +70°C
4.75 V ≤ VCC ≤ 5.25 V
–55°C to +125°C
4.50 V ≤ VCC ≤ 5.50 V
ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4)
Symbol
Parameter
Test Condition
Min
VOH
Output High Voltage
VCC = Min., IOH = –2.0 mA
2.4
VOL
Output Low Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input High Voltage
VIL
Input Low Voltage
(Note 3)
IIX
Input Current
IOZ
Typ
Max
Unit
V
0.5
V
2.0
VCC
V
0.0
0.8
V
Ground ≤ VIN ≤ VCC (Note 12)
±20
µA
Output Leakage Current
Ground ≤ VOUT ≤ VCC (Note 12)
±20
µA
ICC1
VCC Current, Dynamic
(Notes 5, 6)
25
mA
ICC2
VCC Current, Quiescent
(Note 7)
1.0
mA
12
Multiplier-Accumulators
3
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
SWITCHING CHARACTERISTICS
COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns)
Symbol
LMA1009/2009–
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*
75
55*
45
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Min Max Min Max Min Max
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75
55
45
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15
15
15
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15
15
12
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2
2
2
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15
15
12
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2
2
2
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30
25
25
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30
30
25
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25
25
25
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Parameter
tMC
Clocked Multiply Time
tPW
Clock Pulse Width
tS
Input Register Setup Time
tH
Input Register Hold Time
tSP
Preload Setup Time
tHP
Preload Hold Time
tD
Output Delay
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
20
Min
Max
20
8
10
2
10
2
18
18
18
MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns)
Symbol
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LMA1009/2009–
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*
95
65*
55*
25*
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Min Max Min Max Min Max Min Max
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95
65
55
25
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20
20
15
10
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20
20
15
12
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2
2
2
2
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20
20
15
12
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2
2
2
2
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35
30
25
20
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35
35
30
20
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30
30
30
20
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Parameter
tMC
Clocked Multiply Time
tPW
Clock Pulse Width
tS
Input Register Setup Time
tH
Input Register Hold Time
tSP
Preload Setup Time
tHP
Preload Hold Time
tD
Output Delay
tENA
Three-State Output Enable Delay (Note 11)
tDIS
Three-State Output Disable Delay (Note 11)
SWITCHING WAVEFORMS
tS
A11-0
B11-0
tH
tPW
CLK A
CLK B
tPW
tMC
CLK R
tD
tPW
PREL
OE*
tSP
R26-0
tHP
tDIS
tENA
HIGH IMPEDANCE
PRELOAD
OUTPUT
*includes OEX, OEM, OEL
123456789012345678901234
123456789012345678901234
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*DISCONTINUED SPEED GRADE
Multiplier-Accumulators
4
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional operation of these products at values beyond
those indicated in the Operating Conditions table is not implied. Exposure to
maximum rating conditions for extended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
tDIS test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec- respectively. Alternatively, a diode
ification include internal circuitry de- bridge with upper and lower current
signed to protect the chip from damagsources of I OH and I OL respectively,
ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be
cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF
less, conventional precautions should minimum, and may be distributed.
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
transient undershoot and overshoot. In- measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
tion will not be adversely affected, how- should be installed between device VCC
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
4. Actual test conditions may vary from b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and VCC
noise to maintain required DUT input
NCV2 F
levels relative to the DUT ground pin.
where
4
10. Each parameter is shown as a min-
11. For the tENA test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the tDIS test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests.
12. These parameters are only tested at
the high temperature extreme, which is
the worst case for leakage current.
FIGURE A. OUTPUT LOADING CIRCUIT
S1
DUT
IOL
VTH
CL
IOH
FIGURE B. THRESHOLD LEVELS
tENA
OE
Z
tDIS
1.5 V
1.5 V
3.5V Vth
0
1.5 V
1.5 V
Z
1
VOL*
0.2 V
VOH*
0.2 V
0
Z
1
Z
0V Vth
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH* Measured VOH with IOH = –10mA and IOL = 10mA
imum or maximum value. Input requirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 5 MHz clock much time to meet the worst-case requirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
VCC or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
any device always provides data within
but not 100% tested.
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
Multiplier-Accumulators
5
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
LMA1009 — ORDERING INFORMATION
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64-pin
68-pin
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64
A4
1
A5
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63
2
A3
A6
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1
2
3
4
5
6
7
8
9
10
11
62
3
A2
A7
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61
4
A1
A8
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60
5
A0
A9
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A
59
6
ACC
A10
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NC RND ACC A1
A11
A3
A5
A7
A9
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58
7
SUB
A11
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B
57
8
RND
CLK A
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56
9
OEL
CLK B
R0 OEL SUB A0
A2
A4
A6
A8
A10 CLK A NC
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10
R0
B0
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C
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54
11
R1
B1
R2
B0 CLK B
R1
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53
12
R2
B2
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D
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52
13
R3
B3
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B1
R4
R3
B2
51
14
R4
B4
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E
50
15
R5
B5
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Top View
B3
GND R5
B4
49
16
GND
VCC
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Through Package
48
17
R6
B6
F
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47
18
R7
B7
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R6
VCC B5
R7
(i.e., Component Side Pinout)
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46
19
R8
B8
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G
45
20
R9
B9
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R9
R8
B7
B6
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44
21
R10
B10
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H
43
22
R11
B11
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B8
R11 R10
B9
42
23
CLK R
TC
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41
24
PREL
OEX
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J
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40
25
OEM
R26
PREL CLK R
B11 B10
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26
R12
R25
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K
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27
R13
R24
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NC OEM R13 R15 R17 R19 R21 R23 R25 OEX TC
37
28
R14
R23
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L
36
29
R15
R22
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R12 R14 R16 R18 R20 R22 R24 R26 NC
35
30
R16
R21
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31
R17
R20
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32
R18
R19
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Discontinued Package
Discontinued Package
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Speed
Sidebraze Hermetic DIP
(D6)
Ceramic Pin Grid Array
(G2)
0°C to +70°C — COMMERCIAL SCREENING
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Multiplier-Accumulators
6
03/29/2000–LDS.10/2009-L
LMA 1009/2009
DEVICES INCORPORATED
12 x 12-bit Multiplier-Accumulator
LMA2009 — ORDERING INFORMATION
TC
B11
B10
B9
B8
B7
B6
VCC
NC
VCC
B5
B4
B3
B2
B1
B0
CLK B
68-pin
10
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
11
59
12
58
13
57
14
56
15
55
16
17
18
19
54
Top
View
53
52
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CLK A
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ACC
SUB
RND
OEL
PREL
CLK R
R11
R10
R9
R8
R7
NC
R6
GND
GND
R5
R4
R3
R2
R1
R0
OEX
R26
R25
R24
R23
R22
R21
R20
R19
R18
R17
R16
R15
R14
R13
R12
OEM
Speed
Plastic J-Lead
Chip Carrier (J2)
0°C to +70°C — COMMERCIAL SCREENING
45 ns
20 ns
LMA2009JC45
LMA2009JC20
–55°C to +125°C — COMMERCIAL SCREENING
–55°C to +125°C — MIL-STD-883 COMPLIANT
Multiplier-Accumulators
7
03/29/2000–LDS.10/2009-L
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