CD4512BM/CD4512BC 8-Channel Buffered Data Selector General Description Features The CD4512BM/CD4512BC buffered 8-channel data selector is a complementary MOS (CMOS) circuit constructed with N- and P-channel enhancement mode transistors. This data selector is primarily used as a digital signal multiplexer selecting 1 of 8 inputs and routing the signal to a TRISTATEÉ output. A high level at the Inhibit input forces a low level at the output. A high level at the Output Enable (OE) input forces the output into the TRI-STATE condition. Low levels at both the Inhibit and (OE) inputs allow normal operation. Y Y Y Y Y Wide supply voltage range High noise immunity TRI-STATE output Low quiescent power dissipation 3.0V to 15V 0.45 VDD (typ.) 0.25 mW/package (typ.) @ VCC e 5.0V Plug-in replacement for Motorola MC14512 Connection Diagram and Truth Table Dual-In-Line Package Order Number CD4512B TL/F/5993 – 1 Top View Address Inputs Control Inputs Output C B A Inhibit OE Z 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 j j j j j j 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 X0 X1 X2 X3 X4 X5 X6 X7 0 Hi-Z j j e Don’t care Hi-Z e TRI-STATE condition Xn e Data at input n TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/5993 RRD-B30M105/Printed in U. S. A. CD4512BM/CD4512BC 8-Channel Buffered Data Selector February 1988 Absolute Maximum Ratings (Notes 1 & 2) Recommended Operating Conditions (Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VDD) b 0.5 to a 18 VDC Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature, (TL) (Soldering, 10 seconds) b 0.5 to VDD a 0.5 VDC b 65§ C to a 150§ C DC Supply Voltage (VDD) 3.0 to 15 VDC Input Voltage (VIN) Operating Temperature Range (TA) CD4512BM CD4512BC 0 to VDD VDC b 55§ C to a 125§ C b 40§ C to a 85§ C 700 mW 500 mW 260§ C DC Electrical Characteristics CD4512BM (Note 2) Symbol Parameter b 55§ C Conditions Min a 25§ C Max Min a 125§ C Typ Max Min Units Max IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS 5.0 10 20 0.005 0.010 0.015 5.0 10 20 150 300 600 mA mA mA VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V VOH High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage VDD e 5V, VO e 0.5V VDD e 10V, VO e 1.0V VDD e 15V, VO e 1.5V VIH High Level Input Voltage VDD e 5V, VO e 4.5V VDD e 10V, VO e 9.0V VDD e 15V, VO e 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.50 8.25 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.64 1.6 4.2 0.51 1.3 3.4 0.78 2.0 7.8 0.36 0.9 2.4 mA mA mA IOH High Level Output Current (Note 3) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5V VDD e 15V, VO e 13.5V b 0.25 b 0.62 b 1.8 b 0.2 b 0.5 b 1.5 b 0.14 b 0.35 b 1.1 mA mA mA IIN Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V IOZ TRI-STATE Output Current ( (l lIOLl k 1 mA IOHl k 1 mA 4.95 9.95 14.95 4.95 9.95 14.95 1.5 3.0 4.0 VDD e 15V, VO e 0V VDD e 15V, VO e 15V 5.0 10.0 15.0 2.25 4.50 6.75 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 V V V b 0.1 b 10 b 5 b 0.1 b 1.0 0.1 10b5 0.1 1.0 mA mA g 0.1 b 10 b 5 g 0.1 g 3.0 mA DC Electrical Characteristics CD4512BC (Note 2) Symbol Parameter b 40§ C Conditions Min IDD Quiescent Device Current VDD e 5V, VIN e VDD or VSS VDD e 10V, VIN e VDD or VSS VDD e 15V, VIN e VDD or VSS VOL Low Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VOH High Level Output Voltage VDD e 5V VDD e 10V VDD e 15V VIL Low Level Input Voltage VDD e 5V, VO e 0.5V VDD e 10V, VO e 1.0V VDD e 15V, VO e 1.5V ( (l lIOLl k 1 mA Max 20 40 80 0.005 0.010 0.015 20 40 80 150 300 600 mA mA mA 0.05 0.05 0.05 0 0 0 0.05 0.05 0.05 0.05 0.05 0.05 V V V 4.95 9.95 14.95 5.0 10.0 15.0 2.25 4.50 6.75 Min Units Max 1.5 3.0 4.0 2 a 85§ C Typ 4.95 9.95 14.95 IOHl k 1 mA a 25§ C Min Max 4.95 9.95 14.95 1.5 3.0 4.0 V V V 1.5 3.0 4.0 V V V DC Electrical Characteristics CD4512BC (Note 2) (Continued) Symbol Parameter b 40§ C Conditions Min a 25§ C Max Min Typ a 85§ C Max Min Units Max VIH High Level Input Voltage VDD e 5V, VO e 4.5V VDD e 10V, VO e 9.0V VDD e 15V, VO e 13.5V 3.5 7.0 11.0 3.5 7.0 11.0 2.75 5.50 8.25 3.5 7.0 11.0 V V V IOL Low Level Output Current (Note 3) VDD e 5V, VO e 0.4V VDD e 10V, VO e 0.5V VDD e 15V, VO e 1.5V 0.52 1.3 3.6 0.44 1.1 3.4 0.78 2.0 7.8 0.36 0.9 2.4 mA mA mA IOH High Level Output Current (Note 3) VDD e 5V, VO e 4.6V VDD e 10V, VO e 9.5 VDD e 15V, VO e 13.5V b 0.2 b 0.5 b 1.4 b 0.16 b 0.4 b 1.2 b 0.12 b 0.3 b 1.0 mA mA mA IIN Input Current VDD e 15V, VIN e 0V VDD e 15V, VIN e 15V IOZ TRI-STATE Output Current VDD e 15V, VO e 0V VDD e 15V, VO e 15V b 0.3 b 10 b 5 b 0.3 b 1.0 0.3 10b5 0.3 1.0 mA mA g 1.0 g 10 b 5 g 1.0 g 7.5 mA AC Electrical Characteristics* TA e 25§ C, tr e tf e 20 ns, CL e 50 pF Symbol Parameter CD4512BM Conditions Min CD4512BC Typ Max Min Units Typ Max tPHL Propagation Delay High-to-Low Level VDD e 5V VDD e 10V VDD e 15V 225 75 57 500 175 130 225 75 57 750 200 150 ns ns ns tPLH Propagation Delay Low-to-High Level VDD e 5V VDD e 10V VDD e 15V 225 75 57 500 175 130 225 75 57 750 200 150 ns ns ns tTHL, tTLH Transition Time VDD e 5V VDD e 10V VDD e 15V 70 35 25 200 100 80 70 35 25 200 100 80 ns ns ns tPHZ, tPLZ Propagation Delay into TRI-STATE from Logic Level VDD e 5V VDD e 10V VDD e 15V 50 25 19 125 75 60 50 25 19 125 75 60 ns ns ns tPZH, tPZL Propagation Delay to Logic Level from TRI-STATE VDD e 5V VDD e 10V VDD e 15V 50 25 19 125 75 60 50 25 19 125 75 60 ns ns ns CIN Input Capacitance (Note 4) 7.5 15 7.5 15 pF COUT TRI-STATE Output Capacitance (Note 4) 7.5 15 7.5 15 pF CPD Power Dissipation Capacity (Note 5) 150 150 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device operation. Note 2: VSS e 0V unless otherwise specified. Note 3: IOH and IOL are tested one output at a time. Note 4: Capacitance guaranteed by periodic testing. Note 5: CPD determines the no load AC power of any CMOS device. For complete explanation, see 54C/74C Family Characteristics Application Note, AN-90. 3 Logic Diagram TL/F/5993 – 2 Typical Application Serial Data Routing Interface TL/F/5993 – 3 4 AC Test Circuit and Switching Time Waveforms TL/F/5993 – 5 TL/F/5993 – 4 Input Connections for tr, tf, tPLH, tPHL Test Inhibit A X0 1 2 3 PG GND GND GND PG GND VDD VDD PG TRI-STATE AC Test Circuit and Switching Time Waveforms TL/F/5993 – 7 TL/F/5993 – 6 Switch Positions for TRI-STATE Test Test S1 S2 S3 S4 tPHZ Open Closed Closed Open tPLZ Closed Open Open Closed tPZL Closed Open Open Closed tPZH Open Closed Closed Open 5 CD4512BM/CD4512BC 8-Channel Buffered Data Selector Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4512BMJ or CD4512BCJ NS Package Number J16A Molded Dual-In-Line Package (N) Order Number CD4512BMN or CD4512BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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