CY29FCT520T MULTILEVEL PIPELINE REGISTER WITH 3-STATE OUTPUTS SCCS011C – MAY 1994 – REVISED NOVEMBER 2001 D D D D D D D D D D D D D, P, OR SO PACKAGE (TOP VIEW) Function, Pinout, and Drive Compatible With FCT, F Logic, and AM29520 Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise and Fall Times Fully Compatible With TTL Input and Output Logic Levels ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Single- and Dual-Pipeline Operation Modes Multiplexed Data Inputs and Outputs CY29FCT520T – 64-mA Output Sink Current 32-mA Output Source Current CY29FCT520ATDMB, CY29FCT520BTDMB – 32-mA Output Sink Current 12-mA Output Source Current 3-State Outputs I0 I1 D0 D1 D2 D3 D4 D5 D6 D7 CLK GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC S0 S1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 OE description The CY29FCT520T is a multilevel 8-bit-wide pipeline register. The device consists of four registers, A1, A2, B1, and B2, which are configured by the instruction inputs I0, I1 as a single four-level pipeline or as two two-level pipelines. The contents of any register can be read at the multiplexed output at any time by using the multiplex-selection controls (S0 and S1). The pipeline registers are positive-edge triggered, and data is shifted by the rising edge of the clock input. Instruction I = 0 selects the four-level pipeline mode. Instruction I = 1 selects the two-level B pipeline, while I = 2 selects the two-level A pipeline. I = 3 is the hold instruction; no shifting is performed by the clock in this mode. In the two-level operation mode, data is shifted from level 1 to level 2 and new data is loaded into level 1. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CY29FCT520T MULTILEVEL PIPELINE REGISTER WITH 3-STATE OUTPUTS SCCS011C – MAY 1994 – REVISED NOVEMBER 2001 PIPELINE INSTRUCTION TABLE I=1 I=0 I1 = 0 I0 = 0 A1 B1 A2 B2 I=2 I=3 I1 = 0 I0 = 1 I1 = 1 I0 = 0 A1 B1 A1 B1 A2 B2 A2 B2 Single four-level I1 = 1 I0 = 1 A1 B1 A2 B2 Dual two-level Hold ORDERING INFORMATION SOIC – SO –40°C to 85°C SOIC – SO DIP – P SOIC – SO 55°C to 125°C –55°C SPEED (ns) ORDERABLE PART NUMBER Tube 6.0 CY29FCT520CTSOC Tape and reel 6.0 CY29FCT520CTSOCT Tube 7.5 CY29FCT520BTSOC Tape and reel 7.5 CY29FCT520BTSOCT Tube 14.0 CY29FCT520ATPC Tube 14.0 CY29FCT520ATSOC Tape and reel 14.0 CY29FCT520ATSOCT Tube 8.0 5962-9220504MLA (CY29FCT520BTDMB) Tube 16.0 5962-9220502MLA (CY29FCT520ATDMB) PACKAGE† TA CDIP – D TOP-SIDE MARKING 29FCT520C 29FCT520B CY29FCT520ATPC 29FCT520A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS 2 OUTPUT S1 1 S0 1 1 0 A2 0 1 B1 0 0 B2 POST OFFICE BOX 655303 A1 • DALLAS, TEXAS 75265 CY29FCT520T MULTILEVEL PIPELINE REGISTER WITH 3-STATE OUTPUTS SCCS011C – MAY 1994 – REVISED NOVEMBER 2001 logic diagram D0–D7 8 Instruction Register Controls I0 I1 MUX MUX CLK Multiplex Selection S0 S1 Octal Register A1 Octal Register B1 Octal Register A2 Octal Register B2 MUX OE 8 Y0–Y7 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V DC output current (maximum sink current/pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 mA Package thermal impedance, θJA (see Note 1): P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W (see Note 2): SO package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W Ambient temperature range with power applied, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 135°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 CY29FCT520T MULTILEVEL PIPELINE REGISTER WITH 3-STATE OUTPUTS SCCS011C – MAY 1994 – REVISED NOVEMBER 2001 recommended operating conditions (see Note 3) CY29FCT520ATDMB CY29FCT520BTDMB CY29FCT520T UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.75 5 5.25 VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –32 mA IOL TA Low-level output current 32 64 mA 85 °C High-level input voltage 2 Operating free-air temperature 2 –55 125 V V –40 NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER CY29FCT520ATDMB CY29FCT520BTDMB TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.75 V, IIN = –18 mA IIN = –18 mA VCC = 4.5 V, IOH = –12 mA IOH = –15 mA VCC = 4 4.75 75 V TYP† MAX –0.7 –1.2 2.4 2.4 IOH = –32 mA IOL = 32 mA Vhys All inputs II VCC = 5.5 V, VCC = 5.25 V, VIN = VCC VIN = VCC 5 IIH VCC = 5.5 V, VCC = 5.25 V, VIN = 2.7 V VIN = 2.7 V ±1 IIL VCC = 5.5 V, VCC = 5.25 V, VIN = 0.5 V VIN = 0.5 V ±1 VCC = 0 V, VCC = 5.5 V, VOUT = 4.5 V VOUT = 0 V ±1 VCC = 5.25 V, VCC = 5.5 V, VOUT = 0 V VIN = 2.7 V VCC = 5.25 V, VCC = 5.5 V, VIN = 2.7 V VIN = 0.5 V VCC = 5.25 V, VCC = 5.5 V, VIN = 0.5 V VIN ≤ 0.2 V, IOZH IOZL ICC ∆ICC UNIT TYP† MAX –0.7 –1.2 V V 3.3 2 VOL IOS‡ MIN 3.3 VCC = 4.5 V, VCC = 4.75 V, Ioff CY29FCT520T 0.3 0.55 IOL = 64 mA 0.3 0.2 0.55 0.2 V 5 ±1 ±1 –60 –120 ±1 –225 –60 –120 –225 10 10 –10 –10 VIN ≥ VCC – 0.2 V VCC = 5.25 V, VIN ≤ 0.2 V, VIN ≥ VCC – 0.2 V VCC = 5.5 V, VIN = 3.4 V§, f1 = 0, Outputs open VCC = 5.25 V, VIN = 3.4 V§, f1 = 0, Outputs open 0.1 0.5 V 0.2 0.1 0.2 0.5 2 2 µA µA µA µA mA µA µA mA mA † Typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample-and-hold techniques are preferable to minimize internal chip heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output can raise the chip temperature well above normal and cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. § Per TTL-driven input (VIN = 3.4 V); all other inputs at VCC or GND 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CY29FCT520T MULTILEVEL PIPELINE REGISTER WITH 3-STATE OUTPUTS SCCS011C – MAY 1994 – REVISED NOVEMBER 2001 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER CY29FCT520ATDMB CY29FCT520BTDMB TEST CONDITIONS MIN ICCD¶ VCC = 5.5 V, Outputs open, One bit switching at 50% duty cycle, OE = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.25 V, Outputs open, One bit switching at 50% duty cycle, OE = GND, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V VCC = 5.5 V, Out uts o en, Outputs open f0 = 10 MHz, OE = GND IC# VCC = 5.25 V, Out uts o en, Outputs open f0 = 10 MHz, OE = GND One bit switching at f1 = 5 MHz at 50% duty cycle Eight bits switching at f1 = 5 MHz at 50% duty cycle One bit switching at f1 = 5 MHz at 50% duty cycle Eight bits switching at f1 = 5 MHz at 50% duty cycle TYP† MAX 0.06 0.12 CY29FCT520T MIN TYP† UNIT MAX mA/ MHz 0.06 0.12 VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.7 1.4 VIN = 3.4 V or GND 1.2 3.4 VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 2.8 5.6|| VIN = 3.4 V or GND 5.1 14.3|| VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 0.7 1.4 VIN = 3.4 V or GND 1.2 3.4 VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 2.8 5.6|| VIN = 3.4 V or GND 5.1 14.3|| Ci Co † Typical values are at VCC = 5 V, TA = 25°C. ¶ This parameter is derived for use in total power-supply calculations. # IC = ICC + ∆ICC × DH × NT + ICCD (f0/2 + f1 × N1) Where: IC = Total supply current ICC = Power-supply current with CMOS input levels ∆ICC = Power-supply current for a TTL high input (VIN = 3.4 V) DH = Duty cycle for TTL inputs high NT = Number of TTL inputs at DH ICCD = Dynamic current caused by an input transition pair (HLH or LHL) f0 = Clock frequency for registered devices, otherwise zero f1 = Input signal frequency N1 = Number of inputs changing at f1 All currents are in milliamperes and all frequencies are in megahertz. || Values for these conditions are examples of the ICC formula. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 mA 5 10 5 10 pF 9 12 9 12 pF 5 CY29FCT520T MULTILEVEL PIPELINE REGISTER WITH 3-STATE OUTPUTS SCCS011C – MAY 1994 – REVISED NOVEMBER 2001 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY29FCT520ATDMB MIN tw Pulse duration, CLK high or low tsu S t time, Setup ti before b f CLK↑ th Hold time, time after CLK↑ CY29FCT520BTDMB MAX MIN 8 6 Data 6 2.8 I 6 4.5 Data 2 2 I 2 2 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) CY29FCT520AT MIN tw Pulse duration, CLK high or low tsu S t time, Setup ti before b f CLK↑ th Hold time, time after CLK↑ MAX CY29FCT520BT MIN MAX CY29FCT520CT MIN 7 5.5 5.5 Data 5 2.5 2.5 I 5 4 4 Data 2 2 2 I 2 2 2 MAX UNIT ns ns ns switching characteristics over operating free-air temperature range (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL CLK Y tPLH tPHL S0 or S1 Y tPHZ tPLZ OE Y tPZH tPZL OE Y CY29FCT520ATDMB CY29FCT520BTDMB MIN MAX MIN MAX 2 16 2 8 2 16 2 8 2 15 2 8 2 15 2 8 1.5 13 1.5 7.5 1.5 13 1.5 7.5 1.5 16 1.5 8 1.5 16 1.5 8 UNIT ns ns ns ns switching characteristics over operating free-air temperature range (see Figure 1) 6 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL CLK Y tPLH tPHL S0 or S1 Y tPHZ tPLZ OE Y tPZH tPZL OE Y POST OFFICE BOX 655303 CY29FCT520AT CY29FCT520BT CY29FCT520CT MIN MAX MIN MAX MIN MAX 2 14 2 7.5 2 6 2 14 2 7.5 2 6 2 13 2 7.5 2 6 2 13 2 7.5 2 6 1.5 12 1.5 7 1.5 6 1.5 12 1.5 7 1.5 6 1.5 15 1.5 7.5 1.5 6 1.5 15 1.5 7.5 1.5 6 • DALLAS, TEXAS 75265 UNIT ns ns ns ns CY29FCT520T MULTILEVEL PIPELINE REGISTER WITH 3-STATE OUTPUTS SCCS011C – MAY 1994 – REVISED NOVEMBER 2001 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test From Output Under Test Test Point CL = 50 pF (see Note A) Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 500 Ω S1 Open 7V Open tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3V 1.5 V Timing Input 0V tw tsu 3V 1.5 V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V tPLH tPHL 1.5 V 1.5 V VOL tPHL Out-of-Phase Output tPLZ ≈3.5 V 1.5 V tPZH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V Output Waveform 1 (see Note B) tPLH 1.5 V 1.5 V tPZL VOH In-Phase Output 3V Output Control Output Waveform 2 (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 21-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9220502MLA ACTIVE CDIP JT 24 1 TBD Call TI Level-NC-NC-NC 5962-9220504MLA ACTIVE CDIP JT 24 1 TBD Call TI Level-NC-NC-NC CY29FCT520ATPC ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CY29FCT520ATPCE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CY29FCT520ATSOC ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520ATSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520ATSOCT ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520ATSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520BTSOC ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520BTSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520BTSOCT ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520BTSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520CTSOC ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520CTSOCE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520CTSOCT ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CY29FCT520CTSOCTE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 21-Nov-2005 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCER004A – JANUARY 1995 – REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0°–15° 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI004 – OCTOBER 1994 NT (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PINS SHOWN PINS ** A 24 28 A MAX 1.260 (32,04) 1.425 (36,20) A MIN 1.230 (31,24) 1.385 (35,18) B MAX 0.310 (7,87) 0.315 (8,00) B MIN 0.290 (7,37) 0.295 (7,49) DIM 24 13 0.280 (7,11) 0.250 (6,35) 1 12 0.070 (1,78) MAX B 0.020 (0,51) MIN 0.200 (5,08) MAX Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0°– 15° 0.010 (0,25) M 0.010 (0,25) NOM 4040050 / B 04/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. 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