LINER LTC2252 12-bit, 125/105msps low power 3v adc Datasheet

LTC2253/LTC2252
12-Bit, 125/105Msps
Low Power 3V ADCs
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FEATURES
DESCRIPTIO
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The LTC®2253/LTC2252 are 12-bit 125Msps/105Msps,
low power 3V A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2253/
LTC2252 are perfect for demanding imaging and communications applications with AC performance that includes
70.1dB SNR and 85dB SFDR for signals at the Nyquist
frequency.
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Sample Rate: 125Msps/105Msps
Single 3V Supply (2.85V to 3.4V)
Low Power: 395mW/320mW
70.2dB SNR
88dB SFDR
No Missing Codes
Flexible Input: 1VP-P to 2VP-P Range
640MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
125Msps: LTC2253 (12-Bit), LTC2255 (14-Bit)
105Msps: LTC2252 (12-Bit), LTC2254 (14-Bit)
80Msps: LTC2229 (12-Bit), LTC2249 (14-Bit)
65Msps: LTC2228 (12-Bit), LTC2248 (14-Bit)
40Msps: LTC2227 (12-Bit), LTC2247 (14-Bit)
25Msps: LTC2226 (12-Bit), LTC2246 (14-Bit)
10Msps: LTC2225 (12-Bit), LTC2245 (14-Bit)
32-Pin (5mm × 5mm) QFN Package
DC specs include ±0.3LSB INL (typ), ±0.15LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.32LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.3V
logic.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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APPLICATIO S
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Wireless and Wired Broadband Communication
Imaging Systems
Ultrasound
Spectral Analysis
Portable Instrumentation
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TYPICAL APPLICATIO
REFH
REFL
LTC2253: SNR vs Input Frequency,
–1dB, 2V Range, 125Msps
73
FLEXIBLE
REFERENCE
72
OVDD
ANALOG
INPUT
INPUT
S/H
–
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
D11
•
•
•
D0
OUTPUT
DRIVERS
OGND
CLOCK/DUTY
CYCLE
CONTROL
SNR (dBFS)
71
+
70
69
68
67
66
65
0
22532 TA01
50
100 150 200 250 300 350
22532 G09
INPUT FREQUENCY (MHz)
CLK
22532fa
1
LTC2253/LTC2252
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
D9
D10
SENSE
VCM
TOP VIEW
VDD
Supply Voltage (VDD) ................................................. 4V
Digital Output Ground Voltage (OGND) ....... –0.3V to 1V
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V)
Digital Output Voltage ................ –0.3V to (OVDD + 0.3V)
Power Dissipation ............................................ 1500mW
Operating Temperature Range
LTC2253C, LTC2252C ............................. 0°C to 70°C
LTC2253I, LTC2252I ...........................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
D11
W
OVDD = VDD (Notes 1, 2)
OF
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AXI U RATI GS
MODE
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ABSOLUTE
32 31 30 29 28 27 26 25
AIN+ 1
24 D8
AIN– 2
23 D7
REFH 3
22 D6
REFH 4
21 OVDD
33
REFL 5
LTC2253CUH
LTC2253IUH
LTC2252CUH
LTC2252IUH
20 OGND
REFL 6
19 D5
VDD 7
18 D4
GND 8
17 D3
QFN PART*
MARKING
D2
D1
D0
NC
NC
OE
CLK
SHDN
9 10 11 12 13 14 15 16
2253
2252
UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W
EXPOSED PAD (PIN 33) IS GND
MUST BE SOLDERED TO PCB
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
●
12
LTC2253
TYP
MAX
MIN
LTC2252
TYP
MAX
12
UNITS
Bits
Integral Linearity Error
Differential Analog Input
(Note 5)
●
–1.5
±0.3
1.5
–1.5
±0.3
1.5
LSB
Differential Linearity Error
Differential Analog Input
●
–0.7
±0.15
0.7
–0.7
±0.15
0.7
LSB
Offset Error
(Note 6)
●
–12
±2
12
–12
±2
12
mV
Gain Error
External Reference
●
–2.5
±0.5
2.5
–2.5
±0.5
2.5
%FS
Offset Drift
±10
±10
µV/°C
Full-Scale Drift
Internal Reference
External Reference
±30
±5
±30
±5
ppm/°C
ppm/°C
Transition Noise
SENSE = 1V
0.32
0.32
LSBRMS
22532fa
2
LTC2253/LTC2252
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A ALOG I PUT
The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
+–
–)
MIN
TYP
MAX
UNITS
±0.5V to ±1V
VIN
Analog Input Range (AIN
2.85V < VDD < 3.4V (Note 7)
●
VIN,CM
Analog Input Common Mode
Differential Input (Note 7)
●
1
IIN
Analog Input Leakage Current
0V < AIN+, AIN– < VDD
●
ISENSE
SENSE Input Leakage
0V < SENSE < 1V
IMODE
MODE Pin Leakage
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
0.2
psRMS
CMRR
Analog Input Common Mode Rejection Ratio
80
dB
640
MHz
AIN
Full Power Bandwidth
1.5
V
1.9
V
–1
1
µA
●
–3
3
µA
●
–3
3
µA
0
Figure 8 Test Circuit
ns
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input
MIN
dB
69.6
69.8
dB
5MHz Input
88
88
dB
30MHz Input
85
88
dB
84
dB
68
●
72
IMD
82
68.5
71
78
79
dB
5MHz Input
90
90
dB
30MHz Input
90
90
dB
●
77
5MHz Input
30MHz Input
70MHz Input
Intermodulation Distortion
70
140MHz Input
140MHz Input
Signal-to-Noise Plus
Distortion Ratio
dB
dB
70MHz Input
S/(N+D)
UNITS
70.2
70MHz Input
Spurious Free Dynamic Range
4th Harmonic or Higher
70.2
70.1
●
140MHz Input
SFDR
LTC2252
TYP
MAX
70.1
70MHz Input
SFDR
MIN
70.2
30MHz Input
Spurious Free Dynamic Range
2nd or 3rd Harmonic
LTC2253
TYP
MAX
90
90
dB
90
78
90
dB
69.8
70.1
dB
69.7
●
67
69.6
67.5
70.1
dB
70
dB
140MHz Input
68.5
68.7
dB
fIN1 = 28.2MHz,
fIN2 = 26.8MHz
85
85
dB
22532fa
3
LTC2253/LTC2252
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I TER AL REFERE CE CHARACTERISTICS
(Note 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
1.475
1.500
1.525
V
±25
VCM Output Tempco
ppm/°C
VCM Line Regulation
2.85V < VDD < 3.4V
3
mV/V
VCM Output Resistance
–1mA < IOUT < 1mA
4
Ω
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
LOGIC INPUTS (CLK, OE, SHDN)
VIH
High Level Input Voltage
VDD = 3V
●
VIL
Low Level Input Voltage
VDD = 3V
●
IIN
Input Current
VIN = 0V to VDD
●
CIN
Input Capacitance
(Note 7)
3
pF
COZ
Hi-Z Output Capacitance
OE = High (Note 7)
3
pF
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = 3V
50
mA
VOH
High Level Output Voltage
IO = –10µA
IO = –200µA
●
IO = 10µA
IO = 1.6mA
●
2
V
–10
0.8
V
10
µA
LOGIC OUTPUTS
OVDD = 3V
VOL
Low Level Output Voltage
2.7
2.995
2.99
0.005
0.09
V
V
0.4
V
V
OVDD = 2.5V
VOH
High Level Output Voltage
IO = –200µA
2.49
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
OVDD = 1.8V
VOH
High Level Output Voltage
IO = –200µA
1.79
V
VOL
Low Level Output Voltage
IO = 1.6mA
0.09
V
22532fa
4
LTC2253/LTC2252
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 8)
MIN
LTC2253
TYP
MAX
MIN
LTC2252
TYP
MAX
SYMBOL
PARAMETER
CONDITIONS
UNITS
VDD
Analog Supply
Voltage
(Note 9)
●
2.85
3
3.4
2.85
3
3.4
V
OVDD
Output Supply Voltage
(Note 9)
●
0.5
3
3.6
0.5
3
3.6
V
IVDD
Supply Current
●
132
156
107
126
mA
PDISS
Power Dissipation
●
395
468
320
378
mW
PSHDN
Shutdown Power
SHDN = H,
OE = H, No CLK
2
2
mW
PNAP
Nap Mode Power
SHDN = H,
OE = L, No CLK
15
15
mW
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
MIN
LTC2253
TYP
MAX
MIN
LTC2252
TYP
MAX
UNITS
105
MHz
500
500
ns
ns
500
500
ns
ns
SYMBOL
PARAMETER
CONDITIONS
fs
Sampling Frequency
(Note 9)
●
1
125
1
tL
CLK Low Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
3.8
3
4
4
500
500
4.5
3
4.76
4.76
tH
CLK High Time
Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
(Note 7)
●
●
3.8
3
4
4
500
500
4.5
3
4.76
4.76
tAP
Sample-and-Hold
Aperture Delay
tD
CLK to DATA Delay
CL = 5pF (Note 7)
●
Data Access Time
After OE↓
CL = 5pF (Note 7)
BUS Relinquish Time
(Note 7)
0
Pipeline
Latency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252),
input range = 2VP-P with differential drive, clock duty cycle stabilizer on,
unless otherwise noted.
1.4
0
2.7
5.4
●
4.3
●
3.3
5
1.4
ns
2.7
5.4
ns
10
4.3
10
ns
8.5
3.3
8.5
ns
5
Cycles
Note 5: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 3V, fSAMPLE = 125MHz (LTC2253) or 105MHz (LTC2252),
input range = 1VP-P with differential drive.
Note 9: Recommend operating conditions.
22532fa
5
LTC2253/LTC2252
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TYPICAL PERFOR A CE CHARACTERISTICS
1.0
1.0
0
0.8
0.8
–10
0.6
0.6
0.4
0.4
0
–0.2
–0.4
–30
0.2
0
–0.2
–0.4
–40
–50
–60
–70
–80
–90
–0.6
–0.8
–0.8
–1.0
–1.0
0
1024
2048
CODE
3072
4096
–100
–110
0
1024
22532 G01
2048
CODE
3072
–120
4096
0
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
0
–50
–40
–50
–60
–70
–80
–70
–80
–90
–100
–100
–110
–110
–110
–120
–120
50
60
0
10
22532 G04
LTC2253: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz, –1dB,
2V Range, 125Msps
20
30
40
FREQUENCY (MHz)
60
50
–30
–60
–70
40000
30000
20000
–90
0
10
20
30
40
FREQUENCY (MHz)
50
60
22532 G07
0
70
69
68
67
10000
–110
60
22532 G06
71
–80
–100
50
72
SNR (dBFS)
COUNT
–50
20
30
40
FREQUENCY (MHz)
73
50000
–40
10
LTC2253: SNR vs Input Frequency,
–1dB, 2V Range, 125Msps
58717
60000
–20
0
22532 G05
70000
–10
–120
–120
LTC2253: Grounded Input
Histogram, 125Msps
0
22532 G03
–60
–100
20
30
40
FREQUENCY (MHz)
60
50
–50
–90
10
20
30
40
FREQUENCY (MHz)
–40
–90
0
10
LTC2253: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
125Msps
–10
–40
0
22532 G02
LTC2253: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
125Msps
LTC2253: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
125Msps
AMPLITUDE (dB)
–20
AMPLITUDE (dB)
0.2
–0.6
AMPLITUDE (dB)
LTC2253: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
125Msps
LTC2253: Typical DNL, 2V Range,
125Msps
DNL ERROR (LSB)
INL ERROR (LSB)
LTC2253: Typical INL, 2V Range,
125Msps
4249
2562
0
2044
2045
2046
CODE
2047
66
0
2048
22532 G08
65
0
50
100 150 200 250 300 350
22532 G09
INPUT FREQUENCY (MHz)
22532fa
6
LTC2253/LTC2252
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TYPICAL PERFOR A CE CHARACTERISTICS
LTC2253: SFDR vs Input Frequency,
–1dB, 2V Range, 125Msps
LTC2253: SNR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
LTC2253: SNR and SFDR vs Sample
Rate, 2V Range, fIN = 5MHz, –1dB
95
90
80
SFDR
70
80
75
80
SNR (dBc AND dBFS)
SNR AND SFDR (dBFS)
85
SNR
70
60
dBFS
60
50
dBc
40
30
20
70
10
65
50
100 150 200 250 300
INPUT FREQUENCY (MHz)
350
0
20
40 60 80 100 120 140 160
SAMPLE RATE (Msps)
22532 G10
0
–60
LTC2253: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
–20
–40
–30
INPUT LEVEL (dBFS)
–10
0
22532 G13
LTC2253: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
145
110
100
140
dBFS
90
135
80
130
70
IVDD (mA)
dBc
60
50
40
2V RANGE
125
1V RANGE
120
115
110
30
20
105
10
100
0
–60
95
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
0
0
20
60
80 100
40
SAMPLE RATE (Msps)
LTC2253: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
72
7
71
6
70
5
69
4
3
68
67
2
66
1
65
20
60
80 100
40
SAMPLE RATE (Msps)
120
140
LTC2253: SNR vs SENSE,
fIN = 5MHz, –1dB
8
0
120
22532 G15
22532 G14
0
–50
22532 G11
SNR (dBFS)
50
SFDR (dBc AND dBFS)
0
IOVDD (mA)
SFDR (dBFS)
90
140
22532 G16
64
0.4
0.5
0.6
0.7 0.8 0.9
SENSE PIN (V)
1.0
1.1
22532 G32
22532fa
7
LTC2253/LTC2252
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TYPICAL PERFOR A CE CHARACTERISTICS
1.0
1.0
0
0.8
0.8
–10
0.6
0.6
–20
0.4
0.4
0
–0.2
–0.4
0.2
0
–0.2
–0.4
–0.6
–0.6
–0.8
–0.8
–1.0
–1.0
1024
2048
CODE
3072
–30
AMPLITUDE (dB)
0.2
0
–50
–60
–70
–80
–90
–110
1024
22532 G17
2048
CODE
3072
–120
4096
0
–10
–20
–20
–20
–30
–30
–30
–60
–70
–80
AMPLITUDE (dB)
0
–10
AMPLITUDE (dB)
0
–50
–40
–50
–60
–70
–80
–60
–70
–80
–90
–100
–100
–100
–110
–110
–110
–120
–120
30
40
20
FREQUENCY (MHz)
50
0
10
22532 G20
30
40
20
FREQUENCY (MHz)
–120
50
30
40
20
FREQUENCY (MHz)
50
22532 G22
73
56911
72
50000
71
–30
COUNT
–50
–60
–70
SNR (dBFS)
40000
–40
30000
20000
–80
70
69
68
67
–90
10000
–100
–110
–120
10
LTC2252: SNR vs Input Frequency,
–1dB, 2V Range, 105Msps
60000
–10
–20
0
22532 G21
LTC2252: Grounded Input
Histogram, 105Msps
0
50
22532 G19
–50
–90
10
30
40
20
FREQUENCY (MHz)
–40
–90
0
10
LTC2252: 8192 Point FFT,
fIN = 140MHz, –1dB, 2V Range,
105Msps
–10
–40
0
22532 G18
LTC2252: 8192 Point FFT,
fIN = 70MHz, –1dB, 2V Range,
105Msps
LTC2252: 8192 Point 2-Tone FFT,
fIN = 28.2MHz and 26.8MHz, –1dB,
2V Range, 105Msps
AMPLITUDE (dB)
–40
–100
0
4096
LTC2252: 8192 Point FFT,
fIN = 30MHz, –1dB, 2V Range,
105Msps
AMPLITUDE (dB)
LTC2252: 8192 Point FFT,
fIN = 5MHz, –1dB, 2V Range,
105Msps
LTC2252: Typical DNL, 2V Range,
105Msps
DNL ERROR (LSB)
INL ERROR (LSB)
LTC2252: Typical INL, 2V Range,
105Msps
0
0
10
30
40
20
FREQUENCY (MHz)
50
22532 G23
66
0
2044
6704
1913
2045
2046
CODE
2047
0
2048
22532 G24
65
0
50
100 150 200 250 300 350
22532 G25
INPUT FREQUENCY (MHz)
22532fa
8
LTC2253/LTC2252
U W
TYPICAL PERFOR A CE CHARACTERISTICS
LTC2252: SNR and SFDR vs
Sample Rate, 2V Range,
fIN = 5MHz, –1dB
LTC2252: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
95
LTC2252: SNR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
80
90
SFDR
70
80
75
80
SNR (dBc AND dBFS)
SNR AND SFDR (dBFS)
85
SNR
70
60
dBFS
60
50
dBc
40
30
20
70
10
50
65
100 150 200 250 300
INPUT FREQUENCY (MHz)
0
350
20
40
60
80 100
SAMPLE RATE (Msps)
120
0
–60
140
–20
–40
–30
INPUT LEVEL (dBFS)
–50
LTC2252: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
–10
0
22532 G28
22532 G27
22532 G26
LTC2252: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
110
120
100
115
dBFS
90
110
80
105
70
IVDD (mA)
dBc
60
50
40
2V RANGE
100
95
1V RANGE
90
30
85
20
80
10
0
–60
75
–50
–40
–30
–20
INPUT LEVEL (dBFS)
–10
0
0
20
80
40
60
SAMPLE RATE (Msps)
22532 G29
100
120
22532 G30
LTC2252: IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB,
OVDD = 1.8V
LTC2252: SNR vs SENSE,
fIN = 5MHz, –1dB
7
72
6
71
70
5
SNR (dBFS)
50
SFDR (dBc AND dBFS)
0
IOVDD (mA)
SFDR (dBFS)
90
4
3
69
68
67
2
66
1
65
0
0
20
80
120
60
100
40
22532 G31
SAMPLE RATE (Msps)
64
0.4
0.5
0.6
0.7 0.8 0.9
SENSE PIN (V)
1.0
1.1
22532 G33
22532fa
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LTC2253/LTC2252
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PI FU CTIO S
AIN+ (Pin 1): Positive Differential Analog Input.
NC (Pins 12, 13): Do Not Connect These Pins.
AIN- (Pin 2): Negative Differential Analog Input.
D0 – D11 (Pins 14, 15, 16, 17, 18, 19, 22, 23, 24, 25, 26,
27): Digital Outputs. D11 is the MSB.
REFH (Pins 3, 4): ADC High Reference. Short together and
bypass to pins 5, 6 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 5, 6 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
REFL (Pins 5, 6): ADC Low Reference. Short together and
bypass to pins 3, 4 with a 0.1µF ceramic chip capacitor as
close to the pin as possible. Also bypass to pins 3, 4 with
an additional 2.2µF ceramic chip capacitor and to ground
with a 1µF ceramic chip capacitor.
VDD (Pins 7, 32): 3V Supply. Bypass to GND with 0.1µF
ceramic chip capacitors.
GND (Pin 8): ADC Power Ground.
CLK (Pin 9): Clock Input. The input sample starts on the
positive edge.
SHDN (Pin 10): Shutdown Mode Selection Pin. Connecting SHDN to GND and OE to GND results in normal
operation with the outputs enabled. Connecting SHDN to
GND and OE to VDD results in normal operation with the
outputs at high impedance. Connecting SHDN to VDD and
OE to GND results in nap mode with the outputs at high
impedance. Connecting SHDN to VDD and OE to VDD
results in sleep mode with the outputs at high impedance.
OE (Pin 11): Output Enable Pin. Refer to SHDN pin
function.
OGND (Pin 20): Output Driver Ground.
OVDD (Pin 21): Positive Supply for the Output Drivers.
Bypass to ground with 0.1µF ceramic chip capacitor. OVDD
can be set to 0.5V to 3.6V.
OF (Pin 28): Over/Under Flow Output. High when an over
or under flow has occurred.
MODE (Pin 29): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to GND selects
offset binary output format and turns the clock duty cycle
stabilizer off. 1/3 VDD selects offset binary output format
and turns the clock duty cycle stabilizer on. 2/3 VDD selects
2’s complement output format and turns the clock duty
cycle stabilizer on. VDD selects 2’s complement output
format and turns the clock duty cycle stabilizer off.
SENSE (Pin 30): Reference Programming Pin. Connecting
SENSE to VCM selects the internal reference and a ±0.5V
input range. VDD selects the internal reference and a ±1V
input range. An external reference greater than 0.5V and
less than 1V applied to SENSE selects an input range of
±VSENSE. ±1V is the largest valid input range.
VCM (Pin 31): 1.5V Output and Input Common Mode Bias.
Bypass to ground with 2.2µF ceramic chip capacitor.
GND (Exposed Pad) (Pin 33): ADC Power Ground. The
exposed pad on the bottom of the package must be
soldered to ground.
22532fa
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LTC2253/LTC2252
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FUNCTIONAL BLOCK DIAGRA
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AIN+
AIN–
VCM
INPUT
S/H
FIRST PIPELINED
ADC STAGE
SECOND PIPELINED
ADC STAGE
THIRD PIPELINED
ADC STAGE
FOURTH PIPELINED
ADC STAGE
FIFTH PIPELINED
ADC STAGE
SIXTH PIPELINED
ADC STAGE
1.5V
REFERENCE
SHIFT REGISTER
AND CORRECTION
2.2µF
RANGE
SELECT
REFH
SENSE
REFL
INTERNAL CLOCK SIGNALS
OVDD
REF
BUF
OF
D11
CLOCK/DUTY
CYCLE
CONTROL
DIFF
REF
AMP
CONTROL
LOGIC
OUTPUT
DRIVERS
•
•
•
D0
REFH
0.1µF
22532 F01
REFL
OGND
M0DE
CLK
SHDN
OE
2.2µF
1µF
1µF
Figure 1. Functional Block Diagram
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TI I G DIAGRA
Timing Diagram
tAP
ANALOG
INPUT
N+4
N+2
N
N+3
tH
N+5
N+1
tL
CLK
tD
D0-D11, OF
N–5
N–4
N–3
N–2
N–1
N
22532 TD01
22532fa
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DYNAMIC PERFORMANCE
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S/(N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Input Bandwidth
Total Harmonic Distortion
Aperture Delay Time
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
The time from when CLK reaches mid-supply to the instant
that the input signal is held by the sample and hold circuit.
2
2
2
2
THD = 20Log (√(V2 + V3 + V4 + . . . Vn )/V1)
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3,
etc. The 3rd order intermodulation products are 2fa + fb,
2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = –20log (2π • fIN • tJITTER)
CONVERTER OPERATION
As shown in Figure 1, the LTC2253/LTC2252 is a CMOS
pipelined multistep converter. The converter has six
pipelined ADC stages; a sampled analog input will result in
a digitized value five cycles later (see the Timing Diagram
section). For optimal AC performance the analog inputs
should be driven differentially. For cost sensitive applications, the analog inputs can be driven single-ended with
slightly worse harmonic distortion. The CLK input is
single-ended. The LTC2253/LTC2252 has two phases of
operation, determined by the state of the CLK input pin.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
22532fa
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LTC2253/LTC2252
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the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and vice versa.
When CLK is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that CLK transitions from low to high, the sampled input is
held. While CLK is high, the held input voltage is buffered
by the S/H amplifier which drives the first pipelined ADC
stage. The first stage acquires the output of the S/H during
this high phase of CLK. When CLK goes back low, the first
stage produces its residue which is acquired by the
second stage. At the same time, the input S/H goes back
to acquiring the analog input. When CLK goes back high,
the second stage produces its residue which is acquired
by the third stage. An identical process is repeated for the
third, fourth and fifth stages, resulting in a fifth stage
residue that is sent to the sixth stage ADC for final
evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally synchronized such
that the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
voltage is held on the sampling capacitors. During the hold
phase when CLK is high, the sampling capacitors are
disconnected from the input and the held voltage is passed
to the ADC core for processing. As CLK transitions from
high to low, the inputs are reconnected to the sampling
capacitors to acquire a new sample. Since the sampling
capacitors still hold the previous sample, a charging glitch
proportional to the change in voltage between samples will
be seen at this time. If the change between the last sample
and the new sample is small, the charging glitch seen at
the input will be small. If the input change is large, such as
the change seen with input frequencies near Nyquist, then
a larger charging glitch will be seen.
Single-Ended Input
For cost sensitive applications, the analog inputs can be
driven single-ended. With a single-ended input the harmonic distortion and INL will degrade, but the SNR and
DNL will remain unchanged. For a single-ended input, AIN+
should be driven with the input signal and AIN– should be
connected to 1.5V or VCM.
Common Mode Bias
For optimal performance the analog inputs should be
driven differentially. Each input should swing ±0.5V for
the 2V range or ±0.25V for the 1V range, around a
common mode voltage of 1.5V. The VCM output pin (Pin
31) may be used to provide the common mode bias level.
VCM can be tied directly to the center tap of a transformer
LTC2253/LTC2252
VDD
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2253/
LTC2252 CMOS differential sample-and-hold. The analog
inputs are connected to the sampling capacitors (CSAMPLE)
through NMOS transistors. The capacitors shown attached to each input (CPARASITIC) are the summation of all
other capacitance associated with each input.
During the sample phase when CLK is low, the transistors
connect the analog inputs to the sampling capacitors and
they charge to and track the differential input voltage.
When CLK transitions from low to high, the sampled input
CSAMPLE
3.5pF
15Ω
AIN+
CPARASITIC
1pF
VDD
AIN–
CSAMPLE
3.5pF
15Ω
CPARASITIC
1pF
VDD
CLK
22532 F02
Figure 2. Equivalent Input Circuit
22532fa
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LTC2253/LTC2252
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to set the DC input level or as a reference level to an op amp
differential driver circuit. The VCM pin must be bypassed to
ground close to the ADC with a 2.2µF or greater capacitor.
frequency input response; however, the limited gain bandwidth of most op amps will limit the SFDR at high input
frequencies.
Input Drive Impedance
Figure 5 shows a single-ended input circuit. The impedance seen by the analog inputs should be matched. This
circuit is not recommended if low distortion is required.
As with all high performance, high speed ADCs, the
dynamic performance of the LTC2253/LTC2252 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and input
reactance can influence SFDR. At the falling edge of CLK,
the sample-and-hold circuit will connect the 3.5pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when CLK rises, holding
the sampled input on the sampling capacitor. Ideally the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2FENCODE); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
The 25Ω resistors and 12pF capacitor on the analog inputs
serve two purposes: isolating the drive circuitry from the
VCM
2.2µF
0.1µF
ANALOG
INPUT
Figure 3 shows the LTC2253/LTC2252 being driven by an
RF transformer with a center tapped secondary. The
secondary center tap is DC biased with VCM, setting the
ADC input signal at its optimum DC level. Terminating on
the transformer secondary is desirable, as this provides a
common mode path for charging glitches caused by the
sample and hold. Figure 3 shows a 1:1 turns ratio transformer. Other turns ratios can be used if the source
impedance seen by the ADC does not exceed 100Ω for
each ADC input. A disadvantage of using a transformer is
the loss of low frequency response. Most small RF
transformers have poor performance at frequencies
below 1MHz.
Figure 4 demonstrates the use of a differential amplifier to
convert a single ended input signal into a differential input
signal. The advantage of this method is that it provides low
AIN+
25Ω
25Ω
0.1µF
LTC2253/
LTC2252
12pF
25Ω
AIN–
T1 = MA/COM ETC1-1T 25Ω
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
22532 F03
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
For the best performance, it is recommended to have a
source impedance of 100Ω or less for each input. The
source impedance should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
Input Drive Circuits
T1
1:1
VCM
HIGH SPEED
DIFFERENTIAL
25Ω
AMPLIFIER
ANALOG
INPUT
+
AIN+
+
CM
–
2.2µF
LTC2253/
LTC2252
12pF
–
25Ω
AIN–
22532 F04
Figure 4. Differential Drive with an Amplifier
VCM
1k
0.1µF
ANALOG
INPUT
1k
2.2µF
25Ω
AIN+
LTC2253/
LTC2252
12pF
25Ω
AIN–
0.1µF
22532 F05
Figure 5. Single-Ended Drive
22532fa
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LTC2253/LTC2252
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sample-and-hold charging glitches and limiting the
wideband noise at the converter input.
For input frequencies above 70MHz, the input circuits of
Figure 6, 7 and 8 are recommended. The balun transformer gives better high frequency response than a flux
coupled center tapped transformer. The coupling capacitors allow the analog inputs to be DC biased at 1.5V. In
Figure 8, the series inductors are impedance matching
elements that maximize the ADC bandwidth.
The 1.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry. An external bypass capacitor is required for
the 1.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry.
Reference Operation
VCM
Figure 9 shows the LTC2253/LTC2252 reference circuitry
consisting of a 1.5V bandgap reference, a difference
amplifier and switching and control circuit. The internal
voltage reference can be configured for two pin selectable
input ranges of 2V (±1V differential) or 1V (±0.5V differential). Tying the SENSE pin to VDD selects the 2V range;
tying the SENSE pin to VCM selects the 1V range.
VCM
0.1µF
12Ω
25Ω
0.1µF
25Ω
25Ω
LTC2253/
LTC2252
VCM
4Ω
1.5V BANDGAP
REFERENCE
2.2µF
1V
0.5V
22532 F06
TIE TO VDD FOR 2V RANGE;
TIE TO VCM FOR 1V RANGE;
RANGE = 2 • VSENSE FOR
0.5V < VSENSE < 1V
VCM
AIN+
0.1µF
RANGE
DETECT
AND
CONTROL
SENSE
BUFFER
INTERNAL ADC
HIGH REFERENCE
1µF
REFH
2.2µF
25Ω
22532 F08
LTC2253/LTC2252
AIN–
Figure 6. Recommended Front End Circuit for
Input Frequencies Between 70MHz and 170MHz
ANALOG
INPUT
8.2nH
–
12Ω
0.1µF
LTC2253/
LTC2252
AIN
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS, INDUCTORS
ARE 0402 PACKAGE SIZE
1.5V
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
0.1µF
T1
0.1µF
8pF
25Ω
AIN+
AIN+
0.1µF
T1
8.2nH
ANALOG
INPUT
Figure 8. Recommended Front End Circuit for
Input Frequencies Above 300MHz
2.2µF
ANALOG
INPUT
2.2µF
0.1µF
LTC2253/
LTC2252
2.2µF
0.1µF
DIFF AMP
T1
0.1µF
1µF
25Ω
T1 = MA/COM, ETC 1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
REFL
AIN–
22532 F07
INTERNAL ADC
LOW REFERENCE
22532 F09
Figure 7. Recommended Front End Circuit for
Input Frequencies Between 170MHz and 300MHz
Figure 9. Equivalent Reference Circuit
22532fa
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The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins. The multiple output
pins are needed to reduce package inductance. Bypass
capacitors must be connected as shown in Figure 9.
Other voltage ranges in-between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 10. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device. The SENSE pin should be tied to the appropriate
level as close to the converter as possible. If the SENSE pin
is driven externally, it should be bypassed to ground as
close to the device as possible with a 1µF ceramic capacitor.
In applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as
possible. Also, if the ADC is clocked with a sinusoidal
signal, filter the CLK signal to reduce wideband noise and
distortion products generated by the source.
Figures 12 and 13 show alternatives for converting a
differential clock to the single-ended CLK input. The use of
CLEAN
SUPPLY
4.7µF
FERRITE
BEAD
0.1µF
1k
0.1µF
SINUSOIDAL
CLOCK INPUT
NC7SVU04
1k
50Ω
1.5V
LTC2253/
LTC2252
CLK
VCM
22532 F11
2.2µF
12k
0.75V
12k
SENSE
LTC2253/
LTC2252
Figure 11. Sinusoidal Single-Ended CLK Drive
1µF
CLEAN
SUPPLY
4.7µF
22532 F10
FERRITE
BEAD
Figure 10. 1.5V Range ADC
Input Range
The input range can be set based on the application. The
2V input range will provide the best signal-to-noise performance while maintaining excellent SFDR. The 1V input
range will have better SFDR performance, but the SNR will
degrade by 4.2dB.
0.1µF
CLK
100Ω
LTC2253/
LTC2252
22532 F12
IF LVDS USE FIN1002 OR FIN1018.
FOR PECL, USE AZ1000ELT21 OR SIMILAR
Figure 12. CLK Drive Using an LVDS or PECL to CMOS Converter
Driving the Clock Input
The CLK input can be driven directly with a CMOS or TTL
level signal. A sinusoidal clock can also be used along with
a low jitter squaring circuit before the CLK pin (Figure 11).
The noise performance of the LTC2253/LTC2252 can
depend on the clock signal quality as much as on the
analog input. Any noise present on the clock signal will
result in additional aperture jitter that will be RMS summed
with the inherent ADC aperture jitter.
ETC1-1T
CLK
5pF-30pF
LTC2253/
LTC2252
DIFFERENTIAL
CLOCK
INPUT
22532 F13
0.1µF
FERRITE
BEAD
VCM
Figure 13. LVDS or PECL CLK Drive Using a Transformer
22532fa
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a transformer provides no incremental contribution to
phase noise. The LVDS or PECL to CMOS translators
provide little degradation below 70MHz, but at 140MHz
will degrade the SNR compared to the transformer solution. The nature of the received signals also has a large
bearing on how much SNR degradation will be experienced. For high crest factor signals such as WCDMA or
OFDM, where the nominal power level must be at least 6dB
to 8dB below full scale, the use of these translators will
have a lesser impact.
The transformer in the example may be terminated with
the appropriate termination for the signaling in use. The
use of a transformer with a 1:4 impedance ratio may be
desirable in cases where lower voltage differential signals
are considered. The center tap may be bypassed to ground
through a capacitor close to the ADC if the differential
signals originate on a different plane. The use of a capacitor at the input may result in peaking, and depending on
transmission line length may require a 10Ω to 20Ω ohm
series resistor to act as both a low pass filter for high
frequency noise that may be induced into the clock line by
neighboring digital signals, as well as a damping mechanism for reflections.
Maximum and Minimum Conversion Rates
The maximum conversion rate for the LTC2253/LTC2252
is 125Msps (LTC2253) and 105Msps (LTC2252). The
lower limit of the LTC2253/LTC2252 sample rate is determined by droop of the sample-and-hold circuits. The
pipelined architecture of this ADC relies on storing analog
signals on small valued capacitors. Junction leakage will
discharge the capacitors. The specified minimum operating frequency for the LTC2253/LTC2252 is 1Msps.
Clock Duty Cycle Stabilizer
An optional clock duty cycle stabilizer circuit ensures
high performance even if the input clock has a non 50%
duty cycle. Using the clock duty cycle stabilizer is
recommended for most applications. To use the clock
duty cycle stabilizer, the MODE pin should be connected to
1/3VDD or 2/3VDD using external resistors.
This circuit uses the rising edge of the CLK pin to sample
the analog input. The falling edge of CLK is ignored and the
internal falling edge is generated by a phase-locked loop.
The input clock duty cycle can vary from 40% to 60% and
the clock duty cycle stabilizer will maintain a constant 50%
internal duty cycle. If the clock is turned off for a long
period of time, the duty cycle stabilizer circuit will require
a hundred clock cycles for the PLL to lock onto the
input clock.
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
to make the sampling clock have a 50% (±5%) duty cycle.
DIGITAL OUTPUTS
Table 1 shows the relationship between the analog input
voltage, the digital data bits and the overflow bit.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D11 – D0
(Offset Binary)
D11 – D0
(2’s Complement)
>+1.000000V
+0.999512V
+0.999024V
1
0
0
1111 1111 1111
1111 1111 1111
1111 1111 1110
0111 1111 1111
0111 1111 1111
0111 1111 1110
+0.000488V
0.000000V
–0.000488V
–0.000976V
0
0
0
0
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
–0.999512V
–1.000000V
<–1.000000V
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
1000 0000 0001
1000 0000 0000
1000 0000 0000
Digital Output Buffers
Figure 14 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND,
isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series
with the output makes the output appear as 50Ω to
external circuitry and may eliminate the need for external
damping resistors.
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2253/LTC2252 should drive a
minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. For
22532fa
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0.1µF
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
TYPICAL
DATA
OUTPUT
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
LTC2253/LTC2252
OVDD
VDD
0.5V
TO 3.6V
VDD
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
OE
OGND
22510 F14
Figure 14. Digital Ouput Buffer
full speed operation the capacitive load should be kept
under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2253/LTC2252 parallel
digital output can be selected for offset binary or 2’s
complement format. Connecting MODE to GND or 1/3VDD
selects offset binary output format. Connecting MODE to
2/3VDD or VDD selects 2’s complement output format. An
external resistor divider can be used to set the 1/3VDD or
2/3VDD logic values. Table 2 shows the logic states for the
MODE pin.
Table 2. MODE Pin Function
Output Format
Clock Duty
Cycle Stablizer
Offset Binary
Off
1/3VDD
Offset Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
MODE Pin
0
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data
access and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed
operation. The output Hi-Z state is intended for use during
long periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to VDD and OE to VDD
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to VDD and OE
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
Grounding and Bypassing
Output Driver Power
The LTC2253/LTC2252 require a printed circuit board with
a clean, unbroken ground plane. A multilayer board with
an internal ground plane is recommended. Layout for the
printed circuit board should ensure that digital and analog
signal lines are separated as much as possible. In particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
High quality ceramic bypass capacitors should be used at
the VDD, OVDD, VCM, REFH, and REFL pins. Bypass capacitors must be located as close to the pins as possible. Of
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
18
22532fa
LTC2253/LTC2252
U
W
U
U
APPLICATIO S I FOR ATIO
particular importance is the 0.1µF capacitor between REFH
and REFL. This capacitor should be placed as close to the
device as possible (1.5mm or less). A size 0402 ceramic
capacitor is recommended. The large 2.2µF capacitor
between REFH and REFL can be somewhat further away.
The traces connecting the pins and bypass capacitors
must be kept short and should be made as wide as
possible.
The LTC2253/LTC2252 differential inputs should run parallel and close to each other. The input traces should be as
short as possible to minimize capacitance and to minimize
noise pickup.
Heat Transfer
Most of the heat generated by the LTC2253/LTC2252 is
transferred from the die through the bottom-side exposed
pad and package leads onto the printed circuit board. For
good electrical and thermal performance, the exposed pad
should be soldered to a large grounded pad on the PC
board. It is critical that all ground pins are connected to a
ground plane of sufficient area.
Clock Sources for Undersampling
Undersampling raises the bar on the clock source and the
higher the input frequency, the greater the sensitivity to
clock jitter or phase noise. A clock source that degrades
SNR of a full-scale signal by 1dB at 70MHz will degrade
SNR by 3dB at 140MHz, and 4.5dB at 190MHz.
In cases where absolute clock frequency accuracy is
relatively unimportant and only a single ADC is required,
a 3V canned oscillator from vendors such as Saronix or
Vectron can be placed close to the ADC and simply
connected directly to the ADC. If there is any distance to
the ADC, some source termination to reduce ringing that
may occur even over a fraction of an inch is advisable. You
must not allow the clock to overshoot the supplies or
performance will suffer. Do not filter the clock signal with
a narrow band filter unless you have a sinusoidal clock
source, as the rise and fall time artifacts present in typical
digital clock signals will be translated into phase noise.
The lowest phase noise oscillators have single-ended
sinusoidal outputs, and for these devices the use of a filter
close to the ADC may be beneficial. This filter should be
close to the ADC to both reduce roundtrip reflection times,
as well as reduce the susceptibility of the traces between
the filter and the ADC. If you are sensitive to close-in phase
noise, the power supply for oscillators and any buffers
must be very stable, or propagation delay variation with
supply will translate into phase noise. Even though these
clock sources may be regarded as digital devices, do not
operate them on a digital supply. If your clock is also used
to drive digital devices such as an FPGA, you should locate
the oscillator, and any clock fan-out devices close to the
ADC, and give the routing to the ADC precedence. The
clock signals to the FPGA should have series termination
at the source to prevent high frequency noise from the
FPGA disturbing the substrate of the clock fan-out device.
If you use an FPGA as a programmable divider, you must
re-time the signal using the original oscillator, and the retiming flip-flop as well as the oscillator should be close to
the ADC, and powered with a very quiet supply.
For cases where there are multiple ADCs, or where the
clock source originates some distance away, differential
clock distribution is advisable. This is advisable both from
the perspective of EMI, but also to avoid receiving noise
from digital sources both radiated, as well as propagated
in the waveguides that exist between the layers of multilayer PCBs. The differential pairs must be close together,
and distanced from other signals. The differential pair
should be guarded on both sides with copper distanced at
least 3x the distance between the traces, and grounded
with vias no more than 1/4 inch apart.
22532fa
19
J3
CLOCK
INPUT
R8
49.9Ω
C12
0.1µF
VDD
E1
EXT REF
VCM
VDD
R9
1k
NC7SVU04
VCM
VDD
4
2
EXT REF
5
6
3
1
JP3 SENSE
4
•
C19
0.1µF
R10
33Ω
VDD
GND
VDD
R16
1k
R15
1k
1/3VDD
2/3VDD
VDD
6
4
2
GND
C15
2.2µF
VDD
7 GND 8
5
3
1
C8
0.1µF
29
30
31
32
11
10
9
8
7
6
5
4
3
2
1
C20
0.1µF
C2
12pF
C11
0.1µF
VDD
JP4 MODE
JP2
OE
C7
2.2µF
R6
24.9Ω
R4
24.9Ω
C4
0.1µF
R14
1k
VDD
R2
24.9Ω
R3
24.9Ω
C14
0.1µF VCM
VDD
VDD
C9
1µF
C6
1µF
JP1
SHDN
R5
50Ω
•3
2
T1
ETC1-1T
5
1
C13
0.1µF
C3
0.1µF VCM
C1
0.1µF
C10
0.1µF
C5
4.7µF
6.3V
NC7SVU04
R1
OPT
R7
1k
L1
BEAD
J1
ANALOG
INPUT
C26
10µF
6.3V
33
R18
100k
R17
105k
LT1763
C16
0.1µF
VCC
VDD
C28
1µF
VCC
VCC
OE1
47
I0
46
I1
44
I2
43
I3
41
I4
40
I5
38
I6
37
I7
36
I8
35
I9
33
I10
32
I11
30
I12
29
I13
27
I14
26
I15
NC7SV86P5X
1
8
IN
OUT
2
7
ADJ GND
3
6
GND GND
4
5
BYP SHDN
VCC
C27
0.01µF
LTC2253/LTC2252
12
AIN+
NC
13
AIN–
NC
14
REFH
D0
15
D1
REFH
16
REFL
D2
17
REFL
D3
18
VDD
D4
19
GND
D5
22
D6
CLK
23
SHDN
D7
24
OE
D8
25
D9
26
D10
27
VDD
D11
28
VCM
OF
21
SENSE
OVDD
20
MODE
OGND
GND
GND
OE2
1
24
28
7
4
10
18
15
21
31
E3
GND
C18
0.1µF
C25
4.7µF E4
PWR
GND
E2
VDD
3V
5
6
8
7
C17 0.1µF
24LC025
1
VCC
A0
2
WP
A1
3
A2
SCL
4
A3 SDA
RN4A 33Ω
RN4B 33Ω
RN4C 33Ω
RN4D 33Ω
RN3A 33Ω
RN3B 33Ω
RN3C 33Ω
RN3D 33Ω
RN2A 33Ω
RN2B 33Ω
RN2C 33Ω
RN2D 33Ω
RN1A 33Ω
RN1B 33Ω
RN1C 33Ω
RN1D 33Ω
VDD
2
O0
3
O1
5
O2
6
O3
8
O4
9
O5
11
O6
12
O7
13
O8
14
O9
16
O10
17
O11
19
O12
20
O13
22
O14
23
O15
VCC
GND
48
LE2
GND
GND
VCC
GND
VCC
GND
GND
GND
74VCX16373MTD
LE1
25
42
39
45
34
VCC
C21
0.1µF
R11
10k
R12
10k
C22
0.1µF
VCC
R13
10k
C23
0.1µF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
40
38
22532 TA02
C24
0.1µF
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3201S-40G1
39
39
37
37
35
35
33
33
31
31
29
29
27
27
25
25
23
23
21
21
19
19
17
17
15
15
13
13
11
11
9
9
7
7
5
5
3
3
1
1
U
U
W
20
VCC
APPLICATIO S I FOR ATIO
U
Evaluation Circuit Schematic
LTC2253/LTC2252
22532fa
LTC2253/LTC2252
U
W
U
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APPLICATIO S I FOR ATIO
Silkscreen Top
Topside
Inner Layer 2 GND
22532fa
21
LTC2253/LTC2252
U
W
U
U
APPLICATIO S I FOR ATIO
Inner Layer 3 Power
Topside
Silkscreen Bottom
22532fa
22
LTC2253/LTC2252
U
PACKAGE DESCRIPTIO
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
0.70 ±0.05
5.50 ±0.05
4.10 ±0.05
3.45 ±0.05
(4 SIDES)
PACKAGE OUTLINE
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD LAYOUT
5.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.30 TYP
OR 0.35 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
0.00 – 0.05
31 32
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
3.45 ± 0.10
(4-SIDES)
(UH32) QFN 1004
0.200 REF
NOTE:
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
22532fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC2253/LTC2252
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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12-Bit, 80Msps ADC
72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1748
14-Bit, 80Msps ADC
76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1749
12-Bit, 80Msps Wideband ADC
Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750
14-Bit, 80Msps Wideband ADC
Up to 500MHz IF Undersampling, 90dB SFDR
LT1993
High Speed Differential Op Amp
600MHz BW, 75dBc Distortion at 70MHz
LTC2220
12-Bit, 170Msps ADC
890mW, 67.5dB SNR, 9mm x 9mm QFN Package
LTC2220-1
12-Bit, 185Msps ADC
910mW, 67.5dB SNR, 9mm x 9mm QFN Package
LTC2221
12-Bit, 135Msps ADC
660mW, 67.5dB SNR, 9mm x 9mm QFN Package
LTC2222
12-Bit, 105Msps ADC
475mW, 67.9dB SNR, 7mm x 7mm QFN Package
LTC2223
12-Bit, 80Msps ADC
366mW, 68dB SNR, 7mm x 7mm QFN Package
LTC2224
12-Bit, 135Msps ADC
660mW, 67.5dB SNR, 7mm x 7mm QFN Package
LTC2225
12-Bit, 10Msps ADC
60mW, 71.4dB SNR, 5mm x 5mm QFN Package
LTC2228
12-Bit, 65Msps ADC
210mW, 71dB SNR, 5mm x 5mm QFN Package
LTC2229
12-Bit, 80Msps ADC
230mW, 71.6dB SNR, 5mm x 5mm QFN Package
LTC2248
14-Bit, 65Msps ADC
210mW, 74dB SNR, 5mm x 5mm QFN Package
LTC2249
14-Bit, 80Msps ADC
230mW, 73dB SNR, 5mm x 5mm QFN Package
LTC2250
10-Bit, 105Msps ADC
320mW, 61.6dB SNR, 5mm x 5mm QFN Package
LTC2251
10-Bit, 125Msps ADC
395mW, 61.6dB SNR, 5mm x 5mm QFN Package
LTC2254
14-Bit, 105Msps ADC
320mW, 72.5dB SNR, 5mm x 5mm QFN Package
LTC2255
14-Bit, 125Msps ADC
395mW, 72.4dB SNR, 5mm x 5mm QFN Package
LTC2292
Dual 12-Bit, 40Msps ADC
240mW, 71dB SNR, 9mm x 9mm QFN Package
LTC2293
Dual 12-Bit, 65Msps ADC
410mW, 71dB SNR, 9mm x 9mm QFN Package
LTC2294
Dual 12-Bit, 80Msps ADC
445mW, 70.6dB SNR, 9mm x 9mm QFN Package
LTC2297
Dual 14-Bit, 40Msps ADC
240mW, 74dB SNR, 9mm x 9mm QFN Package
LTC2298
Dual 14-Bit, 65Msps ADC
410mW, 74dB SNR, 9mm x 9mm QFN Package
LTC2299
Dual 14-Bit, 80Msps ADC
445mW, 73dB SNR, 9mm x 9mm QFN Package
LT5512
DC-3GHz High Signal Level Downconverting Mixer
DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514
Ultralow Distortion IF Amplifier/ADC Driver with Digitally
Controlled Gain
450MHz 1dB BW, 47dB OIP3, Digital Gain Control
10.5dB to 33dB in 1.5dB/Step
LT5522
600MHz to 2.7GHz High Linearity Downconverting Mixer
4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz,
NF = 12.5dB, 50Ω Single-Ended RF and LO Ports
22532fa
24
Linear Technology Corporation
LT 0306 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2005