LINER LTC1662 Ultralow power, dual 10-bit dac in msop Datasheet

LTC1662
Ultralow Power, Dual
10-Bit DAC in MSOP
Features
n
n
n
n
n
n
n
n
n
Description
Ultralow Power: 1.5µA (Typ) ICC per DAC Plus
0.05µA Sleep Mode for Extended Battery Life
Tiny: Two 10-Bit DACs in an 8-Lead MSOP—
Half the Size of an SO-8
Wide 2.7V to 5.5V Supply Range
Double Buffered for Simultaneous DAC Updates
Rail-to-Rail Voltage Outputs Drive 1000pF
Reference Range Includes Supply for Ratiometric
0V to VCC Output
Reference Input Impedance Is Code-Independent
(7.1MΩ Typ)—Eliminates External Buffers
3-Wire Serial Interface with Schmitt Trigger Inputs
Differential Nonlinearity: ±0.75LSB Max
Applications
n
n
n
n
n
Mobile Communications
Portable Battery-Powered Instruments
Remote or Inaccessible Adjustments
Digitally Controlled Amplifiers and Attenuators
Factory or Field Calibration
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
The LTC®1662 is an ultralow power, fully buffered voltage
output, dual 10-bit digital-to-analog converter (DAC). Each
DAC channel draws just 1.7µA (typ) total supply-plusreference operating current, yet is capable of supplying
DC output currents in excess of 1mA and reliably driving
capacitive loads of up to 1000pF. A programmable sleep
mode further reduces total operating current to 0.05µA.
Linear Technology’s proprietary, inherently monotonic
architecture provides excellent linearity and an exceptionally small external form factor. The double-buffered input
logic provides simultaneous update capability and can be
used to write to the DACs without interrupting sleep mode.
With its tiny operating current and exceptionally small
size, the LTC1662 is ideal for use in the most powerconstrained products. For most designs, there is no
perceptible impact on the power budget; the LTC1662
draws many times less current than even a trimpot,
while providing buffered, low impedance (0.5Ω typical,
VCC = 5V) rail-to-rail outputs.
The LTC1662 is pin and software compatible with the
LTC1661 dual, 60µA 10-bit DAC. It is available in 8‑pin
MSOP and PDIP packages and is specified over the industrial temperature range.
Block Diagram
VOUT A
GND
VCC
VOUT B
8
7
6
5
Total Supply-Plus-Reference
Operating Current
LATCH
LATCH
LATCH
10-BIT
DAC A
LATCH
5.0
4.5
10-BIT
DAC B
5.5V
4.0
4.5V
CONTROL
LOGIC
ICC + IREF (µA)
3.5
ADDRESS
DECODER
3.0
2.5
2.0
3.6V
VCC = 2.7V
1.5
1.0
0.5 VREF = VCC
CODE = 1023
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
SHIFT REGISTER
1
2
3
4
CS/LD
SCK
SDI
REF
1662 BD
1662 TA01b
1662fa
1
LTC1662
Absolute Maximum Ratings
(Note 1)
VCC to GND................................................ –0.3V to 7.5V
Logic Inputs to GND ................................. –0.3V to 7.5V
VOUT A, VOUT B, REF to GND.......... –0.3V to (VCC + 0.3V)
Maximum Junction Temperature........................... 125°C
Storage Temperature Range................... –65°C to 150°C
Operating Temperature Range
LTC1662C................................................ 0°C to 70°C
LTC1662I............................................. –40°C to 85°C
Lead Temperature (Soldering, 10 sec)................... 300°C
Pin Configuration
TOP VIEW
TOP VIEW
CS/LD
SCK
SDI
REF
1
2
3
4
8
7
6
5
VOUT A
GND
VCC
VOUT B
MS8 PACKAGE
8-LEAD PLASTIC MSOP
CS/LD 1
8
VOUT A
SCK 2
7
GND
SDI 3
6
VCC
REF 4
5
VOUT B
N8 PACKAGE
8-LEAD PLASTIC DIP
TJMAX = 125°C, θJA = 150°C/W
TJMAX = 125°C, θJA = 100°C/W
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1662CMS8#PBF
LTC1662CMS8#TRPBF
LTKB
8-Lead Plastic MSOP
0°C to 70°C
LTC1662IMS8#PBF
LTC1662IMS8#TRPBF
LTKC
8-Lead Plastic MSOP
–40°C to 85°C
LTC1662CN8#PBF
LTC1662CN8#TRPBF
LTC1662CN8
8-Lead Plastic DIP
0°C to 70°C
LTC1662IN8#PBF
LTC1662IN8#TRPBF
LTC1662IN8
8-Lead Plastic DIP
–40°C to 85°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC1662CMS8
LTC1662CMS8#TR
LTKB
8-Lead Plastic MSOP
0°C to 70°C
LTC1662IMS8
LTC1662IMS8#TR
LTKC
8-Lead Plastic MSOP
–40°C to 85°C
LTC1662CN8
LTC1662CN8#TR
LTC1662CN8
8-Lead Plastic DIP
0°C to 70°C
LTC1662IN8
LTC1662IN8#TR
LTC1662IN8
8-Lead Plastic DIP
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
1662fa
2
LTC1662
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range (TA = TMIN to TMAX), otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VREF ≤ VCC, VOUT unloaded
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Accuracy
Resolution
l
10
Bits
10
Bits
Monotonicity
(Note 2)
l
DNL
Differential Nonlinearity
(Note 2)
l
±0.12
±0.75
LSB
INL
Integral Nonlinearity
(Note 2)
l
±0.8
±4
LSB
VOS
Offset Error
VCC = 5V, VREF = 4.096V, Measured at Code 20
l
±5
±25
VOS TC
VOS Temperature Coefficient
GE
Gain Error
GE TC
Gain Error Temperature Coefficient
PSR
Power Supply Rejection
±15
VCC = 5V, VREF = 4.096V
±1
l
VREF = 2.5V
mV
µV/°C
±8
LSB
±12
µV/°C
0.18
LSB/V
Reference Input
Input Voltage Range
Input Resistance
Active Mode
Sleep Mode
l
0
l
3.9
Input Capacitance
VCC
V
7.1
2.5
MΩ
GΩ
10
pF
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
ICC
Supply Current
VCC = 3V (Note 3)
VCC = 5V (Note 3)
VCC = 3V (Note 3)
VCC = 5V (Note 3)
Sleep Mode Operating Current
l
2.7
5.5
V
3.0
3.5
4.0
4.5
5.0
5.5
µA
µA
µA
µA
0.05
0.10
0.18
µA
µA
l
l
Supply Plus Reference Current, VCC = VREF = 5V (Note 3)
l
DC Performance
Short-Circuit Current Low
VOUT = 0V, VCC = VREF = 5V, Code = 1023 (Note 7)
l
5
12
70
mA
Short-Circuit Current High
VOUT = VCC = VREF = 5V, Code = 0 (Note 7)
l
3
10
80
mA
AC Performance
Voltage Output Slew Rate
Rising (Notes 4, 5)
Falling (Notes 4, 5)
Voltage Output Settling Time
Rising 0.1VFS to 0.9VFS ±0.5LSB (Notes 4, 5)
Falling 0.9VFS to 0.1VFS ±0.5LSB (Notes 4, 5)
20
7
Capacitive Load Driving
V/ms
V/ms
0.40
0.75
ms
ms
1000
pF
Digital I/O
VIH
Digital Input High Voltage
VCC = 2.7V to 5.5V
VCC = 2.7V to 3.6V
l
l
VIL
Digital Input Low Voltage
VCC = 4.5V to 5.5V
VCC = 2.7V to 5.5V
l
l
ILK
Digital Input Leakage
VIN = GND to VCC
l
CIN
Digital Input Capacitance
2.4
2.0
V
V
±0.05
1.5
0.8
0.6
V
V
±1.0
µA
pF
1662fa
3
LTC1662
Timing Characteristics
range, otherwise specifications are at TA = 25°C.
SYMBOL
PARAMETER
The l denotes the specifications which apply over the full operating temperature
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 4.5V to 5.5V
t1
SDI Setup
Relative to SCK Positive Edge
l
t2
SDI Hold
Relative to SCK Positive Edge
l
0
ns
t3
SCK High Time
(Note 6)
l
30
ns
t4
SCK Low Time
(Note 6)
l
30
ns
t5
CS/LD Pulse Width
(Note 6)
l
100
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
30
ns
t7
CS/LD Low to SCK High
(Note 6)
l
20
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
0
ns
CS/LD High to SCK Positive Edge
(Note 6)
l
20
SCK Frequency
Square Wave (Note 6)
l
t11
55
ns
ns
16.7
MHz
VCC = 2.7V to 5.5V
t1
SDI Setup
Relative to SCK Positive Edge (Note 6)
l
75
ns
t2
SDI Hold
Relative to SCK Positive Edge (Note 6)
l
0
ns
t3
SCK High Time
(Note 6)
l
50
ns
t4
SCK Low Time
(Note 6)
l
50
ns
t5
CS/LD Pulse Width
(Note 6)
l
150
ns
t6
LSB SCK High to CS/LD High
(Note 6)
l
50
ns
t7
CS/LD Low to SCK High
(Note 6)
l
30
ns
t9
SCK Low to CS/LD Low
(Note 6)
l
0
ns
t11
CS/LD High to SCK Positive Edge
(Note 6)
l
30
SCK Frequency
Square Wave (Note 6)
l
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Nonlinearity and monotonicity are defined and tested at VCC = 5V,
VREF = 4.096V, from code 20 to code 1023. See Figure 2.
ns
10
MHz
Note 3: Digital inputs at 0V or VCC.
Note 4: Load is 10kΩ in parallel with 100pF.
Note 5: VCC = VREF = 5V. DAC switched between 0.1VFS and 0.9VFS ;
i.e., codes k = 102 and k = 922.
Note 6: Guaranteed by design, not subject to test.
Note 7: One DAC output loaded.
1662fa
4
LTC1662
Typical Performance Characteristics
Total Supply-Plus-Reference
Operating Current
Supply Current vs Temperature
4.5
4.5
4.0
4.5V
3.0
2.5
2.0
3.6V
1.5
VCC = 2.7V
3.0
2.5
3.6V
2.0
VCC = 2.7V
1.0
0.5
0.5 VREF = VCC
CODE = 1023
0
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE (°C)
1662 G01
Integral Nonlinearity (INL)
ICC (mA)
0.7
0.6
0.5
0.4
0.3
0.2
3
2
1
0
–1
–2
0.1
–3
0
–4
0
1.5
1 1.5 2 2.5 3 3.5 4
LOGIC INPUT VOLTAGE (V)
4.5
5
0
256
512
CODE
768
1023
Integral Nonlinearity (INL)
vs Reference Voltage
VCC = 5.5V
3
0
–0.20
–0.40
–0.60
–0.75
MAX NEG INL
VCC = 5.5V
2
3
4
5
512
CODE
768
6
0.25
MAX POS DNL
0
MAX NEG DNL
–0.25
VREF (V)
–0.75
VCC = 5V
VREF = 4.096V
–2
–3
–4
0
1
2
3
4
5
6
VREF (V)
1662 G07
1023
–1
–0.50
–3
1
256
Offset Voltage vs Temperature
–2
0
0
1662 G06
OFFSET ERROR (mV)
PEAK DNL (LSB)
PEAK INL (LSB)
0
–4
0.20
0.50
MAX POS INL
10M 100M
0.40
0
2
–1
10k 100k 1M
FREQUENCY (Hz)
0.75
0.60
Differential Nonlinearity (DNL)
vs Reference Voltage
0.75
1
1k
1662 G05
1662 G04
4
100
Differential Nonlinearity (DNL)
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
0.8
10
1662 G03
4
VCC = 5V
ALL DIGITAL INPUTS
SHORTED TOGETHER
0.9
1
1662 G02
Supply Current
vs Logic Input Voltage
1.0
VCC = 3V
10
1.5
5 25 45 65 85 105 125
TEMPERATURE (°C)
VCC = 5V
100
1.0
0
–55 –35 –15
CS/LD = LOGIC LOW
CODE = 0
4.5V
3.5
ICC + IREF (µA)
ICC (µA)
5.5V
4.0
5.5V
3.5
1000
5.0
VREF = VCC
CODE = 1023
ICC (µA)
5.0
Supply Current
vs Clock Frequency
1662 G08
–5
25 45 65
–55 –35 –15 5
TEMPERATURE (°C)
85
105
1662 G09
1662fa
5
LTC1662
Typical Performance Characteristics
Load Regulation vs Output
Current at 5V
Gain Error vs Temperature
0
1.0
VCC = 5V
VREF = 4.096V
0.6
–3
0.6
0.4
0.2
0
–0.2
–0.4
–1.0
105
SINK
–5 –4 –3 –2 –1 0 1
IOUT (mA)
2
3
Output Amplifier Current Sourcing
Capability (Mid-Scale)
5.0
4.0
VCC = 5.5V
VCC = 5V
VCC = 4.5V
2.0
1.5
VCC = 3.6V
VCC = 3V
VCC = 2.7V
4.5
1
10
100
1m
10m
OUTPUT SOURCE CURRENT (A)
3.5
2.5
2.0
0.5
0
1µ
10µ
100µ
1m
10m
OUTPUT SINK CURRENT (A)
Max/Min Output Voltage vs Source/
Sink Output Current (VCC = 3V)
1.0
VOUT (V)
VOUT (V)
VREF = VCC
TA = 25°C
3
2
CODE = 0
1
VREF = VCC = 5V
10% TO 90% STEP
0.3
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
OUTPUT SOURCE/SINK CURRENT (mA)
0.5 1 1.5 2 2.5 3 3.5 4 4.5
OUTPUT SOURCE/SINK CURRENT (mA)
2
1662 G16
0
5
1662 G15
180
0.9
0
0
Output Minimum Series
Resistance vs Load Capacitance
4
1.8
0.6
0
100m
2.1
1.2
CODE = 0
0.5
5
CODE = 1023
1.5
2.0
Large-Signal Step Response
3.0
2.4
VREF = VCC
TA = 25°C
2.5
1662 G14
1662 G13
2.7
3.0
1.5
VCC = 3.6V
VCC = 3V
VCC = 2.7V
1.0
100m
CODE = 1023
4.0
MINIMUM SERIES RESISTANCE (Ω)
0.5
0
3.0
1
Max/Min Output Voltage vs Source/
Sink Output Current (VCC = 5V)
1.5
1.0
–1 –0.8–0.6–0.4– 0.2 0 0.2 0.4 0.6 0.8
IOUT (mA)
5.0
VCC = 5.5V
VCC = 5V
VCC = 4.5V
3.5
2.5
SINK
1662 G12
VREF = VCC
CODE = 512
TA = 25°C
4.5
VOUT (V)
VOUT (V)
3.0
5
Output Amplifier Current Sinking
Capability (Mid-Scale)
5.0
3.5
4
–1.0
1662 G11
1662 G10
VREF = VCC
4.5 CODE = 512
TA = 25°C
4.0
SOURCE
–0.8
VOUT (V)
85
0
–0.2
–0.6
SOURCE
–0.8
–5
25 45 65
–55 –35 –15 5
TEMPERATURE (°C)
0.2
–0.4
–0.6
–4
VREF = VCC = 3V
VOUT = 1.5V
CODE = 512
TA = 25°C
0.8
∆VOUT (LSB)
∆VOUT (LSB)
GAIN ERROR (mV)
0.4
–2
1.0
VREF = VCC = 5V
VOUT = 2.5V
CODE = 512
TA = 25°C
0.8
–1
Load Regulation vs Output
Current at 3V
160
140
120
100
80
60
40
20
0
100p 1000p 0.01µ 0.1µ
1µ
CAPACITANCE (F)
0
TIME (0.5ms/DIV)
1662 G17
10µ
100µ
1662 G18
1662fa
6
LTC1662
Pin Functions
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When CS/LD is pulled high, SCK is
disabled and the operation(s) specified in the control code,
A3-A0, is (are) performed. CMOS and TTL compatible.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 3): Serial Interface Data Input. Input word data
on the SDI pin is shifted into the 16-bit register on the
rising edge of SCK. CMOS and TTL compatible.
REF (Pin 4): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
VOUT A, VOUT B (Pin 8, Pin 5): DAC Analog Voltage Outputs.
The output range is
 1023 
0 ≤ VOUTA ,VOUTB ≤ VREF 
 1024 
VCC (Pin 6): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
GND (Pin 7): System Ground.
Definitions
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆VOUT – LSB)/LSB
where ∆VOUT is the measured voltage difference between
two adjacent codes.
Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset
and gain errors (see Figure 2).
Gain Error (GE): The deviation from the slope of the ideal
DAC transfer function, expressed in LSBs at full-scale.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (endpoint INL). Because the output cannot go
below zero, the linearity is measured between full-scale
and the lowest code which guarantees the output will be
greater than zero. The INL error at a given input code is
calculated as follows:
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF /1024
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Figure 2).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
INL = [VOUT – VOS – (VFS – VOS)(code/1023)]/LSB
where VOUT is the output voltage of the DAC measured at
the given input code.
1662fa
7
LTC1662
Timing Diagram
t1
t2
t3
t6
t4
SCK
t9
t11
SDI
A3
t5
A1
A2
X1
X0
t7
CS/LD
1662 TD
Operation
SCK
SDI
1
A3
2
A2
3
A1
CONTROL CODE
4
A0
5
D9
6
D8
7
D7
8
D6
9
D5
10
D4
11
D3
INPUT CODE
12
D2
13
D1
14
D0
15
X1
16
X0
DON’T CARE
INPUT WORD W0
CS/LD
(INSTRUCTION
EXECUTED) 1662 F01
(SCK ENABLED)
Figure 1. Register Loading Sequence
1662fa
8
LTC1662
Operation
Table 1. DAC Control Functions
CONTROL
INPUT REGISTER
STATUS
DAC REGISTER
STATUS
POWER-DOWN STATUS
(SLEEP/WAKE)
0
No Change
No Update
No Change
No Operation. Power-Down Status Unchanged
(Part Stays In Wake or Sleep Mode)
0
1
Load DAC A
No Update
No Change
Load Input Register A with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
0
1
0
Load DAC B
No Update
No Change
Load Input Register B with Data. DAC Outputs Unchanged.
Power-Down Status Unchanged
1
0
0
0
No Change
Update Outputs
Wake
Load Both DAC Regs with Existing Contents of Input Regs.
Outputs Update. Part Wakes Up
1
0
0
1
Load DAC A
Update Outputs
Wake
Load Input Reg A. Load DAC Regs with New Contents of
Input Reg A and Existing Contents of Reg B. Outputs Update.
Part Wakes Up
1
0
1
0
Load DAC B
Update Outputs
Wake
Load Input Reg B. Load DAC Regs with Existing Contents of
Input Reg A and New Contents of Reg B. Outputs Update.
Part Wakes Up
1
1
0
1
No Change
No Update
Wake
Part Wakes Up. Input and DAC Regs Unchanged.
DAC Outputs Reflect Existing Contents of DAC Regs
1
1
1
0
No Change
No Update
Sleep
Part Goes to Sleep. Input and DAC Regs Unchanged.
DAC Outputs Set to High Impedance State
1
1
1
1
Load DACs A, B
with Same
10-Bit Code
Update Outputs
Wake
Load Both Input Regs. Load Both DAC Regs with New
Contents of Input Regs. Outputs Update. Part Wakes Up
A3
A2
A1 A0
0
0
0
0
0
0
COMMENTS
Note: All control codes other than those shown are undefined and not subject to test.
Transfer Function
The transfer function for the LTC1662 is:
 k 
VOUT(IDEAL) = 
V
 1024  REF
where k is the decimal equivalent of the binary DAC input
code D9-D0 and VREF is the voltage at REF (Pin 4).
Power-On Reset
The LTC1662 actively clears the outputs to zero-scale
when power is first applied, making system initialization
consistent and repeatable.
Power Supply Sequencing
The voltage at REF (Pin 4) should be kept within the range
–0.3V ≤ VREF ≤ VCC + 0.3V (see the Absolute Maximum
Ratings). Particular care should be taken during power
supply turn-on and turn-off sequences, when the voltage at
VCC (Pin 6) is in transition. If it is not possible to sequence
the supplies, clamp the voltage at REF by connecting a
Schottky diode between Pin 4 (anode) and Pin 6 (cathode).
Serial Interface
See Table 2. The 16-bit input word consists of the 4-bit
control code, the 10-bit input code and two don’t-care bits.
Table 2. LTC1662 Input Word
Input Word
A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X1 X0
Control Code
Input Code
Don’t
Care
After the input word is loaded into the register (see Figure 1),
it is internally converted from serial to parallel format. The
parallel 10-bit-wide input code data path is then buffered
by two latch registers.
1662fa
9
LTC1662
Operation
The first of these, the input register, is used for loading
new input codes. The second buffer, the DAC register, is
used for updating the DAC outputs. Each DAC has its own
10‑bit input register and 10-bit DAC register.
By selecting the appropriate 4-bit control code (see Table 1)
it is possible to perform single operations, such as loading
one DAC or changing power-down status (sleep/wake).
In addition, some control codes perform two or more
operations at the same time. For example, one such code
loads DAC A, updates both outputs and Wakes the part
up. The DACs can be loaded separately or together, but
the outputs are always updated together.
Register Loading Sequence
See Figure 1. With CS/LD held low, data on the SDI input
is shifted into the 16-bit shift register on the positive edge
of SCK. The 4-bit control code, A3-A0, is loaded first, then
the 10-bit input code, D9-D0, ordered MSB to LSB in each
case. Two don’t-care bits, X1 and X0, are loaded last. When
the full 16-bit input word has been shifted in, CS/LD is
pulled high, causing the system to respond according to
Table 1. The clock is disabled internally when CS/LD is
high. Note: SCK must be low when CS/LD is pulled low.
and 0010 b); then, a single command (1000 b) can be used
both to wake the part and to update the output values.
Alternatively, one DAC may be loaded with a new input
code during sleep; then with just one command, the other
DAC is loaded, the part is awakened and both outputs are
updated.
For example, control code 0001b is used to load DAC A
during sleep. Then control code 0101b loads DAC B, wakes
the part and simultaneously updates both DAC outputs.
Voltage Outputs
Each of the rail-to-rail output amplifiers contained in
the LTC1662 can typically source or sink at least 1mA
(VCC = 5V). The outputs swing to within a few millivolts
of either supply when unloaded and have an equivalent
output resistance of 130Ω (typical) when driving a load to
the rails. The output amplifiers are stable driving capacitive
loads of up to 1000pF.
A small resistor placed in series with the output can be
used to achieve stability for any load capacitance. Please
see the Output Minimum Resistance vs Load Capacitance
curve in the Typical Performance Characteristics section.
Sleep Mode
Rail-to-Rail Output Considerations
DAC control code 1110b is reserved for the special sleep
instruction (see Table 1). In this mode, static power
consumption is greatly reduced. The reference input and
analog outputs are set in a high impedance state and all
DAC settings are retained in memory so that when sleep
mode is exited, the outputs of DACs not updated by the
Wake command are restored to their last active state.
In any rail-to-rail DAC, the output swing is limited to voltages within the supply range.
Sleep mode is initiated by performing a load sequence
using control code 1110b (the DAC input code D9-D0 is
ignored).
To save instruction cycles, the DACs may be prepared
with new input codes during sleep (control codes 0001b
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 2b.
Similarly, limiting can occur near full-scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
(FSE = VOS + GE) is positive, the output for the highest
codes limits at VCC as shown in Figure 2c. No full-scale
limiting can occur if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
1662fa
10
LTC1662
Operation
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(2c)
VREF = VCC
OUTPUT
VOLTAGE
0
512
INPUT CODE
1023
(2a)
OUTPUT
VOLTAGE
NEGATIVE
OFFSET
0V
INPUT CODE
1662 F02
(2b)
Figure 2. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero-Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full-Scale When VREF = VCC
1662fa
11
LTC1662
Typical Applications
Micropower Trim Circuit with Coarse/Fine Adjustment. Total Supply Current Is 9.5µA
3.3V
0.1µF
R2
1.1M
0.1µF
3.3V
2
LTC1258-2.5
1
2.5V
4
4 REF
6
SDI
SCK
3.3V
VCC
2
R1
COARSE
11k
8
DAC A
CS/LD
R1
11k
–
8
LT1495
3
VOUT A
0.1µF
1
VOUT
+
0.1µF
4
1
LTC1662
U1
3
2
5
DAC B
 CODE A R1 CODE B
VOUT = VREF 
+
•
 1024
R2 1024 
R2
FINE
1.1M
VOUT B
7 GND
1 CODE B
 CODE A
+
•
= 2.5V 
 1024
100 1024 
1662 TA02
Using the LTC1258 and the LTC1662 in a Portable Application
Powered by a Single Li-Ion Battery. Total Supply Current Is 8.2µA
Li-Ion BATTERY INPUT
VIN ≥ 4.3V
0.1µF
0.1µF
6
2
LTC1258-4.1
4
4
1
4.096V
3
2
1
VCC
VOUT A
REF
8
0V TO 4.096V
(4mV/BIT)
5
0V TO 4.096V
(4mV/BIT)
SDI
LTC1662
SCK
CS/LD
VOUT B
GND
7
1662 TA03
1662fa
12
LTC1662
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
0.254
(.010)
7 6 5
0.52
(.0205)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
3.20 – 3.45
(.126 – .136)
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.42 ± 0.038
(.0165 ± .0015)
TYP
8
0.65
(.0256)
BSC
1
1.10
(.043)
MAX
2 3
4
0.86
(.034)
REF
0.18
(.007)
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS8) 0307 REV F
1662fa
13
LTC1662
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
N Package
N Package
8-Lead PDIP
(Narrow .300 Inch)
8-Lead PDIP
(Narrow
.300 Inch)
(Reference
LTC DWG
# 05-08-1510
Rev I)
(Reference LTC DWG # 05-08-1510 Rev I)
.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
.255 ± .015*
(6.477 ± 0.381)
.300 – .325
(7.620 – 8.255)
.008 – .015
(0.203 – 0.381)
(
+.035
.325 –.015
8.255
+0.889
–0.381
)
.045 – .065
(1.143 – 1.651)
.065
(1.651)
TYP
.100
(2.54)
BSC
.130 ± .005
(3.302 ± 0.127)
.120
(3.048) .020
MIN
(0.508)
MIN
.018 ± .003
N8 REV I 0711
(0.457 ± 0.076)
NOTE:
1. DIMENSIONS ARE
INCHES
MILLIMETERS
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)
1662fa
14
LTC1662
Revision History
REV
DATE
DESCRIPTION
PAGE NUMBER
A
01/12
Removed Typical values in the Timing Characteristics section.
4
Corrected Related Parts listing for the LTC1659.
16
1662fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LTC1662
Typical Application
Ultralow Power DAC Optimizes Mixer Performance
3.3V
0.1µF
0.1µF
3.3V
2
LTC1258-2.5
1
2.5V
4
4 REF
6
SDI
8
SCK
560k
VOUT A
1
3
IP
VCC
DAC A
CS/LD
I
LO
3.9k
0.1%
3.9k
0.1%
3.9k, 0.1%
3.9k
0.1%
I
I+Q
MIXER
LO
LTC1662
Q
2
5
DAC B
7 GND
560k
VOUT B
IP
RF
QP
3.9k
0.1%
3.9k, 0.1%
3.9k
0.1%
3.9k
0.1%
Q
1662 TA04
Q
QP
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC1661
Dual 10-Bit VOUT DAC in 8-Lead MSOP Package
VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1663
Single 10-Bit VOUT DAC with 2-Wire Interface in SOT-23 Package
VCC = 2.7V to 5.5V, Internal Reference, 60µA
LTC1664
Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1665/LTC1660
Octal 8-/10-Bit VOUT DAC in 16-Pin Narrow SSOP
VCC = 2.7V to 5.5V, 60µA per DAC, Rail-to-Rail Output
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC in SO-8 Package
VCC = 2.7V to 5.5V, External Reference Can Be Tied to VCC
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1458/LTC1458L
Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Lead MSOP Package
VCC = 2.7V to 5.5V, Low Power Multiplying VOUT DAC. Output
Swings from GND to REF. REF Input Can Be Tied to VCC
1662fa
16 Linear Technology Corporation
LT 0112 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2000