SLAS508 − APRIL 2006
D
D
D
D
D
D
D
D
D
D
D
D
− Active Mode: 350 µA at 1 MHz, 2.2 V
− Standby Mode: 1.1 µA
− Off Mode (RAM Retention): 0.3 µA
Five Power Saving Modes
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture, Extended
Memory, 125-ns Instruction Cycle Time
Three Channel Internal DMA
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and Autoscan
Feature
Three Configurable Operational Amplifiers
Dual 12-Bit D/A Converters With
Synchronization
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Seven
Capture/Compare-With-Shadow Registers
On-Chip Comparator
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Serial Communication Interface (USART1),
Select Asynchronous UART or
Synchronous SPI by Software
D Universal Serial Communication Interface
D
D
D
D
D
D
− Enhanced UART supporting
auto-baudrate detection
− IrDA Encoder and Decoder
− Synchronous SPI
− I2CTM
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
Brownout Detector
Basic Timer with Real Time Clock Feature
Integrated LCD Driver up to 160 Segments
With Regulated Charge Pump
Family Members Include:
− MSP430FG4616:
92KB+256B Flash Memory,
4KB RAM
− MSP430FG4617:
92KB+256B Flash Memory,
8KB RAM
− MSP430FG4618:
116KB+256B Flash Memory,
8KB RAM
− MSP430FG4619:
120KB+256B Flash Memory,
4KB RAM
For Complete Module Descriptions, Refer
to the MSP430x4xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430FG461x series are microcontroller configurations with two 16-bit timers, a high performance 12-bit
A/D converter, dual 12-bit D/A converters, three configurable operational amplifiers, one universal serial
communication interface (USCI), one universal synchronous/asynchronous communication interface
(USART), DMA, 80 I/O pins, and a liquid crystal display (LCD) driver with regulated charge pump.
Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2006, Texas Instruments Incorporated
!" ##$% &'(#"% ")$ !"*$ '$%+ &)!%$ '$*$,&$"- )!!#"$%"# '!"! !' ")$
%&$##!"% !$ '$%+ +!,%- $ !% %"($"% $%$*$% ")$ +)" "
#)!+$ '%#"($ ")$%$ &'(#"% .")(" "#$-
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
PRODUCT PREVIEW
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
SLAS508 − APRIL 2006
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC 100-PIN TQFP
(PZ)
MSP430FG4616IPZ
MSP430FG4617IPZ
−40°C to 85°C
MSP430FG4618IPZ
PRODUCT PREVIEW
MSP430FG4619IPZ
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UCA0TXD
P2.5/UCA0RXD
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
P4.0/UTXD1
P4.1/URXD1
DVSS2
DVCC2
LCDCAP/R33
P5.7/R23
P5.6/LCDREF/R13
P5.5/R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P4.2/STE1/S39
P8.1/S24
P8.0/S25
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
P7.3/UCA0CLK/S30
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
P7.0/UCA0STE/S33
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
P8.5/S20
P8.4/S21
P8.3/S22
P8.2/S23
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MSP430FG4616IPZ
MSP430FG4617IPZ
MSP430FG4618IPZ
MSP430FG4619IPZ
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
PRODUCT PREVIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P9.3/S14
P9,2/S15
P9.1/S16
P9.0/S17
P8.7/S18
P8.6/S19
DVCC1
P6.3/A3/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
VeREF+/DAC0
VREF−/VeREF−
P5.1/S0/A12/DAC1
P5.0/S1/A13/OA1I1
P10.7/S2/A14/OA2I1
P10.6/S3/A15
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
82
81
80
79
78
77
76
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P1.7/CA1
P6.2/A2/OA0I1
P6.1/A1/OA0O
P6.0/A0/OA0I0
RST/NMI
TCK
TMS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
AVCC
DV SS1
AVSS
pin designation, MSP430FG461xIPZ
SLAS508 − APRIL 2006
MSP430FG461x functional block diagram
XIN /
XT2 IN
XOUT /
XT2OUT
2
2
Oscillators
FLL +
DVCC 1/2
ACLK
SMCLK
Flash
RAM
120kB
116 kB
92kB
92kB
4kB
8kB
8kB
4kB
PRODUCT PREVIEW
AVSS
P1. x/P2 .x
ADC 12
12−Bit
DAC 12
12−Bit
12
Channels
2 Channels
Voltage out
OA0, OA 1,
OA 2
Ports P 1/P 2
Comparator
_A
3 Op Amps
P 7.x/ P8. x
P 9.x/P 10.x
4x8/2 x16
Ports
P3 /P4
P5 /P6
Ports
P7/ P8
P 9/P 10
4x8 I/O
4x8/2x16 I/O
DMA
Controller
MDB
3 Channels
Brownout
Protection
SVS/ SVM
Hardware
Multiplier
MPY ,
MPYS,
MAC ,
MACS
Watchdog
WDT+
Timer_ A3
Timer_B 7
3 CC
Registers
7 CC
Registers
Shadow
Reg
15/16−Bit
Basic Timer
&
Real −Time
Clock
RST/NMI
4
2x8 I/O
Interrupt
capability
P3. x/P4 .x
P5. x/P6 .x
4x8
MAB
Enhanced
Emulation
JTAG
Interface
AVCC
2x8
MCLK
8MHz
CPUX
incl. 16
Registers
DVSS1/2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
LCD_A
160
Segments
1, 2,3,4 Mux
USCI _A 0:
UART,
IrDA, SPI
USCI _B 0:
SPI, I2 C
USART 1
UART , SPI
SLAS508 − APRIL 2006
MSP430FG461x Terminal Functions
NAME
NO.
I/O
DESCRIPTION
DVCC1
1
P6.3/A3/OA1O
2
I/O
Digital supply voltage, positive terminal.
General-purpose digital I/O / analog input a3—12-bit ADC / OA1 output
P6.4/A4/OA1I0
3
I/O
General-purpose digital I/O / analog input a4—12-bit ADC / OA1 input multiplexer on
+terminal and −terminal
P6.5/A5/OA2O
4
I/O
General-purpose digital I/O / analog input a5—12-bit ADC / OA2 output
P6.6/A6/DAC0/OA2I0
5
I/O
General-purpose digital I/O / analog input a6—12-bit ADC / DAC12.0 output / OA2 input
multiplexer on +terminal and −terminal
P6.7/A7/DAC1/SVSIN
6
I/O
General-purpose digital I/O / analog input a7—12-bit ADC / DAC12.1 output / analog input
to brownout, supply voltage supervisor
VREF+
XIN
7
O
Output of positive terminal of the reference voltage in the ADC
8
I
Input port for crystal oscillator XT1. Standard or watch crystals can be connected.
XOUT
9
O
Output terminal of crystal oscillator XT1
VeREF+/DAC0
10
I/O
Input for an external reference voltage to the ADC / DAC12.0 output
VREF−/VeREF−
11
I
Negative terminal for the ADC’s reference voltage for both sources, the internal reference
voltage, or an external applied reference voltage
P5.1/S0/A12/DAC1 (see Note 1)
12
I/O
General-purpose digital I/O / LCD segment output 0 / analog input a12 − 12−bit ADC /
DAC12.1 output
P5.0/S1/A13/OA1I1 (see Note 1)
13
I/O
General-purpose digital I/O / LCD segment output 1 / analog input a13 − 12−bit ADC/OA1
input multiplexer on +terminal and −terminal
P10.7/S2/A14/OA2I1 (see Note 1)
14
I/O
General-purpose digital I/O / LCD segment output 2 / analog input a14 − 12−bit ADC/OA2
input multiplexer on +terminal and −terminal
P10.6/S3/A15 (see Note 1)
15
I/O
General-purpose digital I/O / LCD segment output 3 / analog input a15 − 12−bit ADC
P10.5/S4
16
I/O
General-purpose digital I/O / LCD segment output 4
P10.4/S5
17
I/O
General-purpose digital I/O / LCD segment output 5
P10.3/S6
18
I/O
General-purpose digital I/O / LCD segment output 6
P10.2/S7
19
I/O
General-purpose digital I/O / LCD segment output 7
P10.1/S8
20
I/O
General-purpose digital I/O / LCD segment output 8
P10.0/S9
21
I/O
General-purpose digital I/O / LCD segment output 9
P9.7/S10
22
I/O
General-purpose digital I/O / LCD segment output 10
P9.6/S11
23
I/O
General-purpose digital I/O / LCD segment output 11
P9.5/S12
24
I/O
General-purpose digital I/O / LCD segment output 12
P9.4/S13
25
I/O
General-purpose digital I/O / LCD segment output 13
P9.3/S14
26
I/O
General-purpose digital I/O / LCD segment output 14
P9.2/S15
27
I/O
General-purpose digital I/O / LCD segment output 15
P9.1/S16
28
I/O
General-purpose digital I/O / LCD segment output 16
P9.0/S17
29
I/O
General-purpose digital I/O / LCD segment output 17
P8.7/S18
30
I/O
General-purpose digital I/O / LCD segment output 18
P8.6/S19
31
I/O
General-purpose digital I/O / LCD segment output 19
P8.5/S20
32
I/O
General-purpose digital I/O / LCD segment output 20
P8.4/S21
33
I/O
General-purpose digital I/O / LCD segment output 21
P8.3/S22
34
I/O
General-purpose digital I/O / LCD segment output 22
PRODUCT PREVIEW
TERMINAL
NOTES: 1. Segments S0 through S3 must be disabled and cannot be used when the LCD charge pump feature is enabled. In addition, when
using segments S0 through S3 with an external LCD voltage supply, VLCD ≤ AVCC.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SLAS508 − APRIL 2006
MSP430FG461x Terminal Functions (Continued)
TERMINAL
PRODUCT PREVIEW
NAME
NO.
I/O
DESCRIPTION
P8.2/S23
35
I/O
General-purpose digital I/O / LCD segment output 23
P8.1/S24
36
I/O
General-purpose digital I/O / LCD segment output 24
P8.0/S25
37
I/O
General-purpose digital I/O / LCD segment output 25
P7.7/S26
38
I/O
General-purpose digital I/O / LCD segment output 26
P7.6/S27
39
I/O
General-purpose digital I/O / LCD segment output 27
P7.5/S28
40
I/O
General-purpose digital I/O / LCD segment output 28
P7.4/S29
41
I/O
General-purpose digital I/O / LCD segment output 29
P7.3/UCA0CLK/S30
42
I/O
General-purpose digital I/O / external clock input—USCI_A0/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 30
P7.2/UCA0SOMI/S31
43
I/O
General-purpose digital I/O / slave out/master in of USCI_A0/SPI mode / LCD segment output
31
P7.1/UCA0SIMO/S32
44
I/O
General-purpose digital I/O / slave in/master out of USCI_A0/SPI mode / LCD segment output
32
P7.0/UCA0STE/S33
45
I/O
General-purpose digital I/O / slave transmit enable—USCI_A0/SPI mode / LCD segment output
33
P4.7/UCA0RXD/S34
46
I/O
General-purpose digital I/O / receive data in − USCI_A0/UART or IrDA mode / LCD segment
output 34
P4.6/UCA0TXD/S35
47
I/O
General-purpose digital I/O / transmit data in − USCI_A0/UART or IrDA mode / LCD segment
output 35
P4.5/UCLK1/S36
48
I/O
General-purpose digital I/O / external clock input—USART1/UART or SPI mode, clock
output—USART1/SPI MODE / LCD segment output 36
P4.4/SOMI1/S37
49
I/O
General-purpose digital I/O / slave out/master in of USART1/SPI mode / LCD segment output
37
P4.3/SIMO1/S38
50
I/O
General-purpose digital I/O / slave in/master out of USART1/SPI mode / LCD segment output
38
P4.2/STE1/S39
51
I/O
General-purpose digital I/O / slave transmit enable—USART1/SPI mode / LCD segment output
39
COM0
52
O
COM0−3 are used for LCD backplanes.
P5.2/COM1
53
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.3/COM2
54
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.4/COM3
55
I/O
General-purpose digital I/O / common output, COM0−3 are used for LCD backplanes.
P5.5/R03
56
I/O
General-purpose digital I/O / Input port of lowest analog LCD level (V5)
P5.6/LCDREF/R13
57
I/O
General-purpose digital I/O / External reference voltage input for regulated LCD voltage / Input
port of third most positive analog LCD level (V4 or V3)
P5.7/R23
58
I/O
General-purpose digital I/O / Input port of second most positive analog LCD level (V2)
LCDCAP/R33
59
I
DVCC2
60
Digital supply voltage, positive terminal.
DVSS2
61
Digital supply voltage, negative terminal.
P4.1/URXD1
62
I/O
General-purpose digital I/O / receive data in—USART1/UART mode
P4.0/UTXD1
63
I/O
General-purpose digital I/O / transmit data out—USART1/UART mode
P3.7/TB6
64
I/O
General-purpose digital I/O / Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6
output
P3.6/TB5
65
I/O
General-purpose digital I/O / Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5
output
P3.5/TB4
66
I/O
General-purpose digital I/O / Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4
output
6
LCD Capacitor connection / Input/output port of most positive analog LCD level (V1)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
TERMINAL
NAME
NO.
I/O
DESCRIPTION
P3.4/TB3
67
I/O
General-purpose digital I/O / Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output
P3.3/UCB0CLK
68
I/O
General-purpose digital I/O / external clock input—USCI_B0/UART or SPI mode, clock
output—USCI_B0/SPI mode
P3.2/UCB0SOMI/
UCB0SCL
69
I/O
General-purpose digital I/O / slave out/master in of USCI_B0/SPI mode /I2C clock USCI_B0/I2C
mode
P3.1/UCB0SIMO/
UCB0SDA
70
I/O
General-purpose digital I/O / slave in/master out of USCI_B0/SPI mode, I2C data − USCI_B0/I2C
mode
P3.0/UCB0STE
71
I/O
General-purpose digital I/O / slave transmit enable—USCI_B0/SPI mode
P2.7/ADC12CLK/
DMAE0
72
I/O
General-purpose digital I/O / conversion clock—12-bit ADC / DMA Channel 0 external trigger
P2.6/CAOUT
73
I/O
General-purpose digital I/O / Comparator_A output
P2.5/UCA0RXD
74
I/O
General-purpose digital I/O / receive data in—USCI_A0/UART or IrDA mode
P2.4/UCA0TXD
75
I/O
General-purpose digital I/O / transmit data out—USCI_A0/UART or IrDA mode
P2.3/TB2
76
I/O
General-purpose digital I/O / Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
P2.2/TB1
77
I/O
General-purpose digital I/O / Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
P2.1/TB0
78
I/O
General-purpose digital I/O / Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
P2.0/TA2
79
I/O
General-purpose digital I/O / Timer_A Capture: CCI2A input, compare: Out2 output
P1.7/CA1
80
I/O
General-purpose digital I/O / Comparator_A input
P1.6/CA0
81
I/O
General-purpose digital I/O / Comparator_A input
P1.5/TACLK/ACLK
82
I/O
General-purpose digital I/O / Timer_A, clock signal TACLK input / ACLK output (divided by 1, 2, 4,
or 8)
P1.4/TBCLK/SMCLK
83
I/O
General-purpose digital I/O / input clock TBCLK—Timer_B7 / submain system clock SMCLK output
P1.3/TBOUTH/SVSOUT
84
I/O
General-purpose digital I/O / switch all PWM digital output ports to high impedance—Timer_B7 TB0
to TB6 / SVS: output of SVS comparator
P1.2/TA1
85
I/O
General-purpose digital I/O / Timer_A, Capture: CCI1A input, compare: Out1 output
P1.1/TA0/MCLK
86
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0B input / MCLK output.
Note: TA0 is only an input on this pin / BSL receive
P1.0/TA0
87
I/O
General-purpose digital I/O / Timer_A. Capture: CCI0A input, compare: Out0 output / BSL transmit
XT2OUT
88
O
Output terminal of crystal oscillator XT2
XT2IN
89
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
90
I/O
TDI/TCLK
91
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
92
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
93
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
94
I
Reset input or nonmaskable interrupt input port
P6.0/A0/OA0I0
95
I/O
General-purpose digital I/O / analog input a0 − 12-bit ADC / OA0 input multiplexer on +terminal and
− terminal
P6.1/A1/OA0O
96
I/O
General-purpose digital I/O / analog input a1 − 12-bit ADC / OA0 output
P6.2/A2/OA0I1
97
I/O
General-purpose digital I/O / analog input a2 − 12-bit ADC / OA0 input multiplexer on + terminal and
− terminal
AVSS
98
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, FLL+, comparator_A,
port 1
DVSS1
99
Digital supply voltage, negative terminal.
AVCC
100
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, FLL+, comparator_A,
port 1; must not power up prior to DVCC1/DVCC2.
PRODUCT PREVIEW
MSP430FG461x Terminal Functions (Continued)
Test data output port. TDO/TDI data output or programming data input terminal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLAS508 − APRIL 2006
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
PRODUCT PREVIEW
Stack Pointer
SP/R1
Constant Generator
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
The MSP430FG461x device family utilizes the
MSP430X CPU and is completely backwards
compatible with the MSP430 CPU. For a complete
description of the MSP430X CPU, refer to the
MSP430x4xx Family User’s Guide.
instruction set
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the
expanded address range. Each instruction can
operate on word and byte data. Table 1 shows
examples of the three types of instruction formats;
the address modes are listed in Table 2.
POST OFFICE BOX 655303
PC/R0
Status Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
8
Program Counter
• DALLAS, TEXAS 75265
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
SLAS508 − APRIL 2006
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 −−−> R5
Single operands, destination only
e.g. CALL
PC −−>(TOS), R8−−> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
SYNTAX
EXAMPLE
Register
F F
MOV Rs,Rd
MOV R10,R11
OPERATION
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
M(EDE) —> M(TONI)
Absolute
F F
MOV & MEM, & TCDAT
M(MEM) —> M(TCDAT)
R10
—> R11
M(2+R5)—> M(6+R6)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) —> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) —> R11
R10 + 2—> R10
F
MOV #X,TONI
MOV #45,TONI
#45
—> M(TONI)
D = destination
PRODUCT PREVIEW
Immediate
NOTE: S = source
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
SLAS508 − APRIL 2006
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode AM;
−
All clocks are active
D Low-power mode 0 (LPM0);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
FLL+ Loop control remains active
D Low-power mode 1 (LPM1);
PRODUCT PREVIEW
−
CPU is disabled
FLL+ Loop control is disabled
ACLK and SMCLK remain active. MCLK is disabled
D Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and FLL+ loop control and DCOCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4);
−
10
CPU is disabled
ACLK is disabled
MCLK, FLL+ loop control, and DCOCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
interrupt vector addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh − 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 3. Interrupt Sources, Flags, and Vectors of MSP430FG461x Configurations
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
31, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1 and 3)
(Non)maskable
(Non)maskable
(Non)maskable
0FFFCh
30
Timer_B7
TBCCR0 CCIFG0 (see Note 2)
Maskable
0FFFAh
29
Timer_B7
TBCCR1 CCIFG1 ... TBCCR6 CCIFG6,
TBIFG (see Notes 1 and 2)
Maskable
0FFF8h
28
Comparator_A
CAIFG
Maskable
0FFF6h
27
Watchdog Timer+
WDTIFG
Maskable
0FFF4h
26
USCI_A0/USCI_B0 Receive
UCA0RXIFG, UCB0RXIFG (see Notes 1)
Maskable
0FFF2h
25
USCI_A0/USCI_B0 Transmit
UCA0TXIFG, UCB0TXIFG (see Notes 1)
Maskable
0FFF0h
24
ADC12
ADC12IFG (see Notes 1 and 2)
Maskable
0FFEEh
23
Timer_A3
TACCR0 CCIFG0 (see Note 2)
Maskable
0FFECh
22
Timer_A3
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Maskable
0FFEAh
21
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
Maskable
0FFE8h
20
USART1 receive
URXIFG1
Maskable
0FFE6h
19
USART1 transmit
UTXIFG1
Maskable
0FFE4h
18
I/O Port P2 (Eight Flags)
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
Maskable
0FFE2h
17
Basic Timer1/RTC
BTIFG
Maskable
0FFE0h
16
DMA
DMA0IFG, DMA1IFG, DMA2IFG (see Notes 1
and 2)
Maskable
0FFDEh
15
DAC12
DAC12.0IFG, DAC12.1IFG (see Notes 1 and 2)
Maskable
0FFDCh
14
0FFDAh
13
Reserved
Reserved (see Note 4)
PRODUCT PREVIEW
INTERRUPT SOURCE
...
...
0FFC0h
0, lowest
NOTES: 1.
2.
3.
.
Multiple source flags
Interrupt flags are located in the module.
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h−01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot
disable it.
4. The interrupt vectors at addresses 0FFDAh to 0FFC0h are not used in this device and can be used for regular program code if
necessary.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
SLAS508 − APRIL 2006
special function registers
The MSP430 special function registers(SFR) are located in the lowest address space, and are organized as
byte mode registers. SFRs should be accessed with byte instructions.
interrupt enable 1 and 2
7
Address
6
0h
5
4
ACCVIE
NMIIE
rw–0
1
OFIE
rw–0
rw–0
OFIE
Oscillator-fault-interrupt enable
NMIIE
Nonmaskable-interrupt enable
ACCVIE
Flash access violation interrupt enable
7
BTIE
rw–0
6
5
4
3
2
1
UTXIE1
URXIE1
UCB0TXIE
UCB0RXIE
UCA0TXIE
rw–0
rw–0
rw–0
UCA0RXIE USCI_A0 receive-interrupt enable
UCA0TXIE
USCI_A0 transmit-interrupt enable
UCB0RXIE USCI_B0 receive-interrupt enable
UCB0TXIE
USCI_B0 transmit-interrupt enable
URXIE1
USART1 UART and SPI receive-interrupt enable
UTXIE1
USART1 UART and SPI transmit-interrupt enable
BTIE
Basic timer interrupt enable
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
rw–0
rw–0
0
WDTIE
rw–0
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
01h
12
2
WDTIE
Address
PRODUCT PREVIEW
3
0
UCA0RXIE
rw–0
SLAS508 − APRIL 2006
interrupt flag register 1 and 2
6
5
02h
4
3
2
NMIIFG
1
0
OFIFG
rw–0
rw–1
WDTIFG
rw–(0)
WDTIFG:
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
OFIFG:
Flag set on oscillator fault
NMIIFG:
Set via RST/NMI pin
7
Address
03h
6
BTIFG
5
4
UTXIFG1
URXIFG1
rw–1
rw–0
3
2
1
UCB0TXIFG
UCB0RXIFG UCA0TXIFG
rw–0
rw–0
rw–0
UCA0RXIFG
USCI_A0 receive-interrupt flag
UCA0TXIFG
USCI_A0 transmit-interrupt flag
UCB0RXIFG
USCI_B0 receive-interrupt flag
UCB0TXIFG
USCI_B0 transmit-interrupt flag
URXIFG0:
USART1: UART and SPI receive flag
UTXIFG0:
USART1: UART and SPI transmit flag
BTIFG:
Basic timer flag
rw–0
0
UCA0RXIFG
rw–0
PRODUCT PREVIEW
7
Address
module enable registers 1 and 2
Address
7
6
5
4
3
2
1
0
7
6
5
UTXE1
4
URXE1
USPIE1
3
2
1
0
04h
Address
05h
rw–0
rw–0
URXE1:
USART1: UART mode receive enable
UTXE1:
USART1: UART mode transmit enable
USPIE1:
USART1: SPI mode transmit and receive enable
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
SLAS508 − APRIL 2006
memory organization
MSP430FG4616
MSP430FG4617
MSP430FG4618
MSP430FG4619
Size
Flash
Flash
92KB
0FFFFh − 0FFC0h
018FFFh − 002100h
92KB
0FFFFh − 0FFC0h
019FFFh − 003100h
116KB
0FFFFh − 0FFC0h
01FFFFh − 003100h
120KB
0FFFFh − 0FFC0h
01FFFFh − 002100h
Size
4KB
020FFh − 01100h
8KB
030FFh − 01100h
8KB
030FFh − 01100h
4KB
020FFh − 01100h
Extended
Size
2KB
020FFh − 01900h
6KB
030FFh − 01900h
6KB
030FFh − 01900h
2KB
020FFh − 01900h
Mirrored
Size
2KB
018FFh − 01100h
2KB
018FFh − 01100h
2KB
018FFh − 01100h
2KB
018FFh − 01100h
Information memory
Size
Flash
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Boot memory
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
2KB
09FFh − 0200h
2KB
09FFh − 0200h
2KB
09FFh − 0200h
2KB
09FFh − 0200h
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
Memory
Main: interrupt vector
Main: code memory
RAM (Total)
PRODUCT PREVIEW
RAM
(mirrored at
018FFh − 01100h)
Peripherals
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. A bootstrap loader
security key is provided at address 0FFBEh to disable the BSL completely or to disable the erasure of the flash
if an invalid password is supplied. For complete description of the features of the BSL and its implementation,
see the Application report Features of the MSP430 Bootstrap Loader, Literature Number SLAA089.
BSLKEY
Description
00000h
Erasure of flash disabled if an invalid password is supplied
0AA55h
BSL disabled
any other value
BSL enabled
BSL Function
PZ Package Pins
Data Transmit
87 − P1.0
Data Receive
86 − P1.1
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PRODUCT PREVIEW
flash memory
SLAS508 − APRIL 2006
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x4xx Family User’s Guide.
DMA controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to
or from a peripheral.
PRODUCT PREVIEW
oscillator and system clock
The clock system in the MSP430FG461x family of devices is supported by the FLL+ module that includes
support for a 32768 Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO) and a high
frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of both low system
cost and low-power consumption. The FLL+ features digital frequency locked loop (FLL) hardware which in
conjunction with a digital modulator stabilizes the DCO frequency to a programmable multiple of the watch
crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The
FLL+ module provides the following clock signals:
D
D
D
D
Auxiliary clock (ACLK), sourced from a 32768 Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8.
brownout, supply voltage supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during power-on
and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may not
have ramped to VCC(min) at that time. The user must insure the default FLL+ settings are not changed until VCC
reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC reaches VCC(min).
digital I/O
There are ten 8-bit I/O ports implemented—ports P1 through P10:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Ports P7/P8 and P9/P10 can be accessed word−wise as ports PA and PB respectively.
Basic Timer1 and Real−Time Clock
The Basic Timer1 has two independent 8-bit timers which can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated Real−Time
Clock (RTC). An internal calendar compensates for months with less than 31 days and includes leap year
correction.
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
LCD_A drive with regulated charge pump
The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump.
Furthermore it is possible to control the level of the LCD voltage and thus contrast by software.
WDT+ watchdog timer
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
The universal serial communication interface (USCI) modules are used for serial data communication. The
USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous
communication protocols like UART, enhanced UART with automatic baudrate detection, and IrDA.
The USCI_A0 module provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
The USCI_B0 module provides support for SPI (3 or 4 pin) and I2C.
USART1
The hardware universal synchronous/asynchronous receive transmit (USART) peripheral module is used for
serial data communication. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART
communication protocols, using double-buffered transmit and receive channels.
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16 16,
16 8, 8 16, and 8 8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
PRODUCT PREVIEW
USCI
SLAS508 − APRIL 2006
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input Pin Number
PZ
Device Input
Signal
Module Input
Name
82- P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
82 - P1.5
TACLK
INCLK
87 - P1.0
TA0
CCI0A
TA0
CCI0B
DVSS
DVCC
GND
PRODUCT PREVIEW
86 - P1.1
85 - P1.2
79 - P2.0
18
Module
Block
Module Output
Signal
Timer
NA
Output Pin Number
PZ
87 - P1.0
CCR0
TA0
TA1
VCC
CCI1A
85 - P1.2
CAOUT (internal)
CCI1B
ADC12 (internal)
DVSS
DVCC
GND
TA2
VCC
CCI2A
ACLK (internal)
CCI2B
DVSS
DVCC
GND
CCR1
79 - P2.0
CCR2
VCC
POST OFFICE BOX 655303
TA1
• DALLAS, TEXAS 75265
TA2
SLAS508 − APRIL 2006
timer_B7
Timer_B7 is a 16-bit timer/counter with seven capture/compare registers. Timer_B7 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B7 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B7 Signal Connections
PZ
Device Input
Signal
Module Input
Name
83 - P1.4
TBCLK
TBCLK
ACLK
ACLK
SMCLK
SMCLK
83 - P1.4
TBCLK
INCLK
78 - P2.1
TB0
CCI0A
TB0
CCI0B
DVSS
DVCC
GND
78 - P2.1
77 - P2.2
TB1
VCC
CCI1A
77 - P2.2
TB1
CCI1B
DVSS
DVCC
GND
76 - P2.3
TB2
VCC
CCI2A
76 - P2.3
TB2
CCI2B
DVSS
DVCC
GND
67 - P3.4
TB3
VCC
CCI3A
67 - P3.4
TB3
CCI3B
DVSS
DVCC
GND
66 - P3.5
TB4
VCC
CCI4A
66 - P3.5
TB4
CCI4B
DVSS
DVCC
GND
65 - P3.6
65 - P3.6
64 - P3.7
TB5
VCC
CCI5A
TB5
CCI5B
DVSS
DVCC
GND
TB6
VCC
CCI6A
ACLK (internal)
CCI6B
DVSS
DVCC
GND
Module
Block
Module Output
Signal
Timer
NA
Output Pin Number
PZ
78 - P2.1
ADC12 (internal)
CCR0
CCR1
TB0
77 - P2.2
ADC12 (internal)
PRODUCT PREVIEW
Input Pin Number
TB1
76 - P2.3
CCR2
TB2
67 - P3.4
CCR3
TB3
66 - P3.5
CCR4
TB4
65 - P3.6
CCR5
TB5
64 - P3.7
CCR6
TB6
VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
SLAS508 − APRIL 2006
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit SAR
core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored without
any CPU intervention.
DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit mode,
and may be used in conjunction with the DMA controller. When multiple DAC12 modules are present, they may
be grouped together for synchronous operation.
OA
PRODUCT PREVIEW
The MSP430FG461x has three configurable low-current general-purpose operational amplifiers. Each OA
input and output terminal is software-selectable and offer a flexible choice of connections for various
applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital
conversion.
OA Signal Connections
Input Pin
Number
PZ
95 - P6.0
97 - P6.2
3 - P6.4
13 - P5.0
20
Device
Output
Signal
Output Pin
Number
OA0I0
OA0O
96 - P6.1
OA0O
ADC12 (internal)
Device Input
Signal
Module Input
Name
OA0I0
Module
Block
Module
Output
Signal
PZ
OA0I1
OA0I1
DAC12_0OUT
(internal)
DAC12_0OUT
DAC12_1OUT
(internal)
DAC12_1OUT
OA1I0
OA1I0
OA1O
2 - P6.3
OA1O
13- P5.0
OA1O
ADC12 (internal)
OA0
OA0OUT
OA1I1
OA1I1
DAC12_0OUT
(internal)
DAC12_0OUT
DAC12_1OUT
(internal)
DAC12_1OUT
5 - P6.6
OA2I0
OA2I0
OA2O
4 - P6.5
14- P10.7
OA2I1
OA2I1
OA2O
14- P10.7
DAC12_0OUT
(internal)
DAC12_0OUT
OA2O
ADC12 (internal)
DAC12_1OUT
(internal)
DAC12_1OUT
POST OFFICE BOX 655303
OA1
OA2
OA1OUT
OA2OUT
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
peripheral file map
Watchdog+
Watchdog timer control
WDTCTL
0120h
Timer_B7
Capture/compare register 6
TBCCR6
019Eh
Capture/compare register 5
TBCCR5
019Ch
Capture/compare register 4
TBCCR4
019Ah
Capture/compare register 3
TBCCR3
0198h
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 0
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 6
TBCCTL6
018Eh
Capture/compare control 5
TBCCTL5
018Ch
Capture/compare control 4
TBCCTL4
018Ah
Capture/compare control 3
TBCCTL3
0188h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Sum extend
SUMEXT
013Eh
Result high word
RESHI
013Ch
Result low word
RESLO
013Ah
Second operand
OP2
0138h
Multiply signed + accumulate/operand1
MACS
0136h
Multiply + accumulate/operand1
MAC
0134h
Multiply signed/operand1
MPYS
0132h
Multiply unsigned/operand1
MPY
0130h
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
Timer_A3
Hardware
Multiplier
Flash
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PRODUCT PREVIEW
PERIPHERALS WITH WORD ACCESS
21
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH WORD ACCESS (CONTINUED)
DMA
DMA Channel 0
DMA Channel 1
PRODUCT PREVIEW
DMA Channel 2
22
DMA module control 0
DMACTL0
0122h
DMA module control 1
DMACTL1
0124h
DMA interrupt vector
DMAIV
0126h
DMA channel 0 control
DMA0CTL
01D0h
DMA channel 0 source address
DMA0SA
01D2h
DMA channel 0 destination address
DMA0DA
01D6h
DMA channel 0 transfer size
DMA0SZ
01DAh
DMA channel 1 control
DMA1CTL
01DCh
DMA channel 1 source address
DMA1SA
01DEh
DMA channel 1 destination address
DMA1DA
01E2h
DMA channel 1 transfer size
DMA1SZ
01E6h
DMA channel 2 control
DMA2CTL
01E8h
DMA channel 2 source address
DMA2SA
01EAh
DMA channel 2 destination address
DMA2DA
01EEh
DMA channel 2 transfer size
DMA2SZ
01F2h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
peripheral file map (continued)
ADC12
Conversion memory 15
ADC12MEM15
015Eh
See also Peripherals
with Byte Access
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Inerrupt-enable register
ADC12IE
01A6h
Inerrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
DAC12_1 data
DAC12_1DAT
01CAh
DAC12_1 control
DAC12_1CTL
01C2h
DAC12_0 data
DAC12_0DAT
01C8h
DAC12_0 control
DAC12_0CTL
01C0h
Port PA selection
PASEL
03Eh
Port PA direction
PADIR
03Ch
Port PA output
PAOUT
03Ah
Port PA input
PAIN
038h
Port PB selection
PBSEL
00Eh
Port PB direction
PBDIR
00Ch
Port PB output
PBOUT
00Ah
Port PB input
PBIN
008h
DAC12
Port PA
Port PB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PRODUCT PREVIEW
PERIPHERALS WITH WORD ACCESS (CONTINUED)
23
SLAS508 − APRIL 2006
peripheral file map (continued)
PRODUCT PREVIEW
PERIPHERALS WITH BYTE ACCESS
OA2
Operational Amplifier 2 control register 1
Operational Amplifier 2 control register 0
OA2CTL1
OA2CTL0
0C5h
0C4h
OA1
Operational Amplifier 1 control register 1
Operational Amplifier 1 control register 0
OA1CTL1
OA1CTL0
0C3h
0C2h
OA0
Operational Amplifier 0 control register 1
Operational Amplifier 0 control register 0
OA0CTL1
OA0CTL0
0C1h
0C0h
LCD_A
LCD Voltage Control 1
LCD Voltage Control 0
LCD Voltage Port Control 1
LCD Voltage Port Control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode
LCDAVCTL1
LCDAVCTL0
LCDAPCTL1
LCDAPCTL0
LCDM20
:
LCDM16
LCDM15
:
LCDM1
LCDCTL
0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h
ADC12
ADC memory-control register 15
(Memory control
ADC memory-control register 14
registers require byte
ADC memory-control register 13
access)
ADC memory-control register 12
ADC12MCTL15
08Fh
ADC12MCTL14
08Eh
ADC12MCTL13
08Dh
ADC12MCTL12
08Ch
ADC memory-control register 11
ADC12MCTL11
08Bh
ADC memory-control register 10
ADC12MCTL10
08Ah
ADC memory-control register 9
ADC12MCTL9
089h
ADC memory-control register 8
ADC12MCTL8
088h
ADC memory-control register 7
ADC12MCTL7
087h
ADC memory-control register 6
ADC12MCTL6
086h
ADC memory-control register 5
ADC12MCTL5
085h
ADC memory-control register 4
ADC12MCTL4
084h
ADC memory-control register 3
ADC12MCTL3
083h
ADC memory-control register 2
ADC12MCTL2
082h
ADC memory-control register 1
ADC12MCTL1
081h
ADC memory-control register 0
ADC12MCTL0
080h
Transmit buffer
U1TXBUF
07Fh
Receive buffer
U1RXBUF
07Eh
Baud rate
U1BR1
07Dh
Baud rate
U1BR0
07Ch
Modulation control
U1MCTL
07Bh
Receive control
U1RCTL
07Ah
Transmit control
U1TCTL
079h
USART control
U1CTL
078h
USART1
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
peripheral file map (continued)
USCI I2C Slave Address
UCBSA
011Ah
USCI I2C Own Address
UCBOA
0118h
USCI Synchronous Transmit Buffer
UCBTXBUF
06Fh
USCI Synchronous Receive Buffer
UCBRXBUF
06Eh
USCI Synchronous Status
UCBSTAT
06Dh
USCI Synchronous Bit Rate 1
UCBBR1
06Bh
USCI Synchronous Bit Rate 0
UCBBR0
06Ah
USCI Synchronous Control 1
UCBCTL1
069h
USCI Synchronous Control 0
UCBCTL0
068h
USCI Transmit Buffer
UCATXBUF
067h
USCI Receive Buffer
UCARXBUF
066h
USCI Status
UCASTAT
065h
USCI Modulation Control
UCAMCTL
064h
USCI Baud Rate 1
UCABR1
063h
USCI Baud Rate 0
UCABR0
062h
USCI Control 1
UCACTL1
061h
USCI Control 0
UCACTL0
060h
USCI IrDA Receive Control
UCAIRRCTL
05Fh
USCI IrDA Transmit Control
UCAIRTCTL
05Eh
USCI LIN Control
UCAABCTL
05Dh
Comparator_A port disable
CAPD
05Bh
Comparator_A control 2
CACTL2
05Ah
Comparator_A control 1
CACTL1
059h
BrownOUT, SVS
SVS control register (Reset by brownout signal)
SVSCTL
056h
FLL+Clock
FLL+ Control 1
FLL_CTL1
054h
FLL+ Control 0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
Real Time Clock Year High Byte
RTCYEARH
04Fh
Real Time Clock Year Low Byte
RTCYEARL
04Eh
Real Time Clock Month
RTCMON
04Dh
Real Time Clock Day of Month
RTCDAY
04Ch
Basic Timer1 Counter 2
BTCNT2
047h
Basic Timer1 Counter 1
BTCNT1
046h
Real Time Counter 4
(Real Time Clock Day of Week)
RTCNT4
(RTCDOW)
045h
Real Time Counter 3
(Real Time Clock Hour)
RTCNT3
(RTCHOUR)
044h
Real Time Counter 2
(Real Time Clock Minute)
RTCNT2
(RTCMIN)
043h
Real Time Counter 1
(Real Time Clock Second)
RTCNT1
(RTCSEC)
042h
Real Time Clock Control
RTCCTL
041h
Basic Timer1 Control
BTCTL
040h
Comparator_A
RTC (Basic Timer 1)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PRODUCT PREVIEW
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
USCI
25
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
Port P10
Port P9
Port P8
PRODUCT PREVIEW
Port P7
Port P6
Port P5
Port P4
Port P3
Port P2
Port P1
26
Port P10 selection
P10SEL
00Fh
Port P10 direction
P10DIR
00Dh
Port P10 output
P10OUT
00Bh
Port P10 input
P10IN
009h
Port P9 selection
P9SEL
00Eh
Port P9 direction
P9DIR
00Ch
Port P9 output
P9OUT
00Ah
Port P9 input
P9IN
008h
Port P8 selection
P8SEL
03Fh
Port P8 direction
P8DIR
03Dh
Port P8 output
P8OUT
03Bh
Port P8 input
P8IN
039h
Port P7 selection
P7SEL
03Eh
Port P7 direction
P7DIR
03Ch
Port P7 output
P7OUT
03Ah
Port P7 input
P7IN
038h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
peripheral file map (continued)
PERIPHERALS WITH BYTE ACCESS (CONTINUED)
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
PRODUCT PREVIEW
Special functions
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
SLAS508 − APRIL 2006
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, Tstg: (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
(programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied
to the TDI/TCLK pin when blowing the JTAG fuse.
recommended operating conditions
PRODUCT PREVIEW
MIN
NOM
MAX
UNITS
Supply voltage during program execution,
VCC (AVCC = DVCC1/2 = VCC)
1.8
3.6
V
Supply voltage during flash memory programming,
VCC (AVCC = DVCC1/2 = VCC)
2.7
3.6
V
2
3.6
V
Supply voltage during program execution,
SVS enabled and PORON = 1 (see Note 1),
VCC (AVCC = DVCC1/2 = VCC)
Supply voltage, VSS (AVSS = DVSS1/2 = VSS)
Operating free-air temperature range, TA
LFXT1 crystal frequency, f(LFXT1)
(see Note 2)
LF selected,
XTS_FLL=0
Watch crystal
XT1 selected,
XTS_FLL=1
Ceramic resonator
XT1 selected,
XTS_FLL=1
Crystal
Ceramic resonator
XT2 crystal frequency, f(XT2)
Crystal
Processor frequency (signal MCLK), f(System)
VCC = 1.8 V
VCC = 2.0 V
0
0
V
−40
85
°C
32.768
kHz
450
8000
kHz
1000
8000
kHz
450
8000
1000
8000
DC
3.0
DC
4.6
kHz
MHz
VCC = 3.6 V
DC
8.0
MHz
NOTES: 1. The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
fSystem (MHz)
8.0 MHz
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
Supply voltage range,
MSP430FG461x, during
program execution
4.6 MHz
3.0 MHz
1.8
2.0
2.7
3
Supply Voltage − V
Supply voltage range, MSP430FG461x,
during flash memory programming
3.6
Figure 1. Frequency vs Supply Voltage, typical characteristic
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
supply current into AVCC + DVCC excluding external current
TEST CONDITIONS
TA = −40°C to 85°C
I(LPM0)
Low-power mode, (LPM0)
(see Note 1 and Note 4)
TA = −40°C to 85°C
I(LPM2)
Low-power mode, (LPM2),
f(MCLK) = f (SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2 and
Note 4)
TA = −40°C to 85°C
I(AM)
I(LPM3)
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
Basic Timer1 enabled, ACLK selected
LCD_A enabled, LCDCPEN = 0;
(static mode; fLCD = f(ACLK) /32)
(see Note 2 and Note 3 and Note 4)
TA = −40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 60°C
TA = 85°C
I(LPM3)
Low-power mode, (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32,768 Hz, SCG0 = 1
Basic Timer1 enabled, ACLK selected
LCD_A enabled, LCDCPEN = 0;
(4−mux mode; fLCD = f(ACLK) /32)
(see Note 2 and Note 3 and Note 4)
TA = −40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = −40°C
TA = 25°C
I(LPM4)
Low-power mode, (LPM4)
f(MCLK) = 0 MHz, f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1
(see Note 2 and Note 4)
TA = 60°C
TA = 85°C
TA = −40°C
TA = 25°C
TA = 60°C
TA = 85°C
NOTES: 1.
2.
3.
4.
MIN
NOM
MAX
VCC = 2.2 V
350
450
VCC = 3 V
550
700
UNIT
A
µA
VCC = 2.2 V
VCC = 3 V
55
70
85
110
VCC = 2.2 V
13
22
VCC = 3 V
18
30
1.0
2.0
1.1
2.0
2.0
5.0
7.0
15.0
1.8
2.8
1.6
2.7
2.5
7.0
8.5
21.0
2.5
3.5
2.5
3.5
3.0
6.0
8.0
16.0
2.9
4.0
2.9
4.0
4.0
8.0
10.0
22.0
0.1
0.5
0.3
0.7
1.7
5.0
7.0
15.0
0.1
0.8
0.4
0.9
2.0
7.0
8.0
21.0
µA
A
A
µA
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
µA
A
PRODUCT PREVIEW
PARAMETER
Active mode, (see Note 1 and Note 4)
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32,768 Hz
XTS=0, SELM=(0,1)
A
µA
µA
A
µA
A
µA
A
µA
A
Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The LPM3 currents are characterized with a Micro Crystal CC4V−T1A (9 pF) crystal and OSCCAPx = 1h.
Current for brownout included.
Current consumption of active mode versus system frequency, F-version:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage, F-version:
I(AM) = I(AM) [3 V] + 200 µA/V × (VCC – 3 V)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
SCHMITT-trigger inputs − Ports P1 to P10; RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT−
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ − VIT−)
MIN
TYP
MAX
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
1.1
1.55
1.5
1.98
0.4
0.9
VCC = 3 V
VCC = 2.2 V
0.9
1.3
0.3
1.1
VCC = 3 V
0.5
1
UNIT
V
V
V
inputs Px.x, TAx, TBx
PRODUCT PREVIEW
PARAMETER
TEST CONDITIONS
t(int)
External interrupt timing
t(cap)
Timer_A, Timer_B capture
timing
f(TAext)
f(TBext)
f(TAint)
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag, (see Note 1)
TA0, TA1, TA2
TB0, TB1, TB2, TB3, TB4, TB5, TB6
Timer_A, Timer_B clock
frequency externally applied
to pin
TACLK, TBCLK, INCLK: t(H) = t(L)
Timer_A, Timer_B clock
frequency
SMCLK or ACLK signal selected
VCC
2.2 V
MIN
TYP
MAX
UNIT
62
3V
50
2.2 V
62
3V
50
ns
ns
2.2 V
8
3V
10
2.2 V
8
MHz
MHz
f(TBint)
3V
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It may be set even with trigger signals
shorter than t(int).
leakage current − Ports P1 to P10 (see Note 1)
PARAMETER
Ilkg(Px.y)
Leakage
current
TEST CONDITIONS
Port Px
V(Px.y) (see Note 2)
(1 ≤ x ≤ 10, 0 ≤ y ≤ 7)
MIN
TYP
VCC = 2.2 V/3 V
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The port pin must be selected as input.
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
UNIT
±50
nA
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
outputs − Ports P1 to P10
PARAMETER
VOH
VOL
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOH(max) = −1.5 mA,
IOH(max) = −6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 2.2 V,
VCC = 2.2 V,
See Note 1
IOL(max) = 1.5 mA,
IOL(max) = 6 mA,
VCC = 3 V,
VCC = 3 V,
See Note 1
See Note 2
See Note 2
TYP
MAX
VCC−0.25
VCC−0.6
VCC
VCC
VCC−0.25
VCC−0.6
VCC
VCC
VSS
VSS
VSS+0.25
VSS+0.6
VSS
VSS
VSS+0.25
VSS+0.6
See Note 2
See Note 2
UNIT
V
V
NOTES: 1. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum
specified voltage drop.
2. The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum
specified voltage drop.
PARAMETER
f(Px.y)
(1 ≤ x ≤ 10, 0 ≤ y ≤ 7)
f(MCLK)
f(SMCLK)
P1.1/TA0/MCLK,
f(ACLK)
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK,
TEST CONDITIONS
MIN
MAX
UNIT
VCC = 2.2 V
VCC = 3 V
DC
10
MHz
DC
12
MHz
10
MHz
DC
12
MHz
40%
60%
CL = 20 pF,
IL = ±1.5 mA
CL = 20 pF
P1.5/TACLK/ACLK,
CL = 20 pF
VCC = 2.2 V / 3 V
t(Xdc)
Duty cycle of output frequency
VCC = 2.2 V
VCC = 3 V
f(ACLK) = f(LFXT1) = f(XT1)
f(ACLK) = f(LFXT1) = f(LF)
f(ACLK) = f(LFXT1)
30%
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(MCLK) = f(XT1)
40%
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V / 3 V
f(SMCLK) = f(XT2)
POST OFFICE BOX 655303
TYP
f(MCLK) = f(DCOCLK)
f(SMCLK) = f(DCOCLK)
• DALLAS, TEXAS 75265
PRODUCT PREVIEW
output frequency
70%
50%
50%−
15 ns
60%
50%
50%+
15 ns
40%
60%
50%−
15 ns
50%
50%+
15 ns
31
SLAS508 − APRIL 2006
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics − outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
I OL − Typical Low-Level Output Current − mA
I OL − Typical Low-Level Output Current − mA
TA = 25°C
VCC = 2.2 V
P2.0
20.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
0.5
1.0
3.0
3.5
0.0
I OH − Typical High-Level Output Current − mA
VCC = 2.2 V
P2.0
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
1.0
1.5
2.0
2.5
VCC = 3 V
P2.0
−10.0
−20.0
−30.0
−40.0
TA = 85°C
−50.0
0.0
VOH − High-Level Output Voltage − V
TA = 25°C
0.5
1.0
1.5
Figure 5
POST OFFICE BOX 655303
2.0
2.5
3.0
VOH − High-Level Output Voltage − V
Figure 4
32
2.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
0.5
2.0
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
−25.0
0.0
1.5
VOL − Low-Level Output Voltage − V
Figure 2
−20.0
TA = 25°C
40.0
VOL − Low-Level Output Voltage − V
I OH − Typical High-Level Output Current − mA
PRODUCT PREVIEW
25.0
• DALLAS, TEXAS 75265
3.5
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
wake-up LPM3
PARAMETER
TEST CONDITIONS
MIN
TYP
f = 1 MHz
td(LPM3)
f = 2 MHz
Delay time
MAX
UNIT
6
6
VCC = 2.2 V/3 V
f = 3 MHz
µs
6
RAM
PARAMETER
VRAMh
TEST CONDITIONS
CPU halted (see Note 1)
MIN
1.6
TYP
MAX
UNIT
V
PRODUCT PREVIEW
NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
LCD_A
PARAMETER
Supply Voltage Range (see Note
2)
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
ICC(LCD)
Supply Current (see Note 2 )
VLCD(typ)=3V; LCDCPEN = 1;
VLCDx= 1000; all segments on.
fLCD = fACLK/32
no LCD connected (see Note 4)
TA = 25°C
CLCD
Capacitor on LCDCAP (see Note
1 and Note 3)
Charge pump enabled
(LCDCPEN = 1; VLCDx > 0000)
VCC(LCD)
PRODUCT PREVIEW
TEST CONDITIONS
VCC
MIN
TYP
2.2
2.2 V
MAX
3.6
UNIT
V
µA
3
µF
4.7
fLCD
VLCD
LCD frequency
1.1
LCD voltage (see Note 3)
VLCDx = 0000
LCD voltage (see Note 3)
VLCDx = 0001
VCC
2.60
V
VLCD
VLCD
LCD voltage (see Note 3)
VLCDx = 0010
2.66
V
VLCD
VLCD
LCD voltage (see Note 3)
VLCDx = 0011
2.72
V
LCD voltage (see Note 3)
VLCDx = 0100
2.78
V
VLCD
VLCD
LCD voltage (see Note 3)
VLCDx = 0101
2.84
V
LCD voltage (see Note 3)
VLCDx = 0110
2.90
V
VLCD
VLCD
LCD voltage (see Note 3)
VLCDx = 0111
2.96
V
LCD voltage (see Note 3)
VLCDx = 1000
3.02
V
VLCD
VLCD
LCD voltage (see Note 3)
VLCDx = 1001
3.08
V
LCD voltage (see Note 3)
VLCDx = 1010
3.14
V
VLCD
VLCD
LCD voltage (see Note 3)
VLCDx = 1011
3.20
V
LCD voltage (see Note 3)
VLCDx = 1100
3.26
V
VLCD
VLCD
LCD voltage (see Note 3)
VLCDx = 1101
3.32
V
LCD voltage (see Note 3)
VLCDx = 1110
3.38
VLCD
LCD voltage (see Note 3)
VLCDx = 1111
3.44
RLCD
LCD Driver Output Impedance
VLCD=3V; CPEN = 1;
VLCDx = 1000, ILOAD = 10 µΑ
2.2 V
kHz
V
V
3.60
10
V
kΩ
NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.
2. Refer to the supply current specifications I(LPM3) for additional current specifications with the LCD_A module active.
3. Segments S0 through S3 must be disabled and cannot be used when the LCD charge pump feature is enabled. In addition, when
using segments S0 through S3 with an external LCD voltage supply, VLCD ≤ AVCC.
4. Connecting an actual display will increase the current consumption depending on the size of the LCD.
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
Comparator_A (see Note 1)
TEST CONDITIONS
I(CC)
CAON=1, CARSEL=0, CAREF=0
I(Refladder/RefDiode)
CAON=1, CARSEL=0, CAREF=1/2/3,
No load at P1.6/CA0 and
P1.7/CA1
V(Ref025)
Voltage @ 0.25 V
MAX
VCC = 2.2 V
VCC = 3 V
25
40
45
60
VCC = 2.2 V
30
50
VCC = 3 V
45
71
UNIT
µA
A
µA
A
PCA0=1, CARSEL=1, CAREF=1,
No load at P1.6/CA0 and P1.7/CA1
VCC = 2.2 V / 3 V
0.23
0.24
0.25
node
PCA0=1, CARSEL=1, CAREF=2,
No load at P1.6/CA0 and P1.7/CA1
VCC = 2.2V / 3 V
0.47
0.48
0.5
PCA0=1, CARSEL=1, CAREF=3,
No load at P1.6/CA0 and P1.7/CA1;
TA = 85°C
VCC = 2.2 V
390
480
540
VCC = 3 V
400
490
550
Common-mode input
voltage range
CAON=1
VCC = 2.2 V / 3 V
0
VCC−1
Offset voltage
See Note 2
VCC = 2.2 V / 3 V
−30
30
mV
Input hysteresis
CAON = 1
VCC = 2.2 V / 3 V
VCC = 2.2 V
0
0.7
1.4
mV
160
210
300
80
150
240
1.4
1.9
3.4
0.9
1.5
2.6
130
210
300
80
150
240
1.4
1.9
3.4
CC
V
V(Ref050)
V
CC
CC
V(RefVT)
Vp−VS
Vhys
TYP
node
CC
Voltage @ 0.5 V
VIC
MIN
TA = 25
25°C,
C,
Overdrive 10 mV, without filter: CAF = 0
t(response LH)
TA = 25
25°C
C
Overdrive 10 mV, with filter: CAF = 1
TA = 25
25°C
C
Overdrive 10 mV, without filter: CAF = 0
t(response HL)
25°C,
TA = 25
C,
Overdrive 10 mV, with filter: CAF = 1
mV
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
VCC = 3 V
VCC = 2.2 V
V
ns
µss
ns
µss
VCC = 3 V
0.9
1.5
2.6
NOTES: 1. The leakage current for the Comparator_A terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
35
PRODUCT PREVIEW
PARAMETER
SLAS508 − APRIL 2006
typical characteristics
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
650
650
PRODUCT PREVIEW
VCC = 2.2 V
600
VREF − Reference Voltage − mV
VREF − Reference Voltage − mV
VCC = 3 V
Typical
550
500
450
400
−45
−25
−5
15
35
55
75
600
Typical
550
500
450
400
−45
95
−25
TA − Free-Air Temperature − °C
−5
15
35
55
Figure 6. V(RefVT) vs Temperature
Figure 7. V(RefVT) vs Temperature
0 V VCC
0
1
CAF
CAON
Low-Pass Filter
V+
V−
+
_
0
0
1
1
To Internal
Modules
CAOUT
Set CAIFG
Flag
τ ≈ 2 µs
Figure 8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V−
400 mV
V+
t(response)
Figure 9. Overdrive Definition
36
75
TA − Free-Air Temperature − °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
95
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
POR/brownout reset (BOR) (see Note 1)
PARAMETER
TEST CONDITIONS
td(BOR)
VCC(start)
MIN
dVCC/dt ≤ 3 V/s (see Figure 10)
V(B_IT−)
Vhys(B_IT−)
MAX
UNIT
2000
µs
0.7 × V(B_IT−)
dVCC/dt ≤ 3 V/s (see Figure 10 through Figure 12)
dVCC/dt ≤ 3 V/s (see Figure 10)
Brownout
(see Note 2)
TYP
70
130
V
1.71
V
180
mV
Pulse length needed at RST/NMI pin to accepted reset internally,
2
µs
VCC = 2.2 V/3 V
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT−)
+ Vhys(B_IT−) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT−) + Vhys(B_IT−). The default
FLL+ settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency. See the MSP430x4xx Family User’s Guide for more information on the brownout/SVS circuit.
t(reset)
typical characteristics
PRODUCT PREVIEW
VCC
Vhys(B_IT−)
V(B_IT−)
VCC(start)
1
0
t d(BOR)
Figure 10. POR/Brownout Reset (BOR) vs Supply Voltage
VCC
3V
2
VCC(drop) − V
VCC = 3 V
Typical Conditions
t pw
1.5
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw − Pulse Width − µs
1 ns
tpw − Pulse Width − µs
Figure 11. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
SLAS508 − APRIL 2006
typical characteristics
VCC
2
VCC(drop) − V
1.5
t pw
3V
VCC = 3 V
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw − Pulse Width − µs
tpw − Pulse Width − µs
Figure 12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
PRODUCT PREVIEW
SVS (supply voltage supervisor/monitor) (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
t(SVSR)
dVCC/dt > 30 V/ms (see Figure 13)
dVCC/dt ≤ 30 V/ms
5
td(SVSon)
tsettle
SVSon, switch from VLD=0 to VLD ≠ 0, VCC = 3 V
VLD ≠ 0‡
20
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 13)
NOM
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 13)
VLD = 2 .. 14
Vhys(SVS_IT−)
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
VCC/dt ≤ 3 V/s (see Figure 13)
V(SVS_IT−)
VCC/dt ≤ 3 V/s (see Figure 13), external voltage applied
on A7
VLD = 15
70
120
V(SVS_IT−)
x 0.001
MAX
UNIT
150
µs
2000
µs
150
µs
12
µs
1.7
V
155
mV
V(SVS_IT−)
x 0.016
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.23
VLD = 3
2.05
2.2
2.35
VLD = 4
2.14
2.3
2.46
VLD = 5
2.24
2.4
2.58
VLD = 6
2.33
2.5
2.69
VLD = 7
2.46
2.65
2.84
VLD = 8
2.58
2.8
2.97
VLD = 9
2.69
2.9
3.10
VLD = 10
2.83
3.05
3.26
VLD = 11
2.94
3.2
VLD = 12
3.11
3.35
VLD = 13
3.24
VLD = 14
3.43
3.5
3.7†
3.39
3.58†
3.73†
VLD = 15
1.1
1.2
mV
V
3.96†
1.3
ICC(SVS)
VLD ≠ 0, VCC = 2.2 V/3 V
10
15
µA
(see Note 1)
† The recommended operating voltage range is limited to 3.6 V.
‡ tsettle is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD ≠ 0 to a different VLD value somewhere
between 2 and 15. The overdrive is assumed to be > 50 mV.
NOTE 1: The current consumption of the SVS module is not included in the ICC current consumption data.
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
typical characteristics
Software Sets VLD>0:
SVS is Active
VCC
V(SVS_IT−)
V(SVSstart)
Vhys(SVS_IT−)
Vhys(B_IT−)
V(B_IT−)
VCC(start)
BrownOut
Region
Brownout
Region
Brownout
1
0
td(BOR)
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT−)
0
td(SVSon)
Set POR
1
PRODUCT PREVIEW
SVSOut
1
td(SVSR)
undefined
0
Figure 13. SVS Reset (SVSR) vs Supply Voltage
VCC
3V
t pw
2
Rectangular Drop
VCC(drop)
VCC(drop) − V
1.5
Triangular Drop
1
1 ns
1 ns
0.5
VCC
t pw
3V
0
1
10
100
1000
tpw − Pulse Width − µs
VCC(drop)
tf = tr
tf
tr
t − Pulse Width − µs
Figure 14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
DCO
PARAMETER
PRODUCT PREVIEW
f(DCOCLK)
TEST CONDITIONS
VCC
2.2 V/3 V
MIN
TYP
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
2.2 V
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
TAP = 27
1.07
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
N(DCO)=01E0h, FN_8=FN_4=FN_3=FN_2=0, D = 2; DCOPLUS= 0
f(DCO2)
FN_8=FN_4=FN_3=FN_2=0 ; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=FN_3=FN_2=0; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=FN_3=0, FN_2=1; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=FN_4=0, FN_3= 1, FN_2=x; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=0, FN_4= 1, FN_3= FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=0, FN_4=1, FN_3= FN_2=x; DCOPLUS = 1, (see Note 1)
f(DCO2)
FN_8=1, FN_4=FN_3=FN_2=x; DCOPLUS = 1
f(DCO27)
FN_8=1,FN_4=FN_3=FN_2=x; DCOPLUS = 1, (see Note 1)
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n), (see Figure 16 for taps 21 to 27)
Dt
Temperature drift, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0
DV
Drift with VCC variation, N(DCO) = 01E0h, FN_8=FN_4=FN_3=FN_2=0
D = 2; DCOPLUS = 0
MAX
1
UNIT
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1.11
1.17
%/_C
%/V
NOTES: 1. Do not exceed the maximum system frequency.
f
f
f
(DCO)
f
(DCO3V)
(DCO)
(DCO205C)
1.0
1.0
0
1.8
2.4
3.0
3.6
VCC − V
−40
−20
0
20
40
60
Figure 15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
85
TA − °C
SLAS508 − APRIL 2006
Sn - Stepsize Ratio between DCO Taps
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
1.17
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Max
1.11
1.07
1.06
1
20
PRODUCT PREVIEW
Min
27
DCO Tap
Figure 16. DCO Tap Step Size
f(DCO)
Legend
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
29 to 25 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 17. Five Overlapping DCO Ranges Controlled by FN_x Bits
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
crystal oscillator, LFXT1 oscillator (see Notes 1 and 2)
PARAMETER
CXIN
CXOUT
Integrated input capacitance
(see Note 4)
Integrated output capacitance
(see Note 4)
TEST CONDITIONS
MIN
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
18
OSCCAPx = 0h, VCC = 2.2 V / 3 V
0
OSCCAPx = 1h, VCC = 2.2 V / 3 V
10
OSCCAPx = 2h, VCC = 2.2 V / 3 V
14
OSCCAPx = 3h, VCC = 2.2 V / 3 V
PRODUCT PREVIEW
VIL
VIH
Input levels at XIN
TYP
OSCCAPx = 0h, VCC = 2.2 V / 3 V
VCC = 2.2 V/3 V (see Note 3)
MAX
UNIT
pF
pF
18
VSS
0.8×VCC
0.2×VCC
VCC
V
NOTES: 1. The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is
(CXIN x CXOUT) / (CXIN + CXOUT). This is independent of XTS_FLL.
2. To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
− Keep as short of a trace as possible between the ’FG461x and the crystal.
− Design a good ground plane around the oscillator pins.
− Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
− Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
− Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
− If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
− Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
3. Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
4. External capacitance is recommended for precision real-time clock applications; OSCCAPx = 0h.
crystal oscillator, XT2 oscillator (see Note 1)
PARAMETER
CXT2IN
Integrated input capacitance
CXT2OUT
Integrated output capacitance
VIL
VIH
Input levels at XT2IN
TEST CONDITIONS
MIN
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
NOM
MAX
2
pF
2
VCC = 2.2 V/3 V (see Note 2)
VSS
0.8 × VCC
pF
0.2 × VCC
V
VCC
V
NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
42
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
USCI (UART Mode)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals Baudrate in MBaud)
tτ
UART receive deglitch time
(see Note 1)
TEST CONDITIONS
VCC
MIN
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ± 10%
TYP
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V /3.0 V
2.2 V
50
150
600
ns
3.0 V
50
100
600
ns
NOTES: 1. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
tVALID,MO
TEST CONDITIONS
VCC
MIN
SMCLK, ACLK
Duty Cycle = 50% ± 10%
SOMI input data hold time
UCLK edge to SIMO valid;
CL = 20 pF
SIMO output data valid time
TYP
MAX
UNIT
fSYSTEM
MHz
2.2 V
TBD
ns
3.0 V
TBD
ns
2.2 V
0
ns
3.0 V
0
ns
2.2 V
30
TBD
ns
3.0 V
30
TBD
ns
TYP
MAX
UNIT
USCI (SPI Slave Mode, see Figure 20 and Figure 21)
PARAMETER
TEST CONDITIONS
VCC
tSTE,LEAD
STE lead time
STE low to clock
2.2 V/3.0 V
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V/3.0 V
tSTE,ACC
STE access time
STE low to SOMI data out
tSTE,DIS
STE disable time
STE high to SOMI high impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time
CL = 20 pF
UCLK edge to SOMI valid;
CL = 20 pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
50
ns
10
ns
2.2 V/3.0 V
50
ns
2.2 V/3.0 V
50
ns
2.2 V
TBD
ns
3.0 V
TBD
ns
2.2 V
0
ns
3.0 V
0
ns
2.2 V
50
TBD
ns
3.0 V
50
TBD
ns
43
PRODUCT PREVIEW
USCI (SPI Master Mode, see Figure 18 and Figure 19)
SLAS508 − APRIL 2006
tSTE ,LEAD
tSTE ,LAG
STE
1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tSU ,MI
tHD,MI
SOMI
tACC
tVALID ,MO
tDIS
PRODUCT PREVIEW
SIMO
Figure 18. SPI Master Mode, CKPH = 0
tSTE ,LAG
tSTE ,LEAD
STE
1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tSU,MI
tHD,MI
SOMI
tACC
tVALID ,MO
SIMO
Figure 19. SPI Master Mode, CKPH = 1
44
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
tDIS
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
tSTE ,LEAD
tSTE ,LAG
STE
1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW /HIGH
tLOW /HIGH
tSU ,SI
tHD,SI
SIMO
tVALID ,SO
tDIS
PRODUCT PREVIEW
tACC
SOMI
Figure 20. SPI Slave Mode, CKPH = 0
tSTE ,LAG
tSTE ,LEAD
STE
1/f UCxCLK
CKPL=0
UCLK
CKPL=1
tLOW /HIGH
tLOW /HIGH
tSU ,SI
tHD,SI
SIMO
tACC
tVALID ,SO
tDIS
SOMI
Figure 21. SPI Slave Mode, CKPH = 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
USCI (I2C Mode, see Figure 22)
PRODUCT PREVIEW
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
2.2 V/3.0 V
0
2.2 V/3.0 V
4.0
us
2.2 V/3.0 V
0.6
us
2.2 V/3.0 V
4.7
us
2.2 V/3.0 V
0.6
us
tHD,STA
Hold time (repeated) START
fSCL ≤ 100kHz
fSCL > 100kHz
tSU,STA
Set−up time for a repeated START
fSCL ≤ 100kHz
fSCL > 100kHz
tHD,DAT
tSU,DAT
Data hold time
2.2 V/3.0 V
0
ns
Data set−up time
2.2 V/3.0 V
250
ns
tSU,STO
Set−up time for STOP
2.2 V/3.0 V
4.0
us
Pulse width of spikes suppressed by
input filter
2.2 V
50
150
600
ns
tSP
3.0 V
50
100
600
ns
tHD , STA
tSU , STA tHD , STA
tBUF
SDA
t
tHIGH
LOW
tSP
SCL
tSU ,DAT
tSU , STO
tHD ,DAT
Figure 22. I2C Mode Timing
USART1 (see Note 1)
PARAMETER
t(τ)
( )
USART1: deglitch time
TEST CONDITIONS
VCC = 2.2 V
VCC = 3 V
MIN
NOM
MAX
200
430
800
150
280
500
UNIT
ns
NOTES: 1. The signal applied to the USART1 receive signal/terminal (URXD1) should meet the timing requirements of t(τ) to ensure that the
URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD1 line.
46
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, power supply and input range conditions (see Note 1)
TEST CONDITIONS
MIN
AVCC
Analog supply voltage
AVCC and DVCC are connected together
AVSS and DVSS are connected together
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage
range (see Note 2)
All external Ax terminals. Analog inputs
selected in ADC12MCTLx register and P6Sel.x=1
V(AVSS) ≤ VAx ≤ V(AVCC)
IADC12
Operating supply current
into AVCC terminal
(see Note 3)
fADC12CLK = 5.0 MHz
ADC12ON = 1, REFON = 0
SHT0=0, SHT1=0, ADC12DIV=0
Operating supply current
into AVCC terminal
(see Note 4)
IREF+
CI
RI
NOTES: 1.
2.
3.
4.
Input capacitance
NOM
MAX
UNIT
2.2
3.6
V
0
VAVCC
V
VCC = 2.2 V
0.65
1.3
VCC = 3 V
0.8
1.6
VCC = 3 V
0.5
0.8
VCC = 2.2 V
0.5
0.8
VCC = 3 V
0.5
0.8
mA
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5.0 MHz
ADC12ON = 0,
REFON = 1, REF2_5V = 0
mA
mA
Only one terminal can be selected
at one time, Ax
VCC = 2.2 V
40
pF
VCC = 3 V
2000
Ω
The leakage current is defined in the leakage current table with Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR− for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
Input MUX ON resistance
0V ≤ VAx ≤ VAVCC
12-bit ADC, external reference (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
VeREF+
Positive external
reference voltage input
VeREF+ > VREF−/VeREF−
(see Note 2)
1.4
VAVCC
V
VREF− /VeREF−
Negative external
reference voltage input
VeREF+ > VREF−/VeREF−
(see Note 3)
0
1.2
V
(VeREF+ −
VREF−/VeREF−)
Differential external
reference voltage input
VeREF+ > VREF−/VeREF−
(see Note 4)
1.4
VAVCC
V
IVeREF+
IVREF−/VeREF−
Input leakage current
0V ≤VeREF+ ≤ VAVCC
±1
µA
Input leakage current
0V ≤ VeREF− ≤ VAVCC
±1
µA
VCC = 2.2 V/3 V
VCC = 2.2 V/3 V
NOTES: 1. The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also
the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
2. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
3. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
4. The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
PRODUCT PREVIEW
PARAMETER
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, built-in reference
PARAMETER
Positive built-in reference
voltage output
VREF+
AVCC(min)
AVCC minimum voltage,
Positive built-in reference
active
IVREF+
Load current out of VREF+
terminal
Load-current regulation
VREF+ terminal
PRODUCT PREVIEW
IL(VREF)+
TEST CONDITIONS
REF2_5V = 1 for 2.5 V
IVREF+max ≤ IVREF+≤ IVREF+min
VCC = 3 V
REF2_5V = 0 for 1.5 V
IVREF+max ≤ IVREF+≤ IVREF+min
VCC =
2.2 V/3 V
MIN
NOM
MAX
2.4
2.5
2.6
1.44
1.5
1.56
V
REF2_5V = 0, IVREF+max ≤ IVREF+≤ IVREF+min
2.2
REF2_5V = 1, IVREF+min ≥ IVREF+≥ −0.5mA
2.8
REF2_5V = 1, IVREF+min ≥ IVREF+≥ −1mA
V
2.9
VCC = 2.2 V
VCC = 3 V
IVREF+ = 500 µA +/− 100 µA
Analog input voltage ~0.75 V;
REF2_5V = 0
UNIT
0.01
−0.5
0.01
−1
mA
VCC = 2.2 V
±2
VCC = 3 V
±2
IVREF+ = 500 µA ± 100 µA
Analog input voltage ~1.25 V;
REF2_5V = 1
VCC = 3 V
±2
LSB
20
ns
IDL(VREF) +
Load current regulation
VREF+ terminal
IVREF+ =100 µA → 900 µA,
CVREF+=5 µF, ax ~0.5 x VREF+
Error of conversion result ≤ 1 LSB
VCC = 3 V
CVREF+
Capacitance at pin VREF+
(see Note 1)
REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
VCC =
2.2 V/3 V
TREF+
Temperature coefficient of
built-in reference
IVREF+ is a constant in the range of
0 mA ≤ IVREF+ ≤ 1 mA
VCC =
2.2 V/3 V
tREFON
Settle time of internal
reference voltage (see
Figure 23 and Note 2)
IVREF+ = 0.5 mA, CVREF+ = 10 µF,
VREF+ = 1.5 V, VAVCC = 2.2 V
5
LSB
µF
10
±100
ppm/°C
17
ms
NOTES: 1. The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses
two capacitors between pins VREF+ and AVSS and VREF−/VeREF− and AVSS: 10 µF tantalum and 100 nF ceramic.
2. The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 µF
tREFON ≈ .66 x CVREF+ [ms] with CVREF+ in µF
10 µF
1 µF
0
1 ms
10 ms
100 ms
tREFON
Figure 23. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
DVCC1/2
From
Power
Supply
+
−
10 µ F
DVSS1/2
100 nF
AVCC
+
−
10 µ F
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
100 nF
VREF+ or VeREF+
+
−
Apply
External
Reference
10 µ F
100 nF
VREF−/VeREF−
+
−
10 µ F
MSP430FG461x
AVSS
100 nF
From
Power
Supply
DVCC1/2
+
−
10 µ F
DVSS1/2
100 nF
AVCC
+
−
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
PRODUCT PREVIEW
Figure 24. Supply Voltage and Reference Voltage Design VREF−/VeREF− External Supply
10 µ F
100 nF
VREF+ or VeREF+
+
−
10 µ F
MSP430FG461x
AVSS
100 nF
Reference Is Internally
Switched to AVSS
VREF−/VeREF−
Figure 25. Supply Voltage and Reference Voltage Design VREF−/VeREF− = AVSS, Internally Connected
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, timing parameters
PARAMETER
TEST CONDITIONS
fADC12CLK
PRODUCT PREVIEW
fADC12OSC
Internal ADC12
oscillator
MIN
NOM
MAX
UNIT
For specified performance of
ADC12 linearity parameters
VCC =
2.2V/3 V
0.45
5
6.3
MHz
ADC12DIV=0,
fADC12CLK=fADC12OSC
VCC =
2.2 V/ 3 V
3.7
5
6.3
MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
VCC =
2.2 V/ 3 V
2.06
3.51
µs
tCONVERT
Conversion time
tADC12ON
Turn on settling time of
the ADC
(see Note 1)
tSample
Sampling time
RS = 400 Ω, RI = 1000 Ω,
CI = 30 pF, τ = [RS + RI] x CI
(see Note 2)
External fADC12CLK from ACLK, MCLK or SMCLK:
ADC12SSEL ≠ 0
13×ADC12DIV×
1/fADC12CLK
µs
100
VCC = 3 V
VCC =
2.2 V
ns
1220
ns
1400
NOTES: 1. The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
2. Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) x (RS + RI) x CI+ 800 ns where n = ADC resolution = 12, RS = external source resistance.
12-bit ADC, linearity parameters
PARAMETER
EI
Integral linearity error
ED
Differential linearity
error
EO
Offset error
EG
Gain error
ET
Total unadjusted
error
50
TEST CONDITIONS
1.4 V ≤ (VeREF+ − VREF−/VeREF−) min ≤ 1.6 V
1.6 V < (VeREF+ − VREF−/VeREF−) min ≤ [VAVCC]
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
(VeREF+ − VREF−/VeREF−)min ≤ (VeREF+ − VREF−/VeREF−),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MIN
NOM
MAX
±2
UNIT
VCC =
2.2 V/3 V
±1.7
LSB
VCC =
2.2 V/3 V
±1
LSB
VCC =
2.2 V/3 V
±2
±4
LSB
VCC =
2.2 V/3 V
±1.1
±2
LSB
VCC =
2.2 V/3 V
±2
±5
LSB
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit ADC, temperature sensor and built-in VMID
TEST CONDITIONS
VCC
2.2 V
MIN
NOM
MAX
40
120
60
160
ISENSOR
Operating supply current into
AVCC terminal (see Note 1)
REFON = 0, INCH = 0Ah,
ADC12ON=NA, TA = 25_C
VSENSOR
(see Note 2)
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V/
3V
986
ADC12ON = 1, INCH = 0Ah
2.2 V/
3V
3.55±3%
TCSENSOR
3V
mV/°C
Sample time required if
channel 10 is selected
(see Note 3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (see Note 4)
ADC12ON = 1, INCH = 0Bh,
1.1
1.1±0.04
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID is ~0.5 x VAVCC
2.2 V
VMID
3V
1.5
1.50±0.04
Sample time required if
channel 11 is selected
(see Note 5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
2.2 V
1400
tVMID(sample)
3V
1220
30
3V
30
µA
A
mV
tSENSOR(sample)
2.2 V
UNIT
µss
2.2 V
NA
3V
NA
µA
A
V
ns
NOTES: 1. The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON=1), or (ADC12ON=1 AND INCH=0Ah and sample signal
is high). When REFON = 1, ISENSOR is already included in IREF+.
2. The temperature sensor offset can be as much as ±20_C. A single-point calibration is recommended in order to minimize the offset
error of the built-in temperature sensor.
3. The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
4. No additional current is needed. The VMID is used during sampling.
5. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
12-bit DAC, supply specifications
PARAMETER
AVCC
IDD
PSRR
Analog supply voltage
Supply Current:
Single DAC Channel
(see Notes 1 and 2)
Power supply
rejection ratio
(see Notes 3 and 4)
TEST CONDITIONS
VCC
AVCC = DVCC,
AVSS = DVSS =0 V
MIN
TYP
2.20
MAX
UNIT
3.60
V
DAC12AMPx=2, DAC12IR=0,
DAC12_xDAT=0800h
2.2V/3V
50
110
DAC12AMPx=2, DAC12IR=1,
DAC12_xDAT=0800h , VeREF+=VREF+= AVCC
2.2V/3V
50
110
DAC12AMPx=5, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC
2.2V/3V
200
440
DAC12AMPx=7, DAC12IR=1,
DAC12_xDAT=0800h, VeREF+=VREF+= AVCC
2.2V/3V
700
1500
DAC12_xDAT = 800h, VREF = 1.5 V
∆AVCC = 100mV
DAC12_xDAT = 800h, VREF = 1.5 V or 2.5 V
∆AVCC = 100mV
µA
A
2.2V
70
dB
3V
NOTES: 1. No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications.
3. PSRR = 20*log{∆AVCC/∆VDAC12_xOUT}.
4. VREF is applied externally. The internal reference is not used.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
PRODUCT PREVIEW
PARAMETER
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (see Figure 26)
PARAMETER
TEST CONDITIONS
Resolution
Differential nonlinearity
(see Note 1)
DNL
Offset voltage w/o
calibration
(see Notes 1, 2)
PRODUCT PREVIEW
EO
MIN
(12-bit Monotonic)
Integral nonlinearity
(see Note 1)
INL
VCC
Offset voltage with
calibration
(see Notes 1, 2)
dE(O)/dT
Offset error
temperature coefficient
(see Note 1)
EG
Gain error (see Note 1)
dE(G)/dT
Gain temperature
coefficient (see Note 1)
tOffset_Cal
Time for offset calibration
(see Note 3)
TYP
MAX
12
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V
DAC12AMPx = 7, DAC12IR = 1
2.2V
Vref = 2.5 V
DAC12AMPx = 7, DAC12IR = 1
3V
UNIT
bits
±2.0
±8.0
LSB
±0.4
±1.0
LSB
±21
mV
±2.5
±30
2.2V/3V
VREF = 1.5 V
VREF = 2.5 V
2.2V
µV/C
±3.50
3V
2.2V/3V
% FSR
ppm of
FSR/°C
10
DAC12AMPx=2
2.2V/3V
100
DAC12AMPx=3,5
2.2V/3V
32
DAC12AMPx=4,6,7
2.2V/3V
6
ms
NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and
“b” of the first order equation: y = a + b*x. VDAC12_xOUT = EO + (1 + EG) * (VeREF+/4095) * DAC12_xDAT, DAC12IR = 1.
2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx
={0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may
effect accuracy and is not recommended.
DAC V OUT
DAC Output
VR+
RLoad =
Ideal transfer
function
AV CC
2
CLoad = 100pF
Offset Error
Positive
Negative
Gain Error
DAC Code
Figure 26. Linearity Test Load Conditions and Gain/Offset Definition
52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, linearity specifications (continued)
TYPICAL INL ERROR
vs
DIGITAL INPUT DATA
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
−1
PRODUCT PREVIEW
INL − Integral Nonlinearity Error − LSB
4
−2
−3
−4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
TYPICAL DNL ERROR
vs
DIGITAL INPUT DATA
DNL − Differential Nonlinearity Error − LSB
2.0
VCC = 2.2 V, VREF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT − Digital Code
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)
12-bit DAC, output specifications
PARAMETER
PRODUCT PREVIEW
VO
TEST CONDITIONS
Output voltage
range
(see Note 1,
Figure 29)
CL(DAC12)
Max DAC12
load capacitance
IL(DAC12)
Max DAC12
load current
RO/P(DAC12)
Output
Resistance
(see Figure 29)
VCC
MIN
TYP
MAX
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
0
0.005
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
AVCC−0.05
AVCC
UNIT
V
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
0
0.1
RLoad= 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2V/3V
AVCC−0.13
AVCC
2.2V/3V
100
2.2V
−0.5
+0.5
3V
−1.0
+1.0
RLoad= 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
2.2V/3V
150
250
RLoad= 3 kΩ,
VO/P(DAC12) > AVCC−0.3 V
DAC12_xDAT = 0FFFh
2.2V/3V
150
250
RLoad= 3 kΩ,
0.3V ≤ VO/P(DAC12) ≤ AVCC − 0.3V
2.2V/3V
1
4
pF
mA
Ω
NOTES: 1. Data is valid after the offset calibration of the output amplifier.
ILoad
RO/P(DAC12_x)
Max
RLoad
AV CC
DAC12
2
O/P(DAC12_x)
CLoad= 100pF
Min
0.3
AV CC−0.3V
VOUT
AV CC
Figure 29. DAC12_x Output Resistance Tests
54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
12-bit DAC, reference input specifications
PARAMETER
TEST CONDITIONS
Reference input
voltage range
VeREF+
Ri(VREF+),
Ri(VeREF+)
NOTES: 1.
2.
3.
4.
5.
Reference input
resistance
DAC12IR=0, (see Notes 1 and 2)
VCC
2.2V/3V
DAC12IR=1, (see Notes 3 and 4)
2.2V/3V
DAC12_0 IR=DAC12_1 IR =0
2.2V/3V
DAC12_0 IR=1, DAC12_1 IR = 0
2.2V/3V
DAC12_0 IR=0, DAC12_1 IR = 1
2.2V/3V
MIN
TYP
MAX
AVCC/3
AVcc
AVCC+0.2
AVcc+0.2
20
UNIT
V
MΩ
40
48
56
kΩ
DAC12_0 IR=DAC12_1 IR =1
DAC12_0 SREFx = DAC12_1 SREFx
2.2V/3V
20
24
28
kΩ
(see Note 5)
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / [3*(1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC − VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
PARAMETER
tON
tS(FS)
tS(C-C)
SR
TEST CONDITIONS
TYP
MAX
60
120
2.2V/3V
15
30
DAC12AMPx=0 → 7
2.2V/3V
6
12
DAC12AMPx=2
2.2V/3V
100
200
DAC12AMPx=3,5
2.2V/3V
40
80
DAC12AMPx=4,6,7
2.2V/3V
15
30
DAC12_xDAT =
3F8h→ 408h→ 3F8h
DAC12AMPx=2
2.2V/3V
5
DAC12AMPx=3,5
2.2V/3V
2
BF8h→ C08h→ BF8h
DAC12AMPx=4,6,7
2.2V/3V
1
DAC12_xDAT =
80h→ F7Fh→ 80h
(see Note 2)
DAC12AMPx=2
2.2V/3V
0.05
0.12
DAC12AMPx=3,5
2.2V/3V
0.35
0.7
DAC12AMPx=4,6,7
2.2V/3V
1.5
2.7
DAC12AMPx=2
2.2V/3V
600
DAC12AMPx=3,5
2.2V/3V
150
DAC12AMPx=4,6,7
2.2V/3V
30
DAC12 ontime
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB
(see Note 1,Figure 30)
Settling
time,full-scale
DAC12_xDAT =
80h→ F7Fh→ 80h
Settling time,
code to code
Slew Rate
Glitch energy: full-scale
DAC12_xDAT =
80h→ F7Fh→ 80h
DAC12AMPx=0 → {2, 3, 4}
VCC
2.2V/3V
DAC12AMPx=0 → {5, 6}
MIN
PRODUCT PREVIEW
12-bit DAC, dynamic specifications; Vref = VCC, DAC12IR = 1 (see Figure 30 and Figure 31)
UNIT
µs
µs
µs
V/µs
nV-s
NOTES: 1. RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 30.
2. Slew rate applies to output voltage steps >= 200mV.
Conversion 1
VOUT
DAC Output
ILoad
RLoad = 3 kΩ
Glitch
Energy
Conversion 2
Conversion 3
+/− 1/2 LSB
AV CC
2
RO/P(DAC12.x)
+/− 1/2 LSB
CLoad = 100pF
tsettleLH
tsettleHL
Figure 30. Settling Time and Glitch Energy Testing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
55
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 31. Slew Rate Testing
12-bit DAC, dynamic specifications continued (TA = 25°C unless otherwise noted)
PRODUCT PREVIEW
PARAMETER
BW−3dB
TEST CONDITIONS
3-dB bandwidth,
VDC=1.5V, VAC=0.1VPP
(see Figure 32)
Channel-to-channel crosstalk
(see Note 1 and Figure 33)
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
40
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
2.2V/3V
550
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h<−>F7Fh, RLoad = 3kΩ
fDAC12_1OUT = 10kHz @ 50/50 duty cycle
2.2V/3V
DAC12_0DAT = 80h<−>F7Fh, RLoad = 3kΩ,
DAC12_1DAT = 800h, No Load
fDAC12_0OUT = 10kHz @ 50/50 duty cycle
2.2V/3V
TYP
MAX
UNIT
kHz
−80
dB
−80
NOTES: 1. RLOAD = 3 kΩ, CLOAD = 100 pF
ILoad
Ve REF+
RLoad = 3 kΩ
AV CC
DAC12_x
2
DACx
AC
CLoad = 100pF
DC
Figure 32. Test Conditions for 3-dB Bandwidth Specification
ILoad
RLoad
AV CC
DAC12_0
DAC12_xDAT 080h
2
DAC0
7F7h
080h
V OUT
CLoad= 100pF
VREF+
ILoad
Ve
V DAC12_yOUT
RLoad
AV CC
DAC12_1
V DAC12_xOUT
2
DAC1
fToggle
CLoad= 100pF
Figure 33. Crosstalk Test Conditions
56
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7F7h
080h
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
operational amplifier OA, supply specifications
PARAMETER
VCC
ICC
PSRR
TEST CONDITIONS
Supply voltage
Supply current
(see Note 1)
Power supply rejection ratio
VCC
—
MIN
TYP
MAX
2.2
UNIT
3.6
Fast Mode, OARRIP OFF
2.2 V/3 V
180
290
Medium Mode, OARRIP OFF
2.2 V/3 V
110
190
Slow Mode, OARRIP OFF
2.2 V/3 V
50
80
Fast Mode, OARRIP ON
2.2 V/3 V
300
490
Medium Mode, OARRIP ON
2.2 V/3 V
190
350
Slow Mode, OARRIP ON
2.2 V/3 V
90
190
Non-inverting
2.2 V/3 V
70
V
µA
A
dB
NOTES: 1. P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.
operational amplifier OA, input/output specifications
VI/P
Voltage supply, I/P
IIkg
Input leakage current, I/P
(see Notes 1 and 2)
TEST CONDITIONS
OARRIP OFF
VCC
—
OARRIP ON
—
TA = −40 to +55_C
TA = +55 to +85_C
—
−5
—
−20
Fast Mode
—
Medium Mode
Vn
Voltage noise density, I/P
—
50
—
65
0.3V ≤ VIN ≤ VCC−0.3V
∆VCC≤ ± 10%, TA = 25°C
2.2 V/3 V
Fast Mode, ISOURCE ≤ −500µA
2.2 V
Slow Mode,ISOURCE ≤ −150µA
3V
Fast Mode, ISOURCE ≤ +500µA
2.2 V
Slow Mode,ISOURCE ≤ +150µA
3V
CMRR
Output
Resistance
(see Figure 34 and Note 4)
Common-mode rejection ratio
NOTES: 1.
2.
3.
4.
RLoad= 3 kΩ, CLoad = 50pF,
OARRIP ON,
VO/P(OAx) > AVCC − 0.2 V
RLoad= 3 kΩ, CLoad = 50pF,
OARRIP ON,
0.2 V ≤ VO/P(OAx) ≤ AVCC − 0.2 V
Non-inverting
V
nV/√Hz
±10
2.2 V/3 V
RLoad= 3 kΩ, CLoad = 50pF,
OARRIP ON,
VO/P(OAx) < 0.2 V
RO/P
(OAx)
nA
30
Offset voltage drift
with supply, I/P
V
50
—
2.2 V/3 V
Low-level output voltage, O/P
20
Fast Mode
see Note 3
VOL
nA
±5
80
Offset temperature drift, I/P
UNIT
±0.5
140
fV(I/P) = 10 kHz
MAX
VCC−1.2
VCC+0.1
5
−0.1
—
Offset voltage, I/P
High-level output voltage, O/P
−0.1
—
fV(I/P) = 1 kHz
Slow Mode
VOH
TYP
Slow Mode
Medium Mode
VIO
MIN
±10
mV
µV/°C
±1.5
mV/V
VCC−0.2
VCC−0.1
VCC
VCC
V
VSS
VSS
0.2
0.1
2.2 V/3 V
150
250
2.2 V/3 V
150
250
2.2 V/3 V
0.1
4
2.2 V/3 V
70
V
Ω
dB
ESD damage can degrade input current leakage.
The input bias current is overridden by the input leakage current.
Calculated using the box method.
Specification valid for voltage-follower OAx configuration.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
PRODUCT PREVIEW
PARAMETER
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
RO/P(OAx)
Max
RLoad
ILoad
AV CC
OAx
2
CLoad
O/P(OAx)
Min
0.2V
AV CC −0.2VAV
V
CC OUT
Figure 34. OAx Output Resistance Tests
operational amplifier OA, dynamic specifications
PARAMETER
TEST CONDITIONS
VCC
—
Fast Mode
Slew rate
φm
GBW
TYP
MAX
UNIT
1.2
Medium Mode
—
0.8
Slow Mode
—
0.3
—
100
dB
Open-loop voltage gain
V/µs
Phase margin
CL = 50 pF
—
60
deg
Gain margin
CL = 50 pF
—
20
dB
Gain-Bandwidth Product
(see Figure 35
and Figure 36)
Non−inverting, Fast Mode, RL = 47kΩ, CL = 50pF
2.2 V/3 V
2.2
Non−inverting, Medium Mode, RL =300kΩ, CL = 50pF
2.2 V/3 V
1.4
Non−inverting, Slow Mode, RL =300kΩ, CL = 50pF
2.2 V/3 V
0.5
ton, non-inverting, Gain = 1
2.2 V/3 V
10
ten(on) Enable time on
ten(off) Enable time off
MHz
2.2 V/3 V
20
µs
1
µs
TYPICAL PHASE vs FREQUENCY
TYPICAL OPEN-LOOP GAIN vs FREQUENCY
0
140
120
Fast Mode
100
−50
Medium Mode
60
40
20
Slow Mode
0
Phase − degrees
80
Gain − dB
PRODUCT PREVIEW
SR
MIN
Fast Mode
−100
Medium Mode
−150
−20
Slow Mode
−40
−200
−60
−80
0.001
0.01
0.1
1
10
100
Input Frequency − kHz
1000 10000
−250
1
100
Figure 36
Figure 35
58
10
Input Frequency − kHz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1000
10000
SLAS508 − APRIL 2006
electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)
Flash Memory
VCC(PGM/
ERASE)
VCC
Program and Erase supply voltage
fFTG
IPGM
Flash Timing Generator frequency
IERASE
Supply current from DVCC during erase
IGMERASE
Supply current from DVCC during global
mass erase
Cumulative program time
257
tWord
tBlock, 0
Word or byte program time
Block program time for 1st byte or word
tBlock, 1-63
Block program time for each additional byte
or word
UNIT
3.6
V
476
kHz
3
5
mA
see Note 3
2.7 V/ 3.6 V
3
7
mA
see Note 4
2.7 V/ 3.6 V
6
14
mA
see Note 1
2.7 V/ 3.6 V
10
ms
2.7 V/ 3.6 V
Program/Erase endurance
Data retention duration
MAX
2.7 V/ 3.6 V
Cumulative mass erase time
tRetention
TYP
2.7
Supply current from DVCC during program
tCPT
tCMErase
MIN
TJ = 25°C
20
104
ms
105
cycles
100
years
30
25
18
see Note 2
tBlock, End
tMass Erase
Block program end-sequence wait time
Mass erase time
10593
tGlobal Mass Erase
tSeg Erase
Global mass erase time
10593
tFTG
6
Segment erase time
4819
NOTES: 1. The cumulative program time must not be exceeded during a block-write operation. This parameter is only relevant if the block write
feature is used.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
3. Lower 64-KB or upper 64-KB Flash memory erased.
4. All Flash memory erased.
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pull-up resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
0
TYP
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
25
60
90
kΩ
MIN
TYP
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
VCC(FB)
VFB
Supply voltage during fuse-blow condition
IFB
tFB
Supply current into TDI/TCLK during fuse blow
TA = 25°C
Voltage level on TDI/TCLK for fuse-blow: F versions
VCC
2.5
6
Time to blow fuse
UNIT
V
7
V
100
mA
1
ms
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
59
PRODUCT PREVIEW
TEST
CONDITIONS
PARAMETER
SLAS508 − APRIL 2006
input/output schematic
Port P1, P1.0 to P1.5, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
DVSS
P1DIR.x
0
Direction
0: Input
1: Output
1
0
Module X OUT
1
PRODUCT PREVIEW
P1OUT.x
Bus
Keeper
P1SEL.x
EN
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
Set
Interrupt
Edge
Select
Note: x = 0,1,2,3,4,5
Port P1 (P1.0 to P1.5) pin functions
PIN NAME (P1.X)
P1.0/TA0
P1.1/TA0/MCLK
60
CONTROL BITS / SIGNALS
X
0
1
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0B
0
1
MCLK
1
1
P1.0 (I/O)
P1.1 (I/O)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P1 (P1.0 to P1.5) pin functions (continued)
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
CONTROL BITS / SIGNALS
X
2
3
4
5
FUNCTION
P1DIR.x
P1SEL.x
I: 0; O: 1
0
Timer_A3.CCI1A
0
1
Timer_A3.TA1
1
1
I: 0; O: 1
0
Timer_B7.TBOUTH
0
1
SVSOUT
1
1
P1.4 (I/O)
I: 0; O: 1
0
Timer_B7.TBCLK
0
1
SMCLK
1
1
I: 0; O: 1
0
Timer_A3.TACLK
0
1
ACLK
1
1
P1.2 (I/O)
P1.3 (I/O)
P1.5 (I/O)
PRODUCT PREVIEW
PIN NAME (P1.X)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
61
SLAS508 − APRIL 2006
input/output schematic (continued)
Port P1, P1.6, P1.7, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
CAPD.x
P1DIR.x
0
Direction
0: Input
1: Output
1
0
Module X OUT
1
PRODUCT PREVIEW
P1OUT.x
P1.6/CA0
P1.7/CA1
Bus
Keeper
P1SEL.x
EN
P1IN.x
EN
Module X IN
D
P2CA0
P1IE.x
P1IRQ.x
EN
Comp_A
Q
P1IFG.x
P1SEL.x
P1IES.x
0
1 CA0
Set
+
Interrupt
Edge
Select
−
0
1 CA1
Note: x = 6,7
P2CA1
Port P1 (P1.6 and P1.7) pin functions
PIN NAME (P1.X)
CONTROL BITS / SIGNALS
X
P1.6/CA0
6
P1.7/CA1
7
FUNCTION
CAPD.x
P1DIR.x
P1SEL.x
P1.6 (I/O)
0
I: 0; O: 1
0
CA0
1
X
X
P1.6 (I/O)
0
I: 0; O: 1
0
CA0
1
X
X
NOTES: 1. X: Don’t care.
62
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
input/output schematic (continued)
port P2, P2.0 to P2.3, P2.6 to P2.7, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
TBOUTH
0
Direction
0: Input
1: Output
1
P2OUT.x
0
Module X OUT
1
Bus
Keeper
P2SEL.x
EN
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.6/CAOUT
P2.7/ADC12CLK/DMAE0
PRODUCT PREVIEW
P2DIR.x
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Note: x = 0,1,2,3,6,7
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
63
SLAS508 − APRIL 2006
Port P2 (P2.0, P2.1, P2.2, P2.3, P2.6 and P2.7) pin functions
PIN NAME (P2.X)
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB3
CONTROL BITS / SIGNALS
X
0
1
2
3
P2.6/CAOUT
6
P2.7/ADC12CLK/DMAE0
7
FUNCTION
P2DIR.x
P2SEL.x
I: 0; O: 1
0
Timer_A3.CCI2A
0
1
Timer_A3.TA2
1
1
I: 0; O: 1
0
Timer_B7.CCI0A and Timer_B7.CCI0B
0
1
Timer_B7.TB0 (see Note 1)
1
1
I: 0; O: 1
0
Timer_B7.CCI1A and Timer_B7.CCI1B
0
1
Timer_B7.TB1 (see Note 1)
1
1
I: 0; O: 1
0
Timer_B7.CCI2A and Timer_B7.CCI2B
0
1
Timer_B7.TB3 (see Note 1)
1
1
I: 0; O: 1
0
P2.0 (I/O)
P2.1 (I/O)
P2.2 (I/O)
P2.3 (I/O)
P2.6 (I/O)
PRODUCT PREVIEW
CAOUT
1
1
I: 0; O: 1
0
ADC12CLK
1
1
DMAE0
0
1
P2.7 (I/O)
NOTES: 1. Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
64
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
input/output schematic (continued)
port P2, P2.4 to P2.5, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
DVSS
Direction control
from Module X
P2OUT.x
Module X OUT
0
Direction
0: Input
1: Output
1
0
1
Bus
Keeper
P2SEL.x
P2.4/UCA0TXD
P2.5/UCA0RXD
EN
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
Set
Interrupt
Edge
Select
Note: x = 4,5
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
65
PRODUCT PREVIEW
P2DIR.x
SLAS508 − APRIL 2006
Port P2 (P2.4 and P2.5) pin functions
PIN NAME (P2.X)
CONTROL BITS / SIGNALS
X
P2.4/UCA0TXD
4
P2.5/UCA0RXD
5
FUNCTION
P2.4 (I/O)
USCI_A0.UCA0TXD (see Note 1, 2)
P2.5 (I/O)
USCI_A0.UCA0RXD (see Note 1, 2)
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. When in USCI mode, P2.4 is set to output, P2.5 is set to input.
66
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2DIR.x
P2SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
SLAS508 − APRIL 2006
input/output schematic (continued)
port P3, P3.0 to P3.3, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
DVSS
0
Direction
0: Input
1: Output
1
P3OUT.x
0
Module X OUT
1
Bus
Keeper
P3SEL.x
P3.0/UCB0STE
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK
PRODUCT PREVIEW
P3DIR.x
EN
P3IN.x
EN
Module X IN
D
Note: x = 0,1,2,3
Port P3 (P3.0 to P3.3) pin functions
PIN NAME (P3.X)
P3.0/UCB0STE
CONTROL BITS / SIGNALS
X
0
FUNCTION
P3.0 (I/O)
UCB0STE (see Notes 1, 2)
P3.1/UCB0SIMO/
UCB0SDA
1
P3.2/UCB0SOMI/
UCB0SCL
2
P3.3/UCB0CLK
3
P3.1 (I/O)
UCB0SIMO/UCB0SDA (see Notes 1, 2, 3)
P3.2 (I/O)
UCB0SOMI/UCB0SCL (see Notes 1, 2, 3)
P3.3 (I/O)
UCB0CLK (see Notes 1, 2)
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
67
SLAS508 − APRIL 2006
input/output schematic (continued)
port P3, P3.4 to P3.7, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
TBOUTH
P3DIR.x
0
Direction
0: Input
1: Output
PRODUCT PREVIEW
1
P3OUT.x
0
Module X OUT
1
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
Bus
Keeper
P3SEL.x
EN
P3IN.x
EN
Module X IN
D
Note: x = 4,5,6,7
Port P3 (P3.4 to P3.7) pin functions
PIN NAME (P3.X)
P3.4/TB3
P3.5/TB4
P3.6/TB5
P3.7/TB6
CONTROL BITS / SIGNALS
X
4
5
6
7
FUNCTION
P3DIR.x
P3SEL.x
I: 0; O: 1
0
Timer_B7.CCI3A and Timer_B7.CCI3B
0
1
Timer_B7.TB3 (see Note 1)
1
1
I: 0; O: 1
0
Timer_B7.CCI4A and Timer_B7.CCI4B
0
1
Timer_B7.TB4 (see Note 1)
1
1
P3.4 (I/O)
P3.5 (I/O)
P3.6 (I/O)
I: 0; O: 1
0
Timer_B7.CCI5A and Timer_B7.CCI5B
0
1
Timer_B7.TB5 (see Note 1)
1
1
P3.7 (I/O)
I: 0; O: 1
0
Timer_B7.CCI6A and Timer_B7.CCI6B
0
1
Timer_B7.TB6 (see Note 1)
1
1
NOTES: 1. Setting TBOUTH causes all Timer_B outputs to be set to high impedance.
68
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
input/output schematic (continued)
port P4, P4.0 to P4.1, input/output with Schmitt-trigger
Pad Logic
DVSS
DVSS
DVSS
P4DIR.x
0
Direction control
from Module X
Direction
0: Input
1: Output
1
0
1
Module X OUT
P4.1/URXD1
P4.0/UTXD1
Bus
Keeper
P4SEL.x
PRODUCT PREVIEW
P4OUT.x
EN
P4IN.x
EN
Module X IN
D
Note: x = 0,1
Port P4 (P4.0 to P4.1) pin functions
PIN NAME (P4.X)
P4.0/UTXD1
CONTROL BITS / SIGNALS
X
0
FUNCTION
P4.0 (I/O)
USART1.UTXD1 (see Notes 1, 2)
P4.1/URXD1
1
P4.1 (I/O)
USART1.URXD1 (see Notes 1, 2)
P4DIR.x
P4SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
NOTES: 1. X: Don’t care.
2. When in USART1 mode, P4.0 is set to output, P4.1 is set to input.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
69
SLAS508 − APRIL 2006
input/output schematic (continued)
port P4, P4.2 to P4.7, input/output with Schmitt-trigger
Pad Logic
LCDS32/36
Segment Sy
DVSS
P4DIR.x
Direction control
from Module X
P4OUT.x
PRODUCT PREVIEW
Module X OUT
0
Direction
0: Input
1: Output
1
0
1
P4.7/UCA0RXD/S34
P4.6/UCA0TXD/S35
P4.5/UCLK1/S36
P4.4/SOMI1/S37
P4.3/SIMO1/S38
P4.2/STE1/S39
Bus
Keeper
P4SEL.x
EN
P4IN.x
EN
Module X IN
D
Note : x = 2,3,4,5,6,7
y = 34,35,36,37,38,39
Port P4 (P4.2 to P4.5) pin functions
PIN NAME (P4.X)
P4.2/STE1/S39
CONTROL BITS / SIGNALS
X
2
FUNCTION
P4.2 (I/O)
USART1.STE1
S39 (see Note 1)
P4.3/SIMO/S38
P4.4/SOMI/S37
P4.5/SOMI/S36
3
4
5
P4.3 (I/O)
P4SEL.x
LCDS36
0
0
0
1
0
X
X
1
I: 0; O: 1
0
0
USART1.SIMO1 (see Notes 1, 2)
0
1
0
S38 (see Note 1)
X
X
1
I: 0; O: 1
0
0
P4.4 (I/O)
USART1.SOMI1 (see Notes 1, 2)
0
1
0
S37 (see Note 1)
X
X
1
I: 0; O: 1
0
0
P4.5 (I/O)
USART1.UCLK1 (see Notes 1, 2)
0
1
0
S36 (see Note 1)
X
X
1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USART1 module.
70
P4DIR.x
I: 0; O: 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P4 (P4.6 to P4.7) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P4.X)
X
P4.6/UCA0TXD/S35
6
P4.7/UCA0RXD/S34
7
FUNCTION
P4.6 (I/O)
P4DIR.x
P4SEL.x
LCDS32
I: 0; O: 1
0
0
USCI_A0.UCA0TXD (see Notes 1, 2)
X
1
0
S35 (see Note 1)
X
X
1
I: 0; O: 1
0
0
P4.7 (I/O)
USCI_A0.UCA0RXD (see Notes 1, 2)
0
1
0
S34 (see Note 1)
X
X
1
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. When in USCI mode, P4.6 is set to output, P4.7 is set to input.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
71
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.0, input/output with Schmitt-trigger
INCH=13#
Pad Logic
A13#
LCDS0
PRODUCT PREVIEW
Segment Sy
P5DIR.x
0
1
P5OUT.x
DVSS
Direction
0: Input
1: Output
0
1
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note: x = 0
y=1
+
OA1
−
72
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P5.0/S1/A13/OA1I1
SLAS508 − APRIL 2006
Port P5 (P5.0) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
P5.0/S1/A13/OA1I1
0
FUNCTION
P5DIR.x
P5SEL.x
INCHx
OANx(OA1)
LCDS0
I: 0; O: 1
0
X
X
0
OAI11 (see Note 1)
X
X
X
1
0
A13 (see Notes 1, 3)
X
1
13
X
X
S1 enabled (see Note 1)
X
0
X
X
1
S1 disabled (see Note 1)
X
1
X
X
1
P5.0 (I/O) (see Note 1)
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
73
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.1, input/output with Schmitt-trigger
INCH=12#
Pad Logic
A12#
LCDS0
Segment Sy
PRODUCT PREVIEW
DAC12.1OPS
P5DIR.x
0
1
P5OUT.x
DVSS
Direction
0: Input
1: Output
0
1
P5.1/S0/A12/DAC1
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note: x = 1
y= 0
DVSS
DAC1
0
1
2
0 if DAC12.1AMPx = 0 and DAC12.1OPS = 1
1 if DAC12.1AMPx = 1 and DAC12.1OPS = 1
2 if DAC12.1AMPx > 1 and DAC12.1OPS = 1
74
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P5 (P5.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P5.X)
X
P5.0/S0/A12/DAC1
1
FUNCTION
P5DIR.x
P5SEL.x
INCHx
DAC12.1OPS
P5.0 (I/O) (see Note 1)
I: 0; O: 1
0
X
0
DAC12.1AMPx
X
LCDS0
0
DAC1 high impedance
(see Note 1)
X
X
X
1
0
X
DVSS (see Note 1)
X
X
X
1
1
X
DAC1 output
(see Note 1)
X
X
X
1
>1
X
A12 (see Notes 1, 2)
X
1
12
0
X
0
S0 enabled (see Note 1)
X
0
X
0
X
1
S0 disabled (see Note 1)
X
1
X
0
X
1
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. Setting theP5SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
75
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.2 to P5.4, input/output with Schmitt-trigger
Pad Logic
LCD Signal
DVSS
P5DIR.x
0
Direction
0: Input
1: Output
1
P5OUT.x
PRODUCT PREVIEW
DVSS
0
1
P5.2/COM1
P5.3/COM2
P5.4/COM3
Bus
Keeper
P5SEL.x
EN
P5IN.x
Note: x = 2,3,4
Port P5 (P5.2 to P5.4) pin functions
PIN NAME (P5.X)
CONTROL BITS / SIGNALS
X
P5.2/COM1
2
P5.3/COM2
3
P5.4/COM3
4
FUNCTION
P5.2 (I/O)
COM1 (see Note 1)
P5.3 (I/O)
COM2 (see Note 1)
P5.4 (I/O)
COM3 (see Note 1)
NOTES: 1. X: Don’t care.
76
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
SLAS508 − APRIL 2006
input/output schematic (continued)
port P5, P5.5 to P5.7, input/output with Schmitt-trigger
Pad Logic
LCD Signal
DVSS
0
Direction
0: Input
1: Output
1
P5OUT.x
DVSS
0
1
Bus
Keeper
P5SEL.x
P5.5/R03
P5.6/LCDREF/R13
P5.7/R03
PRODUCT PREVIEW
P5DIR.x
EN
P5IN.x
Note: x = 5,6,7
Port P5 (P5.5 to P5.7) pin functions
PIN NAME (P5.X)
CONTROL BITS / SIGNALS
X
P5.5/R03
5
P5.6/LCDREF/R13
6
P5.7/R03
7
FUNCTION
P5.5 (I/O)
R03 (see Note 1)
P5.6 (I/O)
R13 or LCDREF (see Notes 1, 2)
P5.7 (I/O)
R03 (see Note 1)
P5DIR.x
P5SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
NOTES: 1. X: Don’t care.
2. External reference for the LCD_A charge pump is applied when VLCDREFx = 01. Otherwise R13 is selected.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
77
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.0, P6.2, and P6.4, input/output with Schmitt-trigger
INCH=0/2/4#
Pad Logic
Ay#
P6DIR.x
0
1
P6OUT.x
PRODUCT PREVIEW
DVSS
Direction
0: Input
1: Output
P6.0/A0/OA0I0
P6.2/A2/OA0I1
P6.4/A4/OA1I0
0
1
Bus
Keeper
P6SEL.x
EN
P6IN.x
Note: x = 0,2,4
y = 0,1
#Signal from or to ADC
12
+
OA0/1
−
78
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P6 (P6.0, P6.2, and P6.4) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
P6.0/A0/OA0I0
X
0
FUNCTION
P6.0 (I/O) (see Note 1)
OA0I0 (see Note 1)
A0 (see Notes 1, 3)
P6.2/A2/OA0I1
2
P6.2 (I/O) (see Note 1)
OA0I1 (see Note 1)
A2 (see Notes 1, 3)
P6.4/A4/OA1I0
4
P6SEL.x
OAPx (OA0)
OANx (OA0)
OAPx (OA1)
OANx(OA1)
INCHx
I: 0; O: 1
0
X
X
X
X
X
0
X
X
P6DIR.x
X
1
X
X
0
I: 0; O: 1
0
X
X
X
X
X
1
X
X
X
1
X
X
2
I: 0; O: 1
0
X
X
X
OA1I0 (see Note 1)
X
X
X
0
X
A4 (see Notes 1, 3)
X
1
X
X
4
P6.4 (I/O) (see Note 1)
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
79
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.1, P6.3, and P6.5 input/output with Schmitt-trigger
INCH=1/3/5#
Pad Logic
Ay#
P6DIR.x
0
1
P6OUT.x
PRODUCT PREVIEW
DVSS
Direction
0: Input
1: Output
P6.1/A1/OA0O
P6.3/A3/OA1O
P6.5/A5/OA2O
0
1
Bus
Keeper
P6SEL.x
EN
P6IN.x
OAPMx> 0
OAADC1
+
OAy
−
Note: x = 1,3,5
y = 0,1,2
#Signal from or to ADC
12
80
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P6 (P6.1, P6.3, and P6.5) pin functions
PIN NAME (P6.X)
P6.1/A1/OA0O
P6.3/A3/OA1O
P6.5/A5/OA2O
CONTROL BITS / SIGNALS
X
1
3
5
FUNCTION
P6DIR.x
P6SEL.x
OAADC1
OAPMx
INCHx
P6.1 (I/O) (see Note 1)
I: 0; O: 1
0
X
X
X
OA0O (see Notes 1, 4)
X
X
1
>0
X
A1 (see Notes 1, 3)
X
1
X
X
1
P6.3 (I/O) (see Note 1)
I: 0; O: 1
0
X
X
X
OA1O (see Notes 1, 4)
X
X
1
>0
X
A3 (see Notes 1, 3)
X
1
X
X
3
P6.5 (I/O) (see Note 1)
I: 0; O: 1
0
X
X
X
OA2O (see Notes 1, 4)
X
X
1
>0
X
A5 (see Notes 1, 3)
X
1
X
X
5
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
4. Setting the OAADC1 bit or setting OAFCx = 00 will cause the operational amplifier to be present at the pin as well as internally
connected to the corresponding ADC12 input.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
81
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.6, input/output with Schmitt-trigger
INCH=6#
Pad Logic
A6#
P6DIR.x
0
1
P6OUT.x
PRODUCT PREVIEW
DVSS
Direction
0: Input
1: Output
P6.6/A6/DAC0/OA2I0
0
1
Bus
Keeper
P6SEL.x
DAC12.0AMP > 0
DAC12.0OPS
EN
P6IN.x
Note: x = 6
#Signal from or to ADC12
+
OA2
−
DVSS
DAC0
0
1
2
0 if DAC12.0AMPx= 0 and DAC12.0OPS = 0
1 if DAC12.0AMPx= 1 and DAC12.0OPS = 0
2 if DAC12.0AMPx> 1 and DAC12.0OPS = 0
82
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P6 (P6.6) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
P6.6/A6/DAC0/OA2I0
6
FUNCTION
P6DIR.x
P6SEL.x
INCHx
DAC12.0OPS
DAC12.0AMPx
OAPx (OA2)
OANx (OA2)
P6.6 (I/O) (see Note 1)
I: 0; O: 1
0
X
1
X
X
DAC0 high impedance
(see Note 1)
X
X
X
0
0
X
DVSS (see Note 1)
X
X
X
0
1
X
DAC0 output
(see Note 1)
X
X
X
0
>1
X
A6 (see Notes 1, 2)
X
1
6
X
X
X
OA2I0 (see Note 1)
X
X
0
X
X
0
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
83
SLAS508 − APRIL 2006
input/output schematic (continued)
port P6, P6.7, input/output with Schmitt-trigger
To SVS Mux
#
INCH=7
Pad Logic
A7#
P6DIR.x
0
PRODUCT PREVIEW
1
P6OUT.x
DVSS
Direction
0: Input
1: Output
0
1
P6SEL.x
Bus
Keeper
VLD =15
EN
P6.7/A7/DAC1/SVSIN
DAC12.1AMP > 0
DAC12.1OPS
P6IN.x
Note: x = 7
#Signal from or to ADC12
DVSS
DAC1
0
1
2
0 if DAC12.1AMPx = 0 and DAC12.1OPS = 0
1 if DAC12.1AMPx = 1 and DAC12.1OPS = 0
2 if DAC12.1AMPx > 1 and DAC12.1OPS = 0
84
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P6 (P6.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P6.X)
X
P6.7/A7/DAC1/SVSIN
7
FUNCTION
P6DIR.x
P6SEL.x
INCHx
DAC12.1OPS
DAC12.1AMPx
P6.7 (I/O) (see Note 1)
I: 0; O: 1
0
X
1
X
DAC1 high impedance
(see Note 1)
X
X
X
0
0
DVSS (see Note 1)
X
X
X
0
1
DAC1 output
(see Note 1)
X
X
X
0
>1
A7 (see Notes 1, 2)
X
1
7
X
X
SVSIN (see Notes 1,3)
0
1
0
1
X
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. Setting the P6SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
3. Setting VLDx = 15 will also cause the external SVSIN to be used. In this case, the P6SEL.x bit is a do not care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
85
SLAS508 − APRIL 2006
input/output schematic (continued)
port P7, P7.0 − P7.3, input/output with Schmitt-trigger
Pad Logic
LCDS28/32
Segment Sy
DVSS
P7DIR.x
Direction control
from Module X
P7OUT.x
PRODUCT PREVIEW
Module X OUT
0
Direction
0: Input
1: Output
1
0
1
P7.3/UCA0CLK/S30
P7.2/UCA0SOMI/S31
P7.1/UCA0SIMO/S32
P7.0/UCA0STE/S33
Bus
Keeper
P7SEL.x
EN
P7IN.x
EN
Module X IN
D
Note: x = 0,1,2,3
y = 30,31,32,33
Port P7 (P7.0 to P7.1) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
P7.0/UCA0STE/S33
0
P7.1/UCA0SIMO/S32
1
FUNCTION
P7.0 (I/O)
P7SEL.x
LCDS32
I: 0; O: 1
0
0
USCI_A0.UCA0STE (see Notes 1, 2)
X
1
0
S33 (see Note 1)
X
X
1
P7.1 (I/O)
I: 0; O: 1
0
0
USCI_A0.UCA0SIMO (see Notes 1, 2)
X
1
0
S32 (see Note 1)
X
X
1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
86
P7DIR.x
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
Port P7 (P7.2 to P7.3) pin functions (continued)
CONTROL BITS / SIGNALS
PIN NAME (P7.X)
X
P7.2/UCA0SOMI/S31
2
P7.3/UCA0CLK/S30
3
FUNCTION
P7.2 (I/O)
P7DIR.x
P7SEL.x
LCDS28
I: 0; O: 1
0
0
USCI_A0.UCA0SOMI (see Notes 1, 2)
X
1
0
S31 (see Note 1)
X
X
1
I: 0; O: 1
0
0
P7.3 (I/O)
USCI_A0.UCA0CLK (see Notes 1, 2)
X
1
0
S30 (see Note 1)
X
X
1
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
87
SLAS508 − APRIL 2006
input/output schematic (continued)
port P7, P7.4 − P7.7, input/output with Schmitt-trigger
Pad Logic
LCDS24/28
Segment Sy
DVSS
P7DIR.x
0
Direction
0: Input
1: Output
1
P7OUT.x
PRODUCT PREVIEW
DVSS
0
1
P7.7/S26
P7.6/S27
P7.5/S28
P7.4/S29
Bus
Keeper
P7SEL.x
EN
P7IN.x
Note: x = 4,5,6,7
y = 26,27,28,29
Port P7 (P7.4 to P7.5) pin functions
PIN NAME (P7.X)
CONTROL BITS / SIGNALS
X
P7.4/S29
4
P7.5/S28
5
FUNCTION
P7.4 (I/O)
S29 (see Note 1)
P7.5 (I/O)
S28 (see Note 1)
NOTES: 1. X: Don’t care.
88
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P7DIR.x
P7SEL.x
LCDS28
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
SLAS508 − APRIL 2006
Port P7 (P7.6 to P7.7) pin functions (continued)
PIN NAME (P7.X)
CONTROL BITS / SIGNALS
X
P7.6/S27
6
P7.7/S26
7
FUNCTION
P7.6 (I/O)
S27 (see Note 1)
P7.7 (I/O)
S26 (see Note 1)
P7DIR.x
P7SEL.x
LCDS24
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
89
SLAS508 − APRIL 2006
input/output schematic (continued)
port P8, P8.0 − P8.7, input/output with Schmitt-trigger
Pad Logic
LCDS16/20/24
Segment Sy
DVSS
P8DIR.x
0
Direction
0: Input
1: Output
1
0
P8OUT.x
PRODUCT PREVIEW
DVSS
1
P8.7/S18
P8.6/S19
P8.5/S20
P8.4/S21
P8.3/S22
P8.2/S23
P8.1/S24
P8.0/S25
Bus
Keeper
P8SEL.x
EN
P8IN.x
Note: x = 0,1,2,3,4,5,6,7
y = 25,24,23,22,21,20,19,18
Port P8 (P8.0 to P8.1) pin functions
PIN NAME (P8.X)
P8.0/S18
CONTROL BITS / SIGNALS
X
0
FUNCTION
P8.0 (I/O)
S18 (see Note 1)
P8.1/S19
0
P8.0 (I/O)
S19 (see Note 1)
NOTES: 1. X: Don’t care.
90
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P8DIR.x
P8SEL.x
LCDS16
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
SLAS508 − APRIL 2006
Port P8 (P8.2 to P8.5) pin functions (continued)
PIN NAME (P8.X)
CONTROL BITS / SIGNALS
X
P8.2/S20
2
P8.3/S21
3
FUNCTION
P8.2 (I/O)
S20 (see Note 1)
P8.3 (I/O)
S21 (see Note 1)
P8.4/S22
4
P8.4 (I/O)
S22 (see Note 1)
P8.5/S23
5
P8.5 (I/O)
S23 (see Note 1)
P8DIR.x
P8SEL.x
LCDS20
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
NOTES: 1. X: Don’t care.
Port P8 (P8.6 to P8.7) pin functions
CONTROL BITS / SIGNALS
X
P8.6/S24
6
P8.7/S25
7
FUNCTION
P8.6 (I/O)
S24 (see Note 1)
P8.7 (I/O)
S25 (see Note 1)
P8DIR.x
P8SEL.x
LCDS24
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
PRODUCT PREVIEW
PIN NAME (P8.X)
NOTES: 1. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
91
SLAS508 − APRIL 2006
input/output schematic (continued)
port P9, P9.0 − P9.7, input/output with Schmitt-trigger
Pad Logic
LCDS8/12/16
Segment Sy
DVSS
P9DIR.x
0
Direction
0: Input
1: Output
1
P9OUT.x
PRODUCT PREVIEW
DVSS
0
1
P9.7/S10
P9.6/S11
P9.5/S12
P9.4/S13
P9.3/S14
P9.2/S15
P9.1/S16
P9.0/S17
Bus
Keeper
P9SEL.x
EN
P9IN.x
Note: x = 0,1,2,3,4,5,6,7
y = 17,16,15,14,13,12,11,10
Port P9 (P9.0 to P9.1) pin functions
PIN NAME (P9.X)
CONTROL BITS / SIGNALS
X
P9.0/S17
0
P9.1/S16
1
FUNCTION
P9.0 (I/O)
S17 (see Note 1)
P9.1 (I/O)
S16 (see Note 1)
NOTES: 1. X: Don’t care.
92
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P9DIR.x
P9SEL.x
LCDS16
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
SLAS508 − APRIL 2006
Port P9 (P9.2 to P9.5) pin functions (continued)
PIN NAME (P9.X)
CONTROL BITS / SIGNALS
X
P9.2/S20
2
P9.3/S21
3
FUNCTION
P9.2 (I/O)
S15 (see Note 1)
P9.3 (I/O)
S14 (see Note 1)
P9.4/S22
4
P9.4 (I/O)
S13 (see Note 1)
P9.5/S23
5
P9.5 (I/O)
S12 (see Note 1)
P9DIR.x
P9SEL.x
LCDS12
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
NOTES: 1. X: Don’t care.
Port P9 (P9.6 to P9.7) pin functions (continued)
CONTROL BITS / SIGNALS
X
P9.6/S24
6
P9.7/S25
7
FUNCTION
P9.6 (I/O)
S11 (see Note 1)
P9.7 (I/O)
S10 (see Note 1)
P9DIR.x
P9SEL.x
LCDS8
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
PRODUCT PREVIEW
PIN NAME (P9.X)
NOTES: 1. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
93
SLAS508 − APRIL 2006
input/output schematic (continued)
port P10, P10.0 − P10.5, input/output with Schmitt-trigger
Pad Logic
LCDS4/8
Segment Sy
DVSS
P10DIR.x
0
Direction
0: Input
1: Output
1
P10OUT.x
PRODUCT PREVIEW
DVSS
0
1
P10.5/S4
P10.4/S5
P10.3/S6
P10.2/S7
P10.1/S8
P10.0/S9
Bus
Keeper
P10SEL.x
EN
P10IN.x
Note: x = 0,1,2,3,4,5
y = 9,8,7,6,5,4
Port P10 (P10.0 to P10.1) pin functions
PIN NAME (P10.X)
CONTROL BITS / SIGNALS
X
P10.0/S8
0
P10.1/S7
1
FUNCTION
P10.0 (I/O)
S8 (see Note 1)
P10.1 (I/O)
S7 (see Note 1)
NOTES: 1. X: Don’t care.
94
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P10DIR.x
P10SEL.x
LCDS8
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
SLAS508 − APRIL 2006
Port P10 (P10.2 to P10.5) pin functions (continued)
PIN NAME (P10.X)
CONTROL BITS / SIGNALS
X
P10.2/S7
2
P10.3/S6
3
FUNCTION
P10.2 (I/O)
S7 (see Note 1)
P10.3 (I/O)
S6 (see Note 1)
P10.4/S5
4
P10.4 (I/O)
S5 (see Note 1)
P10.5/S4
5
P10.5 (I/O)
S4 (see Note 1)
P10DIR.x
P10SEL.x
LCDS4
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
I: 0; O: 1
0
0
X
X
1
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
95
SLAS508 − APRIL 2006
input/output schematic (continued)
port P10, P10.6, input/output with Schmitt-trigger
INCH=15#
Pad Logic
A15#
LCDS0
PRODUCT PREVIEW
Segment Sy
P10DIR.x
0
Direction
0: Input
1: Output
1
P10OUT.x
DVSS
0
1
P10.6/S3/A15
Bus
Keeper
P10SEL.x
EN
P10IN.x
Note: x = 6
y =3
Port P10 (P10.6) pin functions
PIN NAME (P10.X)
P10.6/S3/A15
CONTROL BITS / SIGNALS
X
6
FUNCTION
P10DIR.x
P10SEL.x
INCHx
LCDS0
I: 0; O: 1
0
X
0
A15 (see Notes 1, 3)
X
1
15
0
S3 enabled (see Note 1)
X
0
X
1
S3 disabled (see Note 1)
X
1
X
1
P5.0 (I/O) (see Note 1)
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
96
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
input/output schematic (continued)
port P10, P10.7, input/output with Schmitt-trigger
INCH=14#
Pad Logic
A14#
LCDS0
P10DIR.x
0
1
P10OUT.x
DVSS
Direction
0: Input
1: Output
0
1
Bus
Keeper
P10SEL.x
P10.7/S2/A14/OA2I1
EN
P10IN.x
Note: x = 7
y= 2
+
OA2
−
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
97
PRODUCT PREVIEW
Segment Sy
SLAS508 − APRIL 2006
Port P10 (P10.7) pin functions
CONTROL BITS / SIGNALS
PIN NAME (P10.X)
X
FUNCTION
P10.7/S2/A14/OA2I1
7
P10.7 (I/O) (see Note 1)
P10DIR.x
P10SEL.x
INCHx
OAPx (OA1)
OANx (OA1)
LCDS0
I: 0; O: 1
0
X
X
0
A14 (see Notes 1, 3)
X
1
14
X
0
OA2I1 (see Notes 1, 3)
X
X
X
1
0
S2 enabled (see Note 1)
X
0
X
X
1
S2 disabled (see Note 1)
X
1
X
X
1
PRODUCT PREVIEW
NOTES: 1. X: Don’t care.
2. N/A: Not available or not applicable.
3. Setting the P10SEL.x bit disables the output driver as well as the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
98
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SLAS508 − APRIL 2006
input/output schematic (continued)
VeREF+/DAC0
DAC12.0OPS
0
DAC0_2_OA
P6.6/A6/DAC0/OA2I0
1
Reference Voltage to DAC1
Reference Voltage to ADC12
Reference Voltage to DAC0
#
Ve REF+ /DAC0
’0’, if DAC12CALON = 0
DAC12AMPx>1 AND DAC12OPS=1
−
1
0
PRODUCT PREVIEW
+
’1’, if DAC12AMPx>1
’1’, if DAC12AMPx=1
DAC12OPS
#
If the reference of DAC0 is taken from pin VeREF+ /DAC0, unpredictable voltage levels will be on pin.
In this situation, the DAC0 output is fed back to its own reference input.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
99
SLAS508 − APRIL 2006
input/output schematic (continued)
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger or output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DVCC
TDI
PRODUCT PREVIEW
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DVCC
TMS
Module
TMS
DVCC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
100
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
G
D
U
S
G
D
U
S
SLAS508 − APRIL 2006
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current (I(TF) ) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be
taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state (see
Figure 37). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition). The JTAG pins are terminated internally and therefore do not require external termination.
Time TMS Goes Low After POR
TMS
PRODUCT PREVIEW
I(TF)
ITDI/TCLK
Figure 37. Fuse Check Mode Current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
101
SLAS508 − APRIL 2006
Data Sheet Revision History
Literature
Number
SLAS508
Summary
Preliminary PRODUCT PREVIEW datasheet release.
PRODUCT PREVIEW
NOTE: The referring page and figure numbers are referred to the respective document revision.
102
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
MSP430FG4616IPZ
PREVIEW
LQFP
PZ
100
90
TBD
Call TI
Call TI
MSP430FG4616IPZR
PREVIEW
LQFP
PZ
100
1000
TBD
Call TI
Call TI
MSP430FG4617IPZ
PREVIEW
LQFP
PZ
100
90
TBD
Call TI
Call TI
MSP430FG4617IPZR
PREVIEW
LQFP
PZ
100
1000
TBD
Call TI
Call TI
MSP430FG4618IPZ
PREVIEW
LQFP
PZ
100
90
TBD
Call TI
Call TI
MSP430FG4618IPZR
PREVIEW
LQFP
PZ
100
1000
TBD
Call TI
Call TI
MSP430FG4619IPZ
PREVIEW
LQFP
PZ
100
90
TBD
Call TI
Call TI
MSP430FG4619IPZR
PREVIEW
LQFP
PZ
100
1000
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
0,08 M
51
76
50
100
26
1
0,13 NOM
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
15,80
0,05 MIN
1,45
1,35
0,25
0°– 7°
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149 /B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Mailing Address:
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated