IDT71V416S IDT71V416L 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Features Description ◆ The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized as 256K x 16. It is fabricated using IDT’s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V416 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ 256K x 16 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. Equal access and cycle times – Commercial and Industrial: 10/12/15ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly LVTTL-compatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Single 3.3V power supply Available in 44-pin, 400 mil plastic SOJ package and a 44pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. Functional Block Diagram OE Output Enable Buffer A0 - A17 Address Buffers Row / Column Decoders 8 CS Chip Select Buffer 8 4,194,304-bit Memory Array WE 16 Write Enable Buffer Sense Amps and Write Drivers 8 8 High Byte Output Buffer High Byte Write Buffer Low Byte Output Buffer Low Byte Write Buffer 8 I/O 15 8 I/O 8 8 I/O 7 8 I/O 0 BHE Byte Enable Buffers BLE 3624 drw 01 JANUARY 2004 1 ©2004 Integrated Device Technology, Inc. DSC-3624/09 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configurations - SOJ/TSOP A0 A1 A2 A3 A4 CS I/O 0 I/O 1 I/O 2 I/O 3 VDD VSS I/O 4 I/O 5 I/O 6 I/O 7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO44-1 SO44-2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 Pin Configurations - 48 BGA A17 A16 A15 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 VSS VDD I/O 11 I/O 10 I/O 9 I/O 8 NC* A14 A13 A12 1 2 3 4 5 6 A BLE OE A0 A1 A2 NC B I/O0 BHE A3 A4 CS I/O8 C I/O1 I/O2 A5 A6 I/O10 I/O9 D VSS I/O3 A 17 A7 I/O11 VDD E VDD I/O4 NC A16 I/O12 VSS F I/O6 I/O5 A 14 A15 I/O13 I/O14 G I/O7 NC A 12 A13 WE I/O15 H NC A8 A9 A10 A11 NC 3624 tbl 11 A11 A10 3624 drw 02 *Pin 28 can either be a NC or connected to Vss Top View SOJ Capacitance Pin Descriptions (TA = +25°C, f = 1.0MHz) A0 - A17 Address Inputs Input Symbol Parameter(1) Conditions Max. Unit CS Chip Select Input CIN Input Capacitance VIN = 3dV 7 pF WE Write Enable Input CI/O I/O Capacitance VOUT = 3dV 8 OE Output Enable Input BHE High Byte Enable Input BLE Low Byte Enable Input I/O0 - I/O15 Data Input/Output I/O VDD 3.3V Power Pwr VSS Ground Gnd pF 3624 tbl 02 48 BGA Capacitance (TA = +25°C, f = 1.0MHz) 3624 tbl 01 Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 3dV 6 pF CI/O I/O Capacitance VOUT = 3dV 7 pF NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 3624 tbl 02b 6.42 2 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Recommended Operating Temperature and Supply Voltage Symbol Rating Value Unit VDD Supply Voltage Relative to VSS -0.5 to +4.6 V Grade Temperature VSS VDD -0.5 to VDD+0.5 V Commercial 0OC to +70OC 0V See Below 0V See Below VIN, VOUT Terminal Voltage Relative to VSS TBIAS Temperature Under Bias -55 to +125 o C TSTG Storage Temperature -55 to +125 o C O Industrial O –40 C to +85 C 3624 tbl 05 PT Power Dissipation 1 W IOUT DC Output Current 50 mA Recommended DC Operating Conditions 3624 tbl 04 Symbol NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 0 0 V V VDD Supply Voltage VSS Ground VIH Input High Voltage 2.0 ____ VDD+0.3(1) VIL Input Low Voltage -0.3(2) ____ 0.8 V 3624 tbl 06 NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. Truth Table(1) CS OE WE BLE BHE I/O0-I/O7 I/O8-I/O15 Function H X X X X High-Z High-Z Deselected - Standby L L H L H DATAOUT High-Z Low Byte Read L L H H L High-Z DATAOUT High Byte Read L L H L L DATAOUT DATAOUT Word Read L X L L L DATAIN DATAIN Word Write L X L L H DATAIN High-Z Low Byte Write L X L H L High-Z DATAIN High Byte Write L H H X X High-Z High-Z Outputs Disabled L X X H H High-Z High-Z Outputs Disabled 3624 tbl 03 NOTE: 1. H = VIH, L = VIL, X = Don't care. 6.42 3 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges DC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) IDT71V416 Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VCC = Max., VIN = VSS to VDD ___ 5 µA |ILO| Output Leakage Current VDD = Max., CS = VIH, VOUT = VSS to VDD ___ 5 µA IOL = 8mA, VDD = Min. ___ 0.4 V 2.4 ___ V VOL VOH Output Low Voltage Output High Voltage IOH = -4mA, VDD = Min. 3624 tbl 07 DC Electrical Characteristics(1, 2, 3) (VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V) 71V416S/L10 Symbol ICC ISB ISB1 Parameter 71V416S/L12 71V416S/L15 Com'l. Ind.(5) Com'l. Ind. Com'l. Ind. Unit mA Dynamic Operating Current CS < VLC, Outputs Open, VDD = Max., f = f MAX(4) S 200 200 180 180 170 170 L 180 — 170 170 160 160 Dynamic Standby Power Supply Current CS > VHC, Outputs Open, VDD = Max., f = f MAX(4) S 70 70 60 60 50 50 L 50 — 45 45 40 40 Full Standby Pow er Supply Current (static) CS > VHC, Outputs Open, VDD = Max., f = 0(4) S 20 20 20 20 20 20 L 10 — 10 10 10 10 mA 3624 tbl 08 NOTES: IDT71V416S/71V416L 1. All values are maximum guaranteed values. 2. All inputs switch between 0.2V (Low) and VDD -0.2V (High). 3. Power specifications are preliminary. 4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 5. Standard power 10ns (S10) speed grade only. AC Test Loads 3.3V +1.5V 320Ω 50Ω I/O mA DATA OUT Z0 = 50Ω 5pF* 30pF 350Ω 3624 drw 03 3624 drw 04 Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 7 • 6 ∆tAA, tACS (Typical, ns) 5 4 AC Test Conditions Input Pulse Levels • 3 • 2 • 1 • • • 8 20 40 60 80 100 120 140 160 180 200 CAPACITANCE (pF) 3624 drw 05 Input Rise/Fall Times 1.5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load Figure 3. Output Capacitive Derating GND to 3.0V Figures 1,2 and 3 3624 tbl 09 6.42 4 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges) 71V416S/L10(2) Symbol Parameter 71V416S/L12 71V416S/L15 Min. Max. Min. Max. Min. Max. Unit READ CYCLE tRC Read Cycle Time 10 ____ 12 ____ 15 ____ ns tAA Address Access Time ____ 10 ____ 12 ____ 15 ns tACS Chip Select Access Time ____ 10 ____ 12 ____ 15 ns 4 ____ 4 ____ 4 ____ ns 5 ____ 6 ____ 7 ns ____ 6 ____ 7 ns ____ 0 ____ ns 7 ns ____ ns (1) tCLZ Chip Select Low to Output in Low-Z (1) tCHZ Chip Select High to Output in High-Z ____ tOE Output Enable Low to Output Valid ____ 5 0 ____ 0 ____ 5 ____ 6 ____ 4 ____ 4 ____ 4 ____ 5 ____ 6 ____ 7 ns 0 ____ 0 ____ 0 ____ ns (1) Output Enable Low to Output in Low-Z tOLZ (1) tOHZ Output Enable High to Output in High-Z tOH Output Hold from Address Change tBE Byte Enable Low to Output Valid (1) tBLZ Byte Enable Low to Output in Low-Z tBHZ(1) Byte Enable High to Output in High-Z ____ 5 ____ 6 ____ 7 ns tWC Write Cycle Time 10 ____ 12 ____ 15 ____ ns tAW Address Valid to End of Write 8 ____ 8 ____ 10 ____ ns tCW Chip Select Low to End of Write 8 ____ 8 ____ 10 ____ ns 8 ____ 8 ____ 10 ____ ns 0 ____ 0 ____ ns 0 ____ 0 ____ ns ns WRITE CYCLE Byte Enable Low to End of Write tBW tAS Address Set-up Time 0 ____ tWR Address Hold from End of Write 0 ____ 8 ____ 8 ____ 10 ____ 6 ____ 7 ____ ns tWP Write Pulse Width tDW Data Valid to End of Write 5 ____ tDH Data Hold Time 0 ____ 0 ____ 0 ____ ns tOW(1) Write Enable High to Output in Low-Z 3 ____ 3 ____ 3 ____ ns Write Enable Low to Output in High-Z ____ 6 ____ 7 ____ 7 ns (1) tWHZ 3624 tbl 10 NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. 2. Low power 10ns (L10) speed 0ºC to +70ºC temperature range only. Timing Waveform of Read Cycle No. 1(1,2,3) tRC ADDRESS tAA tOH tOH DATAOUT DATAOUT VALID PREVIOUS DATAOUT VALID NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. OE, BHE, and BLE are LOW. 3624 drw 06 6.42 5 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 2 (1) tRC ADDRESS tOH tAA OE tOHZ (3) tOE tOLZ CS tCLZ (3) (3) tACS (2) tCHZ (3) BHE, BLE tBE tBLZ (2) tBHZ (3) (3) DATAOUT DATA OUT VALID 3624 drw 07 NOTES: 1. WE is HIGH for Read Cycle. 2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter. 3. Transition is measured ±200mV from steady state. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4) tWC ADDRESS tAW CS tCW (2) tCHZ (5) tBW BHE, BLE tWR (5) tWP WE tAS tWHZ (5) tOW DATAOUT tBHZ PREVIOUS DATA VALID (3) (5) DATA VALID tDW DATAIN tDH DATAIN VALID 3624 drw 0 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as short as the specified tWP. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured ±200mV from steady state. 6.42 6 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3) tWC ADDRESS tAW CS tCW (2) tAS tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 3624 drw 09 Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,3) tWC ADDRESS tAW CS tCW (2) tAS tBW BHE, BLE tWP tWR WE DATAOUT tDW DATAIN tDH DATAIN VALID 3624 drw 10 NOTES: 1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE. 2. During this period, I/O pins are in the output state, and input signals must not be applied. 3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6.42 7 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Ordering Information IDT 71V416 Device Type X X Die Power Revistion XX XXX Speed Package X X Process/ Temperature Range Blank I Commercial (0°C to +70°C) Industrial (-40°C to +85°C) G Restricted hazardous substance device Y PH BE 44-pin, 400-mil SOJ (SO44-1) 44-pin TSOP Type II (SO44-2) 48 Ball Grid Array 10* 12 15 Speed in nanoseconds S L Standard Power Low Power Blank First generation or current stepping being shipped * Commercial only for low power 10ns (L10) speed grade. 3624 drw 11a 6.42 8 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Datasheet Document History 08/5/99 08/31/99 03/24/00 08/10/00 Pg 6 Pg. 1–9 Pg. 9 Pg. 6 09/11/ 02 11/26/02 07/31/03 10/13/03 Pg. 1 Pg. 2 Pg. 8 Pg. 8 Pg. 8 01/30/04 Pg. 8 Updated to new format Revised footnote for tCW on Write Cycle No. 1 diagram Added Industrial temperature range offering Added Datasheet Document History Changed note to Write cycle No. 1 according to footnotes Add 48 ball grid array package offering Correct TTL to LVTTL Updated TBD information for the 48 BGA Capacitance table Added "Die Revision" to ordering information Updated note, L10 speed grade commercial temperature only and updated die stepping from YF to Y. Updated ordering information. Refer to 71V416YS and 71V416YL datasheet for latest generation die step. Added "Restricted hazardous substance device" to ordering information. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 9 for Tech Support: [email protected] 800-544-7726