Cypress CY7C374I-66GMB Ultralogicâ ¢ 128-macrocell flash cpld Datasheet

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CY7C374i
UltraLogic™ 128-Macrocell Flash CPLD
Features
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Functional Description
128 macrocells in eight logic blocks
64 I/O pins
Five dedicated inputs including four clock pins
In-System Reprogrammable™ (ISR™) Flash technology
— JTAG interface
Bus Hold capabilities on all I/Os and dedicated inputs
No hidden delays
High speed
— fMAX = 125 MHz
— tPD = 10 ns
— tS = 5.5 ns
— tCO = 6.5 ns
Fully PCI-compliant
3.3V or 5.0V I/O operation
Available in 84-pin PLCC, 84-pin CLCC, and 100-pin
TQFP packages
Pin-compatible with the CY7C373i
The CY7C374i is an In-System Reprogrammable Complex
Programmable Logic Device (CPLD) and is part of the
FLASH370i™ family of high-density, high-speed CPLDs. Like
all members of the FLASH370i family, the CY7C374i is
designed to bring the ease of use as well as PCI Local Bus
Specification support and high performance of the 22V10 to
high-density CPLDs.
Like all of the UltraLogic™ FLASH370i devices, the CY7C374i
is electrically erasable and In-System Reprogrammable (ISR),
which simplifies both design and manufacturing flows, thereby
reducing costs. The Cypress ISR function is implemented
through a JTAG serial interface. Data is shifted in and out
through the SDI and SDO pin. The ISR interface is enabled
using the programming voltage pin (ISREN). Additionally,
because of the superior routability of the FLASH370i devices,
ISR often allows users to change existing logic designs while
simultaneously fixing pinout assignments.
The 128 macrocells in the CY7C374i are divided between
eight logic blocks. Each logic block includes 16 macrocells, a
72 x 86 product term array, and an intelligent product term
allocator.
Inputs
Logic Block Diagram
Clock
Inputs
1
4
INPUT/CLOCK
MACROCELLS
4
INPUT
MACROCELL
4
I/O0–I/O7
8 I/Os
LOGIC
BLOCK
A
16
LOGIC
BLOCK
8 I/Os
I/O8–I/O15
B
LOGIC
BLOCK
8 I/Os
I/O16–I/O23
C
LOGIC
BLOCK
8 I/Os
I/O24–I/O31
36
D
LOGIC
BLOCK
36
PIM
16
36
36
16
16
36
36
16
16
36
36
LOGIC
BLOCK
I/O56–I/O63
8 I/Os
I/O48–I/O55
G
LOGIC
BLOCK
8 I/Os
I/O40–I/O47
F
LOGIC
BLOCK
8 I/Os
I/O32–I/O39
E
16
16
8 I/Os
H
32
32
Selection Guide
7C374i–125 7C374i–100 7C374i–83 7C7374iL–83 7C374i–66 7C374iL–66 Unit
Maximum Propagation Delay[1], tPD
10
12
15
15
20
20
ns
Minimum Set-up, tS
5.5
6
8
8
10
10
ns
Maximum Clock to Output[1], tCO
6.5
7
8
8
10
10
ns
75
125
75
mA
Typical Supply Current, ICC
125
125
125
Note:
1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
Cypress Semiconductor Corporation
Document #: 38-03031 Rev. *A
•
3901 North First Street
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San Jose, CA 95134
•
408-943-2600
Revised April 19, 2004
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CY7C374i
Pin Configurations
I/O 63
I/O 62
I/O
61
I/O 60
I/O
59
I/O
58
I/O
57
I/O
56
GND
I/O55
I/O54 /SDI
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I 4
GND
VCCIO
CLK2/I 3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I/O26 /SMODE
I/O27
I/O28
I/O29
I/O30
I/O31
I2
VCCIO
GND
VCCINT
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38 /SDO
I/O39
GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
72
14
71
15
70
16
69
17
68
18
67
19
66
20
65
21
64
22
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
I/O24
I/O25
I/O8
I/O9
I/O10 /SCLK
I/O11
I/O12
I/O13
I/O14
I/O15
CLK0/I 0
VCCIO
GND
CLK1/I 1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O 2
I/O 1
I/O 0
VCCIO
GND
VCCINT
ISREN
GND
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
PLCC
Top View
PGA
Bottom View
Document #: 38-03031 Rev. *A
L
I/O23
I/O25
I/O26 I/O28
SMODE
I/O31
I/O33
VCC
I/O34
I/O36
I/O37
I/O39
K
I/O21
GND
I/O24
I/O30
I2
I/O32
I/O35
I/O38
SDO
GND
I/O41
J
I/O20
I/O22
I/O29
VCC
GND
I/O40
I/O42
H
I/O18
I/O19
I/O43
I/O44
G
CLK1
/ I1
I/O16
GND
CLK2
/I3
I/O46
I/O47
F
I/O17
CLK0
/I0
VCC
VCC
I/O45
GND
E
I/O15
I/O14
I/O13
I/O49
I/O48
CLK3
/I4
D
I/O12
I/O11
I/O51
I/O50
C
I/O10
SCLK
I/O8
I/O54
SDI
I/O52
B
I/O9
GND
I/O6
A
I/O7
I/O5
1
2
I/O27
I/O1
VCC
ISREN
I/O3
I/O0
I/O61
I/O62
I/O59
I/O56
GND
I/O53
I/O4
I/O2
VCC
GND
I/O63
I/O60
I/O58
I/O57
I/O55
3
4
5
6
8
9
10
11
7
Page 2 of 15
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CY7C374i
Pin Configurations (continued)
I/O 62
I/O
61
I/O 60
I/O 59
I/O
58
I/O
57
I/O
56
GND
NC
I/O 63
VCCINT
NC
GND
ISREN
I/O 0
VCCIO
I/O 4
I/O 3
I/O 2
I/O 1
NC
VCCIO
I/O
7
I/O 6
I/O 5
TQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SCLK
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CLK0/I0
VCCIO
N/C
GND
CLK1/I1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
VCCIO
NC
SDI
VCCIO
I/O55
I/O54
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I4
GND
NC
VCCIO
CLK2/I3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
GND
NC
SDO
VCCIO
NC
GND
VCCINT
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38
I/O39
VCCIO
I/O30
I/O31
I2
SMODE
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Document #: 38-03031 Rev. *A
I/O 63
I/O 62
I/O
61
I/O 60
I/O
59
I/O
58
I/O
57
I/O
56
GND
I/O55
I/O54 /SDI
I/O53
I/O52
I/O51
I/O50
I/O49
I/O48
CLK3/I 4
GND
VCC
CLK2/I 3
I/O47
I/O46
I/O45
I/O44
I/O43
I/O42
I/O41
I/O40
I/O26 /SMODE
I/O27
I/O28
I/O29
I/O30
I/O31
I2
VCC
GND
VCC
I/O32
I/O33
I/O34
I/O35
I/O36
I/O37
I/O38 /SDO
I/O39
GND
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75
74
12
73
13
72
14
71
15
70
16
69
17
68
18
67
19
66
20
65
21
64
22
63
23
62
24
61
25
60
26
59
27
58
28
57
29
56
30
55
31
54
47
48 49 50 51 52 53
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
I/O24
I/O25
I/O8
I/O9
I/O10 /SCLK
I/O11
I/O12
I/O13
I/O14
I/O15
CLK0/I 0
VCC
GND
CLK1/I 1
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O 2
I/O 1
I/O 0
VCC
GND
VCC
ISREN
GND
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
CLCC
Top View
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Functional Description
The logic blocks in the FLASH370i architecture are connected
with an extremely fast and predictable routing resource—the
Programmable Interconnect Matrix (PIM). The PIM brings
flexibility, routability, speed, and a uniform delay to the interconnect.
Like all members of the FLASH370i family, the CY7C374i is rich
in I/O resources. Every two macrocells in the device feature
an associated I/O pin, resulting in 64 I/O pins on the
CY7C374i. In addition, there is one dedicated input and four
input/clock pins.
Finally, the CY7C374i features a very simple timing model.
Unlike other high-density CPLD architectures, there are no
hidden speed delays such as fanout effects, interconnect
delays, or expander delays. Regardless of the number of
resources used or the type of application, the timing parameters on the CY7C374i remain the same.
Logic Block
The number of logic blocks distinguishes the members of the
FLASH370i family. The CY7C374i includes eight logic blocks.
Each logic block is constructed of a product term array, a
product term allocator, and 16 macrocells.
Product Term Array
The product term array in the FLASH370i logic block includes
36 inputs from the PIM and outputs 86 product terms to the
product term allocator. The 36 inputs from the PIM are
available in both positive and negative polarity, making the
overall array size 72 x 86. This large array in each logic block
allows for very complex functions to be implemented in single
passes through the device.
Product Term Allocator
The product term allocator is a dynamic, configurable resource
that shifts product terms to macrocells that require them. Any
number of product terms between 0 and 16 inclusive can be
assigned to any of the logic block macrocells (this is called
product term steering). Furthermore, product terms can be
shared among multiple macrocells. This means that product
terms that are common to more than one output can be implemented in a single product term. Product term steering and
product term sharing help to increase the effective density of
the FLASH370i CPLDs. Note that product term allocation is
handled by software and is invisible to the user.
CY7C374i
whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent
directly to the PIM regardless of its configuration.
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) connects the
eight logic blocks on the CY7C374i to the inputs and to each
other. All inputs (including feedbacks) travel through the PIM.
There is no speed penalty incurred by signals traversing the
PIM.
Programming
For an overview of ISR programming, refer to the FLASH370i
Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of
ISR capabilities, refer to the Cypress application note, “An
Introduction to In System Reprogramming with FLASH370i.”
PCI Compliance
The FLASH370i family of CMOS CPLDs are fully compliant with
the PCI Local Bus Specification published by the PCI Special
Interest Group. The simple and predictable timing model of
FLASH370i ensures compliance with the PCI AC specifications
independent of the design. On the other hand, in CPLD and
FPGA architectures without simple and predictable timing, PCI
compliance is dependent upon routing and product term distribution.
3.3V or 5.0V I/O Operation
The FLASH370i family can be configured to operate in both
3.3V and 5.0V systems. All devices have two sets of VCC pins:
one set, VCCINT, for internal operation and input buffers, and
another set, VCCIO, for I/O output drivers. VCCINT pins must
always be connected to a 5.0V power supply. However, the
VCCIO pins may be connected to either a 3.3V or 5.0V power
supply, depending on the output requirements. When VCCIO
pins are connected to a 5.0V source, the I/O voltage levels are
compatible with 5.0V systems. When VCCIO pins are
connected to a 3.3V source, the input voltage levels are
compatible with both 5.0V and 3.3V systems, while the output
voltage levels are compatible with 3.3V systems. There will be
an additional timing delay on all output buffers when operating
in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is
available in commercial and industrial temperature ranges.
Bus Hold Capabilities on all I/Os and Dedicated Inputs
Half of the macrocells on the CY7C374i have I/O pins
associated with them. The input to the macrocell is the sum of
between 0 and 16 product terms from the product term
allocator. The I/O macrocell includes a register that can be
optionally bypassed, polarity control over the input sum-term,
and two global clocks to trigger the register. The macrocell
also features a separate feedback path to the PIM so that the
register can be buried if the I/O pin is used as an input.
In addition to ISR capability, a new feature called bus-hold has
been added to all FLASH370i I/Os and dedicated input pins.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device’s performance. As a latch, bus-hold
recalls the last state of a pin when it is three-stated, thus
reducing system noise in bus-interface applications. Bus-hold
additionally allows unused device pins to remain unconnected
on the board, which is particularly useful during prototyping as
designers can route new signals to the device without cutting
trace connections to VCC or GND.
Buried Macrocell
Design Tools
The buried macrocell is very similar to the I/O macrocell.
Again, it includes a register that can be configured as combinatorial, as a D flip-flop, a T flip-flop, or a latch. The clock for
this register has the same options as described for the I/O
macrocell. One difference on the buried macrocell is the
addition of input register capability. The user can program the
buried macrocell to act as an input register (D-type or latch)
Development software for the CY7C371i is available from
Cypress’s Warp™, Warp Professional™, and Warp Enterprise™ software packages. Please refer to the data sheets on
these products for more details. Cypress also actively
supports almost all third-party design tools. Please refer to
third-party tool support for further information.
I/O Macrocell
Document #: 38-03031 Rev. *A
Page 4 of 15
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Maximum Ratings
CY7C374i
Output Current into Outputs ........................................ 16 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
Range
Ambient
Temperature
DC Voltage Applied to Outputs
in High-Z State ............................................... –0.5V to +7.0V
Commercial
0°C to +70°C
DC Input Voltage............................................ –0.5V to +7.0V
Industrial
−40°C to +85°C
Military[2]
–55°C to +125°C 5V ± 0.5V
DC Program Voltage .....................................................12.5V
VCC VCCINT
VCCIO
5V ± 0.25V 5V ± 0.25V or
3.3V ± 0.3V
5V ± 0.5V
5V ± 0.5V or
3.3V ± 0.3V
Electrical Characteristics Over the Operating Range[3, 4]
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VOHZ
Output HIGH Voltage with VCC = Max.
Output Disabled[9]
VCC = Min.
Min.
IOH = –3.2 mA (Com’l/Ind)[5]
Typ.
Max.
2.4
Unit
V
IOH = –2.0 mA (Mil)
V
IOH = 0 µA (Com’l/Ind)[5, 6]
4.0
V
IOH = –50 µA (Com’l/Ind)[5, 6]
3.6
V
IOL = 16 mA (Com’l/Ind)[5]
0.5
V
VOL
Output LOW Voltage
VCC = Min.
VIH
Input HIGH Voltage
Guaranteed Input Logical HIGH voltage for all inputs[7]
2.0
inputs[7]
IOL = 12 mA (Mil)
V
7.0
V
VIL
Input LOW Voltage
Guaranteed Input Logical LOW voltage for all
–0.5
0.8
V
IIX
Input Load Current
VI = Internal GND, VI = VCC
–10
+10
µA
IOZ
Output Leakage Current
VCC = Max., VO = GND or VO = VCC, Output Disabled
–50
VCC = Max., VO = 3.3V, Output Disabled[6]
IOS
Output Short
Circuit Current[8, 9]
ICC
Power Supply Current
VCC = Max., VOUT = 0.5V
0
–70
–30
+50
µA
–125
µA
–160
mA
VCC = Max., IOUT = 0 mA,
Com’l/Ind.
125
200
mA
f = 1 MHz, VIN = GND, VCC[10]
Com’l “L” –66
75
125
mA
125
250
mA
Military
IBHL
Input Bus Hold LOW
Sustaining Current
VCC = Min., VIL = 0.8V
+75
µA
IBHH
Input Bus Hold HIGH
Sustaining Current
VCC = Min., VIH = 2.0V
–75
µA
IBHLO
Input Bus Hold LOW
Overdrive Current
VCC = Max.
+500
µA
IBHHO
Input Bus Hold HIGH
Overdrive Current
VCC = Max.
–500
µA
Notes:
2. TA is the “instant on” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT.
5. IOH = –2 mA, IOL = 2 mA for SDO.
6. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly
by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note “Understanding Bus Hold” for additional
information.
7. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
8. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test
problems caused by tester ground degradation.
9. Tested initially and after any design or process changes that may affect these parameters.
10. Measured with 16-bit counter programmed into each logic block.
Document #: 38-03031 Rev. *A
Page 5 of 15
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CY7C374i
Capacitance[9]
Parameter
CI/O
Description
[11, 12]
CCLK
Test Conditions
Input Capacitance
VIN = 5.0V at f = 1 MHz
Clock Signal Capacitance
VIN = 5.0V at f = 1 MHz
Min.
Max.
Unit
8
pF
5
12
pF
Inductance[9]
Parameter
L
Description
Maximum Pin Inductance
Test Conditions
100-PinTQFP 84-Lead PLCC 84-Lead CLCC Unit
VIN = 5.0V at f = 1 MHz
8
8
5
nH
Endurance Characteristics[9]
Parameter
N
Description
Maximum Reprogramming Cycles
Test Conditions
Max.
Unit
Normal Programming Conditions
100
Cycles
AC Test Loads and Waveforms
238Ω (COM'L)
319Ω (MIL)
238Ω (COM'L)
319Ω (MIL)
5V
5V
OUTPUT
90%
170Ω (COM'L)
236Ω (MIL)
OUTPUT
35 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
OUTPUT
170Ω (COM'L)
236Ω (MIL)
ALL INPUT PULSES
3.0V
5 pF
GND
90%
10%
10%
<2ns
INCLUDING
JIG AND
(b)
SCOPE
<2ns
(c)
THÉVENIN EQUIVALENT
99Ω (COM'L)
136Ω (MIL) 2.08V (COM'L)
2.13V (MIL)
Parameter[13]
VX
tER(–)
1.5V
Output Waveform Measurement Level
VOH
–0.5V
tER(+)
2.6V
–0.5V
VX
VX
VOH
tEA(+)
1.5V
–0.5V
VOH
VX
tEA(–)
Vthc
VX
–0.5V
VOH
Notes:
11. CI/O for the CLCC package are 12 pF Max
12. CI/O for dedicated Inputs, and for I/O pins with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max.
13. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Document #: 38-03031 Rev. *A
Page 6 of 15
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CY7C374i
Switching Characteristics Over the Operating Range [14]
Parameter
Description
7C374i–125
7C374i–100
7C374i–83
7C374iL–83
7C374i–66
7C374iL–66
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
10
12
15
20
ns
tPDL
Input to Output Through Transparent Input or
Output Latch[1]
13
15
18
22
ns
tPDLL
Input to Output Through Transparent Input and
Output Latches[1]
15
16
19
24
ns
tEA
Input to Output Enable[1]
14
16
19
24
ns
tER
Input to Output Disable
14
16
19
24
ns
Input Registered/Latched Mode Parameters
tWL
Clock or Latch Enable Input LOW Time[9]
tWH
Clock or Latch Enable Input HIGH
Time[9]
3
3
4
5
ns
tIS
Input Register or Latch Set-Up Time
2
2
3
4
ns
tIH
Input Register or Latch Hold Time
2
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
14
16
19
24
ns
tICOL
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch[1]
16
18
21
26
ns
3
3
4
2
5
3
ns
4
ns
Output Registered/Latched Mode Parameters
tCO
Clock or Latch Enable to Output[1]
tS
Set-Up Time from Input to Clock or Latch Enable
tH
Register or Latch Data Hold Time
tCO2
Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1]
tSCS
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
8
10
12
15
ns
tSL
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
10
12
15
20
ns
tHL
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
0
0
0
0
ns
fMAX1
Maximum Frequency with Internal Feedback
(Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[9]
125
100
83
66
MHz
fMAX2
Maximum Frequency Data Path in Output
Registered/Latched Mode (Lesser of 1/(tWL +
tWH), 1/(tS + tH), or 1/tCO)
158.3
143
125
100
MHz
fMAX3
Maximum Frequency with External Feedback
(Lesser of 1/(tCO + tS) and 1/(tWL + tWH))
83.3
76.9
67.5
50
MHz
tOH–tIH
37x
Output Data Stable from Output Clock Minus
Input Register Hold Time for 7C37x[9, 15]
0
0
0
0
ns
6.5
5.5
7
6
0
0
14
8
8
0
16
10
10
0
19
ns
ns
ns
24
ns
Pipelined Mode Parameters
tICS
Input Register Clock to Output Register Clock
8
10
12
15
ns
fMAX4
Maximum Frequency in Pipelined Mode (Least
of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),
or 1/tSCS)
125
100
83.3
66.6
MHz
Notes:
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03031 Rev. *A
Page 7 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Switching Characteristics Over the Operating Range (continued)[14]
Parameter
Description
7C374i–125
7C374i–100
7C374i–83
7C374iL–83
7C374i–66
7C374iL–66
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Unit
Reset/Preset Parameters
tRW
Asynchronous Reset Width[9]
10
12
15
20
ns
tRR
Asynchronous Reset Recovery Time[9]
12
14
17
22
ns
[1]
tRO
Asynchronous Reset to Output
tPW
Asynchronous Preset Width[9]
10
16
tPR
Asynchronous Preset Recovery Time[9]
12
tPO
Asynchronous Preset to Output[1]
18
12
14
16
21
15
17
18
26
20
22
21
ns
ns
ns
26
ns
Tap Controller Parameter
fTAP
Tap Controller Frequency
500
500
500
500
kHz
3.3V I/O Mode Parameters
t3.3IO
3.3V I/O mode timing adder
1
1
1
1
ns
Switching Waveforms
Combinatorial Output
INPUT
tPD
COMBINATORIAL
OUTPUT
Registered Output
INPUT
tH
tS
CLOCK
tCO
REGISTERED
OUTPUT
tWH
tWL
CLOCK
Latched Output
INPUT
tS
tH
LATCH ENABLE
tPDL
tCO
LATCHED
OUTPUT
Document #: 38-03031 Rev. *A
Page 8 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Switching Waveforms (continued)
Registered Input
REGISTERED
INPUT
tIH
tIS
INPUT REGISTER
CLOCK
tICO
COMBINATORIAL
OUTPUT
tWH
tWL
CLOCK
Latched Input
LATCHED INPUT
tIH
tIS
LATCH ENABLE
tICO
tPDL
COMBINATORIAL
OUTPUT
tWH
tWL
LATCH ENABLE
Latched Input and Output
LATCHED INPUT
tPDLL
LATCHED
OUTPUT
tICOL
tSL
tHL
INPUT LATCH
ENABLE
tICS
OUTPUT LATCH
ENABLE
tWH
tWL
LATCH ENABLE
Document #: 38-03031 Rev. *A
Page 9 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Switching Waveforms (continued)
Asynchronous Reset
tRW
INPUT
tRO
REGISTERED
OUTPUT
tRR
CLOCK
Asynchronous Preset
tPW
INPUT
tPO
REGISTERED
OUTPUT
tPR
CLOCK
Output Enable/Disable
INPUT
tER
tEA
OUTPUTS
Ordering Information
Speed
(MHz)
125
100
83
Ordering Code
Package
Name
CY7C374i–125AC
A100
CY7C374i–125JC
J83
CY7C374i–100AC
A100
CY7C374i–100JC
J83
CY7C374i–100AI
A100
CY7C374i–100JI
J83
Package Type
100-Pin Thin Quad Flat Pack
Commercial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
Commercial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
Industrial
84-Lead Plastic Leaded Chip Carrier
CY7C374i–83AC
A100
CY7C374i–83JC
J83
CY7C374i–83AI
A100
CY7C374i–83JI
J83
CY7C374i–83GMB
G84
84-Pin Ceramic Pin Grid Array
CY7C374i–83YMB
Y84
84-Pin Ceramic Leaded Chip Carrier
CY7C374iL–83AC
A100
100-Pin Thin Quad Flat Pack
CY7C374iL–83JC
J83
Document #: 38-03031 Rev. *A
Operating
Range
100-Pin Thin Quad Flat Pack
Commercial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
Industrial
84-Lead Plastic Leaded Chip Carrier
Military
Commercial
84-Lead Plastic Leaded Chip Carrier
Page 10 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Ordering Information
Speed
(MHz)
66
Ordering Code
Package
Name
Operating
Range
Package Type
CY7C374i–66AC
A100
CY7C374i–66JC
J83
100-Pin Thin Quad Flat Pack
CY7C374i–66AI
A100
CY7C374i–66JI
J83
CY7C374i–66GMB
G84
84-Pin Ceramic Pin Grid Array
CY7C374i–66YMB
Y84
84-Pin Ceramic Leaded Chip Carrier
CY7C374iL–66AC
A100
100-Pin Thin Quad Flat Pack
CY7C374iL–66JC
J83
Commercial
84-Lead Plastic Leaded Chip Carrier
100-Pin Thin Quad Flat Pack
Industrial
84-Lead Plastic Leaded Chip Carrier
Military
Commercial
84-Lead Plastic Leaded Chip Carrier
MILITARY SPECIFICATIONS
Group A Subgroup Testing
Switching Characteristics
DC Characteristics
tPD
9, 10, 11
tPDL
9, 10, 11
9, 10, 11
Parameter
Subgroups
Parameter
Subgroups
VOH
1, 2, 3
tPDLL
VOL
1, 2, 3
tCO
9, 10, 11
VIH
1, 2, 3
tICO
9, 10, 11
VIL
1, 2, 3
tICOL
9, 10, 11
IIX
1, 2, 3
tS
9, 10, 11
IOZ
1, 2, 3
tSL
9, 10, 11
1, 2, 3
tH
9, 10, 11
tHL
9, 10, 11
tIS
9, 10, 11
tIH
9, 10, 11
tICS
9, 10, 11
tEA
9, 10, 11
tER
9, 10, 11
ICC1
Document #: 38-03031 Rev. *A
Page 11 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Package Diagrams
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-*B
Document #: 38-03031 Rev. *A
Page 12 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Package Diagrams (continued)
84-Pin Grid Array (Cavity Up) G84
51-80015-*A
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
Document #: 38-03031 Rev. *A
Page 13 of 15
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Package Diagrams (continued)
84-Pin Ceramic Leaded Chip Carrier Y84
51-80095-*A
ISR, UltraLogic, FLASH370, FLASH370i, Warp, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are trademarks of their respective holders.
Document #: 38-03031 Rev. *A
Page 14 of 15
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
USE ULTRA37000™ FOR
ALL NEW DESIGNS
CY7C374i
Document History Page
Document Title: CY7C374i UltraLogic™ 128-Macrocell Flash CPLD
Document Number: 38-03031
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106376
07/11/01
SZV
Changed from Spec number: 38-00496 to 38-03031
*A
213375
See ECN
FSG
Added note to title page: “Use Ultra37000 For All New Designs”
Document #: 38-03031 Rev. *A
Page 15 of 15
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