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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN73932 Half-Bridge Gate Drive IC Features Description Floating Channel for Bootstrap Operation to +600V The FAN73932 is a half-bridge, gate-drive IC with shutdown and dead-time functions which can drive highspeed MOSFETs and IGBTs that operate up to +600V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction. Typically 2.5A/2.5A Sourcing/Sinking Current Driving Capability Extended Allowable Negative VS Swing to -9.8V for Signal Propagation at VBS=15V High-Side Output in Phase of IN Input Signal 3.3V and 5V Input Logic Compatible Matched Propagation Delay for Both Channels Built-in Shutdown Function Built-in UVLO Functions for Both Channels Built-in Common-Mode dv/dt Noise Canceling Circuit Internal 400ns Minimum Dead-Time Fairchild’s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8V (typical) for VBS=15V. The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage. Applications High-Speed Power MOSFET and IGBT Gate Driver Induction Heating The high-current and low-output voltage drop feature makes this device suitable for all kinds of half- and fullbridge inverters, like motor drive inverter, switching mode power supply, induction heating, and high-power DC-DC converter applications. High-Power DC-DC Converter Synchronous Step-Down Converter Motor Drive Inverter 8-SOP Ordering Information Part Number FAN73932M FAN73932MX Package Operating Temperature Range 8-SOP -40°C to +125°C Eco Status RoHS Packing Method Tube Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com FAN73932 — Half-Bridge Gate Drive IC February 2010 FAN73932 — Half-Bridge Gate Drive IC Typical Application Diagrams Up to 600V +15V PWM PWM IC Shutdown Control 1 IN VB 8 2 SD HO 7 3 COM VS 6 DBOOT CBOOT Load RBOOT 4 LO VDD 5 +15V Figure 1. Typical Application Circuit Internal Block Diagram 8 VB UVLO 1 200K NOISE CANCELLER R DRIVER IN PULSE GENERATOR HS(ON/OFF) R S Q 6 SCHMITT TRIGGER INPUT VS 5 VDD UVLO 5V 7 HO SHOOT THOUGH PREVENTION DEAD-TIME { 400ns } DELAY LS(ON/OFF) DRIVER SD 2 4 LO 3 COM Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com FAN73932 — Half-Bridge Gate Drive IC Pin Configuration 1 SD 2 COM 3 LO 4 FAN73932 IN 8 VB 7 HO 6 VS 5 VDD Figure 3. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 IN Logic Input for High-Side and Low-Side Gate Driver Output, In-Phase with HO 2 SD Logic Input for Shutdown 3 COM 4 LO Low-Side Driver Return 5 VDD Supply Voltage Ground 6 VS High-Voltage Floating Supply Return 7 HO High-Side Driver Output 8 VB High-Side Floating Supply © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C unless otherwise specified. Symbol Parameter Min. Max. Unit VB High-Side Floating Supply Voltage -0.3 625.0 V VS High-Side Floating Offset Voltage VB-25.0 VB+0.3 V VHO High-Side Floating Output Voltage VS-0.3 VB+0.3 V VLO Low-Side Output Voltage -0.3 VDD+0.3 V VDD Low-Side and Logic Fixed Supply Voltage -0.3 25.0 V VIN Logic Input Voltage (IN) -0.3 VDD+0.3 V VSD Logic Input Voltage (SD) -0.3 5.5 V COM Logic Ground and Low-Side Driver Return VDD-25.0 VDD+0.3 V dVS/dt Allowable Offset Voltage Slew Rate ± 50 V/ns PD Power Dissipation(1, 2, 3) 0.625 W θJA Thermal Resistance 200 °C/W TJ Junction Temperature +150 °C TSTG Storage Temperature +150 °C -55 Notes: 1. 2. Mounted on 76.2 x 114.3 x 1.6mm PCB (FR-4 glass epoxy material). Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection; JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages Do not exceed PD under any circumstances. 3. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit VB High-Side Floating Supply Voltage VS+10 VS+20 V VS High-Side Floating Supply Offset Voltage 6-VDD 600 V VHO High-Side Output Voltage VS VB V VDD Low-Side and Logic Fixed Supply Voltage 10 20 V VLO Low-Side Output Voltage COM VDD V VIN Logic Input Voltage (IN) COM VDD V VSD TA Logic Input Voltage (SD)(4) Operating Ambient Temperature COM 5 V -40 +125 °C Note: 4. Shutdown (SD) input is internally clamped with 5.2V. © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com FAN73932 — Half-Bridge Gate Drive IC Absolute Maximum Ratings VBIAS(VDD, VBS)=15.0V, COM=0V, and TA = 25°C, unless otherwise specified. The VIN and IIN parameters are referenced to COM and are applicable to the respective input leads: IN and SD. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO and LO. Symbol Parameter Test Condition Min. Typ. Max. Unit POWER SUPPLY SECTION IQDD Quiescent VDD Supply Current VIN=0V, SD=5V 320 700 μA IQBS Quiescent VBS Supply Current VIN=0V or 5V, SD=5V 50 120 μA IPDD Operating VDD Supply Current fIN=20KHz, No Load, SD=5V 700 1300 μA IPBS Operating VBS Supply Current CL=1nF, fIN=20KHz, rms, SD=5V 420 800 μA ISD Shutdown mode Supply Current SD=0V, SD=5V 400 800 µA ILK Offset Supply Leakage Current VB=VS=600V 10 μA BOOTSTRAPPED SUPPLY SECTION VDDUV+ VBSUV+ VDD and VBS Supply Under-Voltage Positive Going Threshold Voltage VDD =VBS=Sweep 8 9 10 V VDDUVVBSUV- VDD and VBS Supply Under-Voltage Negative Going Threshold Voltage VDD =VBS=Sweep 7.4 8.4 9.4 V VDD and VBS Supply Under-Voltage Lockout Hysteresis Voltage VDD=VBS=Sweep VDDUVHVBSUVH 0.6 V INPUT LOGIC SECTION VIH Logic “1” Input Voltage for HO & Logic “0” for LO 2.5 VIL Logic “0” Input Voltage for HO & Logic “1” for LO IIN+ Logic Input High Bias Current VIN=5V, SD=0V IIN- Logic Input Low Bias Current VIN=0V, SD=5V RIN Logic Input Pull-Down Resistance 25 Shutdown (SD) input Positive-Going Threshold SD- Shutdown (SD) input Negative-Going Threshold RPSD 0.8 V 60 μA 3 μA 200 VSDCLAMP Shutdown (SD) Input Clamping Voltage SD+ V 5.0 KΩ 5.5 V 0.8 V 2.5 Shutdown (SD) Input Pull-Up Resistance V 200 KΩ GATE DRIVER OUTPUT SECTION VOH High-level Output Voltage (VBIAS - VO) No Load 1.5 V VOL Low-level Output Voltage No Load 100 mV IO+ Output High, Short-Circuit Pulsed Current(5) VHO=0V, VIN=5V, PW ≤10µs 2.0 2.5 A IO- Output Low, Short-Circuit Pulsed Current(5) VHO=15V,VIN=0V, PW ≤10µs 2.0 2.5 A VS Allowable Negative VS Pin Voltage for IN Signal Propagation to HO -9.8 -7.0 V Note: 5 These parameters guaranteed by design. © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com FAN73932 — Half-Bridge Gate Drive IC Electrical Characteristics VBIAS(VDD, VBS)=15.0V, COM=0V, CL=1000pF, and TA=25°C, unless otherwise specified. Symbol tON Parameter Conditions (6) Turn-On Propagation Delay Time VS=0V tOFF Turn-Off Propagation Delay Time VS=0V tSD Shutdown Propagation Delay Time Min. Typ. Max. Unit 600 850 ns 200 350 ns 140 220 ns MtON Delay Matching, HO and LO Turn-On 0 50 ns MtOFF Delay Matching, HO and LO Turn-Off 0 50 ns tR Turn-On Rise Time VS=0V 25 50 ns tF Turn-Off Fall Time VS=0V 20 35 ns DT Dead-Time: LO Turn-Off to HO Turn-On and HO Turn-Off to LO Turn-On 400 500 ns 0 50 ns MDT Dead-time matching=|DTLO-HO - DTHO-LO| 300 Note: 6. The turn-on propagation delay time included dead-time. © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com FAN73932 — Half-Bridge Gate Drive IC Dynamic Electrical Characteristics 280 800 750 240 tOFF [ns] tON [ns] 700 650 600 550 200 160 120 500 80 450 400 -40 -20 0 20 40 60 80 100 40 -40 120 -20 0 Temperature [°C] Figure 4. Turn-On Propagation Delay vs. Temperature 40 60 80 100 120 Figure 5. Turn-Off Propagation Delay vs. Temperature 30 50 40 20 tF [ns] tR [ns] 20 Temperature [°C] 30 10 20 0 10 0 -40 -20 0 20 40 60 80 100 -10 -40 120 -20 0 40 60 80 100 120 Figure 7. Turn-Off Fall Time vs. Temperature 30 30 20 20 MTOFF [ns] MTON [ns] Figure 6. Turn-On Rise Time vs. Temperature 10 0 -10 -20 -40 20 Temperature [°C] Temperature [°C] 10 0 -10 -20 0 20 40 60 80 100 -20 -40 120 Temperature [°C] 0 20 40 60 80 100 120 Temperature [°C] Figure 8. Turn-On Delay Matching vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 -20 Figure 9. Turn-Off Delay Matching vs. Temperature www.fairchildsemi.com 7 FAN73932 — Half-Bridge Gate Drive IC Typical Characteristics 300 500 250 tSD [ns] DT [ns] 550 450 200 400 150 350 100 300 -40 -20 0 20 40 60 80 100 50 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 10. Dead-Time vs. Temperature Figure 11. Shutdown Propagation Delay vs. Temperature 120 400 IQBS [μA] IQDD [μA] 100 350 80 60 40 300 20 250 -40 -20 0 20 40 60 80 100 0 -40 120 -20 0 1200 1000 1000 800 800 400 400 200 0 20 40 60 80 100 0 -40 120 80 100 120 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 14. Operating VDD Supply Current vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 60 600 600 -20 40 Figure 13. Quiescent VBS Supply Current vs. Temperature IPBS [μA] IPDD [μA] Figure 12. Quiescent VDD Supply Current vs. Temperature 200 -40 20 Temperature [°C] Temperature [°C] Figure 15. Operating VBS Supply Current vs. Temperature www.fairchildsemi.com 8 FAN73932 — Half-Bridge Gate Drive IC Typical Characteristics (Continued) 9.5 9.5 9.0 VDDUV- [V] VDDUV+ [V] 10.0 9.0 8.0 8.5 8.0 -40 8.5 -20 0 20 40 60 80 100 7.5 -40 120 -20 0 Figure 16. VDD UVLO+ vs. Temperature 40 60 80 100 120 Figure 17. VDD UVLO- vs. Temperature 10.5 10.0 10.0 9.5 VBSUV- [V] VBSUV+ [V] 20 Temperature [°C] Temperature [°C] 9.5 9.0 9.0 8.5 8.0 8.5 8.0 -40 7.5 -20 0 20 40 60 80 100 7.0 -40 120 -20 0 Temperature [°C] 20 40 60 80 100 120 Temperature [°C] Figure 18. VBS UVLO+ vs. Temperature Figure 19. VBS UVLO- vs. Temperature 2.0 1.0 1.8 0.8 1.6 0.6 VOL [V] 1.4 VOH [V] 1.2 1.0 0.4 0.2 0.8 0.0 0.6 0.4 -0.2 0.2 -0.4 0.0 -40 -20 0 20 40 60 80 100 -40 120 Figure 20. High-Level Output Voltage vs. Temperature © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 -20 0 20 40 60 80 100 120 Temperature [°C] Temperature [°C] Figure 21. Low-Level Output Voltage vs. Temperature www.fairchildsemi.com 9 FAN73932 — Half-Bridge Gate Drive IC Typical Characteristics (Continued) 3.0 3.0 2.5 VIL [V] VIH [V] 2.5 2.0 2.0 1.5 1.5 1.0 1.0 -40 -20 0 20 40 60 80 100 0.5 -40 120 -20 0 Temperature [°C] 50 -8 40 -9 30 -11 10 -12 0 20 40 60 60 80 100 120 -10 20 -20 40 Figure 23. Logic Low Input Voltage vs. Temperature VS [V] IIN+ [μA] Figure 22. Logic High Input Voltage vs. Temperature 0 -40 20 Temperature [°C] 80 100 -13 -40 120 Temperature [°C] -20 0 20 40 60 80 100 120 Temperature [°C] Figure 24. Logic Input High Bias Current vs. Temperature Figure 25. Allowable Negative VS Voltage vs. Temperature . © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com 10 FAN73932 — Half-Bridge Gate Drive IC Typical Characteristics (Continued) FAN73932 — Half-Bridge Gate Drive IC Switching Time Definitions SD 1 IN VB 8 2 SD HO 7 +15V HO 10uF LO 3 COM 4 LO VS 6 VDD 5 100nF 1nF +15V 1nF 10uF 100nF Figure 26. Switching Time Test Circuit IN HO LO SD DT1 DT2 DT1 DT2 Shutdown DT2 Shutdown DT1 DT1 DT2 Figure 27. Input/Output Timing Diagram IN 50% 50% tOFF tR tON tR 90% 90% LO 10% tON 10% tR 90% 90% HO 10% tOFF tF 10% Figure 28. Switching Time Waveform Definition © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com FAN73932 — Half-Bridge Gate Drive IC 50% SD tSD 90% HO or LO Figure 29. Shutdown Waveform Definition IN 50% 50% tOFF DTHO-LO 90% LO 10% DTLO-HO 90% HO tOFF 10% MDT= DTLO-HO - DTHO-LO Figure 30. Dead-Time Waveform Definition IN(LO) 50% 50% 50% 50% IN(HO) MToff LO HO MTon 10% 90% 90% 10% Figure 31. Delay Matching Waveform Definition © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com 5.00 4.80 A 0.65 3.81 8 5 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 CB A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.25 0.10 1.75 MAX 0.25 0.19 C 0.51 0.33 0.50 x 45 0.25 R0.10 0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 0.36 OPTION B - NO BEVEL EDG E NOTES: UNLESS OTHERWI SE SPECIFIED 8 0 0.90 0.406 SEATI NG PLANE (1.04) DETAIL A SCALE: 2: 1 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIO NS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FI LENAME: M08AREV13 Figure 32. 8-Lead Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2008 Fairchild Semiconductor Corporation FAN73932 • Rev. 1.0.1 www.fairchildsemi.com FAN73932 — Half-Bridge Gate Drive IC Mechanical Dimensions FAN73932 — Half-Bridge Gate Drive IC © 2008 Fairchild Semiconductor Corporation FAN73932 Rev. 1.0.1 www.fairchildsemi.com 14 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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