Exar MP7651AS 8-channel, voltage output 10 mhz input bandwidth 8-bit multiplying dacs with serial digital data port and chip select decoder Datasheet

MP7651
8-Channel, Voltage Output
10 MHz Input Bandwidth 8-Bit Multiplying
DACs with Serial Digital Data Port
and Chip Select Decoder
FEATURES
• 8 Independent 2-Quadrant Multiplying 8-Bit DACs
• Serial Digital Input Data and Address Port (3-Wire
Standard) plus Internal Chip Address Decoder
• Dual Supplies (+5 V typ.)
• High Speed:
– 12.5 MHz Digital Clock Rate
– VREF to VOUT Settling Time: 150ns to
8-bit (typ)
– Voltage Reference Input Bandwidth:
10 MHz (typ)
• Low Power: 150mW (typ)
• Low AC Voltage Reference Feedthrough
• Excellent Channel-to-Channel Isolation
• DNL = +0.8 LSB, INL = +1 LSB (typ)
• DACs Matched to +0.5% (typ)
• Low Harmonic Distortion: 0.25% typical
with VREF = 1 V p-p @ 1 MHz
• VREF/2 Output Preset Level
• Latch-Up Proof
• Greater than 2000 V ESD Protection
APPLICATIONS
• ATE
• Process Control (Low Noise)
• Convergence Adjustment for High
Resolution Monitors (Work Stations)
• Digital Gain/Attenuation/Offset Control
• Trimmer Replacement
GENERAL DESCRIPTION
fast output settling time, and VREF feedthrough isolation of
–65dB or better. In addition, low distortion in the order of 0.25%
with a 1 V p–p, 1 MHz signal.
The MP7651 is ideal for direct gain control of video, composite video, CCD and other high frequency analog signals. The device includes 8-channels of high speed, high bandwidth, two
quadrant, multiplying, 8-bit accurate digital-to-analog converter.
It includes an output drive buffer per channel capable of driving
+1mA (typ) to a load. DNL of better than +0.8 LSB is achieved
with a channel-to-channel matching of better than 0.5%. Stability, matching, and precision of the DACs is achieved by using
EXAR’s thin film technology. Also, excellent channel-to-channel
isolation is achieved with EXAR’s BiCMOS process which cannot be achieved using a typical CMOS technology.
A specified and constant input impedance of each VREF+ input gives flexibility for optimal system design. The serial data
3-wire standard µ-processor logic interface reduces pin count,
package size (28 pin), and board wire (space). Additionally, the
internal chip select decoder allows for easy daisy chaining without the addition of separate control logic.
MP7651 is fabricated on a junction isolated, high speed, dual
metal, linear compatible BiCMOS (BiCMOS IVTM) thin film resistors. This process enables precision high speed analog/digital
(mixed-mode) circuits to be fabricated on the same chip.
An open loop architecture (patent pending) provides wide
small signal bandwidth from VREF to output up to 10 MHz (typ),
Rev. 2.00
1
MP7651
SIMPLIFIED BLOCK DIAGRAM
VCC
VR0
RST
8
8-Bit Latch
+1
DAC 0
VO0
VR1
8
8-Bit Latch
DAC 1
VO1
+1
VR7
8
8-Bit Latch
VO7
+1
DAC 7
8
8
LD
LD
8
LD
1-Bit
Latch
CLK
LD
DB0 to DB7
COMP
4
4-Bit CH
Address
4
4-Bit CS
Address
4
3-State
Buffer
VEE
GND
ORDERING INFORMATION
Package
Type
Temperature
Range
Part No.
INL
(LSB)
DNL
(LSB)
Gain Error
(% FSR)
SOIC
–40 to +85°C
MP7651AS
+1
+0.8
+1.5
Plastic Dip
–40 to +85°C
MP7651AN
+1
+0.8
+1.5
Rev. 2.00
2
CS0P to
CS3P
SDO
16-Bit Shift Register
1-Bit
Latch
SDI
8
4-8 DEC
MP7651
PIN CONFIGURATIONS
See Packaging Section for
Package Dimensions
VR1
VO1
VO2
VR2
VR3
VO3
VCC
VEE
GND
VO4
VR4
VR5
VO5
VO6
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VR0
VO0
CS3P
CS2P
RST
LD
CLK
SDO
SDI
CS1P
CSOP
VO7
VR7
VR6
VR1
VO1
VO2
VR2
VR3
VO3
VCC
VEE
GND
VO4
VR4
VR5
VO5
VO6
28 Pin PDIP (0.300”)
NN28
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
VR0
VO0
CS3P
CS2P
RST
LD
CLK
SDO
SDI
CS1P
CSOP
VO7
VR7
VR6
28 Pin SOIC (EIAJ, 0.335”)
R28
PIN OUT DEFINITIONS
PIN NO.
NAME
DESCRIPTION
PIN NO.
NAME
DESCRIPTION
1
VR1
DAC 1 Reference Input
16
VR7
DAC 7 Reference Input
2
VO1
DAC 1 Output
17
VO7
DAC 7 Output
3
VO2
DAC 2 Output
18
CSOP
Chip Select Bit 0 (LSB)
4
VR2
DAC 2 Reference Input
19
CS1P
Chip Select Bit 1
5
VR3
DAC 3 Reference Input
20
SDI
Serial Data/Address Input
6
VO3
DAC 3 Output
21
SDO
Serial Data Output
7
VCC
Positive Supply
22
CLK
Shift Register Clock
8
VEE
Negative Supply
23
LD
9
GND
Ground
Load Signal; Load Data
to Selected DACs
10
VO4
DAC 4 Output
24
RST
Reset Signal; Reset all DACs to
VREF/2
11
VR4
DAC 4 Reference Input
25
CS2P
Chip Select Bit 2
12
VR5
DAC 5 Reference Input
26
CS3P
Chip Select Bit 3 (MSB)
13
VO5
DAC 5 Output
27
VO0
DAC 0 Output
14
VO6
DAC 6 Output
28
VR0
DAC 0 Reference Input
15
VR6
DAC 6 Reference Input
Rev. 2.00
3
MP7651
ELECTRICAL CHARACTERISTICS TABLE
Unless Otherwise Noted: VCC = +5 V, VEE = –5 V and –3 V, VREF = 3 V and –3 V, T = 25°C,
Output Load = Open
Parameter
25°C
Typ
Symbol
Min
N
DNL
INL
8
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
DC CHARACTERISTICS
Resolution (All Grades)
Differential Non-Linearity
Integral Non-Linearity
Monotonicity
Gain Error
Zero Scale Offset
Output Drive Capability
8
+0.8
+1
+1
+1
+1.5
+75
Guaranteed
+1.5
+75
Guaranteed
GE
+20
+1
ZOFS
IO
Bits
LSB
LSB
% FSR
mV
mA
FSR = Full Scale Range (1)
REFERENCE INPUTS
Impedance of VREF
Voltage Range
REF
VR
6
VEE +1.5
12
18
VCC–1.8
6
18
V
kΩ
VREF
DYNAMIC
CHARACTERISTICS2
Input to Output Bandwidth
Input to Output Settling Time5
Small Signal Voltage Reference
Input to Output Bandwidth
Small Signal Voltage Reference
Input to Output Bandwidth
Voltage Settling from VREF to
VDAC Out
Voltage Settling from Digital
Code to VDAC Out
VREF Feedthrough
Group Delay
Harmonic Distortion
Channel-to-Channel Crosstalk
Digital Feedthrough
Power Supply
Rejection Ratio
Max Swing is AGND +3 V
RL = 5 k, CL = 20 pF
ƒtr
ƒtr
5
10
150
10
MHz
ns
MHz
VR = 1.6 V p–p, RL = 5k to VEE
VR = 1.6 V p–p, RL = 5k to VEE
VOUT=50mV p-p above code 16
8
MHz
VOUT=50mV p-p for all codes
VR=0 to VR = 3V Step (6)
to 1 LSB
ZS to FS to 1 LSB
tsr
275
300
325
ns
tsd
275
300
325
ns
FDT
GD
THD
CT
Q
PSRR
–65
20
0.5
–75
ICC
IEE
15
15
150
dB
ns
%
dB
nVs
%/%
VREF=1MHz Sine 3V p-p
@ 1 MHz, single channel
CLK to VOUT
∆ V = +5%
30
30
300
mA
mA
mW
VREF = 0 V
VREF = 0 V
VREF = 0 V, Codes = all 1
0.8
+10
8
V
V
µA
pF
1
0.02
Codes=0 @ 1 MHz
POWER CONSUMPTION
Positive Supply Current
Negative Supply Current
Power Dissipation
PDISS
25
25
250
DIGITAL INPUT
CHACTERISTICS
Logic High3
Logic Low3
Input Current
Input Capacitance2
VIH
VIL
IL
CL
2.4
2.4
0.8
+10
8
Rev. 2.00
4
MP7651
ELECTRICAL CHARACTERISTICS TABLE
Description
25°C
Typ
Max
Tmin to Tmax
Min
Max
Symbol
Min
Units
tCH, tCL
tDS
tDH
tPD
tLD
tRST
tCKLD1
tCKLD2
tHZ1
40
10
15
100
50
100
0
50
100
60
100
0
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHZ2
35
50
ns
tLDCK1
tLDCK2
tLDSU
25
35
15
40
50
20
ns
ns
ns
tCSLD
25
35
ns
Conditions
DIGITAL TIMING
SPECIFICATIONS2, 4
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
DAC Register Load Pulse Width
Reset Pulse Width
Clock Edge to Load Rising Edge
Clock Edge to Load Falling Edge
Load Falling Edge to SDO
3-state Enable
Load Rising Edge to SDO
3-state Disable
Load Falling Edge to CLK Disable
Load Rising Edge to CLK Enable
LD Set-up Time with Respect
to CLK
CS0-CS3 Set-Up Time with
Respect to LD
50
10
15
40
50
NOTES:
1
Full Scale Range (FSR) is 3V.
2
Guaranteed but not production tested.
3
Digital Input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.
4
See Figures 2 and 3.
5
For reference input pulse: tR = tF > 100 ns.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25°C unless otherwise noted)1, 2
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.5 V
VEE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 V
VRi to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to VEE
VOi to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC to VEE
Digital Input & Output Voltage
to GND . . . . . . . . . . . . . . . . . . . . GND –0.5 to VCC +0.5 V
Operating Temperature Range
Extended Industrial . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
Package Power Dissipation Rating @ 75°C
PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000mW
Derates above 75°C . . . . . . . . . . . . . . . . . . . . . . 6mW/°C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short
transients outside the supplies of less than 100mA for less than 100µs.
APPLICATIONS INFORMATION
Refer to Section 8 for Applications Information
Rev. 2.00
5
MP7651
SDI
(Data In)
CLK
LD
1
0
CS3S CS2S CS1S CS0S
A3
A2
A1
A0
D7
D6
D0
1
0
1
0
DAC Register
Loaded
VOUT
Figure 1. Serial Data Timing and Loading
tDS
SDI
1
0
SDO
tDH
tHZ2
tHZ1
1
HIGH Z
0
tCSLD
tPD
CSOP-CS3P
1
0
tCH
CLK
0
tCL
LD
tLDCK2
tLDSU
1
1
tCKLD2
tCKLD1
tLDCK1
0
tLD
+5 V
VOUT
0V
tSD
+ 1/2 LSB BAND
Figure 2. Detail Serial Data Input Timing (RST = “1”)
RST
1
tRST
0
tSD
VO = VREF
VO = VREF/2
+ 1/2 LSB ERROR BAND
Figure 3. RESET Operation
Rev. 2.00
6
MP7651
THEORY OF OPERATION
MP7651 is equipped with a serial data 3-wire standard µprocessor logic interface to reduce pin count, package size (28
pin), and board wire (space). This interface consists of LD which
controls the transfer of data to the selected DAC channel, SDI
(serial data/address input), CLK (shift register clock) and SDO
(serial data output). When the LD signal is high, CLK signal
loads the digital input bits (SDI) into the 16-bit shift register (8 bits
data D7 to D0, plus 4 bits address A3 to A0, and 4 bits of Chip
Select data CS0S to CS3S). If the CS0S to CS3S in the shift register match the parallel chip-select address (CS0P to CS3P) for
the selected chip, then the LD signal going low loads the data
Function
X
X
CS0S CS1S CS2S CS3S
LD
A3 A2 A1 A0
X
into the selected DAC of that chip. The LD signal going low also
disables the serial data input (SDI), output (SDO 3-stated) and
the CLK input. This design tremendously reduces digital noise,
and glitch transients into the DACs due to free running CLK and
SDI. Also, 3-stating the SDO output with LD signal would allow
read back of pre-stored digital data of the selected package using one SDO wire for all DAC ICs on the board. Note also that
the reset signal (RST) resets all analog outputs to 1/2 of VREF,
regardless of any digital inputs. Also note that the input VRi is
referenced to GND.
X
Shift Data In
and Out
X
1
Stop Shifting
Data In and
Out
X
X
X
X
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
No Operation
1→0
1→0
1→0
1→0
1→0
1→0
1→0
1→0
No Operation
1
1
1
1
1
1
0
1
No Operation
No Operation
Reset all DACs X
to VREF/2
X
X
X
X
X
X
X
CLK
RST
SDI
SDO
0→1
1
Data Input
Data Output
X
1
X
Hi-Z
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
1
1
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
1
X
X
Hi-Z
Hi-Z
X
0
X
X
Repeat
Load DACs
DAC 0
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
X
X
X
X
Matched with 4 parallel
chip select data
CS0P to CS3P
X
X
X
X
Table 1. Digital Function Truth Table
Serial In/Serial Out
D0 DAC Output Voltage
D
LSB VOi = AGND + (VRi – AGND) ( 256 )
D7
MSB
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
254
(VRi – AGND) ( 256 ) + AGND
1
1
1
1
1
1
1
1
255
(VRi – AGND) ( 256 ) + AGND
AGND
1
(VRi – AGND) ( 256 ) + AGND
Table 2. DAC Transfer Function
Analog Output vs. Digital Code
Rev. 2.00
7
MP7651
8
ENABLE DAC
NOT USED
LD
8
8
4 To 16
Decoder
CS3P
CS2P
CS1P
CS0P
3-STATE
SDI
LAT
D Q
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
CS0S
CS1S CS2S
CS3S
SDO
E
EN
LD
CLK
LAT
D Q
EN
LD
Figure 4. Internal Chip Address Decoder Plus Logic Interface
Rev. 2.00
8
MP7651
ADDRESS BUS
A0 to A23
AS
CS
4
ADDRESS
DECODER
VMA
MC68000
CLK
LD
CS0P to CS3P
VPA
SDI
1/4 7HC125
MP7651
RST
VDS
DB0
FROM SYSTEM RESET
16
DB0 to DB15
16
DATA BUS
Figure 5. MC68000 Interface (Simplified Diagram)
16
A0 to A15
16
ADDRESS BUS
3
A0 to A2
E1
MC6800
02
E3
R/W
E2
DB0 to DB7
74LS138
ADDRESS
DECODER
8
4
8
DATA BUS
LD
DB7
SDI
CLK CS0P to CS3P
MP7651
RST
FROM SYSTEM RESET
NOTES:
1. Execute consecutive memory write instructions while manipulating the data between WRITEs so that
each WRITE presents the next bit
2. The serial data loading is triggered by the CLK pulse which is asserted by a decoded memory WRITE
location 2000, R/W, and 02. A WRITE to address 4000 transfers data from the input shift register to the
DAC register.
Figure 6. MC6800 Interface (Simplified Diagram)
Rev. 2.00
9
MP7651
APPLICATION NOTES
VRI1
VRI2
VOI1
8
8
µPC
VOI2
8
VOI16
8
8
MP7651
MP7651
MP7651
IC (1)
IC (2)
IC (16)
CS1P
SDI
VRI16
8
CS1P
SDO
LD
SDI
LD
CS1P
SDO
4
SDI
LD
SDO
4
4
DATA
4
CS0P-CS3P
LD
CLK
Figure 7. Simplified Diagram
Configuration A
VRI1
VOI1
8
VRI2
8
VOI2
8
8
MP7651
LD
8
MP7651
IC (2)
CSIP
SDI
8
MP7651
IC (1)
µPC
VOIn
VRIn
IC (n)
CSIP
SDO
SDI
LD
4
CSIP
SDO
4
SDI
4
DATA
4
n
#2
#1
CS OR LD
CLK
Figure 8. Simplified Diagram
Configuration B
Rev. 2.00
10
SDO
4
DATA OUT
CS0P-CS3P
LD
#n
MP7651
SDO0
ROW ADDRESS
SDO1
SDOE
SDOF
SDI
WR
n
ADDRESS
DECODER
2n
3
2
1
7651
4
0
SDO
7651
4
LD SDI
1
SDO
7651
4
LD SDI
SDO
LD SDI
LD SDI
F
SDO
E
SDO
4
LD SDI
F
SDO
LD SDI
Figure 9. Simplified Diagram
Configuration C
Rev. 2.00
11
SDO
LD SDI
LD SDI
7651
4
E
LD SDI
7651
4
7651
1
SDO
LD SDI
7651
7651
4
0
7651
4
E
SDO
4
1
SDO
7651
4
LD SDI
7651
4
0
SDO
7651
4
F
SDO
LD SDI
CLK
MP7651
ADDRESS BUS
8
8
8085
3
+5 V
8212
ALE
E1
E3
E2
WR
A0 to A2
74LS138
ADDRESS
DECODER
DATA BUS
8
SOD
LD CLK CS0P to CS3P
SDI
MP7651
RST
NOTES:
FROM SYSTEM RESET
1. Clock generated by WR and decoding address 8000
2. Data is clocked into the DAC shift register by executing memory write instructions. The clock input is
generated by decoding address 8000 and WR. Data is then loaded into the DAC register with a memory
write instruction to address 4000.
3. Serial data must be present in the right justified format in registers H & L of the microprocessor.
Figure 10. 8085 Interface (Simplified Diagram)
MP7651 EVALUATION BOARD
Measurement
Buffer
1.6 Vp–p
5 pF
1k
Test Load
DUT
VR0 VO0
20 pF
5k
VR1 VO1
VR2 VO2
VR3 VO3
VR4 VO4
VR5 VO5
VR6 VO6
VR7 VO7
N/C
SDI
SDO
CLK
LD
RST
N/C
VOUT
DGND
MP7651
All resistors = 50 Ω unless otherwise specified
Gain of all DACs set to 1 (no attenuation)
Figure 1. Crosstalk Measurement Set-Up
Rev. 2.00
12
MP7651
PERFORMANCE CHARACTERISTICS
Channel-to-Channel Crosstalk (Gain vs. Frequency; All DACs set to full scale; VREF=1.6 Vp-p)
Output DACs shown below are:
DAC 7, 1, 2, 5, 6, 3 and 4
Output DACs shown below are:
DAC 2, 0, 3, 4, 7, 5 and 6
dB
dB
DAC 2
DAC 7
DAC 0 Driven
MHz
DAC 1 Driven
Graph 1.
Output DACs shown below are:
DAC 1, 3, 4, 5, 0, 6 and 7
Output DACs shown below are:
DAC 4, 2, 1, 7, 0, 5 and 6
DAC 1
dB
MHz
Graph 2.
dB
DAC 4
DAC 2 Driven
MHz
DAC 3 Driven
Graph 3.
MHz
Graph 4.
Output DACs shown below are:
DAC 5, 3, 6, 7, 0, 1 and 2
Output DACs shown below are:
DAC 6, 4, 7, 0, 3, 1 and 2
DAC 6
dB
dB
DAC 5
DAC 4 Driven
MHz
DAC 5 Driven
Graph 5.
Output DACs shown below are:
DAC 5, 7, 0, 4, 3, 1 and 2
Output DACs shown below are:
DAC 0, 6, 5, 4, 3, 1 and 2
DAC 5
dB
MHz
Graph 6.
dB
DAC 0
DAC 6 Driven
MHz
DAC 7 Driven
Graph 7.
MHz
Graph 8.
Rev. 2.00
13
MP7651
Digital Input Code
Digital Input Code
Graph 9. Linearity Error vs.
Digital Input Code
DACs 0 to 3
Graph 10. Linearity Error
vs. Digital Input Code
DACs 4 to 7
Graph 11. Preset Voltage vs. Temperature
VR = 500 mV p-p
Graph 12. PSRR vs. Frequency
Phase
VR = 1.6 V p-p
Gain
Graph 13. Gain & Phase vs. Frequency
Graph 14. Feedthrough vs. Frequency
Rev. 2.00
14
MP7651
VR = 6 V p-p
3 V p-p
1.5 V p-p
1 V p-p
0.5 V p-p
Graph 15. Gain (VO/VR) vs. Frequency
Open Loop/Unloaded Output*
Graph 16. THD vs. Frequency
Graph 17. ICC vs. Temperature
Graph 18. IEE vs. Temperature
A
GE = +1.5% FSR
VRR Positive
All DACs driven, measured DAC
@ zero scale and other DACs
@ full scale
B
VRR Negative
All DACs except monitored
driven, all DACs @ full scale
–V
Graph 19. Reference Input Voltage
Range vs. Supply Voltages
Graph 20. All Channel
Crosstalk vs. Frequency
* A 2K or 5K resistor across output and VEE will remove peaking (See graph 26).
Rev. 2.00
15
MP7651
LD
(5 V/DIV)
VR
(2 V/DIV)
VR = 3 V
Digital Code =
255→0→255
Digital Code =
All Ones
VO
(2 V/DIV)
VO
(2 V/DIV)
2µs/DIV
2µs/DIV
Graph 21. Digital Settling
Graph 22. Pulse Response
(tR = tF = 100 ns for VR)
VR
(2 V/DIV)
LD
(5 V/DIV)
VO
(2 V/DIV)
VO
(10mV/DIV)
2µs/DIV
2µs/DIV
Graph 23. 128 kHz
Sawtooth Waveform Response
Graph 24. Clock and SDI
Feedthrough
LD
(5 V/DIV)
Gain
(5 dB/DIV)
VO
(10mV/DIV)
Group Delay
(20 ns/DIV)
MHz
2µs/DIV
Graph 25. Clock/SDI
Feedthrough
Graph 26. Typical Gain and Group
Delay vs. Frequency (with 5K resistor
across output to VEE)
Rev. 2.00
16
MP7651
28 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
NN28
S
28
15
1
14
Q1
E1
E
D
A1
Seating
Plane
A
L
B
e
B1
α
MILLIMETERS
INCHES
SYMBOL
MIN
MAX
MIN
MAX
A
0.130
0.230
3.30
5.84
A1
0.015
––
0.381
––
B
0.014
0.023
0.356
0.584
B1 (1)
0.038
0.065
0.965
1.65
C
0.008
0.015
0.203
0.381
D
1.340
1.485
34.04
37.72
E
0.290
0.325
7.37
8.26
E1
0.240
0.310
6.10
7.87
e
0.100 BSC
L
0.115
α
0.150
2.54 BSC
2.92
3.81
0°
15°
0°
15°
Q1
0.055
0.070
1.40
1.78
S
0.020
0.100
0.508
2.54
Note:
(1)
The minimum limit for dimensions B1 may be 0.023”
(0.58 mm) for all four corner leads only.
Rev. 2.00
17
C
MP7651
28 LEAD SMALL OUTLINE
(335 MIL EIAJ SOIC)
R28
D
28
15
E
1
H
14
C
A
Seating
Plane
e
B
A1
L
MILLIMETERS
SYMBOL
A
A1
MIN
2.60
INCHES
MAX
MIN
2.80
0.102
0.2 (typ.)
MAX
0.110
0.008 (typ.)
B
0.3
0.5
0.012
0.020
C
0.10
0.20
0.004
0.008
D
17.6
18.0
0.693
0.709
E
8.3
8.5
0.327
0.335
e
1.27 (typ.)
0.050 (typ.)
H
11.5
12.1
0.453
0.477
L
0.8
1.2
0.031
0.047
Rev. 2.00
18
MP7651
Notes
Rev. 2.00
19
MP7651
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 1993 EXAR Corporation
Datasheet April 1995
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00
20
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