FK Series Crystal Clock Oscillator (XO) 3.2 x 2.5mm FK 1.8V CMOS Low Jitter XO Package: 3.2 x 2.5mm Ceramic SMD Recommended Land Pattern: Product Features •1 to 156.25 MHz Frequency Range •<1 ps RMS jitter •1.8V CMOS compatible logic levels •Designed for standard reflow and washing techniques CREATED USING CADSTD LITE FREEWARE FROM WWW.CADSTD.COM. NON-COMMERCIAL USE ONLY. •Low power standby mode •Pb-free and RoHS/Green compliant Pin Functions: Pin Function Product Description 1 OE The FK Series 1.8V crystal clock oscillator achieves superb stability and low power consumption over a broad range of operating conditions and frequencies. The low jitter output clock signal, generated internally with a non-PLL oscillator design, is compatible with LVCMOS logic levels. The device, available on tape and reel, is contained in a 3.2 x 2.5mm surface-mount ceramic package. 2 Ground 3 Clock Output 4 V DD CREATED USING CADSTD LITE FREEWARE FROM WWW.CADSTD.COM. NON-COMMERCIAL USE ONLY. Applications Ideal for compact, high-density applications requiring low power or tight stability, including: •Network adapter cards •Portable Multimedia Devices •Hard Disk Drives Part Ordering Information: UM FK XXX YYYY YYYY = Specification�Code XXX = Frequency�Code Product�Family •GPS/Navigation •Bluetooth •802.11a/b/g WiFi SaRonix-eCera™ is a Pericom® Semiconductor company • US: +1-408-435-0800 TW: +886-3-4518888 15-0086 All specifications are subject to change without notice. • www.saronix-ecera.com FK 1.8V REV2015 1 1.8V CMOS Low Jitter XO FK FK Series Crystal Clock Oscillator (XO) 3.2 x 2.5mm Electrical Performance Parameter Min. Output Frequency Typ. 1 Supply Voltage 1.62 1.8 Max. Units 156.25 MHz 1.98 V Notes As specified 4 7 Supply Current, Output Enabled 10 1 to 36 MHz 36 to 50 MHz mA 50 to 70 MHz 20 Supply Current, Standby Mode Frequency Stability Operating Temperature Range Output Logic 1, VOH 10 µA Output Hi-Z ±20 to ±50 ppm See Note 1 below -20 +70 -40 +85 Output Logic 0, VOL 70 to 156.25 MHz 10% V DD V 15 pF 90% V DD Industrial (standard) V Output Load Duty Cycle Commercial (standard) °C 55 % Measured 50% V DD Rise and Fall Time 45 5 ns Measured 10/90% of waveform Jitter, Phase 1 to 156.25 MHz 1 ps RMS (1-σ) 12kHz to 20 MHz frequency band Jitter, Accumulated up to 75 MHz 5 75 to 156.25 MHz 3 ps RMS (1-σ) 20.000 adjacent periods Jitter, Total up to 75 MHz 50 75 to 156.25 MHz 30 ps pk-pk 100.000 random periods Notes: 1. Stability includes all combinations of operating temperature, load changes, rated input (supply) voltage changes, initial calibration tolerance (25°C), aging (1 year at 25°C average effective ambient temperature), shock and vibration. 2. For specifications othere than those listed, please contact sales. Output Enable / Disable Function Parameter Min. Input Voltage (pin 1), Output Enable Typ. Max. 0.7 V DD Input Voltage (pin 1), Output Disable (low power standby) 0.3 V DD Internal Pullup Resistance 50 Units Notes V or open V Output is Hi-Z kΩ Output Disable Delay 200 ns Output Enable Delay 10 ms Absolute Maximum Ratings Parameter Min. Storage Temperature -55 For the latest product information visit: For test circuit go to: Typ. Max. Units +125 °C Notes http://www.pericom.com/products/timing/oscillators/FK1.8/ http://www.pericom.com/pdf/sre/tc_hcmos2.pdf For soldering reflow profile and reliability test ratings go to: http://www.pericom.com/pdf/sre/reflow.pdf For tape and reel information go to: http://www.pericom.com/pdf/sre/tr_3225_xo.pdf SaRonix-eCera™ is a Pericom® Semiconductor company • US: +1-408-435-0800 TW: +886-3-4518888 15-0086 All specifications are subject to change without notice. • www.saronix-ecera.com FK 1.8V REV2015 2