Cypress CY7C4261-15JC 16k/32k x 9 deep sync fifo Datasheet

CY7C4261
CY7C4271
16K/32K x 9 Deep Sync FIFOs
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — ICC = 35 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
• TTL-compatible
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
D2
D3
D4
D5
D6
D7
D8
REN1
RCLK
REN2
OE
WRITE
CONTROL
EF
FF
Q0
Q1
Q2
READ
CONTROL
OE
24
WEN1
D0
2
23
WCLK
PAF
3
22
WEN2/LD
PAE
4
21
GND
5
REN1
6
19
VCC
Q8
Q7
RCLK
7
18
Q6
REN2
8
17
Q5
CY7C4261
CY7C4271
3901 North First Street
20
•
Q3
Q4
Q2
9 10 11 12 13 14 15 16
RCLK REN1 REN2
•
D6
1
OE
Cypress Semiconductor Corporation
Document #: 38-06015 Rev. *B
D5
D1
Q1
Q0 − 8
D4
32 31 30 29 28 27 26 25
RESET
LOGIC
THREE-STATE
OUTPUT REGISTER
D3
D2
READ
POINTER
TQFP
Top View
Q0
RS
RAM
ARRAY
16K x 9
32K x 9
EF
PAE
PAF
FF
FF
FLAG
LOGIC
RS
FLAG
PROGRAM
REGISTER
RS
WEN1
WCLK
WEN2/LD
VCC
Q8
Q7
Q6
Q5
Q3
Q4
WCLK WEN1 WEN2/LD
4 3 2 1 32 31 30
29
5
28
6
27
7
8
CY7C4261 26
9
25
CY7C4271 24
10
11
23
12
22
21
13
14 15 16 17 18 19 20
D8
D1
D0
PAF
PAE
GND
D7
INPUT
REGISTER
WRITE
POINTER
PLCC/LCC
Top View
Pin Configuration
D0 − 8
EF
Logic Block Diagram
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
San Jose, CA 95134
•
408-943-2600
Revised August 21, 2003
CY7C4261
CY7C4271
Functional Description (continued)
The CY7C4261/71 provides four status pins: Empty, Full,
Programmable Almost Empty, and Programmable Almost Full.
The Almost Empty/Almost Full flags are programmable to
single word granularity. The programmable flags default to
Empty+7 and Full–7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Pin Definitions
Signal Name
Description
I/O
Description
D0−8
Data Inputs
I
Data Inputs for 9-bit bus.
Q0−8
Data Outputs
O
Data Outputs for 9-bit bus.
WEN1
Write Enable 1
I
The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF
is HIGH. If the FIFO is configured to have two write enables, data is written on a
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
WEN2/LD
Dual Mode Pin
Write Enable 2
I
If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
REN1, REN2
Read Enable
Inputs
I
Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
WCLK
Write Clock
I
The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable
flag-offset register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and
the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the programmable flag-offset register.
Load
EF
Empty Flag
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
FF
Full Flag
O
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
PAE
Programmable
Almost Empty
O
When PAE is LOW, the FIFO is almost empty based on the almost empty offset
value programmed into the FIFO. PAE is synchronized to RCLK.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
RS
Reset
I
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Selection Guide
Maximum Frequency
7C4261/71-10
7C4261/71-15
7C4261/71-25
7C4261/71-35
Unit
100
66.7
40
28.6
MHz
Maximum Access Time
8
10
15
20
ns
Minimum Cycle Time
10
15
25
35
ns
Minimum Data or Enable Set-up
3
4
6
7
ns
Minimum Data or Enable Hold
0.5
1
1
2
ns
Maximum Flag Delay
8
10
15
20
ns
Active Power Supply Commercial
Current (ICC1)
Industrial/
Military
35
35
35
35
mA
40
40
40
40
Document #: 38-06015 Rev. *B
Page 2 of 18
CY7C4261
CY7C4271
CY7C4261
CY7C4271
Density
16K × 9
32K × 9
Package
32-pin PLCC,TQFP
32-pin
LCC,PLCC,TQFP
Architecture
The CY7C4261/71 consists of an array of 16K to 32K words
of nine bits each (implemented by a dual-port array of SRAM
cells), a read pointer, a write pointer, control signals (RCLK,
WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF,
FF).
Resetting the FIFO
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs (Q0−8) go LOW tRSF after the rising
edge of RS. In order for the FIFO to reset to its default state, a falling
edge must occur on RS and the user must not read or write while RS
is LOW. All flags are guaranteed to be valid tRSF after RS is taken
LOW.
FIFO Operation
When the WEN1 signal is active LOW, WEN2 is active HIGH, and
FF is active HIGH, data present on the D0−8 pins is written into the
FIFO on each rising edge of the WCLK signal. Similarly, when the
REN1 and REN2 signals are active LOW and EF is active HIGH, data
in the FIFO memory will be presented on the Q0−8 outputs. New data
will be presented on each rising edge of RCLK while REN1 and
REN2 are active. REN1 and REN2 must set up tENS before RCLK
for it to be a valid read function. WEN1 and WEN2 must occur tENS
before WCLK for it to be a valid write function.
An output enable (OE) pin is provided to three-state the Q0−8
outputs when OE is asserted. When OE is enabled (LOW), data in
the output register will be available to the Q0−8 outputs after tOE. If
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and underflow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0−8 outputs even
after additional reads occur.
Write Enable 1 (WEN1). If the FIFO is configured for programmable flags, Write Enable 1 (WEN1) is the only write enable
control pin. In this configuration, when Write Enable 1 (WEN1)
is LOW, data can be loaded into the input register and RAM
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored is the RAM array sequentially and
independently of any on-going read operation.
Write Enable 2/Load (WEN2/LD). This is a dual-purpose pin.
The FIFO is configured at Reset to have programmable flags
or to have two write enables, which allows for depth
expansion. If Write Enable 2/Load (WEN2/LD) is set active
HIGH at Reset (RS = LOW), this pin operates as a second
write enable pin.
If the FIFO is configured to have two write enables, when Write
Enable (WEN1) is LOW and Write Enable 2/Load (WEN2/LD) is
HIGH, data can be loaded into the input register and RAM
Document #: 38-06015 Rev. *B
array on the LOW-to-HIGH transition of every write clock
(WCLK). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
Programming
When WEN2/LD is held LOW during Reset, this pin is the load (LD)
enable for flag offset programming. In this configuration, WEN2/LD
can be used to access the four 8-bit offset registers contained in the
CY7C4261/71 for writing or reading data to these registers.
When the device is configured for programmable flags and
both WEN2/LD and WEN1 are LOW, the first LOW-to-HIGH
transition of WCLK writes data from the data inputs to the empty offset
least significant bit (LSB) register. The second, third, and fourth
LOW-to-HIGH transitions of WCLK store data in the empty offset
most significant bit (MSB) register, full offset LSB register, and full
offset MSB register, respectively, when WEN2/LD and WEN1 are
LOW. The fifth LOW-to-HIGH transition of WCLK while WEN2/LD
and WEN1 are LOW writes data to the empty LSB register again.
Figure 1 shows the registers sizes and default values for the various
device types.
16K × 9
8
32K × 9
0
7
8
Empty Offset (LSB) Reg.
Default Value = 007h
Empty Offset (LSB) Reg.
Default Value = 007h
0
5
8
0
7
(MSB)
000000
8
(MSB)
0000000
0
7
8
Full Offset (LSB) Reg
Default Value = 007h
8
0
7
Full Offset (LSB) Reg
Default Value = 007h
0
5
0
6
8
8
(MSB)
000000
0
6
(MSB)
0000000
Figure 1. Offset Register Location and Default Values
It is not necessary to write to all the offset registers at one time.
A subset of the offset registers can be written; then by bringing
the WEN2/LD input HIGH, the FIFO is returned to normal read and
write operation. The next time WEN2/LD is brought LOW, a write
operation stores data in the next offset register in sequence.
The contents of the offset registers can be read to the data
outputs when WEN2/LD is LOW and both REN1 and REN2 are
LOW. LOW-to-HIGH transitions of RCLK read register
contents to the data outputs. Writes and reads should not be
performed simultaneously on the offset registers.
Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as
described in Table 1 or the default values are used, the
programmable almost-empty flag (PAE) (PAF) states are determined by their corresponding offset registers and the
difference between the read and write pointers.
Page 3 of 18
CY7C4261
CY7C4271
The number formed by the empty offset least significant bit
register and empty offset most significant bit register is
referred to as n and determines the operation of PAE. PAF is
synchronized to the LOW-to-HIGH transition of RCLK by one
flip-flop and is LOW when the FIFO contains n or fewer unread
words. PAE is set HIGH by the LOW-to-HIGH transition of
RCLK when the FIFO contains (n+1) or greater unread words.
Table 1. Writing the Offset Registers
LD
WEN
0
0
Selection
WCLK[1]
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
1
No Operation
1
0
Write Into FIFO
1
1
No Operation
The number formed by the full offset least significant bit
register and full offset most significant bit register is referred to
as m and determines the operation of PAF. PAE is synchronized
to the LOW-to-HIGH transition of WCLK by one flip-flop and is
set LOW when the number of unread words in the FIFO is
greater than or equal to CY7C4261 (16K-m) and CY7C4271
(32K-m). PAF is set HIGH by the LOW-to-HIGH transition of
WCLK when the number of available memory locations is
greater than m.
Table 2. Status Flags
Number of Words in FIFO
CY7C4261
0
CY7C4271
0
[2]
PAF
PAE
EF
H
H
L
L
H
H
L
H
(n+1) to (16384 − (m+1))
(n+1) to (32768 − (m+1))
H
H
H
H
(16384 −
(32768 −
H
L
H
H
L
L
H
H
1 to n
1 to
n[2]
FF
m)[3] to 16383
16384
m)[3] to 32767
32768
Width-Expansion Configuration
Flag Operation
Word width may be increased simply by connecting the corresponding input controls signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and PAF)
can be detected from any one device. Figure 2 demonstrates
a 18-bit word width by using two CY7C4261/71s. Any word
width can be attained by adding additional CY7C4261/71s.
The CY7C4261/71 devices provide four flag pins to indicate
the condition of the FIFO contents. Empty, Full, PAE, and PAF
are synchronous.
When the CY7C4261/71 is in a Width-Expansion Configuration, the Read Enable (REN2) control input can be grounded
(see Figure 2). In this configuration, the Write Enable 2/Load
(WEN2/LD) pin is set to LOW at Reset so that the pin operates
as a control to load and read the programmable flag offsets.
Full Flag
The Full Flag (FF) will go LOW when the device is full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN1 and WEN2/LD. FF is synchronized to WCLK, i.e.,
it is exclusively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN1 and REN2. EF is synchronized
to RCLK, i.e., it is exclusively updated by each rising edge of
RCLK.
Note:
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06015 Rev. *B
Page 4 of 18
CY7C4261
CY7C4271
RESET (RS)
DATA IN (D) 18
RESET (RS)
9
9
READ CLOCK (RCLK)
WRITECLOCK (WCLK)
READ ENABLE 1 (REN1)
WRITE ENABLE 1(WEN1)
OUTPUT ENABLE (OE)
WRITE ENABLE 2/LOAD
(WEN2/LD)
CY7C4261/71
CY7C4261/71
PROGRAMMABLE(PAF)
PROGRAMMABLE(PAE)
EMPTY FLAG (EF) #1
EMPTY FLAG (EF) #2
FULL FLAG (FF) # 1
FF
FF
EF
EF
9
FULL FLAG (FF) # 2
DATA OUT (Q)
18
9
Read Enable 2 (REN2)
Read Enable 2 (REN2)
Figure 2. Block Diagram of 16K × 18/32K × 18 Deep Sync FIFO Memory Used in a Width-Expansion Configuration
Document #: 38-06015 Rev. *B
Page 5 of 18
CY7C4261
CY7C4271
Maximum Ratings[4]
DC Input Voltage..........................................−0.5V to Vcc+0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ....................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................... −55°C to +125°C
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current...................................................... >200 mA
Operating Range
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Range
Ambient Temperature
VCC
DC Voltage Applied to Outputs
in High-Z State ............................................−0.5V to VCC + 0.5V
Commercial
0°C to +70°C
5V ± 10%
Industrial[5]
−40°C to +85°C
5V ± 10%
Military
−55°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range[6]
7C4261/71− 10 7C4261/71− 15 7C4261/71− 25 7C4261/71− 35
Parameter
Description
Test Conditions
Min.
Max.
Min.
Max.
Min.
Max.
VOH
Output HIGH Voltage VCC = Min.,
IOH = −2.0 mA
VOL
Output LOW Voltage
VIH
Input HIGH Voltage
(comm./ind.)
2.0
VCC
2.0
VCC
2.0
VCC
VIH
Input HIGH Voltage
(military)
2.2
VCC
2.2
VCC
2.2
VIL
Input LOW Voltage
−0.5
0.8
−0.5
0.8
IIX
Input Leakage Current VCC = Max.
−10
+10
−10
+10
IOZL
IOZH
Output OFF,
High Z Current
−10
+10
−10
+10
ICC1[7]
Active Power Supply
Current
Com’l
35
35
Ind/Mil
40
40
Average Standby
Current
Com’l
10
10
Ind/Mil
15
15
ISB[8]
2.4
VCC = Min.,
IOL = 8.0 mA
OE > VIH,
VSS < VO< VCC
2.4
0.4
Min.
2.4
0.4
Max.
2.4
Unit
V
0.4
0.4
V
2.0
VCC
V
VCC
2.2
VCC
V
−0.5
0.8
−0.5
0.8
V
−10
+10
−10
+10
µA
−10
+10
−10
+10
µA
35
35
mA
40
40
mA
10
10
mA
15
15
mA
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
AC Test Loads and
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
5
pF
7
pF
Waveforms[10, 11]
R11.1KW
5V
OUTPUT
INCLUDING CL
JIG AND
SCOPE
ALL INPUT PULSES
3.0V
R2
680Ω
GND
≤3 ns
90%
10%
90%
10%
≤ 3 ns
Equivalent to:
THÉVENIN EQUIVALENT
420Ω
OUTPUT
1.91V
Notes:
4. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
5. TA is the “instant on” case temperature.
6. See the last page of this specification for Group A subgroup testing information.
7. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency 20 Mhz, while data inputs switch
at 10 MHz. Outputs are unloaded. ICC1(typical) = (20 mA + (freq – 20 MHz) * (0.7 mA/MHz)).
8. All inputs = VCC – 0.2V, except WCLK and RCLK (which are switching at frequency = 20 MHz). All outputs are unloaded.
9. Tested initially and after any design or process changes that may affect these parameters.
10. CL = 30 pF for all AC parameters except for tOHZ.
11. CL = 5 pF for tOHZ.
Document #: 38-06015 Rev. *B
Page 6 of 18
CY7C4261
CY7C4271
Switching Characteristics Over the Operating Range
7C4261/71−10 7C4261/71−15 7C4261/71−25 7C4261/71− 35
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
tS
Clock Cycle Frequency
tA
Data Access Time
2
tCLK
Clock Cycle Time
10
tCLKH
Clock HIGH Time
4.5
tCLKL
Clock LOW Time
4.5
tDS
Data Set-up Time
3
tDH
Data Hold Time
0.5
tENS
Enable Set-up Time
3
4
6
7
ns
tENH
Enable Hold Time
0.5
1
1
2
ns
tRS
Reset Pulse Width[12]
10
15
25
35
ns
tRSS
Reset Set-up Time
8
10
15
20
ns
tRSR
Reset Recovery Time
8
tRSF
Reset to Flag and Output Time
tOLZ
Output Enable to Output in Low Z[13]
0
tOE
Output Enable to Output Valid
3
7
3
3
7
3
100
8
66.7
2
2
15
28.6 MHz
2
20
ns
25
35
ns
6
10
14
ns
6
10
14
ns
4
6
7
ns
1
1
2
ns
10
10
Z[13]
10
15
40
15
15
0
20
25
0
ns
35
0
8
3
12
3
8
3
12
3
ns
ns
15
ns
tOHZ
Output Enable to Output in High
15
ns
tWFF
Write Clock to Full Flag
8
10
15
20
ns
tREF
Read Clock to Empty Flag
8
10
15
20
ns
tPAF
Clock to Programmable Almost-Full Flag
8
10
15
20
ns
tPAE
Clock to Programmable Almost-Full Flag
tSKEW1
Skew Time between Read Clock and Write
Clock for Empty Flag and Full Flag
5
6
10
12
ns
tSKEW2
Skew Time between Read Clock and Write Clock
for Almost-Empty Flag and Almost-Full Flag
10
15
18
20
ns
8
10
15
20
ns
Notes:
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
Document #: 38-06015 Rev. *B
Page 7 of 18
CY7C4261
CY7C4271
Switching Waveforms
Write Cycle Timing
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0 –D17
tENS
tENH
WEN1
NO OPERATION
NO OPERATION
WEN2
(if applicable)
tWFF
tWFF
FF
tSKEW1
[14]
RCLK
REN1, REN2
Read Cycle Timing
tCKL
tCLKH
tCLKL
RCLK
tENS
tENH
REN1, REN2
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 –Q17
tOLZ
tOHZ
tOE
OE
tSKEW1[15]
WCLK
WEN1
WEN2
Notes:
14. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK rising edge.
15. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK rising edge.
Document #: 38-06015 Rev. *B
Page 8 of 18
CY7C4261
CY7C4271
Switching Waveforms (continued)
Reset Timing [16]
tRS
RS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN1,
REN2
WEN1
WEN2/LD [18]
tRSF
EF,PAE
tRSF
FF,PAF
tRSF
OE=1
Q0 - Q8
[17]
OE=0
First Data Word Latency after Reset with Read and Write
WCLK
tDS
D0 –D8
D0(FIRST VALID WRITE)
D1
D2
D3
D4
tENS
tFRL [19]
WEN1
WEN2
(if applicable)
tSKEW1
RCLK
tREF
EF
tA[20]
tA
REN1,
REN2
Q0 –Q8
D0
D1
tOLZ
tOE
OE
Notes:
16. The clocks (RCLK, WCLK) can be free-running during reset.
17. After reset, the outputs will be LOW if OE = 0 and three-state if OE=1.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the
programmable flag offset registers.
19. When tSKEW1 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06015 Rev. *B
Page 9 of 18
CY7C4261
CY7C4271
Switching Waveforms (continued)
Empty Flag Timing
WCLK
tDS
tDS
DATA WRITE 2
DATA WRITE 1
D0 –D8
tENH
tENS
tENH
tENS
WEN1
tENS
tENH
tENH
tENS
WEN2
(if applicable)
tFRL
[19]
tFRL
[19]
RCLK
tREF
tSKEW1
tREF
tREF
tSKEW1
EF
REN1,
REN2
LOW
OE
tA
DATA IN OUTPUT REGISTER
Q0 –Q8
DATA READ
NO WRITE
NO WRITE
Full Flag Timing
WCLK
tSKEW1[14]
[14]
tDS
DATA WRITE
tSKEW1
DATA WRITE
D0 –D8
tWFF
tWFF
tWFF
FF
WEN1
WEN2
(if applicable)
RCLK
tENH
OE
tENH
tENS
REN1,
REN2
tENS
LOW
tA
Q0 –Q8
DATA IN OUTPUT REGISTER
Document #: 38-06015 Rev. *B
tA
DATA READ
NEXT DATA READ
Page 10 of 18
CY7C4261
CY7C4271
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing
tCLKL
tCLKH
WCLK
tENS tENH
WEN1
WEN2
(if applicable)
tENS tENH
PAE
tESKEW2[21]
Note
22
N + 1 WORDS
IN FIFO
tPAE
Note 23 t
PAE
RCLK
tENS
tENS tENH
REN1,
REN2
Programmable Almost Full Flag Timing
tCLKL
tCLKH
Note
24
WCLK
tENS tENH
WEN1
WEN2
(if applicable)
Note
25
tENS tENH
PAF
tPAF
FULL − MWORDS
IN FIFO [26]
FULL − (M+1)WORDS
IN FIFO
tSKEW2 [27]
tPAF
RCLK
tENS
tENS tENH
REN1,
REN2
Note:
21. tSKEW2 is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the rising
RCLK is less than tSKEW2, then PAE may not change state until the next RCLK.
22. PAE offset= n.
23. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW
24. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
25. PAF offset = m.
26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271.
27. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.
Document #: 38-06015 Rev. *B
Page 11 of 18
CY7C4261
CY7C4271
Switching Waveforms (continued)
Write Programmable Registers
tCLK
tCLKL
tCLKH
WCLK
tENS
tENH
WEN2/LD
tENS
WEN1
tDS
tDH
D0 –D8
PAE OFFSET
LSB
PAE OFFSET
MSB
PAF OFFSET
LSB
PAF OFFSET
MSB
Read Programmable Registers
tCLK
tCLKL
tCLKH
RCLK
tENS
tENH
WEN2/LD
tENS
PAF OFFSET
MSB
REN1,
REN2
tA
Q0 –Q15
Document #: 38-06015 Rev. *B
UNKNOWN
PAE OFFSET LSB
PAE OFFSET MSB
PAF OFFSET
LSB
Page 12 of 18
CY7C4261
CY7C4271
Typical AC and DC Characteristics
NORMALIZED tA vs. AMBIENT
TEMPERATURE
NORMALIZED tA vs. SUPPLY
VOLTAGE
1.60
NORMALIZED t A
NORMALIZED t A
1.20
1.10
1.00
0.90
TA =25°C
0.80
4.00
4.50
5.00
5.50
6.00
1.40
1.20
1.00
0.60
−55.00
VIN =3.0V
TA =25°C
f = 28 MHz
0.80
4.50
5.00
5.50
SUPPLY VOLTAGE (V)
6.00
NORMALIZED I CC
NORMALIZED I CC
NORMALIZED I CC
1.00
125.00
1.75
1.20
1.20
65.00
NORMALIZED SUPPLY CURRENT
vs. FREQUENCY
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
1.40
0.60
4.00
5.00
AMBIENT TEMPERATURE( °C)
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
VCC =5.0V
0.80
1.10
1.00
VIN =3.0V
VCC=5.0V
f = 28 MHz
0.90
0.80
−55.00
5.00
65.00
125.00
1.50
1.25
1.00
VCC =5.0V
TA =25°C
VIN =3.0V
0.75
0.50
20.00
AMBIENT TEMPERATURE (°C)
30.00
40.00
50.00
60.00
FREQUENCY (MHz)
Ordering Information
16Kx9 Deep Sync FIFO
Speed
(ns)
10
15
25
Ordering Code
Package
Name
Package
Type
CY7C4261-10AC
A32
32-Lead Thin Quad Flatpack
CY7C4261-10JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-10AI
A32
32-Lead Thin Quad Flatpack
CY7C4261-10JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4261-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4261-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4261-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-25AI
A32
32-Lead Thin Quad Flatpack
CY7C4261-25JI
J65
32-Lead Plastic Leaded Chip Carrier
Document #: 38-06015 Rev. *B
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Page 13 of 18
CY7C4261
CY7C4271
Ordering Information (continued)
16Kx9 Deep Sync FIFO
Speed
(ns)
35
Ordering Code
Package
Name
Package
Type
CY7C4261-35AC
A32
32-Lead Thin Quad Flatpack
CY7C4261-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4261-35AI
A32
32-Lead Thin Quad Flatpack
CY7C4261-35JI
J65
32-Lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
Industrial
32Kx9 Deep Sync FIFO
Speed
(ns)
10
Ordering Code
CY7C4271-10AC
15
25
35
Package
Name
Package
Type
A32
32-Lead Thin Quad Flatpack
CY7C4271-10JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-10AI
A32
32-Lead Thin Quad Flatpack
CY7C4271-10JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-15AC
A32
32-Lead Thin Quad Flatpack
CY7C4271-15JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-15AI
A32
32-Lead Thin Quad Flatpack
CY7C4271-15JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-15LMB
L55
32-Lead Ceramic Leaded Chip Carrier
5962-9736101QYA
L55
32-Lead Ceramic Leaded Chip Carrier
CY7C4271-25AC
A32
32-Lead Thin Quad Flatpack
CY7C4271-25JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-25AI
A32
32-Lead Thin Quad Flatpack
CY7C4271-25JI
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-35AC
A32
32-Lead Thin Quad Flatpack
CY7C4271-35JC
J65
32-Lead Plastic Leaded Chip Carrier
CY7C4271-35AI
A32
32-Lead Thin Quad Flatpack
CY7C4271-35JI
J65
32-Lead Plastic Leaded Chip Carrier
Operating
Range
Commercial
Industrial
Commercial
Industrial
Military
Commercial
Industrial
Commercial
Industrial
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Subgroups
VOH
1, 2, 3
VOL
1, 2, 3
VIH
1, 2, 3
VIL Max.
1, 2, 3
IIX
1, 2, 3
ICC
1, 2, 3
ICC1
1, 2, 3
ISB1
1, 2, 3
ISB2
1, 2, 3
IOS
1, 2, 3
Document #: 38-06015 Rev. *B
Page 14 of 18
CY7C4261
CY7C4271
Switching Characteristics
Parameters
Subgroups
tRC
9, 10, 11
tA
9, 10, 11
tRR
9, 10, 11
tPR
9, 10, 11
tDVR
9, 10, 11
tWC
9, 10, 11
tPW
9, 10, 11
tWR
9, 10, 11
tSD
9, 10, 11
tHD
9, 10, 11
tMRSC
9, 10, 11
tPMR
9, 10, 11
tRMR
9, 10, 11
tRPW
9, 10, 11
tWPW
9, 10, 11
tRTC
9, 10, 11
tPRT
9, 10, 11
tRTR
9, 10, 11
tEFL
9, 10, 11
tHFH
9, 10, 11
tFFH
9, 10, 11
tREF
9, 10, 11
tRFF
9, 10, 11
tWEF
9, 10, 11
tWFF
9, 10, 11
tWHF
9, 10, 11
tRHF
9, 10, 11
tRAE
9, 10, 11
tRPE
9, 10, 11
tWAF
9, 10, 11
tWPF
9, 10, 11
tXOL
9, 10, 11
tXOH
9, 10, 11
Document #: 38-06015 Rev. *B
Page 15 of 18
CY7C4261
CY7C4271
Package Diagrams
32-Lead Thin Plastic Quad Flatpack 7 × 7 × 1.0 mm A32
51-85063-*B
32-Lead Plastic Leaded Chip Carrier J65
51-85002-*B
Document #: 38-06015 Rev. *B
Page 16 of 18
CY7C4261
CY7C4271
Package Diagrams (continued)
32-Pin Rectangular Leadless Chip Carrier L55
MIL-STD-1835 C-12
51-80068-**
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-06015 Rev. *B
Page 17 of 18
CY7C4261
CY7C4271
Document History Page
Document Title: CY7C4261, CY7C4271 16K/32K X 9 Deep Synchronous FIFOs
Document Number: 38-06015
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
106476
09/10/01
SZV
Changed from Spec number: 38-00658 to 38-06015
*A
122267
12/26/02
RBI
Added power-up requirements Maximum Ratings Information
*B
127853
08/22/03
FSG
Switching Waveforms section: fixed misplaced footnote in tA in “First Data
Word Latency after Reset with Read and Write” drawing
Switching Waveforms section: changed tSKEW2 to tSKEW1 (typo) in “Empty
Flag Timing” drawing
Document #: 38-06015 Rev. *B
Page 18 of 18