LTC1060 Universal Dual Filter Building Block U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Guaranteed Filter Specification for ±2.37V and ±5V Supply Operates Up to 30kHz Low Power and 88dB Dynamic Range at ±2.5V Supply Center Frequency Q Product Up to 1.6MHz Guaranteed Offset Voltages Guaranteed Clock-to-Center Frequency Accuracy Over Temperature: 0.3% for LTC1060A 0.8% for LTC1060 Guaranteed Q Accuracy Over Temperature Low Temperature Coefficient of Q and Center Frequency Low Crosstalk, 70dB Clock Inputs TTL and CMOS Compatible U APPLICATIO S ■ ■ ■ ■ The LTC®1060 consists of two high performance, switched capacitor filters. Each filter, together with 2 to 5 resistors, can produce various 2nd order filter functions such as lowpass, bandpass, highpass notch and allpass. The center frequency of these functions can be tuned by an external clock or by an external clock and resistor ratio. Up to 4th order full biquadratic functions can be achieved by cascading the two filter blocks. Any of the classical filter configurations (like Butterworth, Chebyshev, Bessel, Cauer) can be formed. The LTC1060 operates with either a single or dual supply from ±2.37V to ±8V. When used with low supply (i.e. single 5V supply), the filter typically consumes 12mW and can operate with center frequencies up to 10kHz. With ±5V supply, the frequency range extends to 30kHz and very high Q values can also be obtained. The LTC1060 is manufactured by using Linear Technology’s enhanced LTCMOS™ silicon gate process. Because of this, low offsets, high dynamic range, high center frequency Q product and excellent temperature stability are obtained. Single 5V Supply Medium Frequency Filters Very High Q and High Dynamic Range Bandpass, Notch Filters Tracking Filters Telecom Filters The LTC1060 is pinout compatible with MF10. , LTC and LT are registered trademarks of Linear Technology Corporation. LTCMOS trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Single 5V, Gain of 1000 4th Order Bandpass Filter Amplitude Response 70 3.16k 3.16k 20 100k 2 19 100k 2k 3 18 2k 4 17 16 5 6 5V CLOCK IN 17.5kHz LTC1060 60 50 5V 1k 0.1µF 15 7 14 8 13 9 12 10 11 GAIN (dB) VIN 1mV(RMS) OUTPUT 1 40 30 20 10 1k 0 –10 0 100 125 150 175 200 225 250 275 INPUT FREQUENCY (Hz) LTC1060 • TA02 LTC1060 • TA01 1060fb 1 LTC1060 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) ORDER PART NUMBER TOP VIEW Supply Voltage ........................................................ 18V Power Dissipation .............................................. 500mW Operating Temperature Range LTC1060AC/LTC1060C ................ – 40°C ≤ TA ≤ 85°C LTC1060AM/LTC1060M ............ – 55°C ≤ TA ≤ 125°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C LPA 1 20 LPB BPA 2 19 BPB N/AP/HPA 3 18 N/AP/HPB INVA 4 17 INVB S1A 5 16 S1B SA/B 6 15 AGND VA + 7 14 VA– VD+ 8 13 VD– LSh 9 12 50/100/HOLD CLKA 10 LTC1060ACN LTC1060CN LTC1060CSW 11 CLKB N PACKAGE SW PACKAGE 20-LEAD PDIP 20-LEAD PLASTIC SO WIDE TJMAX = 100°C, θJA = 100°C/W (N) TJMAX = 150°C, θJA = 80°C/W (SW) LTC1060ACJ LTC1060MJ LTC1060AMJ LTC1060CJ J PACKAGE 20-LEAD CERDIP TJMAX = 150°C, θJA = 70°C/W OBSOLETE PACKAGE Consider the N20 and SW20 Package for Alternate Source Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Complete Filter) Vs = ± 5V, unless otherwise noted. PARAMETER Center Frequency Range (See Applications Information) Clock-to-Center Frequency Ratio LTC1060A LTC1060 LTC1060A LTC1060 Q Accuracy LTC1060A LTC1060 f0 Temperature Coefficient Q Temperature Coefficient DC Offset VOS1 VOS2 VOS2 VOS2 VOS2 VOS3 VOS3 DC Lowpass Gain Accuracy BP Gain Accuracy at f0 Clock Feedthrough Max Clock Frequency Power Supply Current CONDITIONS f0 • Q ≤ 400kHz, Mode 1, Figure 4 f0 • Q ≤ 1.6MHz, Mode 1, Figure 4 MIN Mode 1, 50:1, fCLK = 250kHz, Q = 10 Mode 1, 50:1, fCLK = 250kHz, Q = 10 Mode 1, 100:1, fCLK = 500kHz, Q = 10 Mode 1, 100:1, fCLK = 500kHz, Q = 10 ● ● ● ● Mode 1, 50:1 or 100:1, f0 = 5kHz, Q=10 Mode 1, 50:1 or 100:1, f0 = 5kHz, Q=10 Mode 1, fCLK < 500kHz Mode 1, fCLK < 500kHz, Q = 10 ● ● fCLK = 250kHz, 50:1, SA/B = High fCLK = 500kHz, 100:1, SA/B = High fCLK = 250kHz, 50:1, SA/B = Low fCLK = 500kHz, 100:1, SA/B = Low fCLK = 250kHz, 50:1, SA/B = Low fCLK = 500kHz, 100:1, SA/B = Low Mode 1, R1 = R2 = 50k Mode 1, Q = 10, f0 = 5kHz fCLK ≤ 1MHz TYP 0.1 to 20k 0.1 to 16k UNITS Hz Hz 50 ± 0.3% 50 ± 0.8% 100 ± 0.3% 100 ± 0.8% ● ● ● ● ● ● ● 3 ±0.5 ±0.5 –10 20 2 3 6 2 4 2 4 ±0.1 ±0.1 10 1.5 5 ● Crosstalk MAX 70 3 5 15 40 80 30 60 30 60 2 8 12 % % ppm/°c ppm/°c mV mV mV mV mV mV mV % % mV(P-P) MHz mA mA dB 1060fb 2 LTC1060 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Complete Filter) VS = ±2.37V. PARAMETER CONDITIONS MIN Center Frequency Range f0 • Q ≤ 100kHz Clock-to-Center Frequency Ratio LTC1060A LTC1060 LTC1060A LTC1060 Mode 1, 50:1, fCLK = 250kHz, Q = 10 Mode 1, 50:1, fCLK = 250kHz, Q = 10 Mode 1, 100:1, fCLK = 250kHz, Q = 10 Mode 1, 100:1, fCLK = 250kHz, Q = 10 Q Accuracy LTC1060A LTC1060 Mode1, 50:1 or 100:1, f0 = 2.5kHz, Q = 10 Mode1, 50:1 or 100:1, f0 = 2.5kHz, Q = 10 TYP MAX 0.1 to 10k UNITS Hz 50 ± 0.5% ● 50 ± 0.8% 100 ± 0.5% 100 ± 0.8% ● ±2 ±4 % % Max Clock Frequency 500 kHz Power Supply Current 2.5 4 mA The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Internal Op Amps). PARAMETER CONDITIONS MIN Supply Voltage Range TYP ±2.37 Voltage Swings LTC1060A LTC01060 LTC01060, LTC01060A VS = ±5V, RL = 5k (Pins 1,2,19,20) RL = 3.5k (Pins 3,18) Output Short-Circuit Current Source Sink VS = ±5V Op Amp GBW Product Op Amp Slew Rate Op Amp DC Open Loop Gain VS = ±5V VS = ±5V RL = 10k, VS = ±5V ±4 ± 3.8 ±3.6 ● MAX ±8 UNITS V ±4 ±4 ±4 V V V 25 3 mA mA 2 7 85 MHz V/µs dB Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. W BLOCK DIAGRA VD+ VA+ 8 N/AP/HPA S1A 7 3 – INVA 4 5 + + ∑ – – BPA LPA 2 1 ∫ ∫ S2A AGND 15 CLKA 10 LEVEL SHIFT NON-OVERLAP CLOCK 50/100/HOLD 12 6 SAB CONTROL LEVEL SHIFT 9 CLKB 11 LEVEL SHIFT NON-OVERLAP CLOCK TO AGND S2B + + – ∑ INVB 17 – – 13 14 VD– VA– 18 16 N/AP/HPB S1B ∫ ∫ 19 20 BPB LPB LTC1060 • BD01 1060fb 3 LTC1060 U W TYPICAL PERFOR A CE CHARACTERISTICS Graph 2. Mode 1: (fCLK/f0) Deviation vs Q VS = ±5V TA = 25°C fCLK = 500kHz 0.1 % DEVIATION (fCLK/f0 ) % DEVIATION (fCLK/f0 ) VS = ±5V 0.4 TA = 25°C = 250kHz f 0 CLK –0.4 –0.8 fCLK = 50 (TEST POINT) f0 –1.2 –1.6 –2.0 Graph 3. Mode 1: Q Error vs Clock Frequency fCLK fCLK = 100 (TEST POINT) f0 DEVIATION FROM IDEAL Q (%) Graph 1. Mode 1: (fCLK/f0) Deviation vs Q 0 – 0.1 – 0.2 – 0.3 – 0.4 – 0.5 –2.4 VS = ±5V TA = 25°C VS = ±2.5V 50 20 10 10 Q = 5 50 20 100 20 10 fCLK = 100:1 f0 0 VS = ±2.5V VS = ±5V 20 10 Q = 5 50 20 10 50 100 20 Q=5 fCLK = 50:1 f0 10 – 0.6 1 10 0.1 100 1 10 LT1060 • TPC02 LT1060 • TPC01 10 Q=5 400 0 Q=5 100 50 20 fCLK = 50:1 f0 10 10 200 VS = ±5V Q = 10 20 fCLK = 100:1 f0 0.8 125°C TA = 25°C –55°C 0 85°C 125°C TA = 25°C – 55°C 20 fCLK = 50:1 f0 0 0.4 0.6 0.8 1.0 1.2 fCLK (MHz) Graph 7. Mode 1: (fCLK/f0) vs fCLK and Q 1.4 1.6 DEVIATION FROM 100:1 (%) Q = 50 Q = 20 0 Q = 10 0 Q = 10 0 0.2 0.4 0.6 0.8 fCLK (MHz) 1.0 VS = ±5V Q = 10 0.8 fCLK = 100:1 f0 1.2 1.4 LTC1060 • TPC06 Graph 9. Mode 1: (fCLK/f0) vs fCLK and Temperature 1.0 TA = 25°C 125°C 85°C 0.6 0.4 –55°C 0.2 0 –0.2 Q = 20 Q = 50 –0.4 1.8 1.0 0.4 0.2 0.2 Graph 8. Mode 1: (fCLK/f0) vs fCLK and Temperature VS = ±5V TA = 25°C fCLK = 50:1 f0 0.6 0.4 LTC1060 • TPC05 LTC1060 • TPC04 0.8 0.6 –0.2 Q = 5 –20 0.2 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 fCLK (MHz) VS = ±5V TA = 25°C fCLK = 100:1 f0 85°C 400 0 DEVIATION FROM 50:1 (%) Graph 6. Mode 1: (fCLK/f0) vs fCLK and Q DEVIATION FROM 50:1 (%) DEVIATION FROM IDEAL Q (%) 50 10 100 200 LTC1060 • TPC03 Graph 5. Mode 1: Measured Q vs fCLK and Temperature DEVIATION FROM IDEAL Q (%) Graph 4. Mode 1: Q Error vs Clock Frequency 20 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 fCLK (MHz) IDEAL Q IDEAL Q VS = ±7.5V TA = 25°C fCLK = 100:1 f0 0 100 DEVIATION FROM 100:1 (%) 0.1 Q=5 VS = ±5V Q = 10 125°C 0.8 fCLK = 50:1 f0 85°C TA= 25°C 0.6 0.4 –55°C 0.2 0 Q=5 –0.4 0 0.2 0.4 0.6 0.8 fCLK (MHz) 1.0 1.2 1.4 LTC1060 • TPC07 –0.2 0.2 0.4 0.6 0.8 1.0 1.2 fCLK (MHz) 1.4 1.6 1.8 –0.2 0.2 0.4 0.6 0.8 1.0 1.2 fCLK (MHz) 1.4 1.6 1.8 LTC1060 • TPC09 LTC1060 • TPC08 1060fb 4 LTC1060 U W TYPICAL PERFOR A CE CHARACTERISTICS Graph 11. Mode 1: (fCLK/f0) vs fCLK and Q Graph 10. Mode 1: (fCLK/f0) vs fCLK and Q 0.6 0.4 Q = 20 0.2 VS = ±2.5V TA = 25°C fCLK = 50:1 f0 0.6 DEVIATION FROM 50:1 (%) Q = 50 0 0.4 Q = 50 0.2 Q = 20 0 Q = 10 100 0.2 Q=5 300 400 500 fCLK (MHz) 600 700 0 100 300 400 500 fCLK (MHz) 200 LTC1060 • TPC10 120 –55°C NOTCH DEPTH (dB) 85°C 0.4 125°C 0.2 VS = ±2.5V Q = 10 fCLK = 50:1 f0 –0.2 0 0.2 0.4 1.0 0.6 0.8 fCLK (kHz) 0.4 0.2 1.0 0.6 0.8 fCLK (kHz) 80 60 Q = 10 50:1 40 20 0 0 1.2 0.2 0.4 0.6 0.8 1.0 fCLK (MHz) 1.2 1.4 LTC1060 • TPC12 VS = ±5V TA = 25°C PIN 12 AT 100:1 fCLK = 500: 1 fO R2 1 = R4 5 0.1 0 (A) –0.1 R2 1 = R4 2 –0.2 –0.3 (B) –0.4 fCLK = 200: 1 fO –0.5 1.6 1 0.1 10 100 IDEAL Q LTC1060 • TPC15 LTC1060 • TPC14 LTC1060 • TPC13 Graph 16. Mode 3: Q Error vs Clock Frequency 1.2 Graph 15. Mode 3: Deviation of (fCLK/f0) with Respect to Q = 10 Measurement VS = ±5V TA = 25°C VIN = 1VRMS Q = 10 100:1 Q = 1 100:1 100 0.6 0 0 700 Graph 14. Mode 1: Notch Depth vs Clock Frequency 1.0 TA = 25°C 600 LTC1060 • TPC11 Graph 13. Mode 1: (fCLK/f0) vs fCLK and Temperature 0.8 TA = 25°C 125°C 0.4 –0.4 200 –55°C 85°C 0 Q = 10 Q=5 0 DEVIATION FROM 50:1 (%) 0.6 – 0.2 –0.2 VS = ±2.5V Q = 10 fCLK = 100:1 f0 0.8 fCLK DEVIATION OF f WITH RESPECT TO O Q = 10 MEASUREMENT (%) DEVIATION FROM 100:1 (%) 0.8 1 0.8 VS = ±2.5V TA = 25°C fCLK = 100:1 f0 DEVIATION FROM 100:1 (%) 1.0 Graph 12. Mode 1: (fCLK/f0) vs fCLK and Temperature Graph 18. Mode 3 (R2 = R4): Measured Q vs fCLK and Temperature Graph 17. Mode 3 (R2 = R4): Q Error vs Clock Frequency 20 10 50 20 10 VS = ±2.5V 20 10 VS = ±5V 10 Q = 5 20 20 50 10 Q = 5 50 fCLK = 50:1 f0 0 VS = ±7.5V TA = 25°C fCLK = 100:1 f0 20 Q=5 50 0 TA = 25°C fCLK = 100:1 f0 Q ERROR (%) DEVIATION FROM IDEAL Q (%) 10 20 Q = 5 VS = ±5V 50 10 Q=5 10 0 10 20 50 10 Q=5 fCLK = 50:1 f0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 fCLK (MHz) LTC1060 • TPC16 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 fCLK (MHz) LTC1060 • TPC17 DEVIATION FROM IDEAL Q (%) 40 VS = ±2.5V VS = ±5V 125°C Q = 10 20 fCLK = 100:1 f0 85°C TA = 25°C –55°C 0 125°C –20 40 fCLK = 50:1 f0 20 85°C TA = 25°C –55°C 0 –20 0.2 0.4 0.6 0.8 1.0 1.2 fCLK (MHz) 1.4 1.6 1.8 LTC1060 • TPC18 1060fb 5 LTC1060 U W TYPICAL PERFOR A CE CHARACTERISTICS Graph 20. Mode 3 (R2 = R4): (fCLK/f0) vs fCLK and Q Graph 19. Mode 3 (R2 = R4): (fCLK/f0) vs fCLK and Q 0.2 Q = 20, Q = 40, Q = 50 0 –0.2 0.4 0.2 Q = 10 0 0.2 0.6 0.8 fCLK (MHz) 0.4 1.2 1.0 0 0.2 0.4 0.6 0.8 fCLK (MHz) 1.2 1.0 LTC1060 • TPC19 TA = 25°C 0.2 –55°C 1.4 0.4 0.8 1.0 1.2 fCLK (MHz) 0.6 TA = 25°C –55°C 0.2 0 Graph 24. Mode 3 (R2 = R4): (fCLK/f0) vs fCLK and Temperature – 55°C –55°C TA = 25°C 0.4 85°C 125°C 0.2 0 0.8 85°C 0.6 TA = 25°C 125°C 0.4 0.2 VS = ±2.5V Q = 10 fCLK = 100:1 f0 0 –0.2 0.4 1.2 0.8 1 fCLK (MHz) 0.6 1.4 1.8 1.6 0 0.2 0.4 1.0 0.6 0.8 fCLK (MHz) LTC1060 • TPC22 10 Q = 20 Q = 10 18 20 16 MODE 2 R2 = R4 Q = 10 fCLK 35.37 1 f0 10 0.4 0.2 0.6 0.8 fCLK (MHz) 1.0 LTC1060 • TPC24 20 0 20 0 Graph 26.Supply Current vs Supply Voltage Q = 20 20 MODE 2 R2 = R4 SUPPLY CURRENT (mA) DEVIATION FROM IDEAL Q (%) 20 1.2 LTC1060 • TPC23 Graph 25. Mode 1c (R5 = 0), Mode 2 (R2 = R4) Q Error vs Clock Frequency VS = ±5V TA = 25°C fCLK 70.7 = 1 f0 1.8 1.6 LTC1060 • TPC21 –0.4 0.2 1.4 1.0 VS = ± 2.5V Q = 10 fCLK = 100:1 f0 0.6 DEVIATION FROM 100:1 (%) DEVIATION FROM 50:1 (%) 0.8 VS = ±5V Q = 10 f 0.8 CLK = 100:1 f0 0.4 0.4 Graph 23. Mode 3 (R2 = R4): (fCLK/f0) vs fCLK and Temperature 1.0 125°C 85°C 85°C 125°C LTC1060 • TPC20 Graph 22. Mode 3 (R2 = R4): (fCLK/f0) vs fCLK and Temperature 0.6 0.6 –0.2 0.2 –0.4 1.4 VS = ± 5V Q = 10 0.8 fCLK = 100:1 f0 0 –0.2 Q = 5 Q = 10 0 Q = 20 Q = 50 Q=5 –0.4 DEVIATION FROM100:1 (%) 0.4 1.0 VS = ± 5V TA = 25°C fCLK = 50:1 f0 0.6 DEVIATION FROM 50:1 (%) 0.6 DEVIATION FROM 100:1 (%) 0.8 VS = ± 5V TA = 25°C fCLK = 100:1 f0 DEVIATION FROM 50:1 (%) 0.8 Graph 21. Mode 3 (R2 = R4): (fCLK/f0) vs fCLK and Temperature 14 fCLK ≤ 1MHz TA = –55°C 12 10 TA = 25°C 8 6 TA = 125°C 4 2 0 0 0.2 0.4 0.6 0.8 fCLK (MHz) 1.0 1.2 1.4 LTC1060 • TPC25 0 ±1 ±2 ±3 ±4 ±5 ±6 ±7 ±8 ±9 ±10 ±11 SUPPLY VOLTAGE (±V) LTC1060 • TPC26 1060fb 6 LTC1060 U W U U U U U PIN DESCRIPTION AND APPLICATIONS INFORMATIO Power Supplies The V +A and V +D (pins 7 and 8) and the V –A and V –D (Pins 14 and 13) are, respectively, the analog and digital positive and negative supply pins. For most cases, Pins 7 and 8 should be tied together and bypassed by a 0.1µF disc ceramic capacitor. The same holds for Pins 13 and 14. If the LTC1060 operates in a high digital noise environment, the supply pins can be bypassed separately. Pins 7 and 8 are internally connected through the IC substrate and should be biased from the same DC source. Pins 13 and 14 should also be biased from the same DC source. The LTC1060 is designed to operate with ±2.5V supply (or single 5V) and with ± 5V to ±8V supplies. The minimum supply, where the filter operates reliably, is ± 2.37V. With low supply operation, the maximum input clock frequency is about 500kHz. Beyond this, the device exhibits excessive Q enhancement and center frequency errors. Clock Input Pins and Level Shift The level shift (LSh) Pin 9 is used to accommodate T2L or CMOS clock levels. With dual supplies equal or higher to ±4.5V, Pin 9 should be connected to ground (same potential as the AGND pin). Under these conditions the clock levels can be T2L or CMOS. With single supply operation, the negative supply pins and the LSh pin should be tied to the system ground. The AGND, Pin 15, should be biased at 1/2 supplies, as shown in the “Single 5V Gain of 1000 4th Order Bandpass Filter” circuit. Again, under these conditions, the clock levels can be T2L or CMOS. The input clock pins (10,11) share the same level shift pin. The clock logic threshold level over temperature is typically 1.5V ± 0.1V above the LSh pin potential. The duty cycle of the input clock should be close to 50%. For clock frequencies below 1MHz, the (fCLK/f0) ratio is independent from the clock input levels and from its rise and fall times. Fast rising clock edges, however, improve the filter DC offsets. For clock frequencies above 1MHz, T2L level clocks are recommended. 50/100/Hold (Pin 12) By tying Pin 12 to (V +A and V +D), the filter operates in the 50:1 mode. With ±5V supplies, Pin 12 can be typically 1V below the positive supply without affecting the 50:1 operation of the device. By tying Pin 12 to 1/2 supplies (which should be the AGND potential), the LTC1060 operates in the 100:1 mode. The 1/2 supply bias of Pin 12 can vary around the 1/2 supply potential without affecting the 100:1 filter operation. This is shown in Table 1. When Pin 12 is shorted to the negative supply pin, the filter operation is stopped and the bandpass and lowpass outputs act as a S/H circuit holding the last sample. The hold step is 20mV and the droop rate is 150µV/second! Table 1 TOTAL POWER SUPPLY VOLTAGE RANGE OF PIN 12 FOR 100:1 OPERATION 5V 2.5 ± 0.5V 10V 5V ± 1V 15V 7.5V ± 1.5V S1A, S1B (Pins 5 and 16) These are voltage signal input pins and, if used, they should be driven with a source impedance below 5kΩ. The S1A, S1B pins can be used to alter the CLK to center frequency ratio (fCLK/f0) of the filter (see Modes 1b, 1c, 2a, 2b) or to feedforward the input signal for allpass filter configurations (see Modes 4 and 5). When these pins are not used, they should be tied to the AGND pin. SA/B (Pin 6) When SA/B is high, the S2 input of the filter’s voltage summer (see Block Diagram) is tied to the lowpass output. This frees the S1 pin to realize various modes of operation for improved applications flexibility. When the SA/B pin is connected to the negative supply, the S2 input switches to ground and internally becomes inactive. This improves the filter noise performance and typically lowers the value of the offset VOS2. AGND (Pln 15) This should be connected to the system ground for dual supply operation. When the LTC1060 operates with a single positive supply, the analog ground pin should be tied to 1/2 supply and bypassed with a 0.1µF capacitor, as shown in the application, “Single 5V, Gain of 1000 4th Order Bandpass Filter.” The positive inputs of all the 1060fb 7 LTC1060 U W U U APPLICATIO S I FOR ATIO internal op amps, as well as the reference point of all the internal switches are connected to the AGND pin. Because of this, a “clean” ground is recommended. fCLK/f0 Ratio The fCLK/f0 reference of 100:1 or 50:1 is derived from the filter center frequency measured in mode 1, with a Q = 10 and VS = ±5V. The clock frequencies are, respectively, 500kHz/250kHz for the 100:1/150:1 measurement. All the curves shown in the Typical Performance Characteristics section are normalized to the above references. Graphs 1 and 2 in the Typical Performance Characteristics show the (fCLK/f0) variation versus values of ideal Q. The LTC1060 is a sampled data filter and it only approximates continuous time filters. In this data sheet, the LTC1060 is treated in the frequency domain because this approximation is good enough for most filter applications. The LTC1060 deviates from its ideal continuous filter model when the (fCLK/f0) ratio decreases and when the Q’s are low. Since low Q filters are not selective, the frequency domain approximation is well justified. In Graph 15 the LTC1060 is connected in mode 3 and its ( fCLK/f0) ratio is adjusted to 200:1 and 500:1. Under these conditions, the filter is over-sampled and the (fCLK/f0) curves are nearly independent of the Q values. In mode 3, the ( fCLK/f0) ratio typically deviates from the tested one in mode 1 by ±0.1%. f0 x Q Product Ratio This is a figure of merit of general purpose active filter building blocks. The f0 x Q product of the LTC1060 depends on the clock frequency, the power supply voltages, the junction temperature and the mode of operation. At 25°C ambient temperature for ±5V supplies, and for clock frequencies below 1MHz, in mode 1 and its derivatives, the f0 x Q product is mainly limited by the desired f 0 and Q accuracy. For instance,from Graph 4 at 50:1 and for fCLK below 800kHz, a predictable ideal Q of 400 can be obtained. Under this condition, a respectable f0 x Q product of 6.4MHz is achieved. The 16kHz center frequency will be about 0.22% off from the tested value at 250kHz clock (see Graph 1). For the same clock frequency of 800kHz and for the same Q value of 400, the f0 x Q product can be further increased if the clock-to-center frequency is lowered below 50:1. In mode 1c with R6 = 0 and R6 = ∞, the (fCLK/f0) ratio is 50/√2. The f0 x Q product can now be increased to 9MHz since, with the same clock frequency and same Q value, the filter can handle a center frequency of 16kHz x √2. For clock frequencies above 1MHz, the f0 x Q product is limited by the clock frequency itself. From Graph 4 at ±7.5V supply, 50:1 and 1.4MHz clock, a Q of 5 has about 8% error; the measured 28kHz center frequency was skewed by 0.8% with respect to the guaranteed value at 250kHz clock. Under these conditions, the f0 x Q product is only 140kHz but the filter can handle higher input signal frequencies than the 800kHz clock frequency, very high Q case described above. Mode 3, Figure 11, and the modes of operation where R4 is finite, are “slower” than the basic mode 1. This is shown in Graph 16 and 17. The resistor R4 places the input op amp inside the resonant loop. The finite GBW of this op amp creates an additional phase shift and enhances the Q value at high clock frequencies. Graph 16 was drawn with a small capacitor, CC, placed across R4 and as such, at VS = ±5V, the (1/2πR4CC) = 2MHz. With VS = ±2.5V the (1/ 2πR4CC) should be equal to 1.4MHz. This allows the Q curve to be slightly “flatter” over a wider range of clock frequencies. If, at ±5V supply, the clock is below 900kHz (or 400kHz for VS = ±2.5V), this capacitor, CC, is not needed. For Graph 25, the clock-to-center frequency ratios are altered to 70.7:1 and 35.35:1. This is done by using mode 1c with R5 = 0, Figure 7, or mode 2 with R2 = R4 = 10kΩ. The mode 1c, where the input op amp is outside the main loop, is much faster. Mode 2, however, is more versatile. At 50:1, and for TA = 25°C the mode 1c can be tuned for center frequencies up to 30kHz. Output Noise The wideband RMS noise of the LTC1060 outputs is nearly independent from the clock frequency, provided that the clock itself does not become part of the noise. The LTC1060 noise slightly decreases with ±2.5V supply. The noise at the BP and LP outputs increases for high Q’s. Table 2 shows typical values of wideband RMS noise. The numbers in parentheses are the noise measurement in mode 1 with the SA/B pin shorted to V – as shown in Figure 25. 1060fb 8 LTC1060 U W U U APPLICATIO S I FOR ATIO Table 2. Wideband RMS Noise VS fCLK f0 NOTCH/HP (µVRMS) BP (µVRMS) LP (µVRMS) ±5V ±5V ±2.5V ±2.5V 50:1 100:1 50:1 100:1 49 (42) 70 (55) 33 (31) 48 (40) 52 (43) 80 (58) 36 (32) 52 (40) 75 (65) 90 (88) 48 (43) 66 (55) ±5V ±5V ±2.5V ±2.5V 50:1 100:1 50:1 100.1 20 (18) 25 (21) 16 (15) 20 (17) 150 (125) 220 (160) 100 (80) 150 (105) 186 (155) 240 (180) 106 (87) 150 (119) ±5V ±5V ±2.5V ±2.5V 50:1 100:1 50:1 100.1 57 72 40 50 57 72 40 50 62 80 42 53 Mode 3, R1 = R2 = R3 = R4 Q=1 ±5V ±5V ±2.5V ±2.5V 50:1 100:1 50:1 100:1 135 170 100 125 120 160 88 115 140 185 100 130 Mode 3, R2 = R4, Q = 10 R3 = R1 for BP out R4 = R1 for LP and HP out CONDITIONS Mode1, R1 = R2 = R3 Q=1 Mode 1, Q = 10 R1 = R3 for BP out R1 = R2 for LP out Short-Circuit Currents Short circuits to ground, positive or negative power supply are allowed as long as the power supplies do not exceed ±5V and the ambient temperature stays below 85˚C. Above ±5V and at elevated temperatures, continuous short circuits to the negative power supply will cause excessive currents to flow. Under these conditions, the device will get damaged if the short-circuit current is allowed to exceed 80mA. U U U U DEFINITION OF FILTER FUNCTIONS Each building block of the LTC1060, together with an external clock and a few resistors, closely approximates 2nd order filter functions. These are tabulated below in the frequency domain. 1. Bandpass function: available at the bandpass output Pins 2 (19). (Figure 1.) G(s) = HOBP sωo/Q 2 s + (sωo/Q) + ωo2 HOBP = Gain at ω = ωo Q = Quality factor of the complex pole pair. It is the ratio of f0 to the –3dB bandwidth of the 2nd order bandpass function. The Q is always measured at the filter BP output. 2. Lowpass function: available at the LP output Pins 1 (20). (Figure 2.) G(s) = HOLP ω2o s2 + s(ωo/Q) + ω2o HOLP DC gain of the LP output. f0 = ω/2π; f0 is the center frequency of the complex pole pair. At this frequency, the phase shift between input and output is –180˚. 1060fb 9 LTC1060 U U U U DEFINITION OF FILTER FUNCTIONS 3. Highpass function: available only in mode 3 at the ouput Pins 3 (18). (Figure 3.) G(s) = HOHP s2 s2 + s(ωo/Q) + ω2o 5. Allpass function: available at Pins 3(18) for mode 4, 4a. G(s) = HOAP HOHP = gain of the HP output for f→ [s2 – s(ωo/Q) + ω2o] s2 + s(ωo/Q) + ω2o fCLK HOAP = gain of the allpass output for 0 < f < 2 fCLK 2 For allpass functions, the center frequency and the Q of the numerator complex zero pair is the same as the denominator. Under these conditions, the magnitude response is a straight line. In mode 5, the center frequency fz, of the numerator complex zero pair, is different than f0. For high numerator Q’s, the magnitude response will have a notch at fz. 4. Notch function: available at Pins 3 (18) for several modes of operation. s2 + ω2o G(s) = (HON2) 2 s + (sωo/Q) + ω2o fCLK HON2 = gain of the notch output for f→ 2 HON1 = gain of the notch output for f→0 fn = ωn/2π; fn is the frequency of the notch occurrence. HOBP 0.707 HOBP HOP HOLP 0.707 HOLP LOWPASS OUTPUT fP fL f0 fH f0 ;f = fH – fL 0 ( ( fL = f0 –1 + 20 fH = f0 1 + 2Q fC f P f(LOG SCALE) fC f(LOG SCALE) f(LOG SCALE) Q= GAIN (V/V) GAIN (V/V) GAIN (V/V) BANDPASS OUTPUT HIGHPASS OUTPUT fC = f0 • fL fH ) ( ( ) ( ( 1 2+ 1 2Q fP = f0 ( 1 – 2Q1 ( + ( 1 – 2Q1 ( + 1 f C = f0 • ( 1 – 2Q1 ( + ( 1 – 2Q1 ( + 1 fP = f 0 • 1– 1 2 2Q 2 2 1– 1 2 2Q 2 1 Q 1– 1 2 4Q TLC1060 • DFF01 –1 1 HOP = HOHP • 1 1 Q 1– 1 2 4Q TLC1060 • DFF03 TLC1060 • DFF02 Figure 1 –1 2 2 2 HOP = HOLP • 1 2+ 1 2Q Figure 2 Figure 3 U W ODES OF OPERATIO HOP HOHP 0.707 HOHP Table 3. Modes of Operation: 1st Order Functions MODE PIN 2 (19) PIN 3 (18) fC 6a LP HP fCLK R2 • 100(50) R3 6b LP LP fCLK R2 • 100(50) R3 7 LP AP fCLK R2 • 100(50) R3 fZ fCLK R2 • 100(50) R3 1060fb 10 LTC1060 U W ODES OF OPERATIO Table 4. Modes of Operation: 2nd Order Functions MODE PIN 1 (20) PIN 2 (19) PIN 3 (18) f0 fn 1 LP BP Notch fCLK 100(50) 1a LP BP BP fCLK 100(50) 1b LP BP Notch fCLK • 100(50) R6 R5 + R6 1c LP BP Notch fCLK • 100(50) 1+ 2 LP BP Notch fCLK • 100(50) 2a LP BP Notch fCLK • 100(50) 2b LP BP Notch fCLK • 100(50) R2 R6 + R4 R5 + R6 3 LP BP HP fCLK • 100(50) R2 R4 3a LP BP Notch fCLK • 100(50) R2 R4 4 LP BP AP fCLK 100(50) 4a LP BP AP fCLK • 100(50) R2 R4 5 LP BP CZ fCLK • 100(50) 1+ fCLK • 100(50) R6 R5 + R6 R6 R5 + R6 fCLK • 100(50) 1+ R6 R5 + R6 1+ R2 R4 fCLK 100(50) 1+ R2 R6 + R4 R5 + R6 fCLK • 100(50) 1+ R6 R5 + R6 fCLK • 100(50) R6 R5 + R6 fCLK • 100(50) Rh RI fCLK • 100(50) 1– R2 R4 R1 R4 VIN R3 R3 R2 VIN N S1A 3 (18) 5 (16) 2 BP (19) 1 R2 LP (20) R1 4 – (17) + + Σ – SA/B 6 4 – ∫ ∫ + TLC1060 • MOO01 15 – (17) 1/2 LTC1060 BP2 S1A 3 (18) 5 (16) BP1 (19) 1 LP (20) – + Σ – SA/B 6 2 ∫ ∫ TLC1060 • MOO02 15 1/2 LTC1060 V+ V+ f0 = fCLK R2 R3 R2 R3 ; fn = f0 ; HOLP = ; HOBP = – ; HON1 = – ;Q= R1 R1 R1 R2 100(50) Figure 4. Mode 1: 2nd Order Filter Providing Notch, Bandpass, Lowpass f0 = fCLK R3 R3 ;Q= ; HOBP1 = – ; HOBP2 = 1(NON-INVERTING) HOLP = – 1 R2 R2 100(50) Figure 5. Mode 1a: 2nd Order Filter Providing Bandpass, Lowpass 1060fb 11 LTC1060 W R6 U ODES OF OPERATIO R6 R5 R3 R3 R2 3 VIN R1 – 4 N S1A 5 (16) + (17) BP (19) 2 1 Σ R2 LP (20) VIN – + ∫ – 4 N S1A 3 (18) 5 (16) – + (17) 2 ∫ – 6 1 LP (20) ∫ SA/B TLC1060 • MOO03 BP (19) – Σ + 1/2 LTC1060 15 R1 ∫ SA/B 6 R5 TLC1060 • MOO04 1/2 LTC1060 15 V+ V– f0 = fCLK 100(50) R6 R3 ; fn = f0 ; Q = R5 + R6 R2 ( f f0 = CLK 100(50) R6 R5 + R6 ) R6 R3 ; fn = f0 ; Q = R5 + R6 R2 ( 1+ R6 ; R5 + R6 ) f R2 –R2/R1 R3 H0N1(f ← 0) = H0N2 f ← CLK = – ; H0BP = – ; H0LP = ; R5 < 5kΩ R1 1 + R6/(R5 + R6) R1 2 f R2 –R2/R1 R3 H0N1(f ← 0) = H0N2 f ← CLK = – ; H0LP = ; H0BP = – ; R5 < 5kΩ R1 R6/(R5 + R6) R1 2 Figure 6. Mode 1b: 2nd Order Filter Providing Notch, Bandpass, Lowpass 1+ Figure 7. Mode 1c: 2nd Order Filter Providing Notch, Bandpass, Lowpass R4 R4 R6 R3 R2 VIN R1 4 – N S1A 3 (18) 5 (16) + (17) + Σ – – 2 BP (19) 1 ∫ 4 – (17) N S1A 3 (18) 5 (16) + + TLC1060 • MOO05 Σ 2 BP (19) 1 LP (20) – – ∫ ∫ SA/B 6 TLC1060 • MOO06 1/2 LTC1060 15 V+ V+ f f0 = CLK 100(50) R1 ∫ 1/2 LTC1060 15 R2 LP (20) VIN SA/B 6 R5 R3 1+ f R2 R3 ; fn = CLK ; Q = R4 R2 100(50) H0BP = – R3/R1 ; H0N1(f ← 0) = 1+ R2 –R2/R1 ; H0LP = R4 1 + (R2 + R4) ( ) f –R2/R1 ; H0N2 = f ← CLK = – R2/R1 1 + (R2 + R4) 2 f f0 = CLK 100(50) 1+ H0N1(f ← 0) = – R2 R1 R2 R6 ; f = fCLK + n R4 R5 + R6 100(50) R6 ; Q = R3 R2 R5 + R6 ( 1+ ) R2 R6 + R4 R5 + R6 f 1 + R6/(R5 + R6) ; H0N2f ← CLK = – R2/R1 1 + (R2/R4) + [R6/(R5 + R6)] 2 H0BP = – R3/R1 ; H0LP = Figure 8. Mode 2: 2nd Order Filter Providing Notch, Bandpass, Lowpass 1+ –R2/R1 1 + (R2/R4) + [R6/(R5 + R6)] Figure 9. Mode 2a: 2nd Order Filter Providing Notch, Bandpass, Lowpass 1060fb 12 LTC1060 U W ODES OF OPERATIO R4 R4 R6 R5 R3 R3 R2 R2 VIN R1 4 N S1A 3 (18) 5 (16) – + (17) Σ + 2 BP (19) 1 LP (20) VIN R1 N S1A 3 (18) 5 (16) – 4 + (17) – ∫ ∫ – + Σ 2 ∫ 6 ∫ – TLC1060 • MOO08 6 TLC1060 • MOO07 LP (20) 1 – SA/B SA/B BP (19) 1/2 LTC1060 15 1/2 LTC1060 15 V– V– f f0 = CLK 100(50) f R2 + R6 ; fn = CLK R4 R5 + R6 100(50) H0N1(f ← 0) = – R2 R1 R3 R6 ;Q= R2 R5 + R6 ( ) f f0 = CLK 100(50) R2 + R6 R4 R5 + R6 R2 ; H0HP = –R2/R1; H0BP = –R3/R1; H0LP = –R4/R1 R4 Figure 11. Mode 3: 2nd Order Filter Providing Highpass, Bandpass, Lowpass f R6/(R5 + R6) ; H0N2 f ← CLK = – R2/R1 (R2/R4) + [R6/(R5 + R6)] 2 H0BP = – R3/R1 ; H0LP = R2 R3 ;Q= R4 R2 –R2/R1 (R2/R4) + [R6/(R5 + R6)] Figure 10. Mode 2b: 2nd Order Filter Providing Notch, Bandpass, Lowpass R4 R3 R2 VIN R1 4 HP S1A 3 (18) 5 (16) – + (17) + Σ 2 BP (19) LP (20) 1 – – ∫ ∫ Rg RI SA/B 6 1/2 LTC1060 15 – EXTERNAL OP AMP Rh NOTCH + V– f f0 = CLK 100(50) f R2 ; fn = CLK R4 100(50) H0N1(f ← 0) = Rg f R4 • ; H0N2 f ← CLK R1 RI 2 ( Rh ; H0HP = – R2/R1; H0BP = – R3/R1, H0LP = – R4/R1 RI ) = ( ) Rg Rg R R2 R3 • ; H0N(f = f0) = Q H0LP – g H0HP ; Q = R1 R2 Rh RI Rh Figure 12. Mode 3a: 2nd Order Filter Providing Highpass, Bandpass, Lowpass, Notch R2 R4 TLC1060 • MOO09 1060fb 13 LTC1060 U W ODES OF OPERATIO R4 R3 R2 HP 3 (18) R3 R2 R1 = R2 VIN S1A AP2 3 (18) 5 (16) – 4 + (17) Σ + BP (19) 2 1 LP (20) VIN R1 4 – ∫ – LP 1 (20) – ∫ – ∫ R5 SA/B 1/2 LTC1060 V+ R 1/2 LTC1060 15 V– TLC1060 • MOO10 f0 = Σ BP 2 (19) ∫ SA/B 15 + + 6 6 – (17) S1A 5 (16) ( ) EXTERNAL OP AMP 2R f f0 = CLK 100(50) fCLK R3 R2 R3 ;Q= ; HOAP = – ; HOLP = –2 HOBP = – 2 R2 R1 R2 100(50) – R2 R3 ;Q= R4 R2 + R2 R5 R2 R3 R4 ; H0AP = ; H0HP = – ; H0BP = – ; H0LP = – R4 2R R1 R1 R1 TLC1060 • MOO11 Figure 13. Mode 4: 2nd Order Filter Providing Allpass, Bandpass, Lowpass Figure 14. Mode 4a: 2nd Order Filter Providing Highpass, Bandpass, Lowpass, Allpass R4 R3 R3 R2 R1 VIN CZ S1A 3 (18) 5 (16) – 4 + (17) Σ + 2 BP (19) 1 LP (20) – – ∫ R2 VIN ∫ R1 4 – (17) + SA/B 6 V Q2 = R3 R1 6 1– HOBP = Σ 1+ f R2 ; fz = CLK R4 100(50) 1– R1 R3 ;Q= R4 R2 ( 1+ R2 R4 ) f R1 R2 ; HOZ = (f ← 0) = (R4/R1) –1 ; HOZ f ← CLK = ; R4 R1 (R4/R2) + 1 2 ( ) BP (19) 1 LP (20) – ∫ ∫ – SA/B + f f0 = CLK 100(50) + 2 TLC1060 • MOO12 1/2 LTC1060 15 N S1A 3 (18) 5 (16) TLC1060 • MOO13 1/2 LTC1060 15 V– fC = fCLK R2 ; H0LP = –R3/R1 ; H0HP = –R2/R1 100(50) R3 R3 R2 1 + (R2/R1) 1+ ; HOLP = R2 R1 1 + (R2/R4) Figure 15. Mode 5: 2nd Order Filter Providing Numerator Complex Zeros, Bandpass, Lowpass Figure 16. Mode 6a: 1st Order Filter Providing Highpass, Lowpass 1060fb 14 LTC1060 U W ODES OF OPERATIO R3 VIN R3 R2 R2=R1 LP1 S1A 3 (18) 5 (16) 2 LP2 (19) 1 (20) VIN R1=R2 4 – (17) 4 – + (17) + Σ – ∫ + ∫ Σ LP (19) ∫ ∫ – TLC1060 • MOO15 15 1/2 LTC1060 TLC1060 • MOO14 1/2 LTC1060 fC = HOLP = 2 x V– fCLK R2 R3 ; HOLP1 = 1 ; HOLP2 = – R2 100(50) R3 Figure 17. Mode 6b: 1st Order Filter Providing Lowpass fP = R3 R2 f R2 f fCLK R2 ; fz = CLK ; GAIN AT AP OUTPUT = 1 FOR 0 ≤ f ≤ CLK 100(50) R3 100(50) R3 2 Figure 18. Mode 7: 1st Order Filter Providing Allpass, Lowpass U 15 1 (20) – SA/B SA/B V– + 2 – 6 6 AP S1A 3 (18) 5 (16) W U U WW COMM E TS ON THE M ODES OF OPERATIO There are basically three modes of operation: mode 1, mode 2, mode 3. In the mode 1 (Figure 4), the input amplifier is outside the resonant loop. Because of this, mode 1 and its derivatives (mode 1a, 1b, 1c) are faster than modes 2 and 3. In mode 1, for instance, the Q errors are becoming noticeable above 1MHz clock frequency. Mode 1a (Figure 5), represents the most simple hook-up of the LTC1060. Mode 1a is useful when voltage gain at the bandpass output is required. The bandpass voltage gain, however, is equal to the value of Q; if this is acceptable, a second order, clock tunable, BP resonator can be achieved with only 2 resistors. The filter center frequency directly depends on the external clock frequency. For high order filters, mode 1a is not practical since it may require several clock frequencies to tune the overall filter response. Mode 1 (Figure 4), provides a clock tunable notch; the depth is shown in Graph 14. Mode 1 is a practical configuration for second order clock tunable bandpass/ notch filters. In mode 1, a bandpass output with a very high Q, together with unity gain, can be obtained without creating problems with the dynamics of the remaining notch and lowpass outputs. Modes 1b and 1c (Figures 6 and 7), are similar. They both produce a notch with a frequency which is always equal to the filter building block center frequency. The notch and the center frequency, however, can be adjusted with an external resistor ratio. The practical clock-to-center frequency ratio range is: 500 ≥ fCLK ≥ 100 or 50 ; mode 1b 1 1 1 f0 100 or 50 ≥ fCLK ≥ 100 or 50 ; mode 1c fo 1 1 √2 √2 The input impedance of the S1 pin is clock dependent, and in general R5 should not be larger than 5k. Mode 1b can be used to increase the clock-to-center frequency ratio beyond 100:1. For this mode, a practical limit for the (fCLK/f0) ratio is 500:1. Beyond this, the filter will exhibit large output offsets. Mode 1c is the fastest mode of operation: In the 50:1 mode and with (R5 = 0, R6 = ∞) the clock-to-center frequency ratio becomes (50/√2) and center frequencies beyond 20kHz can easily be achieved as shown in Graph 25. Figure 19 illustrates how to cascade the two sections of the LTC1060 connected in mode 1c to obtain a sharp fourth order, 1dB ripple, BP Chebyshev filter. Note that the center frequency to the BW ratio for this fourth order bandpass filter is 20/1. By varying the clock frequency to sweep the filter, the center frequency of the overall filter will increase proportionally and so will the BW to maintain the 20:1 ratio constant. All the modes of operation yield constant Q’s; with any filter realization the BW’s will vary when the filter is swept. This is shown in Figure 19, where the BP filter is swept from 1kHz to 20kHz center frequency. 1060fb 15 LTC1060 U W U U WW COMM E TS ON THE M ODES OF OPERATIO Modes 2, 2a, and 2b have a notch output which frequency, fn, can be tuned independently from the center frequency, f0. For all cases, however, fn<f0. These modes are useful when cascading second order functions to create an overall elliptic highpass, bandpass or notch response. The input amplifier and its feedback resistors (R2/R4) are now part of the resonant loop. Because of this, mode 2 and its derivatives are slower than mode 1’s. fCLK = 40kHz 0dB LTC1060 R61 VIN R51 1 R31 2 R21 3 R11 4 LPB BPA BPB NA NB 20 R52 19 R32 18 R22 INVB S1A S1B SA/B AGND 7 VA+ VA– 14 8 VD+ VD– 13 LSh 50/100 6 9 10 CLKA CLKB VOUT –5dB 50Hz –10dB R62 R12 17 INVA 5 V+ = 5V LPA –15dB –20dB 16 –25dB 15 12 0.9kHz V – = –5V 1.1kHz 1kHz fCLK = 800kHz 0dB 5V –5dB 11 1kHz –10dB 2 T L OR CMOS CLK IN PRECISE RESISTOR VALUES R11 = 149.21k R12 = 45.14k R21 = 4.99k R22 = 5.00k R31 = 149.12k R32 = 142.64k R51 = 2.55k R5 = 2.49k R61 = 2.49k R62 = 4.29k –15dB –20dB –25dB LTC1060 • CM01 18kHz 19kHz 20kHz 21kHz 22kHz TLC1060 • CMO01b Figure 19. Cascading the Two Sections of the LTC1060 Connected in Mode 1c to Obtain a Clock Tunable 4th Order 1dB Ripple Bandpass Chebyshev Filter with (Center Frequency)/(Ripple Bw) = 20/1. In mode 3 (Figure 11), a single resistor ratio (R2/R4) can tune the center frequency below or above the fCLK/100 (or fCLK/50) ratio. Mode 3 is a state variable configuration since it provides a highpass, bandpass, lowpass output through progressive integration; notches are obtained by summing the highpass and lowpass outputs (mode 3a, Figure 12). The notch frequency can be tuned below or above the center frequency through the resistor ratio (Rh/Ri). Because of this, modes 3 and 3a are the most versatile and useful modes for cascading second order sections to obtain high order elliptic filters. Figure 20 shows the two sections of an LTC1060 connected in mode 3a to obtain a clock tunable 4th order sharp elliptic bandpass filter. The first notch is created by summing directly the HP and LP outputs of the first section into the inverting input of the second section op amp. The individual Q’s are 29.6 and the filter maintains its shape and performance up to 20kHz center frequency (Figure 21). For this circuit an external op amp is required to obtain the 2nd notch. The dynamics of Figure 20 are excellent be- cause the amplitude response at each output pin does not exceed 0dB. The gain in the passband depends on the ratio of (Rg/Rh2) • (R22/Rh1)• (R21/R11). Any gain value can be obtained by acting on the (Rg/Rh2) ratio of the external op amp, meanwhile the remaining ratios are adjusted for optimum dynamics of the LTC1060 output nodes. The external op amp of Figure 20 is not always required. In Figure 22, one section of the LTC1060 in mode 3a is cascaded with the other section in mode 2b to obtain a 4th order, 1dB ripple, elliptic bandreject filter. This configuration is interesting because a 4th order function with two different notches is realized without requiring an external op amp. The clock-to-center frequency ratio is adjusted to 200:1; this is done in order to better approximate a linear R,C notch filter. The amplitude response of the filter is shown in Figure 23 with up to 1MHz clock frequency. The 0dB bandwidth to the stop bandwidth ratio is 9/1. When the filter is centered at 1kHz, it should theoretically have a 44dB rejection with a 50Hz stop bandwidth. For a more narrow filter than the above, the unused BP output of the 1060fb 16 LTC1060 U W U U WW COMM E TS ON THE M ODES OF OPERATIO mode 2b section (Figure 22), has a gain exceeding unity which limits the dynamic range of the overall filter. For very selective bandpass/bandreject filters, the mode 3a approach, as in Figure 20, yields better dynamic range since the external op amp helps to optimize the dynamics of the output nodes of the LTC1060. RH1 RG RL1 RL2 LTC1060 VIN R41 1 R31 2 R21 3 R11 4 5 –7.5V V+ = 7.5V 6 LPB BPA BPB HPA HPB INVA INVB S1A S1B 20 R42 19 R32 18 R22 VA+ VA– 14 8 VD+ VD– 13 LSh 50/100 CLKA CLKB VOUT + RH2 15 AGND T2L OR CMOS CLOCK IN EXTERNAL OP AMP 16 SA/B 9 – 17 7 10 R11 = 155.93k RH1 = 13.2k R42 = 5k LPA –7.5V 12 7.5V 11 PRECISE RESISTOR VALUES R31 = 152k R21 = 5k R22 = 5.26k RL1 = 10.74k RH2 = 5k RL2 = 6.11k R41 = 5.27k R32 = 151.8k RG = 37.3k NOTE: FOR CLOCK FREQUENCIES ABOVE 700kHz, A 12pF CAPACITOR ACROSS R41 AND A 20pF CAPACITOR ACROSS R42 WERE USED TO PREVENT THE PASSBAND RIPPLE FROM ANY ADDITIONAL PEAKING LTC1060 • CM02 Figure 20. Combining Mode 3 with Mode 3a to Make The 4th Order BP Filter of Figure 21 with Improved Dynamics. The Gain at Each Output Node is ≤ 0dB for all Input Frequencies. fCLK = 100kHz fCLK = 1MHz 0dB 0dB –10dB –10dB –20dB –20dB –30dB –30dB –40dB –40dB –50dB –50dB 1.5kHz 1.75kHz 2kHz 2.25kHz 2.5kHz 15kHz 17.5kHz 20kHz 22.5kHz 25kHz TLC1060 • CMO03 Figure 21. The BP Filter of Figure 20, When Swept From a 2kHz to 20kHz Center Frequency. 1060fb 17 LTC1060 U W U U WW COMM E TS ON THE M ODES OF OPERATIO fCLK 200 = ; fCLK ≤ 1MHz f0 1 RH1 RL1 1 R31 2 R21 3 R11 VIN 4 5 6 –5V + V = –5V LPB BPA BPB HPA NB INVA INVB S1A S1B SA/B AGND 20 R52 19 R32 18 8 VD+ VD– LSh 50/100 CLKB VOUT 15 14 VA– CLKA R22 16 VA+ 10 –10 R62 17 7 9 T2L OR CMOS CLOCK IN LPA VOUT /VIN (dB) R41 0 R42 LTC1060 –20 –30 V– = –5V 13 12 – 40 11 – 50 R11 = 60k R41 = 28.84k R52 = 5k R32 = 455.75k RESISTOR VALUES R31 = 54.75k R21 = 5k RL1 = 19.3k RH1 = 5k R62 = 1.59k R22 = 60k R42 = 503.85k – 60 0.7 0.9 0.8 1.1 f0 = 1.0 1.2 1.3 LTC1060 • CM04 INPUT FREQUENCY NORMALIZED TO FILTER CENTER FREQUENCY TLC1060 • CMO05 Figure 22. Combining Mode 3 with Mode 2b to Create a 4th Order BR Elliptic Filter with 1dB Ripple and a Ratio of 0dB to Stop Bandwidth Equal to 9/1. Figure 23. Amplitude Response of the Notch Filter of Figure 22 LTC1060 OFFSETS Switched capacitor integrators generally exhibit higher input offsets than discrete R, C integrators. These offsets are mainly due to the charge injection of the CMOS switches into the integrating capacitors and they are temperature independent. The internal op amp offsets also add to the overall offset budget and they are typically a couple of millivolts. Because of this, the DC output offsets of switched capacitor filters are usually higher than the offsets of discrete active filters. (17) 4 + VOS1 (18) (16) 3 5 – – + + – Σ (19) 2 + VOS2 – – – + Figure 24 shows half of an LTC1060 filter building block with its equivalent input offsets VOS1, VOS2, VOS3. All three are 100% tested for both sides of the LTC1060. VOS2 is generally the larger offset. When the SA/B, Pin 6, of the LTC1060 is shorted to the negative supply (i.e., mode 3), the value of the VOS2 decreases. Additionally, with SA/B low, a 20% to 30% noise reduction is observed. Mode 1 can still be achieved, if desired, by shorting the S1 pin to the lowpass output (Figure 25). R3 (20) 1 VOS3 – R2 VIN R1 4 – – (17) + + N S1A 3 (18) 5 (16) + – Σ – 2 ∫ BP (19) 1 LP (20) ∫ + SA/B TLC1060 • LO01 15 6 TLC1060 • LO02 15 1/2 LTC1060 V– Figure 24. Equivalent Input Offsets of 1/2 LTC1060 Filter Building Block Figure 25. Mode 1(LN): Same Operation as Mode 1 but Lower VOS2 Offset and Lower Noise 1060fb 18 LTC1060 LTC1060 OFFSETS Output Offsets dynamic range. As a rule of thumb, the output DC offsets increase when: The DC offset at the filter bandpass output is always equal to VOS3. The DC offsets at the remaining two outputs (Notch and LP) depend on the mode of operation and external resistor ratios. Table 5 illustrates this. 1. The Q’s decrease. 2. The ratio (fCLK/f0) increases beyond 100:1. This is done by decreasing either the (R2/R4) or the R6/(R5 + R6) resistor ratios. It is important to know the value of the DC output offsets, especially when the filter handles input signals with large Table 5 VOSN PIN 3 (18) MODE VOSBP PIN 2 (19) VOSLP PIN 1 (20) 1,4 VOS1 [(1/Q) + 1 + ||HOLP||] – VOS3/Q VOS3 VOSN – VOS2 1a VOS1 [1 + (1/Q)] – VOS3/Q VOS3 VOSN – VOS2 1b VOS1 [(1/Q) + 1 + R2/R1] – VOS3/Q VOS3 ~ (VOSN – VOS2) (1 + R5/R6) 1c VOS1 [(1/Q) + 1 + R2/R1] – VOS3/Q VOS3 2, 5 [VOS1(1 + R2/R1 + R2/R3 + R2/R4) – VOS3(R2/R3)] • [R4/(R2 + R4)] + VOS2[R2/(R2 + R4)] VOS3 VOSN – VOS2 2a [VOS1(1 + R2/R1 + R2/R3 + R2/R4) – VOS3(R2/R3)] VOS3 ~ (VOSN – VOS2) VOS3 ~ (VOSN – VOS2) (1 + R5/R6) • R4(1 + k) R2 R6 + VOS2 ;k = R2 + R4(1 + k) R2 + R4(1 + k) R5 + R6 ~(VOSN – VOS2) (R5 + R6) (R5 + 2R6) (R5 + R6) (R5 + 2R6) [VOS1(1 + R2/R1 + R2/R3 + R2/R4) – VOS3(R2/R3)] 2b • 3, 4a R4k R2 R6 + VOS2 ;k = R2 + R4k R2 + R4k R5 + R6 VOS2 VOS3 R4 R4 R4 R4 + + – VOS2 R1 R2 R3 R2 R4 R3 VOS1 1 + – VOS3 U PACKAGE DESCRIPTIO N Package 20-Lead PDIP (Narrow .300 Inch) (Reference LTC DWG # 05-08-1510) .300 – .325 (7.620 – 8.255) 1.040* (26.416) MAX 20 .008 – .015 (0.203 – 0.381) ( 17 16 15 14 13 12 11 .020 (0.508) MIN 1 ) 18 .255 ± .015* (6.477 ± 0.381) +.035 .325 –.015 +0.889 8.255 –0.381 19 NOTE: 1. DIMENSIONS ARE .045 – .065 (1.143 – 1.651) .125 – .145 (3.175 – 3.683) 2 3 4 5 6 7 8 9 10 .065 (1.651) TYP .120 (3.048) MIN .005 (0.127) MIN .100 (2.54) BSC INCHES MILLIMETERS *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm) .018 ± .003 (0.457 ± 0.076) N20 1002 1060fb Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC1060 U PACKAGE DESCRIPTIO J Package 20-Lead CERDIP (Narrow .300 Inch, Hermetic) (Reference LTC DWG # 05-08-1110) 1.060 (26.924) MAX CORNER LEADS OPTION (4 PLCS) .023 – .045 (0.584 – 1.143) HALF LEAD OPTION 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 .025 .220 – .310 (5.588 – 7.874) (0.635) RAD TYP .045 – .065 (1.143 – 1.650) FULL LEAD OPTION .005 (0.127) MIN .300 BSC (7.62 BSC) .200 (5.080) MAX .015 – .060 (0.381 – 1.524) .008 – .018 (0.203 – 0.457) 0° – 15° NOTE: LEAD DIMENSIONS APPLY TO SOLDER DIP/PLATE OR TIN PLATE LEADS .125 (3.175) MIN .045 – .065 (1.143 – 1.651) .100 (2.54) BSC .014 – .026 (0.356 – 0.660) J20 0801 OBSOLETE PACKAGE SW Package 20-Lead Plastic Small Outline (Wide .300 Inch) (Reference LTC DWG # 05-08-1620) .050 BSC .045 ±.005 .030 ±.005 TYP .496 – .512 (12.598 – 13.005) NOTE 4 N 20 19 18 17 16 15 14 13 12 11 N .325 ±.005 .420 MIN .394 – .419 (10.007 – 10.643) NOTE 3 1 2 3 N/2 N/2 RECOMMENDED SOLDER PAD LAYOUT .005 (0.127) RAD MIN .009 – .013 (0.229 – 0.330) NOTE: 1. DIMENSIONS IN .291 – .299 (7.391 – 7.595) NOTE 4 .010 – .029 × 45° (0.254 – 0.737) 1 2 3 4 5 6 7 8 .093 – .104 (2.362 – 2.642) 9 10 .037 – .045 (0.940 – 1.143) 0° – 8° TYP .050 (1.270) BSC NOTE 3 .016 – .050 (0.406 – 1.270) .014 – .019 (0.356 – 0.482) TYP .004 – .012 (0.102 – 0.305) S20 (WIDE) 0502 INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS 4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm) 1060fb 20 Linear Technology Corporation LW/TP 1202 1K REV B • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 1988