ATMEL AT28BV64B-20JC 64k (8k x 8) battery-voltageâ ¢ parallel eeprom with page write and software data protection Datasheet

Features
• Single 2.7V to 3.6V Supply
• Hardware and Software Data Protection
• Low Power Dissipation
•
•
•
•
•
•
•
– 15 mA Active Current
– 20 µA CMOS Standby Current
Fast Read Access Time - 200 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 64 Bytes
– Internal Control Timer
Fast Write Cycle Times
– Page Write Cycle Time: 10 ms Maximum
– 1 to 64 Byte Page Write Operation
DATA Polling for End of Write Detection
High-reliability CMOS Technology
– Endurance: 100,000 Cycles
– Data Retention: 10 Years
JEDEC Approved Byte-wide Pinout
Commercial and Industrial Temperature Ranges
Description
The AT28BV64B is a high-performance electrically erasable programmable read only
memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20 µA.
(continued)
64K (8K x 8)
Battery-Voltage™
Parallel EEPROM
with Page Write
and Software
Data Protection
AT28BV64B
Pin Configurations
PDIP, SOIC
Top View
Pin Name
Function
A0 - A12
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
DC
Don’t Connect
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
PLCC
Top View
A7
A12
NC
DC
VCC
WE
NC
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
5
6
7
8
9
10
11
12
13
Note:
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
3-Volt, 64K
E2PROM with
Data Protection
TSOP
Top View
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PLCC package pins 1 and 17
are DON’T CONNECT.
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
Rev. 0299F–05/28/99
1
The AT28BV64B is accessed like a static RAM for the read
or write cycle without the need for external components.
The device contains a 64 byte page register to allow writing
of up to 64 bytes simultaneously. During a write cycle, the
addresses and 1 to 64 bytes of data are internally latched,
freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer.
The end of a write cycle can be detected by DATA polling of
I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV64B has additional features to ensure high
quality and manufacturability. A software data protection
mechanism guards against inadvertent writes. The device
also includes an extra 64 bytes of EEPROM for device
identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
2
AT28BV64B
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
AT28BV64B
Device Operation
READ: The AT28BV64B is accessed like a static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems.
BYTE WRITE: A low pulse on the WE or CE input with CE
or WE low (respectively) and OE high initiates a write cycle.
The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising
edge of CE or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated and for the duration
of tWC, a read operation will effectively be a polling operation.
PA G E W R I T E : T h e p a g e w r i t e o p e r a t i o n o f t h e
AT28BV64B allows 1 to 64 bytes of data to be written into
the device during a single internal programming period. A
page write operation is initiated in the same manner as a
byte write; the first byte written can then be followed by 1 to
63 additional bytes. Each successive byte must be written
within 100 µs (tBLC) of the previous byte. If the tBLC limit is
exceeded, the AT28BV64B will cease accepting data and
commence the internal programming operation. All bytes
during a page write operation must reside on the same
page as defined by the state of the A6 to A12 inputs. For
each WE high to low transition during the page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are
to be written. The bytes may be loaded in any order and
may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary
cycling of other bytes within the page does not occur.
DATA POLLING: The AT28BV64B features DATA Polling
to indicate the end of a write cycle. During a byte or page
write cycle an attempted read of the last byte written will
result in the complement of the written data to be presented
on I/O7. Once the write cycle has been completed, true
data is valid on all outputs, and the next write cycle may
begin. DATA Polling may begin at anytime during the write
cycle.
TOGGLE BIT: In addition to DATA Polling, the AT28BV64B
provides another method for determining the end of a write
cycle. During the write operation, successive attempts to
read data from the device will result in I/O6 toggling
between one and zero. Once the write has completed, I/O6
will stop toggling and valid data will be read. Reading the
toggle bit may begin at any time during the write cycle.
DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware
and software features that will protect the memory against
inadvertent writes.
HARDWARE PROTECTION: Hardware features protect
against inadvertent writes to the AT28BV64B in the following ways: (a) VCC power-on delay—once VCC has reached
1.8V (typical) the device will automatically time out 10 ms
(typical) before allowing a write; (b) write inhibitholding
any one of OE low, CE high or WE high inhibits write
cycles; and (c) noise filterpulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle.
SOFTWARE DATA PROTECTION: A software-controlled
data protection feature has been implemented on the
AT28BV64B. Software data protection (SDP) helps prevent
inadvertent writes from corrupting the data in the device.
SDP can prevent inadvertent writes during power-up and
power-down as well as any other potential periods of system instability.
The AT28BV64B can only be written using the software
data protection feature. A series of three write commands
to specific addresses with specific data must be presented
to the device before writing in the byte or page mode. The
same three write commands must begin each write operation. All software write commands must obey the page
mode write timing specifications. The data in the 3-byte
command sequence is not written to the device; the
addresses in the command sequence can be utilized just
like any other location in the device.
Any attempt to write to the device without the 3-byte
sequence will start the internal write timers. No data will be
written to the device; however, for the duration of tWC, read
operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 64 bytes of EEPROM
memory are available to the user for device identification.
By raising A9 to 12V ± 0.5V and using address locations
7FC0H to 7FFFH, the additional bytes may be written to or
read from in the same manner as the regular memory
array.
3
DC and AC Operating Range
Operating
Temperature (Case)
Com.
Ind.
VCC Power Supply
AT28BV64B-20
AT28BV64B-25
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
2.7V to 3.6V
2.7V to 3.6V
Operating Modes
Mode
CE
OE
WE
I/O
Read
VIL
VIL
VIH
DOUT
VIL
VIH
VIL
DIN
VIH
(1)
X
High Z
(2)
Write
Standby/Write Inhibit
X
Write Inhibit
X
X
VIH
Write Inhibit
X
VIL
X
Output Disable
X
VIH
X
High Z
VIL
High Z
Chip Erase
Notes:
VIL
VH
(3)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC + 1V
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
20
µA
VCC Standby Current CMOS
CE = VCC - 0.3V to
VCC + 1V
Com.
ISB
Ind.
50
µA
ICC
VCC Active Current
f = 5 MHz; IOUT = 0 mA
15
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6 mA
VOH
Output High Voltage
IOH = -100 µA
4
AT28BV64B
Min
2.0
V
0.45
2.0
V
V
AT28BV64B
AC Read Characteristics
Symbol
Parameter
tACC
AT28BV64B-20
AT28BV64B-25
Min
Min
Max
Max
Units
Address to Output Delay
200
250
ns
(1)
CE to Output Delay
200
250
ns
(2)
OE to Output Delay
0
80
0
100
ns
tDF(3)(4)
CE or OE to Output Float
0
55
0
60
ns
tOH
Output Hold from OE, CE or Address, whichever
occurred first
0
tCE
tOE
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 20 ns
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Set-up Time
tAH
Address Hold Time
tCS
Min
Max
Units
0
ns
100
ns
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
200
ns
tDS
Data Set-up Time
100
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tDV
tWPH
Notes:
Time to Data Valid
Write Pulse Width High
(1)
NR
100
1. NR = No Restriction
2. All byte write operations must be preceded by the SDP command sequence.
AC Write Waveforms
WE Controlled
CE Controlled
6
AT28BV64B
ns
AT28BV64B
Page Mode Characteristics
Symbol
Parameter
tWC
Write Cycle Time
tAS
Address Set-up Time
tAH
Min
Max
Units
10
ms
0
ns
Address Hold Time
100
ns
tDS
Data Set-up Time
100
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
200
ns
tBLC
Byte Load Cycle Time
tWPH
Write Pulse Width High
100
100
µs
ns
Write Algorithm(1)
LOAD DATA AA
TO
ADDRESS 1555
LOAD DATA 55
TO
ADDRESS 0AAA
LOAD DATA A0
TO
ADDRESS 1555
WRITES ENABLED(2)
LOAD DATA XX
TO
ANY ADDRESS(3)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
Notes for software program code:
1. Data Format: I/O7 - I/O0 (Hex); Address Format: A12 - A0 (Hex).
2. Data protect state will be re-activated at the end of the write cycle.
3. 1 to 64 bytes of data are loaded.
7
Software Data Protection Write Cycle Waveforms(1)(2)(3)
Notes:
1.
A0 - A12 must conform to the addressing sequence for the first three bytes as shown above.
2.
A6 through A12 must specify the same page address during each high to low transition of WE (or CE) after the software
code has been entered.
3.
OE must be high only when WE and CE are both low.
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
OE to Output Delay
tWR
Write Recovery Time
Notes:
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Data Polling Waveforms
8
AT28BV64B
Max
Units
0
ns
0
ns
(2)
tOE
Typ
ns
0
ns
AT28BV64B
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
OE to Output Delay
tOEHP
OE High Pulse
tWR
Notes:
Write Recovery Time
Max
Units
10
ns
10
ns
(2)
tOE
Typ
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See AC Read Characteristics.
Toggle Bit Waveforms
Notes:
1.
Toggling either OE or CE or both OE and CE will operate toggle bit.
2.
Beginning and ending state of I/O6 will vary.
3.
Any address location may be used, but the address should not vary.
9
Ordering Information(1)
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
200
15
0.05
AT28BV64B-20JC
AT28BV64B-20PC
AT28BV64B-20SC
AT28BV64B-20TC
32J
28P6
28S
28T
Commercial
(0°C to 70°C)
15
0.05
AT28BV64B-20JI
AT28BV64B-20PI
AT28BV64B-20SI
AT28BV64B-20TI
32J
28P6
28S
28T
Industrial
(-40°C to 85°C)
15
0.05
AT28BV64B-25JC
AT28BV64B-25PC
AT28BV64B-25SC
AT28BV64B-25TC
32J
28P6
28S
28T
Commercial
(0°C to 70°C)
15
0.05
AT28BV64B-25JI
AT28BV64B-25PI
AT28BV64B-25SI
AT28BV64B-25TI
32J
28P6
28S
28T
Industrial
(-40°C to 85°C)
250
Note:
1. See Valid Part Number table below.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers
Speed
Package and Temperature Combinations
AT28BV64B
20
JC, JI, PC, PI, SC, SI, TC, TI
AT28BV64B
25
JC, JI, PC, PI, SC, SI, TC, TI
Package Type
32J
32-lead, Plastic J-leaded Chip Carrier (PLCC)
28P6
28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
28S
28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)
28T
28-lead, Plastic Thin Small Outline Package (TSOP)
10
AT28BV64B
Operation Range
AT28BV64B
Packaging Information
32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
28P6, 28-lead, 0.600" Wide,
Plastic Dual In-Line Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
.045(1.14) X 45˚
PIN NO. 1
IDENTIFY
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
1.47(37.3)
1.44(36.6)
.025(.635) X 30˚ - 45˚
.012(.305)
.008(.203)
PIN
1
.530(13.5)
.490(12.4)
.566(14.4)
.530(13.5)
.021(.533)
.013(.330)
.090(2.29)
MAX
1.300(33.02) REF
.050(1.27) TYP
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.030(.762)
.015(.381)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.022(.559) X 45˚ MAX (3X)
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
28S, 28-lead, 0.300" Wide,
Plastic Gull Wing Small Outline (SOIC)
Dimensions in Inches and (Millimeters)
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
28T, 28-lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)*
INDEX
MARK
AREA
11.9 (0.469)
11.7 (0.461)
13.7 (0.539)
13.1 (0.516)
0.27 (0.011)
0.18 (0.007)
0.55 (0.022)
BSC
7.15 (0.281)
REF
8.10 (0.319)
7.90 (0.311)
1.25 (0.049)
1.05 (0.041)
0.20 (0.008)
0.10 (0.004)
0
REF
5
0.20 (0.008)
0.15 (0.006)
0.70 (0.028)
0.30 (0.012)
*Controlling dimension: millimeters
11
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© Atmel Corporation 1999.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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are registered trademarks and trademarks of Atmel Corporation.
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0299F–05/28/99/xM
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